Wired it up

crcChecker.vhd

@@ -2,45 +2,41 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 
 ENTITY crcChecker IS
-	PORT (
-		Resetx					: IN		STD_LOGIC;
-		Clock						: IN		STD_LOGIC;
-		compute_enable	: IN		STD_LOGIC;
-		u4							: IN		STD_LOGIC_VECTOR(3 DOWNTO 0);
-		CRC_out					: OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
-	);
+	PORT (	aclr			: IN		STD_LOGIC;
+			clk				: IN		STD_LOGIC;
+			compute_enable	: IN		STD_LOGIC;
+			u4				: IN		STD_LOGIC_VECTOR(3 DOWNTO 0);
+			CRC_out			: OUT		STD_LOGIC_VECTOR(31 DOWNTO 0) );
+
 END crcChecker;
 
 --	for the input u4, the leftmost bit u4(3) is the first bit received
 
 ARCHITECTURE rtl OF crcChecker IS
 	SIGNAL Q_next		: STD_LOGIC_VECTOR(31 DOWNTO 0);
 	SIGNAL Q_current	: STD_LOGIC_VECTOR(31 DOWNTO 0);
-	CONSTANT init		: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '1');
-
-
+--	CONSTANT init		: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '1');	
 
 BEGIN
--- state update
-	PROCESS(Resetx,Clock)
+-- state update 
+	PROCESS(aclr,clk)
 	BEGIN
-		IF Resetx = '1' THEN
+		IF aclr = '1' THEN 
 			Q_current <= ( OTHERS => '0');
-		ELSIF Clock'EVENT AND Clock = '1' THEN
+		ELSIF clk'EVENT AND clk = '1' THEN
 			Q_current <= Q_next;
 		END IF;
 	END PROCESS;
-
+	
 -- logic for determining next state
 	PROCESS(u4,Q_current,compute_enable)
-	VARIABLE ux4	: STD_LOGIC_VECTOR(3 DOWNTO 0);
+	VARIABLE ux4	: STD_LOGIC_VECTOR(3 DOWNTO 0);	
 
 	BEGIN
-		ux4(0) := Q_current(31) XOR u4(3);  -- fixed
+		ux4(0) := Q_current(31) XOR u4(3);
 		ux4(1) := Q_current(30) XOR u4(2);
 		ux4(2) := Q_current(29) XOR u4(1);
 		ux4(3) := Q_current(28) XOR u4(0);
-
 		IF compute_enable = '0' THEN
 			Q_next <= (OTHERS => '1');
 		ELSE
@@ -53,7 +49,7 @@ BEGIN
 			Q_next(25) <= Q_current(21) XOR ux4(1) XOR ux4(0);
 			Q_next(24) <= Q_current(20) XOR ux4(2) XOR ux4(1);
 			Q_next(23) <= Q_current(19) XOR ux4(3) XOR ux4(2);
-			Q_next(22) <= Q_current(18) XOR ux4(3);
+			Q_next(22) <= Q_current(18) XOR ux4(3);		
 			Q_next(21) <= Q_current(17);
 			Q_next(20) <= Q_current(16);
 			Q_next(19) <= Q_current(15) XOR ux4(0);
@@ -79,9 +75,8 @@ BEGIN
 		END IF;
 
 	END PROCESS;
-
+	
 -- output
-	CRC_OUT <=  Q_current;
-
+	CRC_out <= Q_current;
 
 END rtl;

inputProcessor.vhd

@@ -24,11 +24,19 @@ SIGNAL signal_hold_count	:	STD_LOGIC_VECTOR(3 DOWNTO 0);
 SIGNAL signal_receiving		:	STD_LOGIC;
 SIGNAL signal_reset				:	STD_LOGIC;
 SIGNAL signal_hold				:	STD_LOGIC;
+SIGNAL signal_crc_check			: 	STD_LOGIC;
 SIGNAL signal_data_out		:	STD_LOGIC_VECTOR(7 DOWNTO 0);
 SIGNAL signal_readBuffer	:	STD_LOGIC;
 SIGNAL signal_crc					:	STD_LOGIC_VECTOR(31 DOWNTO 0);
 SIGNAL signal_shifter			:	STD_LOGIC_VECTOR(31 DOWNTO 0);
 SIGNAL crc_valid					:	STD_LOGIC;
+SIGNAL signal_frame_counter_length	:	STD_LOGIC_VECTOR(11 DOWNTO 0); 
+SIGNAL signal_frame_current_length	:	STD_LOGIC_VECTOR(11 DOWNTO 0); 
+SIGNAL signal_frame_register_length	:	STD_LOGIC_VECTOR(11 DOWNTO 0); 
+SIGNAL signal_next_length	:	STD_LOGIC; 
+
+
+
 
 	COMPONENT inputProcessor_stateController IS
 		PORT (
@@ -40,7 +48,8 @@ SIGNAL crc_valid					:	STD_LOGIC;
 			hold_count	:	IN 	STD_LOGIC_VECTOR(3 DOWNTO 0);
 			receiving		:	OUT STD_LOGIC; -- HIGH if currently in receiving state; will act as enable signal for other modules
 			reset				:	OUT STD_LOGIC; -- HIGH if transitioned into IDLE state; resets all components for next frame
-			hold				:	OUT STD_LOGIC-- HIGH if transitioned into HOLD state; must remain in state until  hold_count = 12
+			hold				:	OUT STD_LOGIC;-- HIGH if transitioned into HOLD state; must remain in state until  hold_count = 12
+			crc_check			:	OUT STD_LOGIC
 		);
 	END COMPONENT;
 
@@ -65,13 +74,11 @@ SIGNAL crc_valid					:	STD_LOGIC;
 	END COMPONENT;
 
 	COMPONENT crcChecker IS
-		PORT (
-			Resetx					: IN		STD_LOGIC;
-			Clock						: IN		STD_LOGIC;
-			compute_enable	: IN		STD_LOGIC;
-			u4							: IN		STD_LOGIC_VECTOR(3 DOWNTO 0);
-			CRC_out					: OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
-		);
+		PORT (	aclr			: IN		STD_LOGIC;
+				clk				: IN		STD_LOGIC;
+				compute_enable	: IN		STD_LOGIC;
+				u4				: IN		STD_LOGIC_VECTOR(3 DOWNTO 0);
+				CRC_out			: OUT		STD_LOGIC_VECTOR(31 DOWNTO 0) );
 	END COMPONENT;
 
 	COMPONENT frameCounter IS
@@ -87,17 +94,56 @@ SIGNAL crc_valid					:	STD_LOGIC;
 				enable		:	IN STD_LOGIC;
 				count		:	OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
 	END COMPONENT;
+
+	COMPONENT countdown_stateController IS
+		PORT (	aclr				:	IN 	STD_LOGIC;
+				clk					:	IN 	STD_LOGIC;
+				begin_count			:	IN 	STD_LOGIC; 
+				frame_length		:	IN 	STD_LOGIC_VECTOR(11 DOWNTO 0);
+				counting			:	OUT STD_LOGIC;
+				next_length			:	OUT STD_LOGIC  
+		);
+	END COMPONENT;
+
+	COMPONENT register12bit IS
+		PORT
+		(
+			aclr		: IN STD_LOGIC ;
+			clock		: IN STD_LOGIC ;
+			data		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+			enable		: IN STD_LOGIC ;
+			q		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+		);
+	END COMPONENT;
+
+	COMPONENT lengthBuffer IS
+		PORT
+		(
+			aclr		: IN STD_LOGIC  := '0';
+			data		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+			rdclk		: IN STD_LOGIC ;
+			rdreq		: IN STD_LOGIC ;
+			wrclk		: IN STD_LOGIC ;
+			wrreq		: IN STD_LOGIC ;
+			q		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+		);
+	END COMPONENT;
+
 
 BEGIN
 
-	Stage1: inputProcessor_stateController PORT MAP (aclr, clk50, signal_frame_start, data_in_valid, crc_valid, signal_hold_count, signal_receiving, signal_reset, signal_hold);
+	Stage1: inputProcessor_stateController PORT MAP (aclr, clk25, signal_frame_start, data_in_valid, crc_valid, signal_hold_count, signal_receiving, signal_reset, signal_hold, signal_crc_check);
 	Stage2: sfdChecker PORT MAP (aclr OR signal_reset, clk25, data_in_valid, data_in, signal_frame_start);
 	Stage3: frameBuffer PORT MAP (aclr OR signal_reset, clk25, clk50, '1', signal_receiving, data_in, signal_data_out);
 	Stage4: crcChecker PORT MAP (aclr OR signal_reset, clk25, signal_receiving, data_in, signal_crc);
-	Stage5: frameCounter PORT MAP (aclr OR signal_reset, clk25, signal_receiving, frame_length);
+	Stage5: frameCounter PORT MAP (aclr OR signal_reset, clk25, signal_receiving, signal_frame_counter_length);
 	Stage6: holdCounter PORT MAP (aclr OR signal_reset, clk25, signal_hold, signal_hold_count);
 	Stage7: data_out <= signal_data_out;
-	Stage8:
+	Stage8: countdown_stateController PORT MAP (aclr OR signal_reset, clk50, crc_valid, signal_frame_register_length, data_out_valid, signal_next_length);
+	Stage9: register12bit PORT MAP (aclr OR signal_reset, clk50, signal_frame_current_length, signal_next_length, signal_frame_register_length);
+	Stage10: lengthBuffer PORT MAP (aclr OR signal_reset, signal_frame_counter_length, clk50, signal_next_length, clk25, signal_crc_check, signal_frame_current_length);
+
+
 	receive_state <= signal_receiving;
 	hold_state <= signal_hold;
 	reset_state <= signal_reset;
@@ -107,4 +153,8 @@ BEGIN
 
 	crc_valid <= '1' WHEN (signal_shifter XOR signal_crc) = "11111111111111111111111111111111" ELSE '0';
 	crc <= crc_valid;
+
+	frame_length <= signal_frame_current_length;
+
+
 END subsystem_level_design;

inputProcessor_stateController.vhd

@@ -12,7 +12,8 @@ ENTITY inputProcessor_stateController IS
 		hold_count	:	IN 	STD_LOGIC_VECTOR(3 DOWNTO 0);
 		receiving		:	OUT STD_LOGIC; -- HIGH if currently in receiving state; will act as enable signal for other modules
 		reset				:	OUT STD_LOGIC; -- HIGH if transitioned into IDLE state; resets all components for next frame
-		hold				:	OUT STD_LOGIC-- HIGH if transitioned into HOLD state; must remain in state until  hold_count = 12
+		hold				:	OUT STD_LOGIC;-- HIGH if transitioned into HOLD state; must remain in state until  hold_count = 12
+		crc_check			: OUT STD_LOGIC
 	);
 END inputProcessor_stateController;
 
@@ -34,7 +35,7 @@ BEGIN
 	END PROCESS;
 
 -- Next State Logic
-	PROCESS (inputProcessor_currentState, frame_start, frame_valid, hold_count)
+	PROCESS (inputProcessor_currentState, frame_start, frame_valid, hold_count, crc_valid)
 	BEGIN
 		CASE inputProcessor_currentState IS
 			WHEN IDLE_STATE =>
@@ -65,9 +66,13 @@ BEGIN
 		receiving <= '0';
 		reset <= '0';
 		hold <= '0';
+		crc_check <= '0';
 		IF inputProcessor_currentState = RECEIVING_STATE THEN receiving <= '1';
 		ELSE receiving <= '0';
 		END IF;
+		IF inputProcessor_currentState = CRC_CHECK_STATE THEN crc_check <= '1';
+		ELSE crc_check <= '0';
+		END IF;
 		IF inputProcessor_currentState = RESET_STATE THEN reset <= '1';
 		ELSE reset <= '0';
 		END IF;

lengthBuffer.cmp

@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lengthBuffer
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+	);
+end component;

lengthBuffer.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lengthBuffer.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lengthBuffer.cmp"]