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Original file line number | Diff line number | Diff line change |
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--Copyright (C) 1991-2010 Altera Corporation | ||
--Your use of Altera Corporation's design tools, logic functions | ||
--and other software and tools, and its AMPP partner logic | ||
--functions, and any output files from any of the foregoing | ||
--(including device programming or simulation files), and any | ||
--associated documentation or information are expressly subject | ||
--to the terms and conditions of the Altera Program License | ||
--Subscription Agreement, Altera MegaCore Function License | ||
--Agreement, or other applicable license agreement, including, | ||
--without limitation, that your use is for the sole purpose of | ||
--programming logic devices manufactured by Altera and sold by | ||
--Altera or its authorized distributors. Please refer to the | ||
--applicable agreement for further details. | ||
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component lengthBuffer | ||
PORT | ||
( | ||
aclr : IN STD_LOGIC := '0'; | ||
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0); | ||
rdclk : IN STD_LOGIC ; | ||
rdreq : IN STD_LOGIC ; | ||
wrclk : IN STD_LOGIC ; | ||
wrreq : IN STD_LOGIC ; | ||
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) | ||
); | ||
end component; |
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set_global_assignment -name IP_TOOL_NAME "FIFO" | ||
set_global_assignment -name IP_TOOL_VERSION "9.1" | ||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lengthBuffer.vhd"] | ||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lengthBuffer.cmp"] |
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