diff --git a/crcChecker.vhd b/crcChecker.vhd
index e7e22bc..e0e7319 100755
--- a/crcChecker.vhd
+++ b/crcChecker.vhd
@@ -2,13 +2,12 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY crcChecker IS
- PORT (
- Resetx : IN STD_LOGIC;
- Clock : IN STD_LOGIC;
- compute_enable : IN STD_LOGIC;
- u4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- CRC_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
- );
+ PORT ( aclr : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ compute_enable : IN STD_LOGIC;
+ u4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ CRC_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
+
END crcChecker;
-- for the input u4, the leftmost bit u4(3) is the first bit received
@@ -16,31 +15,28 @@ END crcChecker;
ARCHITECTURE rtl OF crcChecker IS
SIGNAL Q_next : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL Q_current : STD_LOGIC_VECTOR(31 DOWNTO 0);
- CONSTANT init : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '1');
-
-
+-- CONSTANT init : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '1');
BEGIN
--- state update
- PROCESS(Resetx,Clock)
+-- state update
+ PROCESS(aclr,clk)
BEGIN
- IF Resetx = '1' THEN
+ IF aclr = '1' THEN
Q_current <= ( OTHERS => '0');
- ELSIF Clock'EVENT AND Clock = '1' THEN
+ ELSIF clk'EVENT AND clk = '1' THEN
Q_current <= Q_next;
END IF;
END PROCESS;
-
+
-- logic for determining next state
PROCESS(u4,Q_current,compute_enable)
- VARIABLE ux4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
+ VARIABLE ux4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
- ux4(0) := Q_current(31) XOR u4(3); -- fixed
+ ux4(0) := Q_current(31) XOR u4(3);
ux4(1) := Q_current(30) XOR u4(2);
ux4(2) := Q_current(29) XOR u4(1);
ux4(3) := Q_current(28) XOR u4(0);
-
IF compute_enable = '0' THEN
Q_next <= (OTHERS => '1');
ELSE
@@ -53,7 +49,7 @@ BEGIN
Q_next(25) <= Q_current(21) XOR ux4(1) XOR ux4(0);
Q_next(24) <= Q_current(20) XOR ux4(2) XOR ux4(1);
Q_next(23) <= Q_current(19) XOR ux4(3) XOR ux4(2);
- Q_next(22) <= Q_current(18) XOR ux4(3);
+ Q_next(22) <= Q_current(18) XOR ux4(3);
Q_next(21) <= Q_current(17);
Q_next(20) <= Q_current(16);
Q_next(19) <= Q_current(15) XOR ux4(0);
@@ -79,9 +75,8 @@ BEGIN
END IF;
END PROCESS;
-
+
-- output
- CRC_OUT <= Q_current;
-
+ CRC_out <= Q_current;
END rtl;
diff --git a/inputProcessor.vhd b/inputProcessor.vhd
index f465e73..c5dfa18 100755
--- a/inputProcessor.vhd
+++ b/inputProcessor.vhd
@@ -24,11 +24,19 @@ SIGNAL signal_hold_count : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL signal_receiving : STD_LOGIC;
SIGNAL signal_reset : STD_LOGIC;
SIGNAL signal_hold : STD_LOGIC;
+SIGNAL signal_crc_check : STD_LOGIC;
SIGNAL signal_data_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL signal_readBuffer : STD_LOGIC;
SIGNAL signal_crc : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL signal_shifter : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL crc_valid : STD_LOGIC;
+SIGNAL signal_frame_counter_length : STD_LOGIC_VECTOR(11 DOWNTO 0);
+SIGNAL signal_frame_current_length : STD_LOGIC_VECTOR(11 DOWNTO 0);
+SIGNAL signal_frame_register_length : STD_LOGIC_VECTOR(11 DOWNTO 0);
+SIGNAL signal_next_length : STD_LOGIC;
+
+
+
COMPONENT inputProcessor_stateController IS
PORT (
@@ -40,7 +48,8 @@ SIGNAL crc_valid : STD_LOGIC;
hold_count : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
receiving : OUT STD_LOGIC; -- HIGH if currently in receiving state; will act as enable signal for other modules
reset : OUT STD_LOGIC; -- HIGH if transitioned into IDLE state; resets all components for next frame
- hold : OUT STD_LOGIC-- HIGH if transitioned into HOLD state; must remain in state until hold_count = 12
+ hold : OUT STD_LOGIC;-- HIGH if transitioned into HOLD state; must remain in state until hold_count = 12
+ crc_check : OUT STD_LOGIC
);
END COMPONENT;
@@ -65,13 +74,11 @@ SIGNAL crc_valid : STD_LOGIC;
END COMPONENT;
COMPONENT crcChecker IS
- PORT (
- Resetx : IN STD_LOGIC;
- Clock : IN STD_LOGIC;
- compute_enable : IN STD_LOGIC;
- u4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- CRC_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
- );
+ PORT ( aclr : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ compute_enable : IN STD_LOGIC;
+ u4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ CRC_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END COMPONENT;
COMPONENT frameCounter IS
@@ -87,17 +94,56 @@ SIGNAL crc_valid : STD_LOGIC;
enable : IN STD_LOGIC;
count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
+
+ COMPONENT countdown_stateController IS
+ PORT ( aclr : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ begin_count : IN STD_LOGIC;
+ frame_length : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+ counting : OUT STD_LOGIC;
+ next_length : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT register12bit IS
+ PORT
+ (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ enable : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT lengthBuffer IS
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+ );
+ END COMPONENT;
+
BEGIN
- Stage1: inputProcessor_stateController PORT MAP (aclr, clk50, signal_frame_start, data_in_valid, crc_valid, signal_hold_count, signal_receiving, signal_reset, signal_hold);
+ Stage1: inputProcessor_stateController PORT MAP (aclr, clk25, signal_frame_start, data_in_valid, crc_valid, signal_hold_count, signal_receiving, signal_reset, signal_hold, signal_crc_check);
Stage2: sfdChecker PORT MAP (aclr OR signal_reset, clk25, data_in_valid, data_in, signal_frame_start);
Stage3: frameBuffer PORT MAP (aclr OR signal_reset, clk25, clk50, '1', signal_receiving, data_in, signal_data_out);
Stage4: crcChecker PORT MAP (aclr OR signal_reset, clk25, signal_receiving, data_in, signal_crc);
- Stage5: frameCounter PORT MAP (aclr OR signal_reset, clk25, signal_receiving, frame_length);
+ Stage5: frameCounter PORT MAP (aclr OR signal_reset, clk25, signal_receiving, signal_frame_counter_length);
Stage6: holdCounter PORT MAP (aclr OR signal_reset, clk25, signal_hold, signal_hold_count);
Stage7: data_out <= signal_data_out;
- Stage8:
+ Stage8: countdown_stateController PORT MAP (aclr OR signal_reset, clk50, crc_valid, signal_frame_register_length, data_out_valid, signal_next_length);
+ Stage9: register12bit PORT MAP (aclr OR signal_reset, clk50, signal_frame_current_length, signal_next_length, signal_frame_register_length);
+ Stage10: lengthBuffer PORT MAP (aclr OR signal_reset, signal_frame_counter_length, clk50, signal_next_length, clk25, signal_crc_check, signal_frame_current_length);
+
+
receive_state <= signal_receiving;
hold_state <= signal_hold;
reset_state <= signal_reset;
@@ -107,4 +153,8 @@ BEGIN
crc_valid <= '1' WHEN (signal_shifter XOR signal_crc) = "11111111111111111111111111111111" ELSE '0';
crc <= crc_valid;
+
+ frame_length <= signal_frame_current_length;
+
+
END subsystem_level_design;
diff --git a/inputProcessor_stateController.vhd b/inputProcessor_stateController.vhd
index d4f014d..743c7c4 100755
--- a/inputProcessor_stateController.vhd
+++ b/inputProcessor_stateController.vhd
@@ -12,7 +12,8 @@ ENTITY inputProcessor_stateController IS
hold_count : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
receiving : OUT STD_LOGIC; -- HIGH if currently in receiving state; will act as enable signal for other modules
reset : OUT STD_LOGIC; -- HIGH if transitioned into IDLE state; resets all components for next frame
- hold : OUT STD_LOGIC-- HIGH if transitioned into HOLD state; must remain in state until hold_count = 12
+ hold : OUT STD_LOGIC;-- HIGH if transitioned into HOLD state; must remain in state until hold_count = 12
+ crc_check : OUT STD_LOGIC
);
END inputProcessor_stateController;
@@ -34,7 +35,7 @@ BEGIN
END PROCESS;
-- Next State Logic
- PROCESS (inputProcessor_currentState, frame_start, frame_valid, hold_count)
+ PROCESS (inputProcessor_currentState, frame_start, frame_valid, hold_count, crc_valid)
BEGIN
CASE inputProcessor_currentState IS
WHEN IDLE_STATE =>
@@ -65,9 +66,13 @@ BEGIN
receiving <= '0';
reset <= '0';
hold <= '0';
+ crc_check <= '0';
IF inputProcessor_currentState = RECEIVING_STATE THEN receiving <= '1';
ELSE receiving <= '0';
END IF;
+ IF inputProcessor_currentState = CRC_CHECK_STATE THEN crc_check <= '1';
+ ELSE crc_check <= '0';
+ END IF;
IF inputProcessor_currentState = RESET_STATE THEN reset <= '1';
ELSE reset <= '0';
END IF;
diff --git a/lengthBuffer.cmp b/lengthBuffer.cmp
new file mode 100755
index 0000000..192c840
--- /dev/null
+++ b/lengthBuffer.cmp
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component lengthBuffer
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+ );
+end component;
diff --git a/lengthBuffer.qip b/lengthBuffer.qip
new file mode 100755
index 0000000..b27a135
--- /dev/null
+++ b/lengthBuffer.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lengthBuffer.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lengthBuffer.cmp"]
diff --git a/lengthBuffer.vhd b/lengthBuffer.vhd
new file mode 100755
index 0000000..adfb025
--- /dev/null
+++ b/lengthBuffer.vhd
@@ -0,0 +1,189 @@
+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo
+
+-- ============================================================
+-- File Name: lengthBuffer.vhd
+-- Megafunction Name(s):
+-- dcfifo
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY lengthBuffer IS
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+ );
+END lengthBuffer;
+
+
+ARCHITECTURE SYN OF lengthbuffer IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
+
+
+
+ COMPONENT dcfifo
+ GENERIC (
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ rdsync_delaypipe : NATURAL;
+ underflow_checking : STRING;
+ use_eab : STRING;
+ write_aclr_synch : STRING;
+ wrsync_delaypipe : NATURAL
+ );
+ PORT (
+ wrclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ rdclk : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (11 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ q <= sub_wire0(11 DOWNTO 0);
+
+ dcfifo_component : dcfifo
+ GENERIC MAP (
+ intended_device_family => "Cyclone II",
+ lpm_numwords => 1024,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo",
+ lpm_width => 12,
+ lpm_widthu => 10,
+ overflow_checking => "ON",
+ rdsync_delaypipe => 4,
+ underflow_checking => "ON",
+ use_eab => "ON",
+ write_aclr_synch => "OFF",
+ wrsync_delaypipe => 4
+ )
+ PORT MAP (
+ wrclk => wrclk,
+ rdreq => rdreq,
+ aclr => aclr,
+ rdclk => rdclk,
+ wrreq => wrreq,
+ data => data,
+ q => sub_wire0
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "12"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "12"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL data[11..0]
+-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q[11..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
+-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lengthBuffer.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lengthBuffer.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lengthBuffer.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lengthBuffer.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lengthBuffer_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lengthBuffer_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lengthBuffer_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/lengthBuffer_wave0.jpg b/lengthBuffer_wave0.jpg
new file mode 100755
index 0000000..c281730
Binary files /dev/null and b/lengthBuffer_wave0.jpg differ
diff --git a/lengthBuffer_waveforms.html b/lengthBuffer_waveforms.html
new file mode 100755
index 0000000..e0f358a
--- /dev/null
+++ b/lengthBuffer_waveforms.html
@@ -0,0 +1,13 @@
+
+
+Sample Waveforms for "lengthBuffer.vhd"
+
+
+Sample behavioral waveforms for design file "lengthBuffer.vhd"
+The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "lengthBuffer.vhd". The design "lengthBuffer.vhd" has a depth of 1024 words of 12 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.
+
+Fig. 1 : Wave showing read and write operation.
+The above waveform shows the behavior of the design under normal read and write conditions with aclr .
+
+
+
diff --git a/receive.qsf b/receive.qsf
index 4f89844..6860f72 100644
--- a/receive.qsf
+++ b/receive.qsf
@@ -38,7 +38,7 @@
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F484C6
-set_global_assignment -name TOP_LEVEL_ENTITY countdown_stateController
+set_global_assignment -name TOP_LEVEL_ENTITY inputProcessor
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:09:10 OCTOBER 31, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
@@ -75,15 +75,17 @@ set_global_assignment -name QIP_FILE shiftReg2bit.qip
set_global_assignment -name VECTOR_WAVEFORM_FILE crcChecker_test.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE inputProcessorTest.vwf
set_global_assignment -name FMAX_REQUIREMENT "25 MHz" -section_id "Clock 25"
+set_instance_assignment -name CLOCK_SETTINGS "Clock 25" -to clk25
set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id "Clock 50"
+set_instance_assignment -name CLOCK_SETTINGS "Clock 50" -to clk50
set_global_assignment -name VHDL_FILE countdown_stateController.vhd
set_global_assignment -name QIP_FILE countdownCounter.qip
+set_global_assignment -name VECTOR_WAVEFORM_FILE countdown_stateController_test.vwf
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE countdown_stateController_test.vwf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_instance_assignment -name CLOCK_SETTINGS "Clock 25" -to clk25
-set_instance_assignment -name CLOCK_SETTINGS "Clock 50" -to clk50
-set_global_assignment -name VECTOR_WAVEFORM_FILE countdown_stateController_test.vwf
-set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE countdown_stateController_test.vwf
+set_global_assignment -name QIP_FILE register12bit.qip
+set_global_assignment -name QIP_FILE lengthBuffer.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/receive.vhd b/receive.vhd
old mode 100644
new mode 100755
index 1ab232a..2691b96
--- a/receive.vhd
+++ b/receive.vhd
@@ -1,74 +1,33 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-USE ieee.numeric_std.all;
-
-ENTITY receive IS
- PORT (
- aclr : IN STD_LOGIC;
- hold : IN STD_LOGIC;
- clk25 : IN STD_LOGIC;
- clk50 : IN STD_LOGIC;
- data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- data_in_valid : IN STD_LOGIC;
- data_out_valid : OUT STD_LOGIC;
- data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- frame_length_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
-END receive;
-
-ARCHITECTURE high_level_design OF receive IS
-SIGNAL signal_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL signal_data_valid : STD_LOGIC;
-SIGNAL signal_crc_complete : STD_LOGIC;
-SIGNAL signal_frame_length : STD_LOGIC_VECTOR(11 DOWNTO 0);
-
- COMPONENT inputProcessor
- PORT (
- aclr : IN STD_LOGIC;
- clk25 : IN STD_LOGIC;
- clk50 : IN STD_LOGIC;
- data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- data_in_valid : IN STD_LOGIC;
- data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- data_out_valid: out std_logic;
- crc : OUT STD_LOGIC;
- frame_length : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
- ); -- Max frame size is 1542 bytes
- END COMPONENT;
-
- COMPONENT forward_interface IS PORT (
- aclr :in std_logic;
- clk :in std_logic;
- hold :in std_logic;
- data_in_valid :in std_logic;
- data_out_valid :out std_logic;
- data_in :in std_logic_vector (7 downto 0);
- data_out :out std_logic_vector (7 downto 0);
- frame_length_in :in std_logic_vector (11 downto 0);
- frame_length_out :out std_logic_vector (11 downto 0)
- );
- END COMPONENT;
-BEGIN
-
- Stage0: inputProcessor PORT MAP (
- aclr,
- clk25,
- clk50,
- data_in,
- data_in_valid,
- signal_data,signal_data_valid,
- signal_crc_complete,
- signal_frame_length
- );
- Stage1: forward_interface PORT MAP (
- aclr => aclr,
- clk => clk50,
- hold => hold,
- data_in_valid => signal_data_valid,
- data_out_valid => data_out_valid,
- data_in => signal_data,
- data_out => data_out,
- frame_length_in => signal_frame_length,
- frame_length_out => frame_length_out
- );
-
-END high_level_design;
\ No newline at end of file
+--LIBRARY ieee;
+--USE ieee.std_logic_1164.all;
+--USE ieee.numeric_std.all;
+--
+--ENTITY receive IS
+-- PORT (
+-- aclr : IN STD_LOGIC;
+-- clk25 : IN STD_LOGIC;
+-- clk50 : IN STD_LOGIC;
+-- data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- data_in_valid : IN STD_LOGIC;
+-- hold : IN STD_LOGIC;
+-- );
+--END receive;
+--
+-- COMPONENT inputProcessor IS
+-- PORT ( aclr : IN STD_LOGIC;
+-- clk25 : IN STD_LOGIC;
+-- clk50 : IN STD_LOGIC;
+-- data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- data_in_valid : IN STD_LOGIC;
+-- data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+-- data_out_valid : OUT STD_LOGIC;
+-- crc : OUT STD_LOGIC;
+-- frame_length : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- Max frame size is 1542 bytes
+-- receive_state : OUT STD_LOGIC;
+-- hold_state : OUT STD_LOGIC;
+-- reset_state : OUT STD_LOGIC);
+-- END COMPONENT;
+--
+--ARCHITECTURE rcv OF receive IS
+--
+--END rcv
\ No newline at end of file
diff --git a/register12bit.cmp b/register12bit.cmp
new file mode 100755
index 0000000..e3d148d
--- /dev/null
+++ b/register12bit.cmp
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component register12bit
+ PORT
+ (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ enable : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+ );
+end component;
diff --git a/register12bit.qip b/register12bit.qip
new file mode 100755
index 0000000..f01396c
--- /dev/null
+++ b/register12bit.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "register12bit.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "register12bit.cmp"]
diff --git a/register12bit.vhd b/register12bit.vhd
new file mode 100755
index 0000000..8dcd832
--- /dev/null
+++ b/register12bit.vhd
@@ -0,0 +1,132 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff
+
+-- ============================================================
+-- File Name: register12bit.vhd
+-- Megafunction Name(s):
+-- lpm_ff
+--
+-- Simulation Library Files(s):
+-- lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY register12bit IS
+ PORT
+ (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+ enable : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+ );
+END register12bit;
+
+
+ARCHITECTURE SYN OF register12bit IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
+
+
+
+ COMPONENT lpm_ff
+ GENERIC (
+ lpm_fftype : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL
+ );
+ PORT (
+ enable : IN STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
+ data : IN STD_LOGIC_VECTOR (11 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ q <= sub_wire0(11 DOWNTO 0);
+
+ lpm_ff_component : lpm_ff
+ GENERIC MAP (
+ lpm_fftype => "DFF",
+ lpm_type => "LPM_FF",
+ lpm_width => 12
+ )
+ PORT MAP (
+ enable => enable,
+ aclr => aclr,
+ clock => clock,
+ data => data,
+ q => sub_wire0
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "12"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL data[11..0]
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
+-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q[11..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
+-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL register12bit.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL register12bit.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL register12bit.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL register12bit.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL register12bit_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm