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Fixed component end statements to ignore case

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1 parent 59567ba commit b0ba35d988d653291aa1bc019aa17b6b2863f218 @yangsu committed Nov 13, 2012
Showing with 1 addition and 1 deletion.
  1. +1 −1 Syntaxes/VHDL.tmLanguage
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@@ -523,7 +523,7 @@
<key>end</key>
<string>(?x)
# The word end $1
- \b((?:end))\s+
+ \b((?i:end))\s+
# The word component $3 or illegal word $4
(((?i:component\b))|(.+?))(?=\s*|;)

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