{"payload":{"header_redesign_enabled":false,"results":[{"id":"241698592","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"yasnakateb/Blinky","hl_trunc_description":"💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":241698592,"name":"Blinky","owner_id":37741028,"owner_login":"yasnakateb","updated_at":"2020-03-10T12:18:40.455Z","has_issues":true}},"sponsorable":false,"topics":["fpga","verilog","verilog-hdl","altera-fpga"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":58,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ayasnakateb%252FBlinky%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/yasnakateb/Blinky/star":{"post":"W5Yxawo3-jIiWGfT1hmfP4XSVSqbJGRrrfUxTIn0lzwhGTMRGhWJlbnwljy0nq9CsrqCxHC49CvMohfBNoxoOw"},"/yasnakateb/Blinky/unstar":{"post":"sk0Q_ugXZbUFOsAOeK1yIYuz7BLmeyqz0kVk1581PWWvEMLu1NGqOQM6tcOXW_wpxHSVFB8XhfwNGN9ACq4kAg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"Vdcx1NdLOlPNrjQPT9dmWlbhjDnscZs4ILwjpZwmmadg2Ppo2HxSVsoolPfAKXj_EkW6OfzvU3cyVGGFkt57Pg"}}},"title":"Repository search results"}