{"payload":{"header_redesign_enabled":false,"results":[{"id":"330659655","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"yenmeng/IC_Design","hl_trunc_description":null,"language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":330659655,"name":"IC_Design","owner_id":44222693,"owner_login":"yenmeng","updated_at":"2021-01-18T12:38:38.481Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":53,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ayenmeng%252FIC_Design%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/yenmeng/IC_Design/star":{"post":"WqNXJMyBEJ-pQE8gj4sBdD868vADS2be71h-71f3BlNvnwY9yyF2eLVDIH6xffN6p8TqI61iBIFl73X9pW4ZPQ"},"/yenmeng/IC_Design/unstar":{"post":"781-ilMRvo683PyaIiUPFVnQPaYhVQfZ1Wep--KoweRrpx-Sv0l3_14F86ElXP2LKOe81oclOdYXrgQoeXVvMw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"W930O7jkcuwvvyxXF0iaaUkhogYTU-UICJkjTTbaHDD0rg0F4K9L1yCQRgfbIqeLXKx89bO4KMrpqFoMBJG4LA"}}},"title":"Repository search results"}