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Commits on Mar 20, 2014
@espindola espindola Remove unused options from test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204401 91177308-0d34-0410-b5e6-96231b3b80d8
e316e00
@espindola espindola Remove llvm-mc's disable-cfi option.
It was dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204404 91177308-0d34-0410-b5e6-96231b3b80d8
a591368
@espindola espindola Convert CodeGen test into a more specific MC test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204406 91177308-0d34-0410-b5e6-96231b3b80d8
f59d05c
Greg Fitzgerald llvm-objdump output hex to match binutils' objdump
Patch by Ted Woodward

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204409 91177308-0d34-0410-b5e6-96231b3b80d8
aff0ab4
@wmzhao wmzhao Fix PR19136: [ARM] Fix Folding SP Update into vpush/vpop
Sicne MBB->computeRegisterLivenes() returns Dead for sub regs like s0,
d0 is used in vpop instead of updating sp, which causes s0 dead before
its use.

This patch checks the liveness of each subreg to make sure the reg is
actually dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204411 91177308-0d34-0410-b5e6-96231b3b80d8
4eb2d22
@espindola espindola Convert another CodeGen test into a MC test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204412 91177308-0d34-0410-b5e6-96231b3b80d8
aeb12e9
Commits on Mar 21, 2014
@espindola espindola Port test to cfi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204416 91177308-0d34-0410-b5e6-96231b3b80d8
fab1a40
@rui314 rui314 Object/COFF: Support large relocation table.
NumberOfRelocations field in COFF section table is only 16-bit wide. If an
object has more than 65535 relocations, the number of relocations is stored
to VirtualAddress field in the first relocation field, and a special flag
(IMAGE_SCN_LNK_NRELOC_OVFL) is set to Characteristics field.

In test we cheated a bit. I made up a test file so that it has
IMAGE_SCN_LNK_NRELOC_OVFL flag but the number of relocations is much smaller
than 65535. This is to avoid checking in a large test file just to test a
file with many relocations.

Differential Revision: http://llvm-reviews.chandlerc.com/D3139

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204418 91177308-0d34-0410-b5e6-96231b3b80d8
9999526
@espindola espindola Convert a CodeGen test into a MC test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204421 91177308-0d34-0410-b5e6-96231b3b80d8
5b460ed
@akyrtzi akyrtzi [Support] Make sure sys::fs::remove can remove symbolic links and mak…
…e sure LockFileManager can handle a symbolic link that points nowhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204422 91177308-0d34-0410-b5e6-96231b3b80d8
2c8cd9a
Kevin Qin [AArch64] Remove .data_region directive from AArch64.
.data_region is only used in Darwin, so it shouldn't be generated
for other OS. Currently AArch64 doesn't support darwin yet, so
I removed it from AArch64. When Darwin is supported someday, we can
add it back and associate it with Darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204424 91177308-0d34-0410-b5e6-96231b3b80d8
287cc35
Kevin Qin Fix an assertion caused by using inline asm with indirect register in…
…puts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204425 91177308-0d34-0410-b5e6-96231b3b80d8
c53b3db
@akyrtzi akyrtzi [Support] Make sure LockFileManager works correctly with relative paths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204426 91177308-0d34-0410-b5e6-96231b3b80d8
fb307be
Jiangning Liu This reverts commit r203762, "ARM: support emission of complex SO exp…
…ressions".

The commit r203762 introduced silent failure for complext SO expression, and it's even worse than compiler crash.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204427 91177308-0d34-0410-b5e6-96231b3b80d8
705e53e
@compnerd compnerd MCParser: add an assertion
Add an assertion that the section is not NULL.  Potential NULL pointer
dereference identified by clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204429 91177308-0d34-0410-b5e6-96231b3b80d8
6785cf0
@ributzka ributzka [Constant Hoisting] Replace the MapVector with a separate Map and Vec…
…tor to keep track of constant candidates.

This simplifies working with the constant candidates and removes the tight
coupling between the map and the vector.

Related to <rdar://problem/16381500>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204431 91177308-0d34-0410-b5e6-96231b3b80d8
4cd2152
@ributzka ributzka [Constant Hoisting] Fix capitalization of function names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204432 91177308-0d34-0410-b5e6-96231b3b80d8
032dafd
@ributzka ributzka [Constant Hoisting] Change the algorithm to only track constants for …
…instructions.

Originally the algorithm would search for expensive constants and track their
users, which could be instructions and constant expressions. This change only
tracks the constants for instructions, but constant expressions are indirectly
covered too. If an operand is an constant expression, then we look through the
expression to find anny expensive constants.

The algorithm keep now track of the instruction and the operand index where the
constant is used. This allows more precise hoisting of constant materialization
code for PHI instructions, because we only hoist to the basic block of the
incoming operand. Before we had to find the idom of all PHI operands and hoist
the materialization code there.

This also makes updating of instructions easier. Before we had to keep track of
the original constant, find it in the instructions, and then replace it. Now we
can just simply update the operand.

Related to <rdar://problem/16381500>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204433 91177308-0d34-0410-b5e6-96231b3b80d8
8ebaf63
@ributzka ributzka [Constant Hoisting] Lazily compute the idom and cache the result.
Related to <rdar://problem/16381500>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204434 91177308-0d34-0410-b5e6-96231b3b80d8
337eb3a
@ributzka ributzka [Constant Hoisting] Make the constant materialization cost operand de…
…pendent

Extend the target hook to take also the operand index into account when
calculating the cost of the constant materialization.

Related to <rdar://problem/16381500>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204435 91177308-0d34-0410-b5e6-96231b3b80d8
d3cf783
Kevin Qin Fix test command line to avoid generating output file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204437 91177308-0d34-0410-b5e6-96231b3b80d8
fc029f2
@ributzka ributzka [RuntimeDyld] Allow processRelocationRef to process more than one rel…
…ocation entry at a time.

Some targets require more than one relocation entry to perform a relocation.
This change allows processRelocationRef to process more than one relocation
entry at a time by passing the relocation iterator itself instead of just
the relocation entry.

Related to <rdar://problem/16199095>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204439 91177308-0d34-0410-b5e6-96231b3b80d8
4923eea
Matheus Almeida [mips] Update namespace.
We should be using the llvm namespace and not an anonymous namespace
in a header file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204450 91177308-0d34-0410-b5e6-96231b3b80d8
d098630
Richard Sandiford [SystemZ] Add support for z196 float<->unsigned conversions
These complement the older float<->signed instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204451 91177308-0d34-0410-b5e6-96231b3b80d8
6b6889d
Richard Sandiford [SystemZ] Use "let Predicates =" for blocks of new instructions
...instead of a separate Requires for each one.  This style was already
used in some places and seems more compact.

No behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204452 91177308-0d34-0410-b5e6-96231b3b80d8
20115c6
@tstellarAMD tstellarAMD Sink: Don't sink static allocas from the entry block
CodeGen treats allocas outside the entry block as dynamically sized
stack objects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204473 91177308-0d34-0410-b5e6-96231b3b80d8
1b05bb2
@tstellarAMD tstellarAMD R600/SI: Use SGPR_(32|64) reg clases when lowering SI_ADDR64_RSRC
The SReg_(32|64) register classes contain special registers in addition
to the numbered SGPRs.  This can lead to machine verifier errors when
these register classes are used as sub-registers for SReg_128, since
SReg_128 only uses the numbered SGPRs.

Replacing SReg_(32|64) with SGPR_(32|64) fixes this problem, since
the SGPR_(32|64) register classes contain only numbered SGPRs.

Tests cases for this are comming in a later commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204474 91177308-0d34-0410-b5e6-96231b3b80d8
af4c7da
@tstellarAMD tstellarAMD R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204475 91177308-0d34-0410-b5e6-96231b3b80d8
1f1c049
@tstellarAMD tstellarAMD R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204476 91177308-0d34-0410-b5e6-96231b3b80d8
a1d28f6
@rengolin rengolin Add overall description, file comments, some structure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204479 91177308-0d34-0410-b5e6-96231b3b80d8
ec15d70
@dsandersimgtec dsandersimgtec [mips] Correct lowering of VECTOR_SHUFFLE to VSHF.
Summary:
VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
  <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
VSHF concatenates the vectors in a bitwise fashion:
  <0b00, 0b01> + <0b10, 0b11> ->
  0b0100       + 0b1110       -> 0b01001110
                                 <0b10, 0b11, 0b00, 0b01>
We must therefore swap the operands to get the correct result.

The test case that discovered the issue was MultiSource/Benchmarks/nbench.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3142

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204480 91177308-0d34-0410-b5e6-96231b3b80d8
e85dd7c
@espindola espindola Split out the MC part of this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204481 91177308-0d34-0410-b5e6-96231b3b80d8
6c22b04
@bogner bogner ProfileData: Introduce the InstrProfReader interface and a text reader
This introduces the ProfileData library and updates llvm-profdata to
use this library for reading profiles. InstrProfReader is an abstract
base class that will be subclassed for both the raw instrprof data
from compiler-rt and the efficient instrprof format that will be used
for PGO.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204482 91177308-0d34-0410-b5e6-96231b3b80d8
c0f3b72
@espindola espindola Remove redundant test.
The production of the .eh symbols is done from MC now and we already have tests
for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204483 91177308-0d34-0410-b5e6-96231b3b80d8
0b50368
@bogner bogner llvm-profdata: Implement show command
The `llvm-profdata show` command summarizes a profdata file's contents
in a human readable format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204485 91177308-0d34-0410-b5e6-96231b3b80d8
60bc906
Paul Robinson Refactor llvm/test/lit.cfg to use lit.util.which.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204486 91177308-0d34-0410-b5e6-96231b3b80d8
b9d6263
@espindola espindola Convert test to using cfi.
An unnamed global in llvm still produces a regular symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204488 91177308-0d34-0410-b5e6-96231b3b80d8
469198f
@bogner bogner ProfileData: Introduce InstrProfWriter using the naive text format
This isn't a format we'll want to write out in practice, but moving it
to the writer library simplifies llvm-profdata and isolates it from
further changes to the format.

This also allows us to update the tests to not rely on the text output
format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204489 91177308-0d34-0410-b5e6-96231b3b80d8
496d7f6
@espindola espindola Move codegen test over to MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204490 91177308-0d34-0410-b5e6-96231b3b80d8
3f687d3
@espindola espindola Remove redundant test.
This is tested from MC already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204491 91177308-0d34-0410-b5e6-96231b3b80d8
d38fea3
@arsenm arsenm R600/SI: Move instruction patterns to scalar versions.
Some of them also had the pattern on both, so this removes the
duplication.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204492 91177308-0d34-0410-b5e6-96231b3b80d8
55d17f4
@bogner bogner ProfileData: Avoid brace initialization, windows doesn't like it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204494 91177308-0d34-0410-b5e6-96231b3b80d8
c61e1f5
@dexonsmith dexonsmith InstrProf: Read raw binary profile in llvm-profdata
Read a raw binary profile that corresponds to a memory dump from the
runtime profile.

The test is a binary file generated from
cfe/trunk/test/Profile/c-general.c with the new compiler-rt runtime and
the matching text version of the input.  It includes instructions on how
to regenerate.

<rdar://problem/15950346>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204496 91177308-0d34-0410-b5e6-96231b3b80d8
ddfcb21
@bogner bogner ProfileData: Avoid double underscores in header guards
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204501 91177308-0d34-0410-b5e6-96231b3b80d8
218c7c8
@rosierm rosierm [AArch64] Add SchedRW lists to NEON instructions.
Previously, only regular AArch64 instructions were annotated with SchedRW lists.
This patch does the same for NEON enabling these instructions to be scheduled by
the MIScheduler. Additionally, store operations are now modeled and a few
SchedRW lists were updated for bug fixes (e.g. multiple def operands).

Reviewers: apazos, mcrosier, atrick
Patch by Dave Estes <cestes@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204505 91177308-0d34-0410-b5e6-96231b3b80d8
1eb67a4
David Blaikie DebugInfo: Omit DW_AT_addr_base from skeletal type units.
Type units have no addresses, so there's no need for DW_AT_addr_base.
This removes another relocation from every skeletal type unit and brings
LLVM's skeletal type units in line with GCC's (containing only
GNU_dwo_name (strp), comp_dir (strp), and GNU_pubnames (flag_present)).

Cary's got some ideas about using str_index in the .o file to reduce
those last two relocations (well, replace two relocations with one
relocation (pointing to the string index) and two indicies)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204506 91177308-0d34-0410-b5e6-96231b3b80d8
4d221b3
@ributzka ributzka [RuntimeDyld] clang-format files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204507 91177308-0d34-0410-b5e6-96231b3b80d8
b0e33fd
@ributzka ributzka [RuntimeDyld] Fix comment for previous commit (r204439)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204508 91177308-0d34-0410-b5e6-96231b3b80d8
56db3a9
@dexonsmith dexonsmith InstrProf: Actually detect bad headers
<rdar://problem/15950346>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204510 91177308-0d34-0410-b5e6-96231b3b80d8
ebaeaa9
@dexonsmith dexonsmith InstrProf: Detect magic numbers in a more scalable way
No functionality change.

<rdar://problem/15950346>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204511 91177308-0d34-0410-b5e6-96231b3b80d8
bb56c48
@dexonsmith dexonsmith InstrProf: Use move semantics with unique_ptr
<rdar://problem/15950346>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204512 91177308-0d34-0410-b5e6-96231b3b80d8
bc2740a
@dexonsmith dexonsmith InstrProf: Change magic number to have non-text characters
Include non-text characters in the magic number so that text files can't
match.

<rdar://problem/15950346>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204513 91177308-0d34-0410-b5e6-96231b3b80d8
813d0a2
@dexonsmith dexonsmith InstrProf: Move constructor to the header
Fixes 80-column violation at the same time.

<rdar://problem/15950346>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204516 91177308-0d34-0410-b5e6-96231b3b80d8
50f9696
@dexonsmith dexonsmith InstrProf: Cleanup binary profdata testcase
Cleanup the current binary testcase for profile data.

  - Rename it to something more specific.
  - Remove the text comparison.
  - Check the output of llvm-profdata show.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204518 91177308-0d34-0410-b5e6-96231b3b80d8
aa4135a
@akyrtzi akyrtzi [Support] Follow up to r204426, for LockFileManager, make the given p…
…ath absolute so relative paths are properly handled in both Windows and Unix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204520 91177308-0d34-0410-b5e6-96231b3b80d8
c1011e6
Manman Ren Register allocator: add condition to hoist a spill to outer loop.
We make sure a spill is not hoisted to a hotter outer loop by adding
a condition. Hoist a spill to outer loop if there are multiple dependents
(it can be beneficial if more than one dependents are hoisted) or
if DepSV (the hoisting source) is hotter than SV (the hoisting destination).

rdar://16268194


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204522 91177308-0d34-0410-b5e6-96231b3b80d8
8dbd561
@Arnaud-de-Grandmaison Arnaud-de-Grandmaison Remove some dead assignements found by scan-build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204526 91177308-0d34-0410-b5e6-96231b3b80d8
96c049d
@espindola espindola Fix the value computation in
sym_a:
sym_d = sym_a + 1

This is the smallest fix I was able to extract from what got reverted in
r204203.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204527 91177308-0d34-0410-b5e6-96231b3b80d8
a60f719
@adrian-prantl adrian-prantl Dwarf Debug: Remove some cargo-cult type uniquing. Scopes do not have
an ID, so this is a noop.
Thanks Manman for catching this!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204528 91177308-0d34-0410-b5e6-96231b3b80d8
0fb178b
@adrian-prantl adrian-prantl Delete stale comment. Thanks, Eric!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204530 91177308-0d34-0410-b5e6-96231b3b80d8
e25ab8e
Commits on Mar 22, 2014
@chapuni chapuni Suppress SupportTests.LockFileManagerTest on win32 for investigating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204533 91177308-0d34-0410-b5e6-96231b3b80d8
4696def
Andrea Di Biagio [DAG] Fix an assertion failure caused by an invalid cast in method 'B…
…uildVectorSDNode::isConstantSplat'

This patch renames method 'isConstantSplat' as 'getConstantSplatValue'
(mainly for consistency reasons), and rewrites its logic to ensure
that we always perform a legal 'cast<ConstantSDNode>'.

Added test shift-combine-crash.ll to verify that DAGCombiner no longer crashes with an assertion failure in the attempt to simplify a vector shift by a vector of all undef counts.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204536 91177308-0d34-0410-b5e6-96231b3b80d8
d47cb57
@ributzka ributzka [Constant Hoisting] Fix multiple entries for the same basic block in …
…PHI nodes.

A PHI node usually has only one value/basic block pair per incoming basic block.
In the case of a switch statement it is possible that a following PHI node may
have more than one such pair per incoming basic block. E.g.:
%0 = phi i64 [ 123456, %case2 ], [ 654321, %Entry ], [ 654321, %Entry ]
This is valid and the verfier doesn't complain, because both values are the
same.

Constant hoisting materializes the constant for each operand separately and the
value is still the same, but the variable names have changed. As a result the
verfier can't recognize anymore that they are the same value and complains.

This fix adds special update code for PHI node in constant hoisting to prevent
this corner case.

This fixes <rdar://problem/16394449>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204537 91177308-0d34-0410-b5e6-96231b3b80d8
5cfc91c
@ributzka ributzka [Constant Hoisting] Erase dead cast instructions.
The cleanup code that removes dead cast instructions only removed them from the
basic block, but didn't delete them. This fix erases them now too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204538 91177308-0d34-0410-b5e6-96231b3b80d8
62f4b48
@chapuni chapuni llvm-profdata: Avoid F_Text in "merge" for now, since "llvm-profdata …
…show" is confused with CRLF.

FIXME: line_iterator should be tolerant of CR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204540 91177308-0d34-0410-b5e6-96231b3b80d8
4e669c9
@hfinkel hfinkel [TableGen] Don't assert, produce an error, when an instruction has to…
…o few operands

When an instruction's operand list does not have a sufficient number of
operands to match with all of the variables that contribute to its
encoding, instead of asserting inside a call to getSubOperandNumber, produce an
informative error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204542 91177308-0d34-0410-b5e6-96231b3b80d8
f20a219
@hfinkel hfinkel [PowerPC] Fix the VSX v2f64 return register
v2f64 values, like other 128-bit values, are returned under VSX in register
vs34 (Altivec register v2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204543 91177308-0d34-0410-b5e6-96231b3b80d8
0d277ab
@compnerd compnerd ARM IAS: properly handle function entries in .thumb
When a label is parsed, check if there is type information available for the
label.  If so, check if the symbol is a function.  If the symbol is a function
and we are in thumb mode and no explicit thumb_func has been emitted, adjust the
symbol data to indicate that the function definition is a thumb function.

The application of this inferencing is improved value handling in the object
file (the required thumb bit is set on symbols which are thumb functions).  It
also helps improve compatibility with binutils.

The one complication that arises from this handling is the MCAsmStreamer.  The
default implementation of getOrCreateSymbolData in MCStreamer does not support
tracking the symbol data.  In order to support the semantics of thumb functions,
track symbol data in assembly streamer.  Although O(n) in number of labels in
the TU, this is already done in various other streamers and as such the memory
overhead is not a practical concern in this scenario.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204544 91177308-0d34-0410-b5e6-96231b3b80d8
7afe000
Craig Topper Prune includes in ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204548 91177308-0d34-0410-b5e6-96231b3b80d8
ac732eb
@bogner bogner llvm-profdata: Don't pipe stderr into show for the tests
Some text shows up on stderr when using guard malloc, and this test
was trying to treat that as input to llvm-profdata show. There's no
reason to pipe stderr into show at all here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204549 91177308-0d34-0410-b5e6-96231b3b80d8
f0e92a8
Commits on Mar 23, 2014
@chapuni chapuni llvm-profdata doesn't require LLVMCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204552 91177308-0d34-0410-b5e6-96231b3b80d8
3880348
@chapuni chapuni [CMake] LLVMProfileData: No need to add LINK_LIBS here. LLVMBuild sho…
…uld do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204553 91177308-0d34-0410-b5e6-96231b3b80d8
c8ca832
@espindola espindola Propagate types from symbol to aliases.
This is similar, but not identical to what gas does. The logic in MC is to just
compute the symbol table after parsing the entire file. GAS is mixed, given

.type b, @object
a = b
b:
.type b, @function

It will propagate the change and make 'a' a function. Given

.type b, @object
b:
a = b
.type b, @function

the type of 'a' is still object.

Since we do the computation in the end, we produce a function in both cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204555 91177308-0d34-0410-b5e6-96231b3b80d8
4ff2dad
@dexonsmith dexonsmith InstrProf: Check pointer size in raw profile
Since the profile can come from 32-bit machines, we need to check the
pointer size.  Change the magic number to facilitate this.

Adds tests for reading 32-bit and 64-bit binaries (both big- and
little-endian).  The tests write a binary using printf in RUN lines
(like raw-magic-but-no-header.test).  Assuming the bots don't complain,
this seems like a better way forward for testing RawInstrProfReader than
committing binary files.

<rdar://problem/16400648>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204557 91177308-0d34-0410-b5e6-96231b3b80d8
0695b20
@lhames lhames Revert r204076 for now - it caused significant regressions in a numbe…
…r of

benchmarks.

<rdar://problem/16368461>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204558 91177308-0d34-0410-b5e6-96231b3b80d8
fb51aac
@hfinkel hfinkel [PowerPC] Make use of VSX f64 <-> i64 conversion instructions
When VSX is available, these instructions should be used in preference to the
older variants that only have access to the scalar floating-point registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204559 91177308-0d34-0410-b5e6-96231b3b80d8
b6cbecd
@nunoplopes nunoplopes remove a bunch of unused private methods
found with a smarter version of -Wunused-member-function that I'm playwing with.
Appologies in advance if I removed someone's WIP code.

 include/llvm/CodeGen/MachineSSAUpdater.h            |    1 
 include/llvm/IR/DebugInfo.h                         |    3 
 lib/CodeGen/MachineSSAUpdater.cpp                   |   10 --
 lib/CodeGen/PostRASchedulerList.cpp                 |    1 
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp    |   10 --
 lib/IR/DebugInfo.cpp                                |   12 --
 lib/MC/MCAsmStreamer.cpp                            |    2 
 lib/Support/YAMLParser.cpp                          |   39 ---------
 lib/TableGen/TGParser.cpp                           |   16 ---
 lib/TableGen/TGParser.h                             |    1 
 lib/Target/AArch64/AArch64TargetTransformInfo.cpp   |    9 --
 lib/Target/ARM/ARMCodeEmitter.cpp                   |   12 --
 lib/Target/ARM/ARMFastISel.cpp                      |   84 --------------------
 lib/Target/Mips/MipsCodeEmitter.cpp                 |   11 --
 lib/Target/Mips/MipsConstantIslandPass.cpp          |   12 --
 lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp              |   21 -----
 lib/Target/NVPTX/NVPTXISelDAGToDAG.h                |    2 
 lib/Target/PowerPC/PPCFastISel.cpp                  |    1 
 lib/Transforms/Instrumentation/AddressSanitizer.cpp |    2 
 lib/Transforms/Instrumentation/BoundsChecking.cpp   |    2 
 lib/Transforms/Instrumentation/MemorySanitizer.cpp  |    1 
 lib/Transforms/Scalar/LoopIdiomRecognize.cpp        |    8 -
 lib/Transforms/Scalar/SCCP.cpp                      |    1 
 utils/TableGen/CodeEmitterGen.cpp                   |    2 
 24 files changed, 2 insertions(+), 261 deletions(-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204560 91177308-0d34-0410-b5e6-96231b3b80d8
2ca6265
@majnemer majnemer WinCOFF: Add support for -ffunction-sections
This is a pretty straight forward translation for COFF, we just need to
stick the function in a COMDAT section marked as
IMAGE_COMDAT_SELECT_NODUPLICATES.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204565 91177308-0d34-0410-b5e6-96231b3b80d8
77df516
@bogner bogner llvm-profdata: Use Format.h instead of handrolling a formatter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204571 91177308-0d34-0410-b5e6-96231b3b80d8
5ecdfc1
@bogner bogner llvm-profdata: Check for bad data in the show command
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204573 91177308-0d34-0410-b5e6-96231b3b80d8
f5afb78
@Arnaud-de-Grandmaison Arnaud-de-Grandmaison ARM: no need to update SplatBits as it is not used
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204575 91177308-0d34-0410-b5e6-96231b3b80d8
b0c513b
@chapuni chapuni SupportTests.LockFileManagerTest: Add assertions for Win32.
  - create_link doesn't work for nonexistent file.
  - remove cannot remove working directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204579 91177308-0d34-0410-b5e6-96231b3b80d8
12da52f
Commits on Mar 24, 2014
@dexonsmith dexonsmith InstrProf: Silence spurious warnings in GCC 4.8
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204580 91177308-0d34-0410-b5e6-96231b3b80d8
b83e788
@espindola espindola Propagate section from base to derived symbol.
We were already propagating the section in

a = b

With this patch we also propagate it for

a = b + 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204581 91177308-0d34-0410-b5e6-96231b3b80d8
0bce334
@espindola espindola Add back tests that were reverted in r204203.
They pass again with the fix in r204581.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204582 91177308-0d34-0410-b5e6-96231b3b80d8
0259b8e
@karthikthecool karthikthecool Allow constant folding of ceil function whenever feasible
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204583 91177308-0d34-0410-b5e6-96231b3b80d8
07707e8
@espindola espindola Teach llvm-readobj to print human friendly description of reserved se…
…ctions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204584 91177308-0d34-0410-b5e6-96231b3b80d8
2236f93
@hfinkel hfinkel [PowerPC] Update comment re: VSX copy-instruction selection
I've done some experimentation with this, and it looks like using the
lower-latency (but lower throughput) copy instruction is essentially always the
right thing to do.

My assumption is that, in order to be relatively sure that the higher-latency
copy will increase throughput, we'd want to have it unlikely to be in-flight
with its use. On the P7, the global completion table (GCT) can hold a maximum
of 120 instructions, shared among all active threads (up to 4), giving 30
instructions per thread.  So specifically, I'd require at least that many
instructions between the copy and the use before the high-latency variant is
used.

Trying this, however, over the entire test suite resulted in zero cases where
the high-latency form would be preferable. This may be a consequence of the
fact that the scheduler views copies as free, and so they tend to end up close
to their uses. For this experiment I created a function:

  unsigned chooseVSXCopy(MachineBasicBlock &MBB,
                         MachineBasicBlock::iterator I,
                         unsigned DestReg, unsigned SrcReg,
                         unsigned StartDist = 1,
                         unsigned Depth = 3) const;

with an implementation like:

  if (!Depth)
    return PPC::XXLOR;

  const unsigned MaxDist = 30;
  unsigned Dist = StartDist;
  for (auto J = I, JE = MBB.end(); J != JE && Dist <= MaxDist; ++J) {
    if (J->isTransient() && !J->isCopy())
      continue;

    if (J->isCall() || J->isReturn() || J->readsRegister(DestReg, TRI))
      return PPC::XXLOR;

    ++Dist;
  }

  // We've exceeded the required distance for the high-latency form, use it.
  if (Dist > MaxDist)
    return PPC::XVCPSGNDP;

  // If this is only an exit block, use the low-latency form.
  if (MBB.succ_empty())
    return PPC::XXLOR;

  // We've reached the end of the block, check the successor blocks (up to some
  // depth), and use the high-latency form if that is okay with all successors.
  for (auto J = MBB.succ_begin(), JE = MBB.succ_end(); J != JE; ++J) {
    if (chooseVSXCopy(**J, (*J)->begin(), DestReg, SrcReg,
                      Dist, --Depth) == PPC::XXLOR)
      return PPC::XXLOR;
  }

  // All of our successor blocks seem okay with the high-latency variant, so
  // we'll use it.
  return PPC::XVCPSGNDP;

and then changed the copy opcode selection from:
    Opc = PPC::XXLOR;
to:
    Opc = chooseVSXCopy(MBB, std::next(I), DestReg, SrcReg);

In conclusion, I'm removing the FIXME from the comment, because I believe that
there is, at least absent other examples, nothing to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204591 91177308-0d34-0410-b5e6-96231b3b80d8
7244814
@hfinkel hfinkel [PowerPC] Don't schedule VSX copy legalization unless VSX is enabled
There is no need to schedule this extra pass if it will have nothing to do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204594 91177308-0d34-0410-b5e6-96231b3b80d8
2393d22
@rengolin rengolin Update release notes with EHABI current behaviour
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204598 91177308-0d34-0410-b5e6-96231b3b80d8
72270aa
@jholewinski jholewinski [NVPTX] Add isel patterns for addrspacecast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204600 91177308-0d34-0410-b5e6-96231b3b80d8
b8cb709
@dsandersimgtec dsandersimgtec [mips] Implement shorthand add / sub forms for MIPS.
Summary:
- If only two registers are passed to a three-register operation, then the
  first argument is both source and destination register.

- If a non-register is passed as the last argument, generate the immediate
  version of the instruction.

Also mark DADD commutative and add scheduling information (to the generic
scheduler), and implement DSUB.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

CC: theraven

Differential Revision: http://llvm-reviews.chandlerc.com/D3148

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204605 91177308-0d34-0410-b5e6-96231b3b80d8
67db74e
@hfinkel hfinkel [PowerPC] Mark many instructions as commutative
I'm under the impression that we used to infer the isCommutable flag from the
instruction-associated pattern. Regardless, we don't seem to do this (at least
by default) any more. I've gone through all of our instruction definitions, and
marked as commutative all of those that should be trivial to commute (by
exchanging the first two operands). There has been special code for the RL*
instructions, and that's not changed.

Before this change, we had the following commutative instructions:

 RLDIMI
 RLDIMIo
 RLWIMI
 RLWIMI8
 RLWIMI8o
 RLWIMIo
 XSADDDP
 XSMULDP
 XVADDDP
 XVADDSP
 XVMULDP
 XVMULSP

After:

 ADD4
 ADD4o
 ADD8
 ADD8o
 ADDC
 ADDC8
 ADDC8o
 ADDCo
 ADDE
 ADDE8
 ADDE8o
 ADDEo
 AND
 AND8
 AND8o
 ANDo
 CRAND
 CREQV
 CRNAND
 CRNOR
 CROR
 CRXOR
 EQV
 EQV8
 EQV8o
 EQVo
 FADD
 FADDS
 FADDSo
 FADDo
 FMADD
 FMADDS
 FMADDSo
 FMADDo
 FMSUB
 FMSUBS
 FMSUBSo
 FMSUBo
 FMUL
 FMULS
 FMULSo
 FMULo
 FNMADD
 FNMADDS
 FNMADDSo
 FNMADDo
 FNMSUB
 FNMSUBS
 FNMSUBSo
 FNMSUBo
 MULHD
 MULHDU
 MULHDUo
 MULHDo
 MULHW
 MULHWU
 MULHWUo
 MULHWo
 MULLD
 MULLDo
 MULLW
 MULLWo
 NAND
 NAND8
 NAND8o
 NANDo
 NOR
 NOR8
 NOR8o
 NORo
 OR
 OR8
 OR8o
 ORo
 RLDIMI
 RLDIMIo
 RLWIMI
 RLWIMI8
 RLWIMI8o
 RLWIMIo
 VADDCUW
 VADDFP
 VADDSBS
 VADDSHS
 VADDSWS
 VADDUBM
 VADDUBS
 VADDUHM
 VADDUHS
 VADDUWM
 VADDUWS
 VAND
 VAVGSB
 VAVGSH
 VAVGSW
 VAVGUB
 VAVGUH
 VAVGUW
 VMADDFP
 VMAXFP
 VMAXSB
 VMAXSH
 VMAXSW
 VMAXUB
 VMAXUH
 VMAXUW
 VMHADDSHS
 VMHRADDSHS
 VMINFP
 VMINSB
 VMINSH
 VMINSW
 VMINUB
 VMINUH
 VMINUW
 VMLADDUHM
 VMULESB
 VMULESH
 VMULEUB
 VMULEUH
 VMULOSB
 VMULOSH
 VMULOUB
 VMULOUH
 VNMSUBFP
 VOR
 VXOR
 XOR
 XOR8
 XOR8o
 XORo
 XSADDDP
 XSMADDADP
 XSMAXDP
 XSMINDP
 XSMSUBADP
 XSMULDP
 XSNMADDADP
 XSNMSUBADP
 XVADDDP
 XVADDSP
 XVMADDADP
 XVMADDASP
 XVMAXDP
 XVMAXSP
 XVMINDP
 XVMINSP
 XVMSUBADP
 XVMSUBASP
 XVMULDP
 XVMULSP
 XVNMADDADP
 XVNMADDASP
 XVNMSUBADP
 XVNMSUBASP
 XXLAND
 XXLNOR
 XXLOR
 XXLXOR

This is a by-inspection change, and I'm not sure how to write a reliable test
case. I would like advice on this, however.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204609 91177308-0d34-0410-b5e6-96231b3b80d8
38a80e9
@dsandersimgtec dsandersimgtec [mips] Allow dsubu to take an immediate as an alias for dsubiu.
Summary:
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3155

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204611 91177308-0d34-0410-b5e6-96231b3b80d8
eaae583
@dsandersimgtec dsandersimgtec [mips] Add regression tests for parenthetic expressions in MIPS assem…
…bly.

Summary:
These expressions already worked but weren't tested.

Patch by Robert N. M. Watson and David Chisnall (it was originally two patches)
Their work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204612 91177308-0d34-0410-b5e6-96231b3b80d8
7500207
@willschm willschm [PPC64LE] ELFv2 ABI updates for the .opd section
[PPC64LE] ELFv2 ABI updates for the .opd section
The PPC64 Little Endian (PPC64LE) target supports the ELFv2 ABI, and as
such, does not have a ".opd" section.  This is keyed off a _CALL_ELF=2
macro check.

The CALL_ELF check is not clearly documented at this time.  The basis
for usage in this patch is from the gcc thread here:
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg01144.html

> Adding comment from Uli:
Looks good to me.  I think the old-style JIT doesn't really work
anyway for 64-bit, but at least with this patch LLVM will compile
and link again on a ppc64le host ...




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204614 91177308-0d34-0410-b5e6-96231b3b80d8
04c252c
@tstellarAMD tstellarAMD R600: Reorganize tablegen instruction definitions
Each GPU family now has its own file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204615 91177308-0d34-0410-b5e6-96231b3b80d8
9958475
@tstellarAMD tstellarAMD SelectionDAG: Allow promotion of SELECT nodes from float to int types
And vice-versa, as long as the types are the same width.

There are a few R600 tests that will cover this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204616 91177308-0d34-0410-b5e6-96231b3b80d8
b15ac1b
@tstellarAMD tstellarAMD R600/SI: Promote fp64 SELECT to i64
This type promotion is replacing a Tablegen pattern and it is already
covered by existing tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204617 91177308-0d34-0410-b5e6-96231b3b80d8
65b5e9b
@tstellarAMD tstellarAMD R600/SI: Fix warning with gcc 4.8.2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204618 91177308-0d34-0410-b5e6-96231b3b80d8
4ddee6a
@eliben eliben Removes the NVPTXSplitBBatBar pass.
This pass is a historic remnant and actually causes less efficient code to be
generated in some cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204620 91177308-0d34-0410-b5e6-96231b3b80d8
2685aa8
@dsandersimgtec dsandersimgtec [mips] Add error message when trying to use $at in '.set noat' mode.
Summary:
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3158

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204621 91177308-0d34-0410-b5e6-96231b3b80d8
8ce101e
@anemet anemet [X86] Fix non-determinism in LowerVectorAllZeroTest
This can be observed with the old testcase of CodeGen/X86/pr12312.ll:

47c47
<       vorps   %ymm0, %ymm1, %ymm0
---
>       vorps   %ymm1, %ymm0, %ymm0
97c97
<       vorps   %ymm1, %ymm0, %ymm0
---
>       vorps   %ymm0, %ymm1, %ymm0

The vector VecIns is populated with all the values from VecInMap. This is done
while iterating VecInMap.  VecInMap uses a hash of pointer values so the
resulting order can vary depending on the memory layout.

The fix is to populate the vector VecIns earlier as VecInMap is populated.
This is done in DAG traversal order.

Fixes <rdar://problem/16398806>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204623 91177308-0d34-0410-b5e6-96231b3b80d8
a1b54dd
@eliben eliben Add test to test/CodeGen/NVPTX for "alloca buffer" arguments.
Make sure such IR gets properly lowered to PTX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204624 91177308-0d34-0410-b5e6-96231b3b80d8
b6f02c1
@zmodem zmodem VS integration installer: set SUCCESS=1 if we find VS 2013
Previously we would print an error message on machines where the only VS
version we find is 2013, even though we successfully install the integration
files for it.

Also, we shouldn't have two END labels.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204629 91177308-0d34-0410-b5e6-96231b3b80d8
657c472
@arsenm arsenm R600/SI: Fix 64-bit private loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204630 91177308-0d34-0410-b5e6-96231b3b80d8
875870f
@qcolombet qcolombet [X86][ISelDAG] Add missing fallback patterns for avx2 broadcast instr…
…uctions.

Those patterns are used when the load cannot be folded into the related broadcast
during the select phase.
This happens when the load gets additional uses that were not anticipated during
the previous lowering phases (constant vector to constant load, then constant
load reused) or when selection DAG is not able to prove that folding the load
will not create a cycle in the DAG.

<rdar://problem/16074331>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204631 91177308-0d34-0410-b5e6-96231b3b80d8
4768df0
@uweigand uweigand [PowerPC] Generate little-endian object files
As a first step towards real little-endian code generation, this patch
changes the PowerPC MC layer to actually generate little-endian object
files.  This involves passing the little-endian flag through the various
layers, including down to createELFObjectWriter so we actually get basic
little-endian ELF objects, emitting instructions in little-endian order,
and handling fixups and relocations as appropriate for little-endian.

The bulk of the patch is to update most test cases in test/MC/PowerPC
to verify both big- and little-endian encodings.  (The only test cases
*not* updated are those that create actual big-endian ABI code, like
the TLS tests.)

Note that while the object files are now little-endian, the generated
code itself is not yet updated, in particular, it still does not adhere
to the ELFv2 ABI.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204634 91177308-0d34-0410-b5e6-96231b3b80d8
47eac58
@AaronBallman AaronBallman Adding some very nascent information about the clang tablegen backend…
…s, with a promise to add more information later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204635 91177308-0d34-0410-b5e6-96231b3b80d8
9f00cd9
@arsenm arsenm R600/SI: Move splitting 64-bit immediates to separate function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204651 91177308-0d34-0410-b5e6-96231b3b80d8
03cd663
@arsenm arsenm R600: Implement isNarrowingProfitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204658 91177308-0d34-0410-b5e6-96231b3b80d8
6c199d8
@yrnkrn yrnkrn In Release modes, Visual Studio complains that the Operator destructo…
…r in User.cpp

never returns, which is true by design. 

Initially assumed that the reason is llvm_unreachable being dependent on NDEBUG.

However, even if llvm_unreachable is replaced by __assume(false), VC still warns in
Release modes but not in Debug modes...

The real reason turned out to be optimization flags.
With /Od in Debug modes the warning is not issued whereas with /O1 it is.

I could not find any documentation to this effect, but it is reproducable:

Try compiling http://msdn.microsoft.com/en-us/library/khwfyc5d(v=vs.90).aspx
with /O1 and then with /Od.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204659 91177308-0d34-0410-b5e6-96231b3b80d8
d816eda
@arsenm arsenm R600/SI: Fix 64-bit bit ops that require the VALU.
Try to match scalar and first like the other instructions.
Expand 64-bit ands to a pair of 32-bit ands since that is not
available on the VALU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204660 91177308-0d34-0410-b5e6-96231b3b80d8
db18071
@arsenm arsenm R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.
No longer asserts, but now you get moves loading legal immediates
into the split 32-bit operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204661 91177308-0d34-0410-b5e6-96231b3b80d8
3a96e61
@arsenm arsenm R600/SI: Fix extra mov from legalizing 64-bit SALU ops.
Check the register class of each operand individually
to avoid an extra copy to a vgpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204662 91177308-0d34-0410-b5e6-96231b3b80d8
add2e2e
David Blaikie Remove unused parameter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204663 91177308-0d34-0410-b5e6-96231b3b80d8
fcd547c
@arsenm arsenm R600: Don't viewCFG() under DEBUG() except on failure.
Having these popping up every time you use -debug is really
irritating.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204664 91177308-0d34-0410-b5e6-96231b3b80d8
e130844
David Blaikie DwarfDebug: Remove an unused parameter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204665 91177308-0d34-0410-b5e6-96231b3b80d8
f2c696a
David Blaikie DebugInfo: Don't emit relocations to abbreviations in debug_info.dwo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204667 91177308-0d34-0410-b5e6-96231b3b80d8
05e62b5
David Blaikie DebugInfo: Implement relative addressing for DW_AT_ranges under fission
This removes the debug_ranges relocations from debug_info.dwo (but
doesn't implement the DW_AT_GNU_ranges_base which is also necessary for
correct functioning)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204668 91177308-0d34-0410-b5e6-96231b3b80d8
f4ec188
@bogner bogner Support: Document Endian.h functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204671 91177308-0d34-0410-b5e6-96231b3b80d8
2563e20
David Blaikie DebugInfo: Add DW_AT_GNU_ranges_base to skeleton CUs
This is used to avoid relocations in the dwo file by allowing
DW_AT_ranges specified in debug_info.dwo to be relative to this base
address. (r204667 implements the base-relative DW_AT_ranges side of
this)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204672 91177308-0d34-0410-b5e6-96231b3b80d8
882d89e
@adrian-prantl adrian-prantl Get rid of an unnecessary use of the * and & operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204673 91177308-0d34-0410-b5e6-96231b3b80d8
1b14452
David Blaikie DwarfDebug: Simplify debug_loc merging
No functional change intended.

Merging up-front rather than delaying this task until later. This just
seems simpler and more efficient (avoiding growing the debug loc list
only to have to skip over those post-merged entries, etc).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204679 91177308-0d34-0410-b5e6-96231b3b80d8
7385c32
David Blaikie DebugInfo: Simplify debug loc list handling by keeping separate lists
Rather than using a flat list with "empty" entries (ala the actual
on-disk format), keep separate lists for each variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204680 91177308-0d34-0410-b5e6-96231b3b80d8
0f53443
Manman Ren Register Allocator: refactoring (no functionality change).
Factor out two functions calculateRegionSplitCost and doRegionSplit
from tryRegionSplit. These two functions will be used in coming patches.

rdar://16162005


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66124f9
Commits on Mar 25, 2014
@enderby enderby Fix crashes when assembler directives are used that are not
for Mach-O object files by generating an error instead.

rdar://16335232


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204687 91177308-0d34-0410-b5e6-96231b3b80d8
4a88cd0
Manman Ren Register Allocator: check other options before using a CSR for the fi…
…rst time.

When register allocator's stage is RS_Spill, we choose spill over using the CSR
for the first time, if the spill cost is lower than CSRCost. 
When register allocator's stage is < RS_Split, we choose pre-splitting over
using the CSR for the first time, if the cost of splitting is lower than
CSRCost.

CSRCost is set with command-line option "regalloc-csr-first-time-cost". The
default value is 0 to generate the same codes as before this commit.

With a value of 15 (1 << 14 is the entry frequency), I measured performance
gain of 3% on 253.perlbmk and 1.7% on 197.parser, with instrumented PGO,
on an arm device.

rdar://16162005


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692d183
@bogner bogner Support: Functions for consuming endian specific data from a buffer.
This adds a function to Endian.h that reads from and updates a pointer
into a buffer with endian specific data. This is more convenient for
stream-like reading of data than endian::read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204693 91177308-0d34-0410-b5e6-96231b3b80d8
9306564
David Blaikie DebugInfo: Remove unnecessary zero-size check
This seems excessive - switching section isn't expensive (or if it is
we're already being wasteful, since we emitted the debug_loc section
symbol earlier anyway) and otherwise there's no work that happens in
this function when the list is empty.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204696 91177308-0d34-0410-b5e6-96231b3b80d8
6cfebbd
David Blaikie DebugInfo: Support debug_loc under fission
Implement debug_loc.dwo, as well as llvm-dwarfdump support for dumping
this section.

Outlined in the DWARF5 spec and http://gcc.gnu.org/wiki/DebugFission the
debug_loc.dwo section has more variation than the standard debug_loc,
allowing 3 different forms of entry (plus the end of list entry). GCC
seems to, and Clang certainly, only use one form, so I've just
implemented dumping support for that for now.

It wasn't immediately obvious that there was a good refactoring to share
the implementation of dumping support between debug_loc and
debug_loc.dwo, so they're separate for now - ideas welcome or I may come
back to it at some point.

As per a comment in the code, we could choose different forms that may
reduce the number of debug_addr entries we emit, but that will require
further study.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204697 91177308-0d34-0410-b5e6-96231b3b80d8
b13d54f
@atrick atrick SLP vectorizer: Don't hoist vector extracts of phis.
Extracts coming from phis were being hoisted, while all others were
sunk to their uses. This was inconsistent and didn't seem to serve a
purpose. Changing all extracts to be sunk to uses is a prerequisite
for adding block frequency to the SLP vectorizer's cost model.

I benchmarked the change in isolation (without block frequency). I
only saw noise on x86 and some potentially significant improvements on
ARM. No major regressions is good enough for me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204699 91177308-0d34-0410-b5e6-96231b3b80d8
f5bf687
@compnerd compnerd test: fix CHECK lines
Thanks to gix for pointing out that the CHECK-LABEL lines were incorrect!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204700 91177308-0d34-0410-b5e6-96231b3b80d8
f50e709
David Blaikie DebugInfo: Add GNU_addr_base and GNU_ranges_base only when there are …
…addresses or ranges

Based on code review feedback from Eric in r204672.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204702 91177308-0d34-0410-b5e6-96231b3b80d8
9d5961d
@majnemer majnemer WinCOFF: Add support for -fdata-sections
This is a pretty straight forward translation for COFF, we just need to
stick the data in a COMDAT section marked as
IMAGE_COMDAT_SELECT_NODUPLICATES.

N.B. We must be careful to avoid sticking entities with private linkage
in COMDAT groups.  COFF is pretty hostile to the renaming of entities so
we must be careful to disallow GlobalVariables with unstable names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204703 91177308-0d34-0410-b5e6-96231b3b80d8
4fd5cd0
@yrnkrn yrnkrn Disable Visual C++ warning 4722 about aborting a destructor,
it has no value for us.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204704 91177308-0d34-0410-b5e6-96231b3b80d8
d8ceb27
Erik Verbruggen Simplify loop that worked around bugs in old GCC/Xcode.
GCC 4.0.1 and Xcode 2 are no longer supported for building llvm/clang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204705 91177308-0d34-0410-b5e6-96231b3b80d8
c5f5d0d
@yrnkrn yrnkrn Remove cmake module support for Visual C++ 2010 (MSVC10)
but keep the MSVC11 (Visual C++ 2012) support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204706 91177308-0d34-0410-b5e6-96231b3b80d8
6e2aab6
@dsandersimgtec dsandersimgtec [mips] Fix assembler temporary expansion and add associated warnings …
…about the use of $at.

Summary:
The assembler temporary is normally $at ($1) but can be reassigned using
'.set at=$reg'. Regardless of which register is nominated as the assembler
temporary, $at remains $1 when written by the user.

Adds warnings under the following conditions:
* The register nominated as the assembler temporary is used by the user.
* '.set noat' is in effect and $at is used by the user.
Both of these only work for named registers. I have a follow up commit that makes it work for numeric registers as well.

XFAIL set-at-directive.s since it incorrectly tests that $at is redefined by
'.set at=$reg'. Testcases will follow in a separate commit.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204710 91177308-0d34-0410-b5e6-96231b3b80d8
c141b33
@dsandersimgtec dsandersimgtec [mips] Correct testcase for .set at=$reg and emit the new warnings fo…
…r numeric registers too.

Summary:
Remove the XFAIL added in my previous commit and correct the test such that
it correctly tests the expansion of the assembler temporary.

Also added a test to check that $at is always $1 when written by the
user.

Corrected the new assembler temporary warnings so that they are emitted for
numeric registers too.

Differential Revision: http://llvm-reviews.chandlerc.com/D3169

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204711 91177308-0d34-0410-b5e6-96231b3b80d8
c7e1663
Cameron McInally Fix AVX2 Gather execution domains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204713 91177308-0d34-0410-b5e6-96231b3b80d8
3ec862b
@dsandersimgtec dsandersimgtec [mips] '.set at=$0' should be equivalent to '.set noat'
Differential Revision: http://llvm-reviews.chandlerc.com/D3171

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204714 91177308-0d34-0410-b5e6-96231b3b80d8
3527e5f
@eugenis eugenis [msan] More precise instrumentation of select IR.
Some bits of select result may be initialized even if select condition
is not.

https://code.google.com/p/memory-sanitizer/issues/detail?id=50


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204716 91177308-0d34-0410-b5e6-96231b3b80d8
8003996
@espindola espindola Fix these tests on windows.
It is impossible to create a hard link to a non existing file, so create a
dummy file, create the link an delete the dummy file.

On windows one cannot remove the current directory, so chdir first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204719 91177308-0d34-0410-b5e6-96231b3b80d8
2cf1cdf
@eugenis eugenis [msan] Make some tests less strict.
This may or may not fix the bots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204720 91177308-0d34-0410-b5e6-96231b3b80d8
0b9bcfa
@eugenis eugenis [msan] Relax the test some more.
This may or may not fix the bots. R204720 did not.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204721 91177308-0d34-0410-b5e6-96231b3b80d8
ffa7f42
@arsenm arsenm Fix creating illegal setcc cond codes.
If GT/UGT or LT/ULT were set to expand, a comparison
with a constant would replace it with the illegal
cond code.

There are several more places later in this function that
will have the same basic problem.

Theoretically R600 should hit this problem for a test,
but for some reason it doesn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204727 91177308-0d34-0410-b5e6-96231b3b80d8
71a8d2b
@d0k d0k ScalarEvolution: Compute exit counts for loops with a power-of-2 step.
If we have a loop of the form
for (unsigned n = 0; n != (k & -32); n += 32) {}
then we know that n is always divisible by 32 and the loop must
terminate. Even if we have a condition where the loop counter will
overflow it'll always hold this invariant.

PR19183. Our loop vectorizer creates this pattern and it's also
occasionally formed by loop counters derived from pointers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204728 91177308-0d34-0410-b5e6-96231b3b80d8
c1c74fb
@arsenm arsenm R600: Add failing testcase for <3 x i32> stores.
This is supposed to have the same store size and alignment as <4 x i32>,
but currently is split into a 64-bit and 32-bit store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204729 91177308-0d34-0410-b5e6-96231b3b80d8
0227461
@d0k d0k Add missing slash to make the doxygen output less confusing.
PR19187.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204731 91177308-0d34-0410-b5e6-96231b3b80d8
33ffbdf
@rlsosborne rlsosborne Reuse earlier variables to make it clear the types involved in the cast.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204732 91177308-0d34-0410-b5e6-96231b3b80d8
902c799
@rlsosborne rlsosborne [InstCombine] Don't fold bitcast into store if it would need addrspac…
…ecast

Summary:
Previously the code didn't check if the before and after types for the
store were pointers to different address spaces. This resulted in
instcombine using a bitcast to convert between pointers to different
address spaces, causing an assertion due to the invalid cast.

It is not be appropriate to use addrspacecast this case because it is
not guaranteed to be a no-op cast. Instead bail out and do not do the
transformation.

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D3117

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204733 91177308-0d34-0410-b5e6-96231b3b80d8
67cb554
@anemet anemet [X86] Factor out new helper getPSHUFB
I found three implementations of this.  This splits it out into a new function
and uses it from the three places.

My plan is to add a fourth use when lowering a vector_shuffle:v16i16.

Compared the assembly output of test/CodeGen/X86 before and after.

The only change is due to how the first PSHUFB was generated in
LowerVECTOR_SHUFFLEv8i16.  If the shuffle mask specified undef (i.e. -1), the
old implementation would write -1 * 2 and -1 * 2 + 1 (254 and 255) in the
control mask.  Now we write 0x80.  These are of course interchangeable since
bit 7 decides if a constant zero is written in the result byte.  The other
instances of this code use 0x80 consistently.

Related to <rdar://problem/16167303>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204734 91177308-0d34-0410-b5e6-96231b3b80d8
9526911
@anemet anemet [X86] Generate VPSHUFB for in-place v16i16 shuffles
This used to resort to splitting the 256-bit operation into two 128-bit
shuffles and then recombining the results.

Fixes <rdar://problem/16167303>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204735 91177308-0d34-0410-b5e6-96231b3b80d8
6f4f46c
@ributzka ributzka [DAG] Keep the opaque constant flag when performing unary constant fo…
…lding operations.

Usually opaque constants shouldn't be folded, unless they are simple unary
operations that don't create new constants. Although this shouldn't drop the
opaque constant flag. This commit fixes this.

Related to <rdar://problem/14774662>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204737 91177308-0d34-0410-b5e6-96231b3b80d8
6ac0491
@ributzka ributzka [Stackmaps][X86TTI] Fix think-o in getIntImmCost calculation.
The cost for the first four stackmap operands was always TCC_Free.
This is only true for the first two operands. All other operands
are TCC_Free if they are within 64bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204738 91177308-0d34-0410-b5e6-96231b3b80d8
e987eb1
@ributzka ributzka [X86TTI] Make constant base pointers for getElementPtr opaque.
If getElementPtr uses a constant as base pointer, then make the constant opaque.
This prevents constant folding it with the offset. The offset can usually be
encoded in the load/store instruction itself and the base address doesn't have
to be rematerialized several times.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204739 91177308-0d34-0410-b5e6-96231b3b80d8
feaa463
@dexonsmith dexonsmith blockfreq: Use const in MachineBlockFrequencyInfo
<rdar://problem/14292693>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204740 91177308-0d34-0410-b5e6-96231b3b80d8
8451e1b
@dexonsmith dexonsmith blockfreq: Implement Pass::releaseMemory()
Implement Pass::releaseMemory() in BlockFrequencyInfo and
MachineBlockFrequencyInfo.  Just delete the private implementation when
not in use.  Switch to a std::unique_ptr to make the logic more clear.

<rdar://problem/14292693>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204741 91177308-0d34-0410-b5e6-96231b3b80d8
27e1ca8
@arsenm arsenm R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp
Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204743 91177308-0d34-0410-b5e6-96231b3b80d8
ab5382f
@hfinkel hfinkel [PowerPC] Add a TableGen relation for A-type and M-type VSX FMA instr…
…uctions

TableGen will create a lookup table for the A-type FMA instructions providing
their corresponding M-form opcodes. This will be used by upcoming commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204746 91177308-0d34-0410-b5e6-96231b3b80d8
fba0a05
@hfinkel hfinkel [PowerPC] Correct commutable indices for VSX FMA instructions
Although the first two operands are the ones that can be swapped, the tied
input operand is listed before them, so we need to adjust for that.

I have a test case for this, but it goes along with an upcoming commit (so it
will come soon).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204748 91177308-0d34-0410-b5e6-96231b3b80d8
7e77dab
@ributzka ributzka [Constant Hoisting] Make the constant candidate map local to the coll…
…ectConstantCandidates method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204758 91177308-0d34-0410-b5e6-96231b3b80d8
63dfd62
@meadori meadori [configure/make] Propagate names of build host tools when making Buil…
…dTools

When cross-compiling LLVM itself the configure/make scripts get confused when
creating the needed build host tools.  For example, building and configuring
like:

  CC_FOR_BUILD='i686-pc-linux-gnu-gcc' CXX_FOR_BUILD='i686-pc-linux-gnu-g++'
  CXX='i686-mingw32-g++' CC='i686-mingw32-gcc' LD='i686-mingw32-ld' /scratch
  /meadori/llvm-trunk/src/trunk/configure --host=i686-mingw32

  CC_FOR_BUILD='i686-pc-linux-gnu-gcc' CXX_FOR_BUILD='i686-pc-linux-gnu-g++'
  CXX='i686-mingw32-g++' CC='i686-mingw32-gcc' LD='i686-mingw32-ld' make

causes the following build break:

  checking whether the C compiler works... configure: error: cannot run C
  compiled programs.
  If you meant to cross compile, use `--host'.
  See `config.log' for more details.

The 'config.log' shows that i686-mingw32-gcc is being used to create
executables for the build host.

This patch fixes the problem by propogating the names of the build host
tools via BUILD_* when configuring/making BuildTools.

Original patch by Ekaterina Sanina.


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fe07617
@espindola espindola Use Endian.h to simplify this code a bit.
While at it, factor some logic into FragmentWriter. This will allow more code
to be factored out of the fairly large ELFObjectWriter.

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78f7e6f
@chapuni chapuni llvm/test/DebugInfo/empty.ll: Suppress crash for targeting pecoff whi…
…le investigating.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204766 91177308-0d34-0410-b5e6-96231b3b80d8
99ab079
@hfinkel hfinkel [PowerPC] Select between VSX A-type and M-type FMA instructions just …
…before RA

The VSX instruction set has two types of FMA instructions: A-type (where the
addend is taken from the output register) and M-type (where one of the product
operands is taken from the output register). This adds a small pass that runs
just after MI scheduling (and, thus, just before register allocation) that
mutates A-type instructions (that are created during isel) into M-type
instructions when:

 1. This will eliminate an otherwise-necessary copy of the addend

 2. One of the product operands is killed by the instruction

The "right" moment to make this decision is in between scheduling and register
allocation, because only there do we know whether or not one of the product
operands is killed by any particular instruction. Unfortunately, this also
makes the implementation somewhat complicated, because the MIs are not in SSA
form and we need to preserve the LiveIntervals analysis.

As a simple example, if we have:

%vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
%vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
                        %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
  ...
  %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19,
                        %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
  ...

We can eliminate the copy by changing from the A-type to the
M-type instruction. This means:

  %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
                        %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16

is replaced by:

  %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9,
                        %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9

and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204768 91177308-0d34-0410-b5e6-96231b3b80d8
6a0f060
@espindola espindola Create .symtab_shndxr only when needed.
We need .symtab_shndxr if and only if a symbol references a section with an
index >= 0xff00.

The old code was trying to figure out if the section was needed ahead of time,
making it a fairly dependent on the code actually writing the table. It was
also somewhat conservative and would create the section in cases where it was
not needed.

If I remember correctly, the old structure was there so that the sections were
created in the same order gas creates them. That was valuable when MC's support
for ELF was new and we tested with elf-dump.py.

This patch refactors the symbol table creation to another class and makes it
obvious that .symtab_shndxr is really only created when we are about to output
a reference to a section index >= 0xff00.

While here, also improve the tests to use macros. One file is one section
short of needing .symtab_shndxr, the second one has just the right number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204769 91177308-0d34-0410-b5e6-96231b3b80d8
81c66bc
Commits on Mar 26, 2014
@qcolombet qcolombet [X86] Add broadcast instructions to the table used by ExeDepsFix pass.
Adds the different broadcast instructions to the ReplaceableInstrsAVX2 table.
That way the ExeDepsFix pass can take better decisions when AVX2 broadcasts are
across domain (int <-> float).

In particular, prior to this patch we were generating:
  vpbroadcastd  LCPI1_0(%rip), %ymm2
  vpand %ymm2, %ymm0, %ymm0
  vmaxps  %ymm1, %ymm0, %ymm0 ## <- domain change penalty

Now, we generate the following nice sequence where everything is in the float
domain:
  vbroadcastss  LCPI1_0(%rip), %ymm2
  vandps  %ymm2, %ymm0, %ymm0
  vmaxps  %ymm1, %ymm0, %ymm0

<rdar://problem/16354675>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204770 91177308-0d34-0410-b5e6-96231b3b80d8
596516b
@espindola espindola Correctly detect if a symbol uses a reserved section index or not.
The logic was incorrect for variables, causing them to end up in the wrong
section if the section had an index >= 0xff00.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204771 91177308-0d34-0410-b5e6-96231b3b80d8
3008f80
David Blaikie DebugInfo: Add fission-related sections to COFF
Allows this test to pass on COFF platforms so we don't need to restrict
this test to a single target anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204780 91177308-0d34-0410-b5e6-96231b3b80d8
577708b
@espindola espindola Prevent alias from pointing to weak aliases.
Aliases are just another name for a position in a file. As such, the
regular symbol resolutions are not applied. For example, given

define void @my_func() {
  ret void
}
@my_alias = alias weak void ()* @my_func
@my_alias2 = alias void ()* @my_alias

We produce without this patch:

        .weak   my_alias
my_alias = my_func
        .globl  my_alias2
my_alias2 = my_alias

That is, in the resulting ELF file my_alias, my_func and my_alias are
just 3 names pointing to offset 0 of .text. That is *not* the
semantics of IR linking. For example, linking in a

@my_alias = alias void ()* @other_func

would require the strong my_alias to override the weak one and
my_alias2 would end up pointing to other_func.

There is no way to represent that with aliases being just another
name, so the best solution seems to be to just disallow it, converting
a miscompile into an error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204781 91177308-0d34-0410-b5e6-96231b3b80d8
33845aa
@hfinkel hfinkel [PowerPC] Generate logical vector VSX instructions
These instructions are essentially the same as their Altivec counterparts, but
have access to the larger VSX register file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204782 91177308-0d34-0410-b5e6-96231b3b80d8
360ee97
@espindola espindola Revert "Prevent alias from pointing to weak aliases."
This reverts commit r204781.

I will follow up to with msan folks to see what is what they
were trying to do with aliases to weak aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204784 91177308-0d34-0410-b5e6-96231b3b80d8
72db10a
Timur Iskhodzhanov Use -LABEL checks in the COFF debug info tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204788 91177308-0d34-0410-b5e6-96231b3b80d8
c61ec18
Timur Iskhodzhanov Fix PR19239 - Add support for generating debug info for functions wit…
…hout lexical scopes and/or debug info at all

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204790 91177308-0d34-0410-b5e6-96231b3b80d8
d4c442f
Timur Iskhodzhanov Add tests for r204790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204791 91177308-0d34-0410-b5e6-96231b3b80d8
47d533f
@dsandersimgtec dsandersimgtec [mips] Move the CHECK lines in mips*-register-names.s to make it more…
… obvious which CHECK matches with which insn

This reveals a small mistake in mips-register-names.s ($sp is tested twice and
$s8 is not tested) which will be fixed in a follow-up commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204792 91177308-0d34-0410-b5e6-96231b3b80d8
d431e0a
@dsandersimgtec dsandersimgtec [mips] $s8 is an alias for $fp in all ABI's, not just N32/N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204793 91177308-0d34-0410-b5e6-96231b3b80d8
95f4d65
Timur Iskhodzhanov Follow-up to r204790: don't try to emit line tables if there are no f…
…unctions with DI in the TU

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204795 91177308-0d34-0410-b5e6-96231b3b80d8
2b84dba
@dsandersimgtec dsandersimgtec [mips] The register names depend on the ABI being N32/N64 rather than…
… the arch being mips64

Summary: Added test cases for O32 and N32 on MIPS64.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3175

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204796 91177308-0d34-0410-b5e6-96231b3b80d8
968ea7b
@dsandersimgtec dsandersimgtec [mips] Add tests for t0-t3 for N32/N64
These are aliases of t4-t7 and are provided for compatibility with both the
original ABI documentation (using t4-t7) and GNU As (using t0-t3)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204797 91177308-0d34-0410-b5e6-96231b3b80d8
23f0634
@hfinkel hfinkel [PowerPC] Lower VSELECT using xxsel when VSX is available
With VSX there is a real vector select instruction, and so we should use it.
Note that VSELECT will still scalarize for v2f64 because the corresponding
SetCC result type (v2i64) is not currently a legal type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204801 91177308-0d34-0410-b5e6-96231b3b80d8
159e7f4
@rengolin rengolin Add @llvm.clear_cache builtin
Implementing the LLVM part of the call to __builtin___clear_cache
which translates into an intrinsic @llvm.clear_cache and is lowered
by each target, either to a call to __clear_cache or nothing at all
incase the caches are unified.

Updating LangRef and adding some tests for the implemented architectures.
Other archs will have to implement the method in case this builtin
has to be compiled for it, since the default behaviour is to bail
unimplemented.

A Clang patch is required for the builtin to be lowered into the
llvm intrinsic. This will be done next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204802 91177308-0d34-0410-b5e6-96231b3b80d8
c4b058f
Matheus Almeida [mips] Add support for '.option pic2'.
The directive '.option pic2' enables PIC from assembly source.
At the moment none of the macros/directives check the PIC bit
but that's going to be fixed relatively soon. For example, the
expansion of macros like 'la' depend on the relocation model.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204803 91177308-0d34-0410-b5e6-96231b3b80d8
0de31d5
Cameron McInally Fix AVX512 Gather and Scatter execution domains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204804 91177308-0d34-0410-b5e6-96231b3b80d8
4de1039
@dsandersimgtec dsandersimgtec [mips] The decision to use MO_GOT_PAGE and MO_GOT_OFST depends on the…
… ABI being N32 or N64 not the arch being MIPS64

Summary: No functional change (in supported use cases)

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3177

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204805 91177308-0d34-0410-b5e6-96231b3b80d8
cee1aec
@rengolin rengolin Change @llvm.clear_cache default to call rt-lib
After some discussion on IRC, emitting a call to the library function seems
like a better default, since it will move from a compiler internal error to
a linker error, that the user can work around until LLVM is fixed.

I'm also adding a note on the responsibility of the user to confirm that
the cache was cleared on platforms where nothing is done.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204806 91177308-0d34-0410-b5e6-96231b3b80d8
58839f4
Matheus Almeida [mips] Hoist common functionality into a new function.
    
Given that we support multiple directives that enable a particular feature
(e.g. '.set mips16'), it's best to hoist that code into a new function
so that we don't repeat the same pattern w.r.t parsing and handling error cases.

No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204811 91177308-0d34-0410-b5e6-96231b3b80d8
637e1da
@jsonn jsonn Clarify llvm.clear_cache description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204812 91177308-0d34-0410-b5e6-96231b3b80d8
25d0cfe
@TNorthover TNorthover ARM: add intrinsics for the v8 ldaex/stlex
We've already got versions without the barriers, so this just adds IR-level
support for generating the new v8 ones.

rdar://problem/16227836

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204813 91177308-0d34-0410-b5e6-96231b3b80d8
fc4fa22
Christian Pirker AArch64_BE function argument passing for ARM ABI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204814 91177308-0d34-0410-b5e6-96231b3b80d8
94708f1
Matheus Almeida [mips] Add support to '.set mips64r2'.
The '.set mips64r2' directive enables the feature Mips:FeatureMips64r2
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64r2 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204815 91177308-0d34-0410-b5e6-96231b3b80d8
53ccc09
Christian Pirker AArch64_BE Elf support for MC-JIT runtime dynamic linker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204816 91177308-0d34-0410-b5e6-96231b3b80d8
a634d0a
Matheus Almeida [mips] Add support to '.set mips64'.
The '.set mips64' directive enables the feature Mips:FeatureMips64
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204817 91177308-0d34-0410-b5e6-96231b3b80d8
5957d10
Matheus Almeida [mips] Rename function in MipsAsmParser.
parseDirectiveWord is a generic function that parses an expression which
means there's no need for it to have such an specific name. Renaming it to
parseDataDirective so that it can also be used to handle .dword directives[1].

[1]To be added in a follow up commit.

No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204818 91177308-0d34-0410-b5e6-96231b3b80d8
bd11396
@jsonn jsonn Clarify that select is only non-branching on the IR-level, it often ends
up as jump table or other forms of branches on the machine level.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204819 91177308-0d34-0410-b5e6-96231b3b80d8
dd6d74f
Matheus Almeida [mips] Add support to the '.dword' directive.
The '.dword' directive accepts a list of expressions and emits
them in 8-byte chunks in successive locations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204822 91177308-0d34-0410-b5e6-96231b3b80d8
75203b6
Matheus Almeida [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.
This enables TableGen to generate an additional two operand matcher
for our ArithLogicR class of instructions (constituted by 3 register operands).
E.g.: and $1, $2 <=> and $1, $1, $2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204826 91177308-0d34-0410-b5e6-96231b3b80d8
8e7aa4b
@hfinkel hfinkel [PowerPC] Add v2i64 as a legal VSX type
v2i64 needs to be a legal VSX type because it is the SetCC result type from
v2f64 comparisons. We need to expand all non-arithmetic v2i64 operations.

This fixes the lowering for v2f64 VSELECT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204828 91177308-0d34-0410-b5e6-96231b3b80d8
7363d22
@zmodem zmodem Revert "X86 memcpy lowering: use "rep movs" even when esi is used as …
…base pointer" (r204174)

>  For functions where esi is used as base pointer, we would previously fall ba
>  from lowering memcpy with "rep movs" because that clobbers esi.
>
>  With this patch, we just store esi in another physical register, and restore
>  it afterwards. This adds a little bit of register preassure, but the more
>  efficient memcpy should be worth it.
>
>  Differential Revision: http://llvm-reviews.chandlerc.com/D2968

This didn't work. I was ending up with code like this:

  lea     edi,[esi+38h]
  mov     ecx,0Fh
  mov     edx,esi
  mov     esi,ebx
  rep movs dword ptr es:[edi],dword ptr [esi]
  lea     ecx,[esi+74h] <-- Ooops, we're now using esi before restoring it from edx.
  add     ebx,3Ch
  mov     esi,edx

I guess if we want to do this we need stronger glue or something, or doing the expansion
much later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204829 91177308-0d34-0410-b5e6-96231b3b80d8
b82f8a2
Jim Grosbach Fix for incorrect address sinking in the presence of potential overfl…
…ows.

In some cases it is possible for CGP to attempt to reuse a base address from
another basic block. In those cases we have to be sure that all the address
math was either done at the same bit width, or that none of it overflowed
before it was extended.

Patch by Louis Gerbarg <lgg@apple.com>

rdar://16307442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204833 91177308-0d34-0410-b5e6-96231b3b80d8
489752d
@eliben eliben Add args() iteartor adapter to Function, for range-for loops.
This patch is in similar vein to what done earlier to Module::globals/aliases
etc. It allows to iterate over function arguments like this:

  for (Argument Arg : F.args()) {
    ...
  }



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204835 91177308-0d34-0410-b5e6-96231b3b80d8
cf2de5a
@eliben eliben Enable range-for iteration over call/invoke arguments.
Similar to r204835



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204836 91177308-0d34-0410-b5e6-96231b3b80d8
65a3ced
@ributzka ributzka [MCJIT] Check if there have been errors during RuntimeDyld execution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204837 91177308-0d34-0410-b5e6-96231b3b80d8
50c3856
@hfinkel hfinkel [PowerPC] Use VSX vector load/stores for v2[fi]64
These instructions have access to the complete VSX register file. In addition,
they "swap" the order of the elements so that element 0 (the scalar part) comes
first in memory and element 1 follows at a higher address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204838 91177308-0d34-0410-b5e6-96231b3b80d8
c6940d4
@hfinkel hfinkel [PowerPC] Remove some dead VSX v4f32 store patterns
These patterns are dead (because v4f32 stores are currently promoted to v4i32
and stored using Altivec instructions), and also are likely not correct
(because they'd store the vector elements in the opposite order from that
assumed by the rest of the Altivec code).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204839 91177308-0d34-0410-b5e6-96231b3b80d8
cb2c252
@arsenm arsenm R600: Add a testcase for sext_in_reg I missed.
This sext_inreg i32 in i64 case was already handled, but not enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204840 91177308-0d34-0410-b5e6-96231b3b80d8
e0e5038
@lhames lhames Change the PBQP graph adjacency list structure from std::set to std::…
…vector.

The edge data structure (EdgeEntry) now holds the indices of its entries in the
adjacency lists of the nodes it connects. This trades a little ugliness for
faster insertion/removal, which is now O(1) with a cheap constant factor. All
of this is implementation detail within the PBQP graph, the external API remains
unchanged.

Individual register allocations are likely to change, since the adjacency lists
will now be ordered differently (or rather, will now be unordered). This
shouldn't affect the average quality of allocations however.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204841 91177308-0d34-0410-b5e6-96231b3b80d8
ec97f95
@hfinkel hfinkel [PowerPC] Use v2f64 <-> v2i64 VSX conversion instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204843 91177308-0d34-0410-b5e6-96231b3b80d8
b397453
@lhames lhames Remove PBQP-cost dimension sanity assertion in PBQP::Graph::addConstr…
…uctedEdge.

We're already effectively checking sanity for that in PBQP::Graph::addEdge.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204844 91177308-0d34-0410-b5e6-96231b3b80d8
2ca8b98
@enderby enderby Fix the ARM VST4 (single 4-element structure from one lane)
size 16 double-spaced registers instruction printing.

This:
	vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!

was being printed as:

	vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!

rdar://16435096


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204847 91177308-0d34-0410-b5e6-96231b3b80d8
9efa4ff
@hfinkel hfinkel [PowerPC] VSX loads and stores support unaligned access
I've not yet updated PPCTTI because I'm not sure what the actual relative cost
is compared to the aligned uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204848 91177308-0d34-0410-b5e6-96231b3b80d8
6da0178
@eliben eliben Fix problem with r204836
In CallInst, op_end() points at the callee, which we don't want to iterate over
when just iterating over arguments. Now take this into account when returning
a iterator_range from arg_operands. Similar reasoning for InvokeInst.

Also adds a unit test to verify this actually works as expected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204851 91177308-0d34-0410-b5e6-96231b3b80d8
1003e8f
@eliben eliben Fix bot breakage in InstructionsTest.
Makes sure the Call dies before the Function



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204856 91177308-0d34-0410-b5e6-96231b3b80d8
927eb31
@lhames lhames Simplify PBQP graph removeAdjEdgeId implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204857 91177308-0d34-0410-b5e6-96231b3b80d8
3a0a1f6
@aschwaighofer aschwaighofer PR15967 Fix in basicaa for faulty returning no alias.
This commit consist of two parts.
The first part fix the PR15967. The wrong conclusion was made when the MaxLookup
limit was reached. The fix introduce a out parameter (MaxLookupReached) to
DecomposeGEPExpression that the function aliasGEP can act upon.
The second part is introducing the constant MaxLookupSearchDepth to make sure
that DecomposeGEPExpression and GetUnderlyingObject use the same search depth.
This is a small cleanup to clarify the original algorithm.

Patch by Karl-Johan Karlsson!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204859 91177308-0d34-0410-b5e6-96231b3b80d8
23463c9
@eliben eliben Add a unit test for Invoke iteration, similar to the one for Call
The tests are refactored to use the same fixture.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204860 91177308-0d34-0410-b5e6-96231b3b80d8
d8f4993
@enderby enderby Fix a problem with the ARM assembler incorrectly matching a
vector list parameter that is using all lanes "{d0[], d2[]}" but can
match and instruction with a ”{d0, d2}" parameter.

I’m finishing up a fix for proper checking of the unsupported
alignments on vld/vst instructions and ran into this.  Thus I don’t
have a test case at this time.  And adding all code that will
demonstrate the bug would obscure the very simple one line fix.
So if you would indulge me on not having a test case at this
time I’ll instead offer up a detailed explanation of what is
going on in this commit message.

This instruction:

	vld2.8  {d0[], d2[]}, [r4:64]

is not legal as the alignment can only be 16 when the size is 8.
Per this documentation:

A8.8.325 VLD2 (single 2-element structure to all lanes)
 <align> The alignment. It can be one of:
16 2-byte alignment, available only if <size> is 8, encoded as a = 1.
32 4-byte alignment, available only if <size> is 16, encoded as a = 1.
64 8-byte alignment, available only if <size> is 32, encoded as a = 1.
omitted Standard alignment, see Unaligned data access on page A3-108.

So when code is added to the llvm integrated assembler to not match
that instruction because of the alignment it then goes on to try to match
other instructions and comes across this:

	vld2.8  {d0, d2}, [r4:64]

and and matches it. This is because of the method
ARMOperand::isVecListDPairSpaced() is missing the check of the Kind.
In this case the Kind is k_VectorListAllLanes . While the name of the method
may suggest that this is OK it really should check that the Kind is
k_VectorList.

As the method ARMOperand::isDoubleSpacedVectorAllLanes() is what was
used to match {d0[], d2[]}  and correctly checks the Kind:

  bool isDoubleSpacedVectorAllLanes() const {
    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
  }

where the original ARMOperand::isVecListDPairSpaced() does not check
the Kind:

  bool isVecListDPairSpaced() const {
    if (isSingleSpacedVectorList()) return false;
    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
              .contains(VectorList.RegNum));
  }

Jim Grosbach has reviewed the change and said:  Yep, that sounds right. …
And by "right" I mean, "wow, that's a nasty latent bug I'm really, really
glad to see fixed." :)

rdar://16436683


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70ea745
@bogner bogner llvm-cov: Handle functions with no line number
Functions may in an instrumented binary but not in the original source
when they're inserted by the compiler or the runtime. These functions
aren't meaningful to the user, so teach llvm-cov to skip over them
instead of crashing.

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2a6873f
Manman Ren Add comments. Addressing review comments from Evan on r204690.
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3d7d0bc
Ekaterina Romanova This is a fix for PR# 19051. I noticed code gen differences due to co…
…de motion when running tests with and without the debug info at O2. The problem is in branch folding. A loop wanted to skip the debug info, but actually it didn't do so.

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899a605
Reid Kleckner CloneFunction: Clone all attributes, including the CC
Summary:
Tested with a unit test because we don't appear to have any transforms
that use this other than ASan, I think.

Fixes PR17935.

Reviewers: nicholas

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D3194

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891835a
@bogner bogner llvm-cov: Disable test on big endian machines
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e8836a7
@bogner bogner llvm-cov: Move XFAIL after the body of the test
llvm-cov tests are sensitive to line number changes, so putting this
at the end will limit churn when we fix the XFAIL.

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7c38741
@hfinkel hfinkel [PowerPC] Generate VSX permutations for v2[fi]64 vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204873 91177308-0d34-0410-b5e6-96231b3b80d8
ee5f4bb
Eric Christopher Reorder arguments on test command line to make it easier to cut and
paste.

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1e0751b
@nlewycky nlewycky Treat lifetime.start'd memory like we treat freshly alloca'd memory. …
…Patch by Björn Steinbrink!

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ce49ab2
Commits on Mar 27, 2014
Jim Grosbach X86: Correct vectorization cost model for v8f32->v8i8.
Fix the cost model to reflect the reality of our codegen.

rdar://16370633

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f20d9ee
@bogner bogner llvm-cov: When reading strings in gcov data, skip leading zeros
It seems that gcov, when faced with a string that is apparently zero
length, just keeps reading words until it finds a length it likes
better. I'm not really sure why this is, but it's simple enough to
make llvm-cov follow suit.

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11d89f4
Jim Grosbach add 'requires asserts' to test that needs it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204882 91177308-0d34-0410-b5e6-96231b3b80d8
e6cee9f
@espindola espindola Correctly propagates st_size.
This also finally removes a bogus call to AliasedSymbol.

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e459f72
@qcolombet qcolombet [X86][Vectorizer Cost Model] Correct vectorization cost model for v2i…
…64->v2f64

and v4i64->v4f64.

The new costs match what we did for SSE2 and reflect the reality of our codegen.

<rdar://problem/16381225>


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566abec
@lhames lhames Remove forward declaration for Target class - Target is already defin…
…ed here.

No functional change.


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85e4ae5
Reid Kleckner inalloca: Fix incorrect example IR and remove LangRef warning
The LangRef warning wasn't formatting the way I intended it to anyway.

Surprisingly inalloca appears to work, even when optimizations are
enabled.  We generate very bad code for it, but we can self-host and run
lots of big tests.

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2ce2122
Reid Kleckner Remove unneeded stale type.
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b1d0dd9
Reid Kleckner inalloca: *Really* fix the docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204890 91177308-0d34-0410-b5e6-96231b3b80d8
7d3c316
@lhames lhames Update MCSymbolizer and its subclasses' constructors to reflect the f…
…act that

they take ownership of the RelocationInfo they're constructed with.



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7fd03c5
@lhames lhames Move MCSymbolizer's constructor into header. It's trivial - there's n…
…o need for

it to be out-of-line.


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7f8e6b9
@lhames lhames Assert that MCSymbolizer is constructed with a valid (or at least non…
…-null)

RelocationInfo argument.


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af0682b
@lhames lhames Add missing #include <cassert> to MCSymbolizer.h.
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2298972
Jiangning Liu ARM: raise error message when complex SO expressions can't really be
solved as a constant at compilation time.


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09b4588
@kaomoneus kaomoneus Fix for pr18931: Crash using integrated assembler with immediate arit…
…hmetic

Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.



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fccc690
@kaomoneus kaomoneus Fixed test for r204899 (pr18931 fix)
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a36286c
@kaomoneus kaomoneus Rejected r204899 and r204900 due to remaining test failures on cmake-…
…llvm-x86_64-linux buildbot.

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fee5d23
Timur Iskhodzhanov Make the recent COFF debug info tests more readable
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45dfc70
Timur Iskhodzhanov Add a PR reference
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43a55da
Elena Demikhovsky AVX-512: Implemented masking for integer arithmetic & logic instructi…
…ons.

By Robert Khasanov rob.khasanov@gmail.com


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61785a0
@chandlerc chandlerc [cleanup] Modernize doxygen comments for the BumpPtrAllocator and
rewrite some of them to be more clear.

The terminology being used in our allocators is making me really sad. We
call things slab allocators that aren't at all slab allocators. It is
quite confusing.

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9e7e3e3
@chandlerc chandlerc [cleanup] Run clang-format over these routines to remove formatting
differences from subsequent diffs, and ease review. Going to be
performing some major surgery to simplify this stuff.

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a7a255f