nlatch Verliog code synthesis question

[lixuzhe]

Version

Yosys 0.31+6 (git sha1 0b8f728, gcc 9.4.0-1ubuntu1~20.04.1 -0g -fPIC))

On which OS did this happen?

Linux

Reproduction Steps

The nlatch in the Verilog code cannot be synthesized into the nlatch std_cell when the nlatch cell exists in my lib.

nlatch.ys :

read_verilog nlatch.v
hierarchy -top nlatch
proc
opt
techmap
opt
dfflibmap mycell.lib
abc -liberty mycell.lib
clean
write_verilog nlatch.syn.v

coding e.g.

module nlatch1(a,b,c);

input a;
input b;
output c;

reg  c;

always @(a,b) begin
    if (~a) begin
        c <= b;
    end  
end

endmodule

Expected Behavior

module nlatch1(a,b,c);
input a,b;
output c;

nlatch c_reg ( .CLK(a), .D(b), .Q(c) );

endmodule

Actual Behavior

module nlatch1(a,b,c);
input a;
wire a;
input b;
wire b;
output c;
reg c;

always @ *
if (!a) c=b;
endmodule