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An HDL embedded in Rust.
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yupferris Clarify docs for Mem read port values
When the enable signal is not asserted, we previously documented the resulting value as undefined, but it actually has guaranteed semantics, so let's specify those instead.
Latest commit 13972ab Mar 27, 2020


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kaze-sim-tests Change Mem semantics for simultaneous read/write Mar 27, 2020
kaze Clarify docs for Mem read port values Mar 27, 2020 Clarify docs for Mem read port values Mar 27, 2020
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LICENSE-MIT Add license files Jan 25, 2020 Change SystemVerilog -> Verilog Mar 27, 2020 Add test script Dec 24, 2019


An HDL embedded in Rust.

Latest version Documentation License

kaze provides an API to describe Modules composed of Signals, which can then be used to generate Rust simulator code or Verilog modules.

kaze's API is designed to be as minimal as possible while still being expressive. It's designed to prevent the user from being able to describe buggy or incorrect hardware as much as possible. This enables a user to hack on designs fearlessly, while the API and generators ensure that these designs are sound.


kaze = "0.1"


use kaze::*;

fn main() -> std::io::Result<()> {
    // Create a context, which will contain our module(s)
    let c = Context::new();

    // Create a module
    let inverter = c.module("Inverter");
    let i = inverter.input("i", 1); // 1-bit input
    inverter.output("o", !i); // Output inverted input

    // Generate Rust simulator code
    sim::generate(inverter, std::io::stdout())?;

    // Generate Verilog code
    verilog::generate(inverter, std::io::stdout())?;



See changelog for release information.


Licensed under either of

at your option.


Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

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