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tree-wide: fix assorted typos all over the place

That is "success", "unknown", "through", "performance", "[re|un]mapping"
, "access", "default", "reasonable", "[con]currently", "temperature"
, "channel", "[un]used", "application", "example","hierarchy", "therefore"
, "[over|under]flow", "contiguous", "threshold", "enough" and others.

Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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andre-rosa authored and Jiri Kosina committed Nov 14, 2009
1 parent 972b94f commit af901ca181d92aac3a7dc265144a9081a86d8f39
Showing 345 changed files with 516 additions and 508 deletions.
@@ -8,7 +8,7 @@ Description:
1 - major number
2 - minor mumber
3 - device name
- 4 - reads completed succesfully
+ 4 - reads completed successfully
5 - reads merged
6 - sectors read
7 - time spent reading (ms)
@@ -4,7 +4,7 @@ Contact: Jerome Marchand <jmarchan@redhat.com>
Description:
The /sys/block/<disk>/stat files displays the I/O
statistics of disk <disk>. They contain 11 fields:
- 1 - reads completed succesfully
+ 1 - reads completed successfully
2 - reads merged
3 - sectors read
4 - time spent reading (ms)
@@ -362,7 +362,7 @@ module_exit(board_cleanup);
<sect1 id="Multiple_chip_control">
<title>Multiple chip control</title>
<para>
- The nand driver can control chip arrays. Therefor the
+ The nand driver can control chip arrays. Therefore the
board driver must provide an own select_chip function. This
function must (de)select the requested chip.
The function pointer in the nand_chip structure must
@@ -492,7 +492,7 @@ struct <link linkend="v4l2-jpegcompression">v4l2_jpegcompression</link> {
* you do, leave them untouched.
* Inluding less markers will make the
* resulting code smaller, but there will
- * be fewer aplications which can read it.
+ * be fewer applications which can read it.
* The presence of the APP and COM marker
* is influenced by APP_len and COM_len
* ONLY, not by this property! */
@@ -5318,7 +5318,7 @@ struct _snd_pcm_runtime {
pages of the given size and map them onto the virtually contiguous
memory. The virtual pointer is addressed in runtime-&gt;dma_area.
The physical address (runtime-&gt;dma_addr) is set to zero,
- because the buffer is physically non-contigous.
+ because the buffer is physically non-contiguous.
The physical address table is set up in sgbuf-&gt;table.
You can get the physical address at a certain offset via
<function>snd_pcm_sgbuf_get_addr()</function>.
@@ -85,7 +85,7 @@ http://www.linuxtv.org/wiki/index.php/DVB_USB
- moved transfer control (pid filter, fifo control) from usb driver to frontend, it seems
better settled there (added xfer_ops-struct)
- created a common files for frontends (mc/p/mb)
- 2004-09-28 - added support for a new device (Unkown, vendor ID is Hyper-Paltek)
+ 2004-09-28 - added support for a new device (Unknown, vendor ID is Hyper-Paltek)
2004-09-20 - added support for a new device (Compro DVB-U2000), thanks
to Amaury Demol for reporting
- changed usb TS transfer method (several urbs, stopping transfer
@@ -304,7 +304,7 @@ static void *map_zeroed_pages(unsigned int num)
addr = mmap(NULL, getpagesize() * num,
PROT_READ|PROT_WRITE|PROT_EXEC, MAP_PRIVATE, fd, 0);
if (addr == MAP_FAILED)
- err(1, "Mmaping %u pages of /dev/zero", num);
+ err(1, "Mmapping %u pages of /dev/zero", num);
/*
* One neat mmap feature is that you can close the fd, and it
@@ -185,7 +185,7 @@ ii. FW enables WCE bit in Mode Sense cmd for drives that are configured
Disks are exposed with WCE=1. User is advised to enable Write Back
mode only when the controller has battery backup. At this time
Synhronize cache is not supported by the FW. Driver will short-cycle
- the cmd and return sucess without sending down to FW.
+ the cmd and return success without sending down to FW.
1 Release Date : Sun Jan. 14 11:21:32 PDT 2007 -
Sumant Patro <Sumant.Patro@lsil.com>/Bo Yang
@@ -538,7 +538,7 @@ SPI MESSAGE QUEUE
The bulk of the driver will be managing the I/O queue fed by transfer().
That queue could be purely conceptual. For example, a driver used only
-for low-frequency sensor acess might be fine using synchronous PIO.
+for low-frequency sensor access might be fine using synchronous PIO.
But the queue will probably be very real, using message->queue, PIO,
often DMA (especially if the root filesystem is in SPI flash), and
@@ -370,7 +370,7 @@ The default is 1 percent.
mmap_min_addr
This file indicates the amount of address space which a user process will
-be restricted from mmaping. Since kernel null dereference bugs could
+be restricted from mmapping. Since kernel null dereference bugs could
accidentally operate based on the information in the first couple of pages
of memory userspace processes should not be allowed to write to them. By
default this value is set to 0 and no protections will be enforced by the
@@ -6,7 +6,7 @@ The modules are:
xxxx vend:prod
----
-spca501 0000:0000 MystFromOri Unknow Camera
+spca501 0000:0000 MystFromOri Unknown Camera
m5602 0402:5602 ALi Video Camera Controller
spca501 040a:0002 Kodak DVC-325
spca500 040a:0300 Kodak EZ200
@@ -301,7 +301,7 @@ static char *page_flag_name(uint64_t flags)
present = (flags >> i) & 1;
if (!page_flag_names[i]) {
if (present)
- fatal("unkown flag bit %d\n", i);
+ fatal("unknown flag bit %d\n", i);
continue;
}
buf[j++] = present ? page_flag_names[i][0] : '_';
View
@@ -197,7 +197,7 @@ setup_memory_node(int nid, void *kernel_end)
}
if (bootmap_start == -1)
- panic("couldn't find a contigous place for the bootmap");
+ panic("couldn't find a contiguous place for the bootmap");
/* Allocate the bootmap and mark the whole MM as reserved. */
bootmap_size = init_bootmem_node(NODE_DATA(nid), bootmap_start,
View
@@ -82,7 +82,7 @@ static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
- /* XXX: I'm usure, but it seems so */
+ /* XXX: I'm unsure, but it seems so */
return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1));
}
@@ -83,7 +83,7 @@ typedef struct {
* @brief Get next available transaction width
*
*
-* @return On sucess : Next avail able transaction width
+* @return On success : Next available transaction width
* On failure : dmacHw_TRANSACTION_WIDTH_8
*
* @note
@@ -651,7 +651,7 @@ int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about t
/**
* Creates a descriptor ring from a memory mapping.
*
-* @return 0 on sucess, error code otherwise.
+* @return 0 on success, error code otherwise.
*/
/****************************************************************************/
@@ -31,7 +31,7 @@
/*
* This __REG() version gives the same results as the one above, except
* that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers. It's a shame that gcc
+ * assembly code for access to contiguous registers. It's a shame that gcc
* doesn't guess this by itself.
*/
#include <asm/types.h>
@@ -463,7 +463,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
writel(win_enable, PCI_BAR_ENABLE);
/*
- * Disable automatic update of address remaping when writing to BARs.
+ * Disable automatic update of address remapping when writing to BARs.
*/
orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
}
@@ -91,7 +91,7 @@
/* BATTERY */
#define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */
#define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */
-#define PALMLD_BAT_MAX_CURRENT 0 /* unknokn */
+#define PALMLD_BAT_MAX_CURRENT 0 /* unknown */
#define PALMLD_BAT_MIN_CURRENT 0 /* unknown */
#define PALMLD_BAT_MAX_CHARGE 1 /* unknown */
#define PALMLD_BAT_MIN_CHARGE 1 /* unknown */
@@ -66,7 +66,7 @@
/* BATTERY */
#define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
-#define PALMT5_BAT_MAX_CURRENT 0 /* unknokn */
+#define PALMT5_BAT_MAX_CURRENT 0 /* unknown */
#define PALMT5_BAT_MIN_CURRENT 0 /* unknown */
#define PALMT5_BAT_MAX_CHARGE 1 /* unknown */
#define PALMT5_BAT_MIN_CHARGE 1 /* unknown */
@@ -68,7 +68,7 @@
/* BATTERY */
#define PALMTC_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */
#define PALMTC_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */
-#define PALMTC_BAT_MAX_CURRENT 0 /* unknokn */
+#define PALMTC_BAT_MAX_CURRENT 0 /* unknown */
#define PALMTC_BAT_MIN_CURRENT 0 /* unknown */
#define PALMTC_BAT_MAX_CHARGE 1 /* unknown */
#define PALMTC_BAT_MIN_CHARGE 1 /* unknown */
@@ -59,7 +59,7 @@
/* BATTERY */
#define PALMTE2_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMTE2_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
-#define PALMTE2_BAT_MAX_CURRENT 0 /* unknokn */
+#define PALMTE2_BAT_MAX_CURRENT 0 /* unknown */
#define PALMTE2_BAT_MIN_CURRENT 0 /* unknown */
#define PALMTE2_BAT_MAX_CHARGE 1 /* unknown */
#define PALMTE2_BAT_MIN_CHARGE 1 /* unknown */
@@ -94,7 +94,7 @@
/* BATTERY */
#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
-#define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */
+#define PALMTX_BAT_MAX_CURRENT 0 /* unknown */
#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */
#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */
#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */
@@ -49,7 +49,7 @@
/* Battery */
#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
-#define PALMZ72_BAT_MAX_CURRENT 0 /* unknokn */
+#define PALMZ72_BAT_MAX_CURRENT 0 /* unknown */
#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */
#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */
#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */
@@ -30,7 +30,7 @@ char *s3c6400_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
- /* [3] = "48m", - note not succesfully used yet */
+ /* [3] = "48m", - note not successfully used yet */
};
void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
@@ -30,7 +30,7 @@ char *s3c6410_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
- /* [3] = "48m", - note not succesfully used yet */
+ /* [3] = "48m", - note not successfully used yet */
};
@@ -65,7 +65,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
/**
- * sa1100_request_dma - allocate one of the SA11x0's DMA chanels
+ * sa1100_request_dma - allocate one of the SA11x0's DMA channels
* @device: The SA11x0 peripheral targeted by this request
* @device_id: An ascii name for the claiming device
* @callback: Function to be called when the DMA completes
@@ -112,7 +112,7 @@ enum iomux_gp_func {
* setups a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
- * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
+ * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
*/
int mxc_iomux_alloc_pin(const unsigned int pin, const char *label);
/*
@@ -48,7 +48,7 @@
* setups a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
- * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
+ * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
*/
int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
/*
View
@@ -94,7 +94,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
* register to follow the ratio of duty_ns vs. period_ns
* accordingly.
*
- * This is good enought for programming the brightness of
+ * This is good enough for programming the brightness of
* the LCD backlight.
*
* The real implementation would divide PERCLK[0] first by
View
@@ -1232,7 +1232,7 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
* OMAP_DMA_DYNAMIC_CHAIN
* @params - Channel parameters
*
- * @return - Succes : 0
+ * @return - Success : 0
* Failure: -EINVAL/-ENOMEM
*/
int omap_request_dma_chain(int dev_id, const char *dev_name,
@@ -124,7 +124,7 @@
#define TIPB_SWITCH_BASE (0xfffbc800)
#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
-/* UART3 Registers Maping through MPU bus */
+/* UART3 Registers Mapping through MPU bus */
#define UART3_RHR (OMAP_UART3_BASE + 0)
#define UART3_THR (OMAP_UART3_BASE + 0)
#define UART3_DLL (OMAP_UART3_BASE + 0)
@@ -64,7 +64,7 @@
/* the calculation for the VA of this must ensure that
* it is the same distance apart from the UART in the
* phsyical address space, as the initial mapping for the IO
- * is done as a 1:1 maping. This puts it (currently) at
+ * is done as a 1:1 mapping. This puts it (currently) at
* 0xFA800000, which is not in the way of any current mapping
* by the base system.
*/
@@ -24,7 +24,7 @@ config BOARD_HAMMERHEAD_SND
bool "Atmel AC97 Sound support"
help
This enables Sound support for the Hammerhead board. You may
- also go trough the ALSA settings to get it working.
+ also go through the ALSA settings to get it working.
Choose 'Y' here if you have ordered a Corona daugther board and
want to make your board funky.
@@ -619,7 +619,7 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
/*
* Similar to get_user, do some address checking, then dereference
- * Return true on sucess, false on bad address
+ * Return true on success, false on bad address
*/
static bool get_instruction(unsigned short *val, unsigned short *address)
{
@@ -542,15 +542,15 @@
#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
@@ -544,15 +544,15 @@
#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
@@ -934,15 +934,15 @@
#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
@@ -491,7 +491,7 @@
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
@@ -501,7 +501,7 @@
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
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