diff --git a/meta-zephyr-sdk/recipes-devtools/arc_qemu/arc-qemu_git.bb b/meta-zephyr-sdk/recipes-devtools/arc_qemu/arc-qemu_git.bb new file mode 100644 index 00000000..71d65a71 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/arc_qemu/arc-qemu_git.bb @@ -0,0 +1,234 @@ + +DEPENDS = "glib-2.0 zlib pixman gnutls libtasn1 dtc ninja-native meson-native" +LICENSE = "GPLv2" +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" +LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ + file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" + +SRCREV = "2625a6fbc3f60233e1d340931d00242d82230091" +SRC_URI = "git://github.com/foss-for-synopsys-dwc-arc-processors/qemu.git;protocol=https \ + file://cross.patch \ +" + +BBCLASSEXTEND = "native nativesdk" +INHIBIT_PACKAGE_DEBUG_SPLIT = "1" +INHIBIT_PACKAGE_STRIP = "1" + +S = "${WORKDIR}/git" + +arc_qemu_prefix = "${base_prefix}/usr/synopsys" + +inherit autotools pkgconfig + +# Standard options: +# --prefix=PREFIX install in PREFIX [$prefix] +# --interp-prefix=PREFIX where to find shared libraries, etc. +# use %M for cpu name [$interp_prefix] +# --target-list=LIST set target list (default: build everything) +# $(echo Available targets: $default_target_list | \ +# fold -s -w 53 | sed -e 's/^/ /') +# +# Advanced options (experts only): +# --source-path=PATH path of source code [$source_path] +# --cross-prefix=PREFIX use PREFIX for compile tools [$cross_prefix] +# --cc=CC use C compiler CC [$cc] +# --iasl=IASL use ACPI compiler IASL [$iasl] +# --host-cc=CC use C compiler CC [$host_cc] for code run at +# build time +# --cxx=CXX use C++ compiler CXX [$cxx] +# --objcc=OBJCC use Objective-C compiler OBJCC [$objcc] +# --extra-cflags=CFLAGS append extra C compiler flags QEMU_CFLAGS +# --extra-ldflags=LDFLAGS append extra linker flags LDFLAGS +# --make=MAKE use specified make [$make] +# --install=INSTALL use specified install [$install] +# --python=PYTHON use specified python [$python] +# --smbd=SMBD use specified smbd [$smbd] +# --static enable static build [$static] +# --mandir=PATH install man pages in PATH +# --datadir=PATH install firmware in PATH$confsuffix +# --docdir=PATH install documentation in PATH$confsuffix +# --bindir=PATH install binaries in PATH +# --libdir=PATH install libraries in PATH +# --sysconfdir=PATH install config in PATH$confsuffix +# --localstatedir=PATH install local state in PATH (set at runtime on win32) +# --with-confsuffix=SUFFIX suffix for QEMU data inside datadir/libdir/sysconfdir [$confsuffix] +# --enable-modules enable modules support +# --enable-debug-tcg enable TCG debugging +# --disable-debug-tcg disable TCG debugging (default) +# --enable-debug-info enable debugging information (default) +# --disable-debug-info disable debugging information +# --enable-debug enable common debug build options +# --enable-sparse enable sparse checker +# --disable-sparse disable sparse checker (default) +# --disable-strip disable stripping binaries +# --disable-werror disable compilation abort on warning +# --disable-stack-protector disable compiler-provided stack protection +# --disable-sdl disable SDL +# --enable-sdl enable SDL +# --with-sdlabi select preferred SDL ABI 1.2 or 2.0 +# --disable-gtk disable gtk UI +# --enable-gtk enable gtk UI +# --with-gtkabi select preferred GTK ABI 2.0 or 3.0 +# --disable-virtfs disable VirtFS +# --enable-virtfs enable VirtFS +# --disable-vnc disable VNC +# --enable-vnc enable VNC +# --disable-cocoa disable Cocoa (Mac OS X only) +# --enable-cocoa enable Cocoa (default on Mac OS X) +# --audio-drv-list=LIST set audio drivers list: +# Available drivers: $audio_possible_drivers +# --block-drv-whitelist=L Same as --block-drv-rw-whitelist=L +# --block-drv-rw-whitelist=L +# set block driver read-write whitelist +# (affects only QEMU, not qemu-img) +# --block-drv-ro-whitelist=L +# set block driver read-only whitelist +# (affects only QEMU, not qemu-img) +# --disable-xen disable xen backend driver support +# --enable-xen enable xen backend driver support +# --disable-xen-pci-passthrough +# --enable-xen-pci-passthrough +# --disable-brlapi disable BrlAPI +# --enable-brlapi enable BrlAPI +# --disable-vnc-tls disable TLS encryption for VNC server +# --enable-vnc-tls enable TLS encryption for VNC server +# --disable-vnc-sasl disable SASL encryption for VNC server +# --enable-vnc-sasl enable SASL encryption for VNC server +# --disable-vnc-jpeg disable JPEG lossy compression for VNC server +# --enable-vnc-jpeg enable JPEG lossy compression for VNC server +# --disable-vnc-png disable PNG compression for VNC server (default) +# --enable-vnc-png enable PNG compression for VNC server +# --disable-vnc-ws disable Websockets support for VNC server +# --enable-vnc-ws enable Websockets support for VNC server +# --disable-curses disable curses output +# --enable-curses enable curses output +# --disable-curl disable curl connectivity +# --enable-curl enable curl connectivity +# --disable-fdt disable fdt device tree +# --enable-fdt enable fdt device tree +# --disable-bluez disable bluez stack connectivity +# --enable-bluez enable bluez stack connectivity +# --disable-slirp disable SLIRP userspace network connectivity +# --disable-kvm disable KVM acceleration support +# --enable-kvm enable KVM acceleration support +# --disable-rdma disable RDMA-based migration support +# --enable-rdma enable RDMA-based migration support +# --enable-tcg-interpreter enable TCG with bytecode interpreter (TCI) +# --enable-system enable all system emulation targets +# --disable-system disable all system emulation targets +# --enable-user enable supported user emulation targets +# --disable-user disable all user emulation targets +# --enable-linux-user enable all linux usermode emulation targets +# --disable-linux-user disable all linux usermode emulation targets +# --enable-bsd-user enable all BSD usermode emulation targets +# --disable-bsd-user disable all BSD usermode emulation targets +# --enable-guest-base enable GUEST_BASE support for usermode +# emulation targets +# --disable-guest-base disable GUEST_BASE support +# --enable-pie build Position Independent Executables +# --disable-pie do not build Position Independent Executables +# --fmod-lib path to FMOD library +# --fmod-inc path to FMOD includes +# --oss-lib path to OSS library +# --cpu=CPU Build for host CPU [$cpu] +# --enable-uuid enable uuid support +# --disable-vde disable support for vde network +# --enable-vde enable support for vde network +# --disable-netmap disable support for netmap network +# --enable-netmap enable support for netmap network +# --disable-linux-aio disable Linux AIO support +# --enable-linux-aio enable Linux AIO support +# --disable-cap-ng disable libcap-ng support +# --enable-cap-ng enable libcap-ng support +# --disable-attr disables attr and xattr support +# --enable-attr enable attr and xattr support +# --disable-blobs disable installing provided firmware blobs +# --enable-docs enable documentation build +# --disable-docs disable documentation build +# --disable-vhost-net disable vhost-net acceleration support +# --enable-vhost-net enable vhost-net acceleration support +# --enable-trace-backends=B Set trace backend +# Available backends: $($python $source_path/scripts/tracetool.py --list-backends) +# --with-trace-file=NAME Full PATH,NAME of file to store traces +# Default:trace- +# --disable-spice disable spice +# --enable-spice enable spice +# --enable-rbd enable building the rados block device (rbd) +# --disable-libiscsi disable iscsi support +# --enable-libiscsi enable iscsi support +# --disable-libnfs disable nfs support +# --enable-libnfs enable nfs support +# --disable-smartcard-nss disable smartcard nss support +# --enable-smartcard-nss enable smartcard nss support +# --disable-libusb disable libusb (for usb passthrough) +# --enable-libusb enable libusb (for usb passthrough) +# --disable-usb-redir disable usb network redirection support +# --enable-usb-redir enable usb network redirection support +# --enable-lzo enable the support of lzo compression library +# --enable-snappy enable the support of snappy compression library +# --disable-guest-agent disable building of the QEMU Guest Agent +# --enable-guest-agent enable building of the QEMU Guest Agent +# --with-vss-sdk=SDK-path enable Windows VSS support in QEMU Guest Agent +# --with-win-sdk=SDK-path path to Windows Platform SDK (to build VSS .tlb) +# --disable-seccomp disable seccomp support +# --enable-seccomp enables seccomp support +# --with-coroutine=BACKEND coroutine backend. Supported options: +# gthread, ucontext, sigaltstack, windows +# --disable-coroutine-pool disable coroutine freelist (worse performance) +# --enable-coroutine-pool enable coroutine freelist (better performance) +# --enable-glusterfs enable GlusterFS backend +# --disable-glusterfs disable GlusterFS backend +# --enable-gcov enable test coverage analysis with gcov +# --gcov=GCOV use specified gcov [$gcov_tool] +# --disable-tpm disable TPM support +# --enable-tpm enable TPM support +# --disable-libssh2 disable ssh block device support +# --enable-libssh2 enable ssh block device support +# --disable-vhdx disables support for the Microsoft VHDX image format +# --enable-vhdx enable support for the Microsoft VHDX image format +# --disable-quorum disable quorum block filter support +# --enable-quorum enable quorum block filter support +# --disable-numa disable libnuma support +# --enable-numa enable libnuma support + + +QEMUS_BUILT = "arc-softmmu arc64-softmmu" +QEMU_FLAGS = "--disable-docs --disable-sdl --disable-debug-info --disable-cap-ng \ + --disable-libnfs --disable-libusb --disable-libiscsi --disable-usb-redir --disable-linux-aio\ + --disable-guest-agent --disable-libssh --disable-vnc-png --disable-seccomp \ + --disable-tpm --disable-numa --disable-glusterfs \ + --disable-virtfs --disable-xen --disable-curl --disable-attr --disable-curses --disable-iconv \ + --disable-kvm --disable-parallels --disable-replication \ + --disable-live-block-migration --disable-dmg --disable-fdt --disable-blobs \ + " + +# NOTE: Once --prefix is set, QEMU configure script automatically figures out adequate sysconfdir, +# libexecdir and localstatedir based on the prefix directory; therefore, it is not necessary +# to manually specify these directories. Using the global directory variables to specify +# these directories will lead to shared file conflict with the upstream QEMU that resides in +# /usr. + +do_configure() { + # Unset the install path environment variables set by the BitBake because the new configure + # script picks these up, and that interferes with prefix-based install path resolution. + unset libdir + unset libexecdir + unset includedir + unset bindir + unset mandir + unset datadir + unset docdir + unset sysconfdir + unset local_statedir + unset firmwarepath + unset localedir + + ${S}/configure ${QEMU_FLAGS} --target-list="${QEMUS_BUILT}" --prefix=${arc_qemu_prefix} \ + --meson=meson +} + +FILES_${PN} = " \ + /opt/zephyr-sdk \ + " + +INSANE_SKIP_${PN} = "already-stripped" diff --git a/meta-zephyr-sdk/recipes-devtools/arc_qemu/files/cross.patch b/meta-zephyr-sdk/recipes-devtools/arc_qemu/files/cross.patch new file mode 100644 index 00000000..618a6036 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/arc_qemu/files/cross.patch @@ -0,0 +1,30 @@ +We need to be able to trigger configure's cross code but we don't want +to set cross_prefix as it does other things we don't want. Patch things +so we can do what we need in the target config case. + +Upstream-Status: Inappropriate [may be rewritten in a way upstream may accept?] +Signed-off-by: Richard Purdie + + +Index: qemu/configure +=================================================================== +--- a/configure ++++ b/configure +@@ -3934,7 +3934,6 @@ if test "$skip_meson" = no; then + fi + echo "strip = [$(meson_quote $strip)]" >> $cross + echo "windres = [$(meson_quote $windres)]" >> $cross +- if test "$cross_compile" = "yes"; then + cross_arg="--cross-file config-meson.cross" + echo "[host_machine]" >> $cross + if test "$mingw32" = "yes" ; then +@@ -3966,9 +3965,6 @@ if test "$skip_meson" = no; then + else + echo "endian = 'little'" >> $cross + fi +- else +- cross_arg="--native-file config-meson.cross" +- fi + mv $cross config-meson.cross + + rm -rf meson-private meson-info meson-logs diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson.inc b/meta-zephyr-sdk/recipes-devtools/meson/meson.inc new file mode 100644 index 00000000..3d29d5dc --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson.inc @@ -0,0 +1,37 @@ +HOMEPAGE = "http://mesonbuild.com" +SUMMARY = "A high performance build system" +DESCRIPTION = "Meson is a build system designed to increase programmer \ +productivity. It does this by providing a fast, simple and easy to use \ +interface for modern software development tools and practices." + +LICENSE = "Apache-2.0" +LIC_FILES_CHKSUM = "file://COPYING;md5=3b83ef96387f14655fc854ddc3c6bd57" + +SRC_URI = "https://github.com/mesonbuild/meson/releases/download/${PV}/meson-${PV}.tar.gz \ + file://0001-gtkdoc-fix-issues-that-arise-when-cross-compiling.patch \ + file://0001-python-module-do-not-manipulate-the-environment-when.patch \ + file://disable-rpath-handling.patch \ + file://0001-modules-python.py-do-not-substitute-python-s-install.patch \ + file://0001-Make-CPU-family-warnings-fatal.patch \ + file://0002-Support-building-allarch-recipes-again.patch \ + " +SRC_URI[sha256sum] = "db586a451650d46bbe10984a87b79d9bcdc1caebf38d8e189f8848f8d502356d" + +UPSTREAM_CHECK_URI = "https://github.com/mesonbuild/meson/releases" +UPSTREAM_CHECK_REGEX = "meson-(?P\d+(\.\d+)+)\.tar" + +inherit setuptools3 + +RDEPENDS_${PN} = "ninja python3-modules python3-pkg-resources" + +FILES_${PN} += "${datadir}/polkit-1" + +do_install_append () { + # As per the same issue in the python recipe itself: + # Unfortunately the following pyc files are non-deterministc due to 'frozenset' + # being written without strict ordering, even with PYTHONHASHSEED = 0 + # Upstream is discussing ways to solve the issue properly, until then let's + # just not install the problematic files. + # More info: http://benno.id.au/blog/2013/01/15/python-determinism + rm ${D}${libdir}/python*/site-packages/mesonbuild/dependencies/__pycache__/mpi.cpython* +} diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-Make-CPU-family-warnings-fatal.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-Make-CPU-family-warnings-fatal.patch new file mode 100644 index 00000000..c5be526b --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-Make-CPU-family-warnings-fatal.patch @@ -0,0 +1,41 @@ +From 6c4eef1d92e9e42fdbc888365cab3c95fb33c605 Mon Sep 17 00:00:00 2001 +From: Ross Burton +Date: Tue, 3 Jul 2018 13:59:09 +0100 +Subject: [PATCH] Make CPU family warnings fatal + +Upstream-Status: Inappropriate [OE specific] +Signed-off-by: Ross Burton + +--- + mesonbuild/envconfig.py | 2 +- + mesonbuild/environment.py | 4 +--- + 2 files changed, 2 insertions(+), 4 deletions(-) + +diff --git a/mesonbuild/envconfig.py b/mesonbuild/envconfig.py +index 307aac3..66fb7ec 100644 +--- a/mesonbuild/envconfig.py ++++ b/mesonbuild/envconfig.py +@@ -267,7 +267,7 @@ class MachineInfo(HoldableObject): + + cpu_family = literal['cpu_family'] + if cpu_family not in known_cpu_families: +- mlog.warning(f'Unknown CPU family {cpu_family}, please report this at https://github.com/mesonbuild/meson/issues/new') ++ raise EnvironmentException('Unknown CPU family {}, see https://wiki.yoctoproject.org/wiki/Meson/UnknownCPU for directions.'.format(cpu_family)) + + endian = literal['endian'] + if endian not in ('little', 'big'): +diff --git a/mesonbuild/environment.py b/mesonbuild/environment.py +index 71286a5..179917e 100644 +--- a/mesonbuild/environment.py ++++ b/mesonbuild/environment.py +@@ -352,9 +352,7 @@ def detect_cpu_family(compilers: CompilersDict) -> str: + trial = 'ppc64' + + if trial not in known_cpu_families: +- mlog.warning(f'Unknown CPU family {trial!r}, please report this at ' +- 'https://github.com/mesonbuild/meson/issues/new with the ' +- 'output of `uname -a` and `cat /proc/cpuinfo`') ++ raise EnvironmentException('Unknown CPU family %s, see https://wiki.yoctoproject.org/wiki/Meson/UnknownCPU for directions.' % trial) + + return trial + diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-gtkdoc-fix-issues-that-arise-when-cross-compiling.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-gtkdoc-fix-issues-that-arise-when-cross-compiling.patch new file mode 100644 index 00000000..ce90e515 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-gtkdoc-fix-issues-that-arise-when-cross-compiling.patch @@ -0,0 +1,36 @@ +From 2f9c59e0489e569c5382404667c10f5c200a72ad Mon Sep 17 00:00:00 2001 +From: Alexander Kanavin +Date: Fri, 4 Aug 2017 16:16:41 +0300 +Subject: [PATCH] gtkdoc: fix issues that arise when cross-compiling + +Specifically: +1) Make it possible to specify a wrapper for executing binaries +(usually, some kind of target hardware emulator, such as qemu) +2) Explicitly provide CC and LD via command line, as otherwise gtk-doc will +try to guess them, incorrectly. +3) If things break down, print the full command with arguments, +not just the binary name. +4) Correctly determine the compiler/linker executables and cross-options when cross-compiling + +Upstream-Status: Pending +Signed-off-by: Alexander Kanavin + +--- + mesonbuild/modules/gnome.py | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/mesonbuild/modules/gnome.py b/mesonbuild/modules/gnome.py +index dc2979e..c9ff9bd 100644 +--- a/mesonbuild/modules/gnome.py ++++ b/mesonbuild/modules/gnome.py +@@ -1053,6 +1053,10 @@ class GnomeModule(ExtensionModule): + args.append(f'--{program_name}={path}') + if namespace: + args.append('--namespace=' + namespace) ++ gtkdoc_exe_wrapper = state.environment.properties.host.get('gtkdoc_exe_wrapper', None) ++ if gtkdoc_exe_wrapper is not None: ++ args.append('--run=' + gtkdoc_exe_wrapper) ++ + args += self._unpack_args('--htmlargs=', 'html_args', kwargs) + args += self._unpack_args('--scanargs=', 'scan_args', kwargs) + args += self._unpack_args('--scanobjsargs=', 'scanobjs_args', kwargs) diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-modules-python.py-do-not-substitute-python-s-install.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-modules-python.py-do-not-substitute-python-s-install.patch new file mode 100644 index 00000000..231414fc --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-modules-python.py-do-not-substitute-python-s-install.patch @@ -0,0 +1,41 @@ +From f8f67c8d5c3f374b1e30e2d40cb56a79f0544471 Mon Sep 17 00:00:00 2001 +From: Alexander Kanavin +Date: Thu, 18 Apr 2019 17:36:11 +0200 +Subject: [PATCH] modules/python.py: do not substitute python's install prefix + with meson's + +Not sure why this is being done, but it +a) relies on Python's internal variable substitution which may break in the future +b) shouldn't be necessary as Python's prefix ought to be correct in the first place + +Upstream-Status: Pending +Signed-off-by: Alexander Kanavin + +--- + mesonbuild/modules/python.py | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/mesonbuild/modules/python.py b/mesonbuild/modules/python.py +index eda70ce..18edd15 100644 +--- a/mesonbuild/modules/python.py ++++ b/mesonbuild/modules/python.py +@@ -251,7 +251,7 @@ INTROSPECT_COMMAND = '''import sysconfig + import json + import sys + +-install_paths = sysconfig.get_paths(scheme='posix_prefix', vars={'base': '', 'platbase': '', 'installed_base': ''}) ++install_paths = sysconfig.get_paths(scheme='posix_prefix') + + def links_against_libpython(): + from distutils.core import Distribution, Extension +@@ -280,8 +280,8 @@ class PythonInstallation(ExternalProgramHolder): + self.variables = info['variables'] + self.paths = info['paths'] + install_paths = info['install_paths'] +- self.platlib_install_path = os.path.join(prefix, install_paths['platlib'][1:]) +- self.purelib_install_path = os.path.join(prefix, install_paths['purelib'][1:]) ++ self.platlib_install_path = install_paths['platlib'] ++ self.purelib_install_path = install_paths['purelib'] + self.version = info['version'] + self.platform = info['platform'] + self.is_pypy = info['is_pypy'] diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-python-module-do-not-manipulate-the-environment-when.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-python-module-do-not-manipulate-the-environment-when.patch new file mode 100644 index 00000000..fdadc686 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-python-module-do-not-manipulate-the-environment-when.patch @@ -0,0 +1,43 @@ +From 2264e67d7c2c22ca634fd26ea8ada6f0344ab280 Mon Sep 17 00:00:00 2001 +From: Alexander Kanavin +Date: Mon, 19 Nov 2018 14:24:26 +0100 +Subject: [PATCH] python module: do not manipulate the environment when calling + pkg-config + +Upstream-Status: Inappropriate [oe-core specific] +Signed-off-by: Alexander Kanavin + +--- + mesonbuild/modules/python.py | 12 ------------ + 1 file changed, 12 deletions(-) + +diff --git a/mesonbuild/modules/python.py b/mesonbuild/modules/python.py +index 422155b..aaf5844 100644 +--- a/mesonbuild/modules/python.py ++++ b/mesonbuild/modules/python.py +@@ -70,11 +70,6 @@ class PythonDependency(ExternalDependency): + old_pkg_libdir = os.environ.get('PKG_CONFIG_LIBDIR') + old_pkg_path = os.environ.get('PKG_CONFIG_PATH') + +- os.environ.pop('PKG_CONFIG_PATH', None) +- +- if pkg_libdir: +- os.environ['PKG_CONFIG_LIBDIR'] = pkg_libdir +- + try: + self.pkgdep = PkgConfigDependency(pkg_name, environment, kwargs) + mlog.debug(f'Found "{pkg_name}" via pkgconfig lookup in LIBPC ({pkg_libdir})') +@@ -83,13 +78,6 @@ class PythonDependency(ExternalDependency): + mlog.debug(f'"{pkg_name}" could not be found in LIBPC ({pkg_libdir})') + mlog.debug(e) + +- if old_pkg_path is not None: +- os.environ['PKG_CONFIG_PATH'] = old_pkg_path +- +- if old_pkg_libdir is not None: +- os.environ['PKG_CONFIG_LIBDIR'] = old_pkg_libdir +- else: +- os.environ.pop('PKG_CONFIG_LIBDIR', None) + else: + mlog.debug(f'"{pkg_name}" could not be found in LIBPC ({pkg_libdir}), this is likely due to a relocated python installation') + diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0002-Support-building-allarch-recipes-again.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0002-Support-building-allarch-recipes-again.patch new file mode 100644 index 00000000..dcc1ce9c --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/0002-Support-building-allarch-recipes-again.patch @@ -0,0 +1,28 @@ +From 656bf55fed01df2d2e2ad6d9d9887173cb16b85c Mon Sep 17 00:00:00 2001 +From: Peter Kjellerstedt +Date: Thu, 26 Jul 2018 16:32:49 +0200 +Subject: [PATCH 2/2] Support building allarch recipes again + +This registers "allarch" as a known CPU family. + +Upstream-Status: Inappropriate [OE specific] +Signed-off-by: Peter Kjellerstedt +--- + mesonbuild/envconfig.py | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/mesonbuild/envconfig.py b/mesonbuild/envconfig.py +index 4d58c91..ff01ad1 100644 +--- a/mesonbuild/envconfig.py ++++ b/mesonbuild/envconfig.py +@@ -36,6 +36,7 @@ from pathlib import Path + + + known_cpu_families = ( ++ 'allarch', + 'aarch64', + 'alpha', + 'arc', +-- +2.24.0 + diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/disable-rpath-handling.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/disable-rpath-handling.patch new file mode 100644 index 00000000..7c766c61 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/disable-rpath-handling.patch @@ -0,0 +1,35 @@ +From 27bbd3c9d8d86de545fcf6608564a14571c98a61 Mon Sep 17 00:00:00 2001 +From: Richard Purdie +Date: Fri, 23 Nov 2018 15:28:28 +0000 +Subject: [PATCH] meson: Disable rpath stripping at install time + +We need to allow our rpaths generated through the compiler flags to make it into +our binaries. Therefore disable the meson manipulations of these unless there +is a specific directive to do something differently in the project. + +RP 2018/11/23 + +Upstream-Status: Submitted [https://github.com/mesonbuild/meson/issues/2567] + +--- + mesonbuild/minstall.py | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/mesonbuild/minstall.py b/mesonbuild/minstall.py +index 212568a..06366d4 100644 +--- a/mesonbuild/minstall.py ++++ b/mesonbuild/minstall.py +@@ -653,8 +653,11 @@ class Installer: + if file_copied: + self.did_install_something = True + try: +- self.fix_rpath(outname, t.rpath_dirs_to_remove, install_rpath, final_path, +- install_name_mappings, verbose=False) ++ if install_rpath: ++ self.fix_rpath(outname, t.rpath_dirs_to_remove, install_rpath, final_path, ++ install_name_mappings, verbose=False) ++ else: ++ print("RPATH changes at install time disabled") + except SystemExit as e: + if isinstance(e.code, int) and e.code == 0: + pass diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-setup.py b/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-setup.py new file mode 100755 index 00000000..7ac4e3ad --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-setup.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 + +import os +import string +import sys + +class Template(string.Template): + delimiter = "@" + +class Environ(): + def __getitem__(self, name): + val = os.environ[name] + val = val.split() + if len(val) > 1: + val = ["'%s'" % x for x in val] + val = ', '.join(val) + val = '[%s]' % val + elif val: + val = "'%s'" % val.pop() + return val + +try: + sysroot = os.environ['OECORE_NATIVE_SYSROOT'] +except KeyError: + print("Not in environment setup, bailing") + sys.exit(1) + +template_file = os.path.join(sysroot, 'usr/share/meson/meson.cross.template') +cross_file = os.path.join(sysroot, 'usr/share/meson/%smeson.cross' % os.environ["TARGET_PREFIX"]) + +with open(template_file) as in_file: + template = in_file.read() + output = Template(template).substitute(Environ()) + with open(cross_file, "w") as out_file: + out_file.write(output) diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-wrapper b/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-wrapper new file mode 100755 index 00000000..d4ffe60f --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-wrapper @@ -0,0 +1,14 @@ +#!/bin/sh + +if [ -z "$OECORE_NATIVE_SYSROOT" ]; then + echo "OECORE_NATIVE_SYSROOT not set; are you in a Yocto SDK environment?" >&2 +fi + +# If these are set to a cross-compile path, meson will get confused and try to +# use them as native tools. Unset them to prevent this, as all the cross-compile +# config is already in meson.cross. +unset CC CXX CPP LD AR NM STRIP + +exec "$OECORE_NATIVE_SYSROOT/usr/bin/meson.real" \ + --cross-file "${OECORE_NATIVE_SYSROOT}/usr/share/meson/${TARGET_PREFIX}meson.cross" \ + "$@" diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson_0.59.1.bb b/meta-zephyr-sdk/recipes-devtools/meson/meson_0.59.1.bb new file mode 100644 index 00000000..de9b905c --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson_0.59.1.bb @@ -0,0 +1,4 @@ +include meson.inc + +BBCLASSEXTEND = "native" + diff --git a/meta-zephyr-sdk/recipes-devtools/meson/nativesdk-meson_0.59.1.bb b/meta-zephyr-sdk/recipes-devtools/meson/nativesdk-meson_0.59.1.bb new file mode 100644 index 00000000..67add2c2 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/nativesdk-meson_0.59.1.bb @@ -0,0 +1,65 @@ +include meson.inc + +inherit nativesdk +inherit siteinfo + +SRC_URI += "file://meson-setup.py \ + file://meson-wrapper" + +def meson_endian(prefix, d): + arch, os = d.getVar(prefix + "_ARCH"), d.getVar(prefix + "_OS") + sitedata = siteinfo_data_for_machine(arch, os, d) + if "endian-little" in sitedata: + return "little" + elif "endian-big" in sitedata: + return "big" + else: + bb.fatal("Cannot determine endianism for %s-%s" % (arch, os)) + +# The cross file logic is similar but not identical to that in meson.bbclass, +# since it's generating for an SDK rather than a cross-compile. Important +# differences are: +# - We can't set vars like CC, CXX, etc. yet because they will be filled in with +# real paths by meson-setup.sh when the SDK is extracted. +# - Some overrides aren't needed, since the SDK injects paths that take care of +# them. +do_install_append() { + install -d ${D}${datadir}/meson + cat >${D}${datadir}/meson/meson.cross.template < -Date: Mon, 12 Apr 2021 14:43:15 +0100 -Subject: [PATCH 01/16] hw/misc/mps2-scc: Add "QEMU interface" comment - -The MPS2 SCC device doesn't have any documentation of its properties; -add a "QEMU interface" format comment describing them. - -Signed-off-by: Peter Maydell -Reviewed-by: Richard Henderson ---- - include/hw/misc/mps2-scc.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h -index 49d070616a..ea261ea30d 100644 ---- a/include/hw/misc/mps2-scc.h -+++ b/include/hw/misc/mps2-scc.h -@@ -9,6 +9,18 @@ - * (at your option) any later version. - */ - -+/* -+ * This is a model of the Serial Communication Controller (SCC) -+ * block found in most MPS FPGA images. -+ * -+ * QEMU interface: -+ * + sysbus MMIO region 0: the register bank -+ * + QOM property "scc-cfg4": value of the read-only CFG4 register -+ * + QOM property "scc-aid": value of the read-only SCC_AID register -+ * + QOM property "scc-id": value of the read-only SCC_ID register -+ * + QOM property array "oscclk": reset values of the OSCCLK registers -+ * (which are accessed via the SYS_CFG channel provided by this device) -+ */ - #ifndef MPS2_SCC_H - #define MPS2_SCC_H - --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-hw-misc-mps2-scc-Support-using-CFG0-bit-0-for-remapp.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-hw-misc-mps2-scc-Support-using-CFG0-bit-0-for-remapp.patch deleted file mode 100644 index ca6014d2..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-hw-misc-mps2-scc-Support-using-CFG0-bit-0-for-remapp.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 6c88579eb30dc6e81bca150ba6be00547cc37185 Mon Sep 17 00:00:00 2001 -From: Peter Maydell -Date: Tue, 4 May 2021 13:09:11 +0100 -Subject: [PATCH 02/16] hw/misc/mps2-scc: Support using CFG0 bit 0 for - remapping -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -On some boards, SCC config register CFG0 bit 0 controls whether -parts of the board memory map are remapped. Support this with: - * a device property scc-cfg0 so the board can specify the - initial value of the CFG0 register - * an outbound GPIO line which tracks bit 0 and which the board - can wire up to provide the remapping - -Signed-off-by: Peter Maydell -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé -Message-id: 20210504120912.23094-3-peter.maydell@linaro.org ---- - hw/misc/mps2-scc.c | 13 ++++++++++--- - include/hw/misc/mps2-scc.h | 9 +++++++++ - 2 files changed, 19 insertions(+), 3 deletions(-) - -diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c -index c56aca86ad..b3b42a792c 100644 ---- a/hw/misc/mps2-scc.c -+++ b/hw/misc/mps2-scc.c -@@ -23,6 +23,7 @@ - #include "qemu/bitops.h" - #include "trace.h" - #include "hw/sysbus.h" -+#include "hw/irq.h" - #include "migration/vmstate.h" - #include "hw/registerfields.h" - #include "hw/misc/mps2-scc.h" -@@ -186,10 +187,13 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, - switch (offset) { - case A_CFG0: - /* -- * TODO on some boards bit 0 controls RAM remapping; -- * on others bit 1 is CPU_WAIT. -+ * On some boards bit 0 controls board-specific remapping; -+ * we always reflect bit 0 in the 'remap' GPIO output line, -+ * and let the board wire it up or not as it chooses. -+ * TODO on some boards bit 1 is CPU_WAIT. - */ - s->cfg0 = value; -+ qemu_set_irq(s->remap, s->cfg0 & 1); - break; - case A_CFG1: - s->cfg1 = value; -@@ -283,7 +287,7 @@ static void mps2_scc_reset(DeviceState *dev) - int i; - - trace_mps2_scc_reset(); -- s->cfg0 = 0; -+ s->cfg0 = s->cfg0_reset; - s->cfg1 = 0; - s->cfg2 = 0; - s->cfg5 = 0; -@@ -308,6 +312,7 @@ static void mps2_scc_init(Object *obj) - - memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000); - sysbus_init_mmio(sbd, &s->iomem); -+ qdev_init_gpio_out_named(DEVICE(obj), &s->remap, "remap", 1); - } - - static void mps2_scc_realize(DeviceState *dev, Error **errp) -@@ -353,6 +358,8 @@ static Property mps2_scc_properties[] = { - DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), - DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), - DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), -+ /* Reset value for CFG0 register */ -+ DEFINE_PROP_UINT32("scc-cfg0", MPS2SCC, cfg0_reset, 0), - /* - * These are the initial settings for the source clocks on the board. - * In hardware they can be configured via a config file read by the -diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h -index ea261ea30d..3b2d13ac9c 100644 ---- a/include/hw/misc/mps2-scc.h -+++ b/include/hw/misc/mps2-scc.h -@@ -18,8 +18,14 @@ - * + QOM property "scc-cfg4": value of the read-only CFG4 register - * + QOM property "scc-aid": value of the read-only SCC_AID register - * + QOM property "scc-id": value of the read-only SCC_ID register -+ * + QOM property "scc-cfg0": reset value of the CFG0 register - * + QOM property array "oscclk": reset values of the OSCCLK registers - * (which are accessed via the SYS_CFG channel provided by this device) -+ * + named GPIO output "remap": this tracks the value of CFG0 register -+ * bit 0. Boards where this bit controls memory remapping should -+ * connect this GPIO line to a function performing that mapping. -+ * Boards where bit 0 has no special function should leave the GPIO -+ * output disconnected. - */ - #ifndef MPS2_SCC_H - #define MPS2_SCC_H -@@ -55,6 +61,9 @@ struct MPS2SCC { - uint32_t num_oscclk; - uint32_t *oscclk; - uint32_t *oscclk_reset; -+ uint32_t cfg0_reset; -+ -+ qemu_irq remap; - }; - - #endif --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0003-hw-arm-mps2-tz-Implement-AN524-memory-remapping-via-.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0003-hw-arm-mps2-tz-Implement-AN524-memory-remapping-via-.patch deleted file mode 100644 index 57724a4f..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0003-hw-arm-mps2-tz-Implement-AN524-memory-remapping-via-.patch +++ /dev/null @@ -1,246 +0,0 @@ -From aefcd8789c4046d9612629060a6c8b0b98af753a Mon Sep 17 00:00:00 2001 -From: Peter Maydell -Date: Tue, 4 May 2021 13:09:12 +0100 -Subject: [PATCH 03/16] hw/arm/mps2-tz: Implement AN524 memory remapping via - machine property -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The AN524 FPGA image supports two memory maps, which differ in where -the QSPI and BRAM are. In the default map, the BRAM is at -0x0000_0000, and the QSPI at 0x2800_0000. In the second map, they -are the other way around. - -In hardware, the initial mapping can be selected by the user by -writing either "REMAP: BRAM" (the default) or "REMAP: QSPI" in the -board configuration file. The board config file is acted on by the -"Motherboard Configuration Controller", which is an entirely separate -microcontroller on the dev board but outside the FPGA. - -The guest can also dynamically change the mapping via the SCC -CFG_REG0 register. - -Implement this functionality for QEMU, using a machine property -"remap" with valid values "BRAM" and "QSPI" to allow the user to set -the initial mapping, in the same way they can on the FPGA, and -wiring up the bit from the SCC register to also switch the mapping. - -Signed-off-by: Peter Maydell -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé -Message-id: 20210504120912.23094-4-peter.maydell@linaro.org ---- - docs/system/arm/mps2.rst | 10 ++++ - hw/arm/mps2-tz.c | 108 ++++++++++++++++++++++++++++++++++++++- - 2 files changed, 117 insertions(+), 1 deletion(-) - -diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst -index f83b151787..8a75beb3a0 100644 ---- a/docs/system/arm/mps2.rst -+++ b/docs/system/arm/mps2.rst -@@ -45,3 +45,13 @@ Differences between QEMU and real hardware: - flash, but only as simple ROM, so attempting to rewrite the flash - from the guest will fail - - QEMU does not model the USB controller in MPS3 boards -+ -+Machine-specific options -+"""""""""""""""""""""""" -+ -+The following machine-specific options are supported: -+ -+remap -+ Supported for ``mps3-an524`` only. -+ Set ``BRAM``/``QSPI`` to select the initial memory mapping. The -+ default is ``BRAM``. -diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c -index 25016e464d..70aa31a7f6 100644 ---- a/hw/arm/mps2-tz.c -+++ b/hw/arm/mps2-tz.c -@@ -55,6 +55,7 @@ - #include "hw/boards.h" - #include "exec/address-spaces.h" - #include "sysemu/sysemu.h" -+#include "sysemu/reset.h" - #include "hw/misc/unimp.h" - #include "hw/char/cmsdk-apb-uart.h" - #include "hw/timer/cmsdk-apb-timer.h" -@@ -72,6 +73,7 @@ - #include "hw/core/split-irq.h" - #include "hw/qdev-clock.h" - #include "qom/object.h" -+#include "hw/irq.h" - - #define MPS2TZ_NUMIRQ_MAX 96 - #define MPS2TZ_RAM_MAX 5 -@@ -153,6 +155,9 @@ struct MPS2TZMachineState { - SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; - Clock *sysclk; - Clock *s32kclk; -+ -+ bool remap; -+ qemu_irq remap_irq; - }; - - #define TYPE_MPS2TZ_MACHINE "mps2tz" -@@ -228,6 +233,10 @@ static const RAMInfo an505_raminfo[] = { { - }, - }; - -+/* -+ * Note that the addresses and MPC numbering here should match up -+ * with those used in remap_memory(), which can swap the BRAM and QSPI. -+ */ - static const RAMInfo an524_raminfo[] = { { - .name = "bram", - .base = 0x00000000, -@@ -457,6 +466,7 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, - - object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); - sccdev = DEVICE(scc); -+ qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); - qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); - qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); - qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); -@@ -573,6 +583,52 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, - return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); - } - -+static hwaddr boot_mem_base(MPS2TZMachineState *mms) -+{ -+ /* -+ * Return the canonical address of the block which will be mapped -+ * at address 0x0 (i.e. where the vector table is). -+ * This is usually 0, but if the AN524 alternate memory map is -+ * enabled it will be the base address of the QSPI block. -+ */ -+ return mms->remap ? 0x28000000 : 0; -+} -+ -+static void remap_memory(MPS2TZMachineState *mms, int map) -+{ -+ /* -+ * Remap the memory for the AN524. 'map' is the value of -+ * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 -+ * for the "option 1" mapping where QSPI is at address 0. -+ * -+ * Effectively we need to swap around the "upstream" ends of -+ * MPC 0 and MPC 1. -+ */ -+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); -+ int i; -+ -+ if (mmc->fpga_type != FPGA_AN524) { -+ return; -+ } -+ -+ memory_region_transaction_begin(); -+ for (i = 0; i < 2; i++) { -+ TZMPC *mpc = &mms->mpc[i]; -+ MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); -+ hwaddr addr = (i ^ map) ? 0x28000000 : 0; -+ -+ memory_region_set_address(upstream, addr); -+ } -+ memory_region_transaction_commit(); -+} -+ -+static void remap_irq_fn(void *opaque, int n, int level) -+{ -+ MPS2TZMachineState *mms = opaque; -+ -+ remap_memory(mms, level); -+} -+ - static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size, - const int *irqs) -@@ -711,7 +767,7 @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms) - MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); - - for (p = mmc->raminfo; p->name; p++) { -- if (p->base == 0) { -+ if (p->base == boot_mem_base(mms)) { - return p->size; - } - } -@@ -1095,6 +1151,16 @@ static void mps2tz_common_init(MachineState *machine) - - create_non_mpc_ram(mms); - -+ if (mmc->fpga_type == FPGA_AN524) { -+ /* -+ * Connect the line from the SCC so that we can remap when the -+ * guest updates that register. -+ */ -+ mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); -+ qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, -+ mms->remap_irq); -+ } -+ - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, - boot_ram_size(mms)); - } -@@ -1117,12 +1183,47 @@ static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, - *iregion = region; - } - -+static char *mps2_get_remap(Object *obj, Error **errp) -+{ -+ MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); -+ const char *val = mms->remap ? "QSPI" : "BRAM"; -+ return g_strdup(val); -+} -+ -+static void mps2_set_remap(Object *obj, const char *value, Error **errp) -+{ -+ MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); -+ -+ if (!strcmp(value, "BRAM")) { -+ mms->remap = false; -+ } else if (!strcmp(value, "QSPI")) { -+ mms->remap = true; -+ } else { -+ error_setg(errp, "Invalid remap value"); -+ error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); -+ } -+} -+ -+static void mps2_machine_reset(MachineState *machine) -+{ -+ MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); -+ -+ /* -+ * Set the initial memory mapping before triggering the reset of -+ * the rest of the system, so that the guest image loader and CPU -+ * reset see the correct mapping. -+ */ -+ remap_memory(mms, mms->remap); -+ qemu_devices_reset(); -+} -+ - static void mps2tz_class_init(ObjectClass *oc, void *data) - { - MachineClass *mc = MACHINE_CLASS(oc); - IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); - - mc->init = mps2tz_common_init; -+ mc->reset = mps2_machine_reset; - iic->check = mps2_tz_idau_check; - } - -@@ -1225,6 +1326,11 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) - mmc->raminfo = an524_raminfo; - mmc->armsse_type = TYPE_SSE200; - mps2tz_set_default_ram_info(mmc); -+ -+ object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); -+ object_class_property_set_description(oc, "remap", -+ "Set memory mapping. Valid values " -+ "are BRAM (default) and QSPI."); - } - - static void mps3tz_an547_class_init(ObjectClass *oc, void *data) --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-qemu-nios2-Add-Altera-MAX-10-board-support-for-Zephy.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-qemu-nios2-Add-Altera-MAX-10-board-support-for-Zephy.patch deleted file mode 100644 index cf771e99..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-qemu-nios2-Add-Altera-MAX-10-board-support-for-Zephy.patch +++ /dev/null @@ -1,194 +0,0 @@ -From 28b2a8f91060dcf14bcfb9d60caa5caf399623a9 Mon Sep 17 00:00:00 2001 -From: Kumar Gala -Date: Thu, 25 Mar 2021 18:24:50 -0500 -Subject: [PATCH 04/16] qemu/nios2: Add Altera MAX 10 board support for Zephyr - OS - -Exisitng 10m50_devboard is not supporting qemu-niso2 on Zephyr OS -and the reason might be that the softcpu build may be different -for Linux and Zephyr OS. - -So added support for Zephyr qemu-nios2 board. - -Signed-off-by: Ramakrishna Pallala ---- - hw/nios2/altera_10m50_zephyr.c | 154 +++++++++++++++++++++++++++++++++ - hw/nios2/meson.build | 2 +- - 2 files changed, 155 insertions(+), 1 deletion(-) - create mode 100644 hw/nios2/altera_10m50_zephyr.c - -diff --git a/hw/nios2/altera_10m50_zephyr.c b/hw/nios2/altera_10m50_zephyr.c -new file mode 100644 -index 0000000000..4b3465429f ---- /dev/null -+++ b/hw/nios2/altera_10m50_zephyr.c -@@ -0,0 +1,154 @@ -+/* -+ * Copyright (c) 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, see . -+ */ -+ -+#include "qemu/osdep.h" -+#include "qapi/error.h" -+#include "qemu-common.h" -+#include "cpu.h" -+#include "hw/sysbus.h" -+#include "hw/hw.h" -+#include "hw/char/serial.h" -+#include "sysemu/sysemu.h" -+#include "sysemu/reset.h" -+#include "hw/qdev-properties.h" -+#include "hw/boards.h" -+#include "hw/loader.h" -+#include "exec/memory.h" -+#include "exec/address-spaces.h" -+#include "qemu/config-file.h" -+#include "qemu/option.h" -+#include "boot.h" -+ -+#define DEBUG -+ -+#ifdef DEBUG -+# define DPRINTF(format, ...) printf(format, ## __VA_ARGS__) -+#else -+# define DPRINTF(format, ...) do { } while (0) -+#endif -+ -+#define ROM_BASE 0x0 -+#define ROM_SIZE 32 -+ -+#define RAM_BASE 0x400000 -+#define RAM_SIZE 262144 -+ -+#define U16550_0_BASE 0x440000 -+#define U16550_0_IRQ_IDX 1 -+ -+#define TIMER_0_BASE 0x440200 -+#define TIMER_0_FREQ 50000000 -+#define TIMER_0_IRQ_IDX 2 -+ -+#define ALT_CPU_EXCEPTION_ADDR 0x00400020 -+#define ALT_CPU_RESET_ADDR 0x00000000 -+ -+#define EM_ALTERA_NIOS2 113 -+ -+static struct { -+ uint32_t bootstrap_pc; -+} boot_info_zephyr; -+ -+static void main_cpu_reset(void *opaque) -+{ -+ Nios2CPU *cpu = opaque; -+ CPUNios2State *env = &cpu->env; -+ -+ cpu_reset(CPU(cpu)); -+ env->regs[R_PC] = boot_info_zephyr.bootstrap_pc; -+} -+ -+static void altera_10m50_zephyr_init(MachineState *machine) -+{ -+ const char *kernel_filename; -+ MemoryRegion *sysmem = get_system_memory(); -+ Nios2CPU *cpu; -+ DeviceState *dev; -+ qemu_irq irq[32]; -+ int kernel_size; -+ int i; -+ -+ MemoryRegion *rom = g_new(MemoryRegion, 1); -+ MemoryRegion *ram = g_new(MemoryRegion, 1); -+ -+ cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU)); -+ object_property_set_bool(OBJECT(cpu), "mmu_present", false, -+ &error_abort); -+ object_property_set_bool(OBJECT(cpu), "realized", true, &error_abort); -+ -+ kernel_filename = current_machine->kernel_filename; -+ -+ memory_region_init_ram(rom, NULL, "nios2.rom", ROM_SIZE, &error_fatal); -+ memory_region_set_readonly(rom, true); -+ memory_region_add_subregion(sysmem, ROM_BASE, rom); -+ -+ memory_region_init_ram(ram, NULL, "nios2.ram", RAM_SIZE, &error_fatal); -+ memory_region_add_subregion(sysmem, RAM_BASE, ram); -+ -+ for (i = 0; i < 32; i++) { -+ irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); -+ } -+ -+ /* Register: Altera 16550 UART */ -+ serial_mm_init(sysmem, U16550_0_BASE, 2, irq[U16550_0_IRQ_IDX], -+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); -+ -+ /* Register: Timer sys_clk_timer */ -+ dev = qdev_new("ALTR.timer"); -+ qdev_prop_set_uint32(dev, "clock-frequency", TIMER_0_FREQ); -+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); -+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_0_BASE); -+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_0_IRQ_IDX]); -+ -+ cpu->reset_addr = ALT_CPU_RESET_ADDR; -+ cpu->exception_addr = ALT_CPU_EXCEPTION_ADDR; -+ cpu->fast_tlb_miss_addr = ALT_CPU_RESET_ADDR; -+ DPRINTF("\tcpu->env.reset_addr: \t\t%0x\n", cpu->reset_addr); -+ DPRINTF("\tcpu->env.exception_addr: \t%0x\n", cpu->exception_addr); -+ -+ if (kernel_filename) { -+ uint64_t entry; -+ -+ /* Boots a kernel elf binary. */ -+ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, -+ &entry, NULL, NULL, NULL, -+ 0, EM_ALTERA_NIOS2, 0, 0); -+ -+ boot_info_zephyr.bootstrap_pc = entry; -+ -+ /* Not an ELF image, try a RAW image. */ -+ if (kernel_size < 0) { -+ hwaddr uentry, loadaddr; -+ -+ kernel_size = load_uimage(kernel_filename, &uentry, -+ &loadaddr, 0, NULL, NULL); -+ boot_info_zephyr.bootstrap_pc = uentry; -+ } -+ -+ if (kernel_size < 0) { -+ fprintf(stderr, "qemu: could not load kernel '%s'\n", -+ kernel_filename); -+ exit(1); -+ } -+ } -+ qemu_register_reset(main_cpu_reset, cpu); -+ -+} -+ -+static void altera_10m50_zephyr_machine_init(MachineClass *mc) -+{ -+ mc->desc = "Altera 10m50 for Zephyr."; -+ mc->init = altera_10m50_zephyr_init; -+ mc->is_default = 0; -+} -+ -+DEFINE_MACHINE("altera_10m50_zephyr", altera_10m50_zephyr_machine_init) -diff --git a/hw/nios2/meson.build b/hw/nios2/meson.build -index 6c58e8082b..bc1dfcd70c 100644 ---- a/hw/nios2/meson.build -+++ b/hw/nios2/meson.build -@@ -1,6 +1,6 @@ - nios2_ss = ss.source_set() - nios2_ss.add(files('boot.c')) --nios2_ss.add(when: 'CONFIG_NIOS2_10M50', if_true: files('10m50_devboard.c')) -+nios2_ss.add(when: 'CONFIG_NIOS2_10M50', if_true: files('10m50_devboard.c', 'altera_10m50_zephyr.c')) - nios2_ss.add(when: 'CONFIG_NIOS2_GENERIC_NOMMU', if_true: files('generic_nommu.c')) - - hw_arch += {'nios2': nios2_ss} --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0005-hw-sparc-Add-leon-at697-machine.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0005-hw-sparc-Add-leon-at697-machine.patch deleted file mode 100644 index 55b28574..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0005-hw-sparc-Add-leon-at697-machine.patch +++ /dev/null @@ -1,980 +0,0 @@ -From d7e0be4e797c79198728a4b4d2dd6e7e7160bebf Mon Sep 17 00:00:00 2001 -From: Yasushi SHOJI -Date: Wed, 9 Mar 2016 12:22:16 +0100 -Subject: [PATCH 05/16] hw/sparc: Add leon (at697) machine - -This commit add LEON2 support. It is taken from AdaCore Qemu -repository at https://github.com/adacore/qemu. - -https://github.com/adacore/qemu/commit/9d94f4803 - -The following is the original commit message. - -> Part of K104-004. -> -> --- merged with --- -> -> Add plug-ins and GNATbus to leon -> -> --- merged with --- -> -> Add HostFs device to leon -> -> 2019-03-24 KONRAD Frederic -> * hw/sparc/leon.c: fix load_elf parameters. -> 2019-02-01 KONRAD Frederic -> * hw/sparc/leon.c: drop plugin. -> 2018-06-08 KONRAD Frederic -> * hw/sparc/leon.c: fixed against serial_hds disparition -> 2018-04-06 KONRAD Frederic -> * hw/sparc/leon.c: Use cpu_type instead of cpu_model which has been -> dropped. -> 2018-02-12 KONRAD Frederic -> * hw/sparc/leon.c: Update to new Chardev API. -> * hw/sparc/leon.c: Update to hostfs, gnatbus, plugin source -> reorganization. -> * hw/sparc/leon.c: Update leon2_intctl_ack prototype. -> -> Change-Id: I594757ad137370479b152e5de8de7be7caf9a911 - -Signed-off-by: Yasushi SHOJI ---- - hw/sparc/leon.c | 878 ++++++++++++++++++++++++++++++++++++++++++ - hw/sparc/meson.build | 1 + - hw/sparc/trace-events | 13 + - target/sparc/cpu.c | 2 +- - 4 files changed, 893 insertions(+), 1 deletion(-) - create mode 100644 hw/sparc/leon.c - -diff --git a/hw/sparc/leon.c b/hw/sparc/leon.c -new file mode 100644 -index 0000000000..316bd70288 ---- /dev/null -+++ b/hw/sparc/leon.c -@@ -0,0 +1,878 @@ -+/* -+ * QEMU Leon2 System Emulator -+ * -+ * Copyright (c) 2009-2013 AdaCore -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a copy -+ * of this software and associated documentation files (the "Software"), to deal -+ * in the Software without restriction, including without limitation the rights -+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -+ * copies of the Software, and to permit persons to whom the Software is -+ * furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -+ * THE SOFTWARE. -+ */ -+#include "qemu/osdep.h" -+#include "qapi/error.h" -+#include "cpu.h" -+#include "hw/hw.h" -+#include "qemu/timer.h" -+#include "chardev/char.h" -+#include "sysemu/sysemu.h" -+#include "hw/boards.h" -+#include "hw/loader.h" -+#include "elf.h" -+#include "trace.h" -+#include "hw/ptimer.h" -+#include "exec/memory.h" -+#include "exec/address-spaces.h" -+#include "hw/adacore/gnat-bus.h" -+#include "hw/adacore/hostfs.h" -+ -+/* Default system clock. */ -+#define CPU_CLK (50 * 1000 * 1000) -+ -+/* Leon registers */ -+ -+#define MEMORY_CONFIGURATION_REGISTER_1 0x00 -+#define MEMORY_CONFIGURATION_REGISTER_2 0x04 -+#define MEMORY_CONFIGURATION_REGISTER_3 0x08 -+#define FAIL_STATUS_REGISTER 0x10 -+ -+/* Cache Control register */ -+ -+#define CACHE_CONTROL_REGISTER 0x14 -+#define CCR_MASK 0x00e13fff -+#define CCR_INIT 0xf7100000 -+ -+/* Cache Control register fields */ -+ -+#define CACHE_STATE_MASK 0x3 -+#define CACHE_DISABLED 0x0 -+#define CACHE_FROZEN 0x1 -+#define CACHE_ENABLED 0x3 -+ -+#define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze On Interrupt */ -+#define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze On Interrupt */ -+#define CACHE_CTRL_DP (1 << 14) /* Data Cache Flush Pending */ -+#define CACHE_CTRL_IP (1 << 15) /* Instruction Cache Flush Pending */ -+#define CACHE_CTRL_IB (1 << 16) /* Instruction Burst Fetch */ -+#define CACHE_CTRL_FI (1 << 21) /* Flush Instruction Cache (Write Only) */ -+#define CACHE_CTRL_FD (1 << 22) /* Flush Data Cache (Write Only) */ -+ -+/* Timers registers */ -+ -+#define TIMER_1_COUNTER_REGISTER 0x40 -+#define TIMER_1_RELOAD_REGISTER 0x44 -+#define TIMER_1_CONTROL_REGISTER 0x48 -+#define WATCHDOG_REGISTER 0x4c -+#define TIMER_2_COUNTER_REGISTER 0x50 -+#define TIMER_2_RELOAD_REGISTER 0x54 -+#define TIMER_2_CONTROL_REGISTER 0x58 -+#define PRESCALER_COUNTER_REGISTER 0x60 -+#define PRESCALER_RELOAD_REGISTER 0x64 -+ -+/* Timers registers fields */ -+ -+#define TIMCTR_EN 0x01 /* Enable Counter */ -+#define TIMCTR_RL 0x02 /* Reload Counter */ -+#define TIMCTR_LD 0x04 /* Load Counter */ -+#define TIMCTR_MASK 0x07 -+ -+/* Interrupt controller registers */ -+ -+#define INTERRUPT_MASK_AND_PRIORITY_REGISTER 0x90 -+#define INTERRUPT_PENDING_REGISTER 0x94 -+#define INTERRUPT_FORCE_REGISTER 0x98 -+#define INTERRUPT_CLEAR_REGISTER 0x9c -+ -+/* IO registers */ -+ -+#define IO_PORT_DATA_REGISTER 0xa0 -+#define IO_PORT_DIRECTION_REGISTER 0xa4 -+#define IO_PORT_INTERRUPT_REGISTER 0xa8 -+ -+/* UART registers */ -+ -+#define UART_1_DATA_REGISTER 0x70 -+#define UART_1_STATUS_REGISTER 0x74 -+#define UART_1_CONTROL_REGISTER 0x78 -+#define UART_1_SCALER_REGISTER 0x7c -+#define UART_2_DATA_REGISTER 0x80 -+#define UART_2_STATUS_REGISTER 0x84 -+#define UART_2_CONTROL_REGISTER 0x88 -+#define UART_2_SCALER_REGISTER 0x8c -+ -+/* UART register fields */ -+ -+#define UART_STATUS_DR 0x01 /* Data Ready */ -+#define UART_STATUS_TS 0x02 /* Transmitter Shift Register Empty */ -+#define UART_STATUS_TH 0x04 /* Transmitter Hold Register Empty */ -+#define UART_STATUS_BR 0x08 /* Break Received */ -+#define UART_STATUS_OV 0x10 /* Overrun */ -+#define UART_STATUS_PE 0x20 /* Parity Error */ -+#define UART_STATUS_FE 0x40 /* Framing Error */ -+ -+#define UART_CONTROL_RE 0x001 /* Receiver Enable */ -+#define UART_CONTROL_TE 0x002 /* Transmitter Enable */ -+#define UART_CONTROL_RI 0x004 /* Receiver Interrupt Enable */ -+#define UART_CONTROL_TI 0x008 /* Transmitter Interrupt Enable */ -+#define UART_CONTROL_PS 0x010 /* Parity Select */ -+#define UART_CONTROL_PE 0x020 /* Parity Enable */ -+#define UART_CONTROL_FL 0x040 /* Flow Control */ -+#define UART_CONTROL_LB 0x080 /* Loop Back */ -+#define UART_CONTROL_EC 0x100 /* External Clock */ -+ -+ -+#define PROM_FILENAME "u-boot.bin" -+ -+#define MAX_PILS 16 -+ -+#define FIFO_LENGTH 1024 -+ -+typedef struct LeonUartState { -+ uint32_t status; -+ uint32_t control; -+ uint32_t scaler; -+ CharBackend chr; -+ qemu_irq irq; -+ -+ /* FIFO */ -+ char buffer[FIFO_LENGTH]; -+ int len; -+ int current; -+ -+} LeonUartState; -+ -+struct LeonTimerState { -+ QEMUBH *bh; -+ struct ptimer_state *ptimer; -+ -+ qemu_irq irq; -+ -+ int id; -+ -+ /* registers */ -+ uint32_t counter; -+ uint32_t reload; -+ uint32_t control; -+}; -+ -+struct LeonIntState { -+ uint32_t lvl_mask; -+ uint32_t pending; -+ uint32_t force; -+ CPUSPARCState *env; -+}; -+ -+typedef struct LeonIoState { -+ uint32_t mcfg[3]; -+ -+ struct LeonIntState intctl; -+ -+ uint32_t ccr; -+ uint32_t scar; -+ uint32_t wdg; -+ uint32_t iodata; -+ uint32_t iodir; -+ uint32_t ioit; -+ -+ struct LeonTimerState timer1; -+ struct LeonTimerState timer2; -+ -+ LeonUartState uart1; -+ LeonUartState uart2; -+} LeonIoState; -+ -+ -+typedef struct ResetData { -+ SPARCCPU *cpu; -+ uint32_t entry; /* save kernel entry in case of reset */ -+ uint32_t stack_pointer; -+} ResetData; -+ -+static void main_cpu_reset(void *opaque) -+{ -+ ResetData *s = (ResetData *)opaque; -+ CPUState *cpu = CPU(s->cpu); -+ CPUSPARCState *env = &s->cpu->env; -+ -+ cpu_reset(cpu); -+ -+ cpu->halted = 0; -+ env->pc = s->entry; -+ env->npc = s->entry + 4; -+ env->regbase[6] = s->stack_pointer; -+} -+ -+static void leon_check_irqs(struct LeonIntState *s) -+{ -+ uint32_t pend = 0; -+ uint32_t level0 = 0; -+ uint32_t level1 = 0; -+ CPUSPARCState *env = s->env; -+ CPUState *cs = CPU(sparc_env_get_cpu(env)); -+ -+ pend = (s->pending | s->force) & (s->lvl_mask & 0xfffe); -+ -+ level0 = pend & ~(s->lvl_mask >> 16); -+ level1 = pend & (s->lvl_mask >> 16); -+ -+ trace_leon_check_irqs(s->pending, s->force, -+ s->lvl_mask, level1, level0); -+ -+ /* Trigger level1 interrupt first and level0 if there is no level1 */ -+ if (level1 != 0) { -+ env->pil_in = level1; -+ } else { -+ env->pil_in = level0; -+ } -+ -+ if (env->pil_in && (env->interrupt_index == 0 || -+ (env->interrupt_index & ~15) == TT_EXTINT)) { -+ unsigned int i; -+ -+ for (i = 15; i > 0; i--) { -+ if (env->pil_in & (1 << i)) { -+ int old_interrupt = env->interrupt_index; -+ -+ env->interrupt_index = TT_EXTINT | i; -+ if (old_interrupt != env->interrupt_index) { -+ trace_leon_set_irq(i); -+ cpu_interrupt(cs, CPU_INTERRUPT_HARD); -+ } -+ break; -+ } -+ } -+ } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { -+ trace_leon_reset_irq(env->interrupt_index & 15); -+ env->interrupt_index = 0; -+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); -+ } -+} -+ -+static void leon2_intctl_ack(CPUSPARCState *env, int intno) -+{ -+ struct LeonIntState *intctl = env->irq_manager; -+ uint32_t mask; -+ uint32_t state = 0; -+ -+ intno &= 15; -+ mask = 1 << intno; -+ -+ trace_leon_intctl_ack(intno); -+ -+ /* Clear registers. */ -+ intctl->pending &= ~mask; -+ intctl->force &= ~mask; -+ -+ /* Cache Control */ -+ if (intctl->env->cache_control & CACHE_CTRL_IF) { -+ /* Instruction cache state */ -+ state = intctl->env->cache_control & CACHE_STATE_MASK; -+ if (state == CACHE_ENABLED) { -+ state = CACHE_FROZEN; -+ } -+ -+ intctl->env->cache_control &= ~CACHE_STATE_MASK; -+ intctl->env->cache_control |= state; -+ } -+ -+ if (intctl->env->cache_control & CACHE_CTRL_DF) { -+ /* Data cache state */ -+ state = (intctl->env->cache_control >> 2) & CACHE_STATE_MASK; -+ if (state == CACHE_ENABLED) { -+ state = CACHE_FROZEN; -+ } -+ -+ intctl->env->cache_control &= ~(CACHE_STATE_MASK << 2); -+ intctl->env->cache_control |= (state << 2); -+ } -+ -+ leon_check_irqs(intctl); -+} -+ -+static void leon_set_irq(void *opaque, int irq, int level) -+{ -+ struct LeonIntState *s = opaque; -+ -+ if (level) { -+ s->pending |= 1 << irq; -+ leon_check_irqs(s); -+ } -+} -+ -+static void leon_uart_check_irq(struct LeonUartState *s) -+{ -+ if (((s->status & UART_STATUS_DR) && (s->control & UART_CONTROL_RI)) -+ || (!(s->status & UART_STATUS_TH) && (s->control & UART_CONTROL_TI))) { -+ qemu_irq_pulse(s->irq); -+ } -+} -+ -+static int uart_data_to_read(LeonUartState *s) -+{ -+ return s->current < s->len; -+} -+ -+static char uart_pop(LeonUartState *s) -+{ -+ char ret; -+ -+ if (s->len == 0) { -+ return 0; -+ } -+ -+ ret = s->buffer[s->current++]; -+ -+ if (s->current >= s->len) { -+ /* Flush */ -+ s->len = 0; -+ s->current = 0; -+ } -+ return ret; -+} -+ -+static void uart_add_to_fifo(LeonUartState *s, -+ const uint8_t *buffer, -+ int length) -+{ -+ if (s->len + length > FIFO_LENGTH) { -+ abort(); -+ } -+ memcpy(s->buffer + s->len, buffer, length); -+ s->len += length; -+} -+ -+static int leon_uart_can_receive(void *opaque) -+{ -+ LeonUartState *s = opaque; -+ -+ return FIFO_LENGTH - s->len; -+} -+ -+static void leon_uart_receive(void *opaque, const uint8_t *buf, int size) -+{ -+ LeonUartState *s = opaque; -+ -+ uart_add_to_fifo(s, buf, size); -+ s->status |= UART_STATUS_DR; -+ leon_uart_check_irq(s); -+} -+ -+static void leon_uart_event(void *opaque, QEMUChrEvent event) -+{ -+ trace_leon_uart_event(event); -+} -+ -+static uint32_t leon_uart_read_uad(struct LeonUartState *s) -+{ -+ uint32_t ret = uart_pop(s); -+ -+ if (!uart_data_to_read(s)) { -+ s->status &= ~UART_STATUS_DR; -+ leon_uart_check_irq(s); -+ } -+ -+ return ret; -+} -+ -+static void leon_uart_init(Chardev *chr, -+ struct LeonUartState *s, -+ qemu_irq irq) -+{ -+ s->control = 0; -+ s->irq = irq; -+ s->status = UART_STATUS_TS | UART_STATUS_TH; -+ -+ qemu_chr_fe_init(&s->chr, chr, &error_abort); -+ qemu_chr_fe_set_handlers(&s->chr, leon_uart_can_receive, leon_uart_receive, -+ leon_uart_event, NULL, s, NULL, true); -+} -+ -+ -+static void leon_timer_enable(struct LeonTimerState *s) -+{ -+ ptimer_stop(s->ptimer); -+ -+ if (s->control & TIMCTR_LD) { -+ /* reload */ -+ s->counter = s->reload; -+ } -+ -+ if (!(s->control & TIMCTR_EN)) { -+ /* Timer disabled */ -+ trace_leon_timer_disabled(s->id, s->control); -+ return; -+ } -+ -+ /* ptimer is triggered when the counter reach 0 but GPTimer is triggered at -+ underflow. Set count + 1 to simulate the GPTimer behavior. */ -+ -+ trace_leon_timer_enable(s->id, s->counter + 1); -+ -+ ptimer_set_count(s->ptimer, s->counter + 1); -+ ptimer_run(s->ptimer, 1); -+} -+ -+static void leon_timer_hit(void *opaque) -+{ -+ struct LeonTimerState *s = opaque; -+ -+ trace_leon_timer_hit(s->id); -+ -+ qemu_irq_pulse(s->irq); -+ -+ if (s->control & TIMCTR_RL) { -+ /* reload */ -+ s->control |= TIMCTR_LD; -+ leon_timer_enable(s); -+ } -+} -+ -+static uint32_t leon_timer_io_read(void *opaque, hwaddr addr) -+{ -+ LeonIoState *s = opaque; -+ uint32_t ret; -+ -+ switch (addr) { -+ case PRESCALER_COUNTER_REGISTER: -+ ret = 0; -+ break; -+ case PRESCALER_RELOAD_REGISTER: -+ ret = s->scar; -+ break; -+ -+ case TIMER_1_COUNTER_REGISTER: -+ ret = ptimer_get_count(s->timer1.ptimer); -+ break; -+ -+ case TIMER_2_COUNTER_REGISTER: -+ ret = ptimer_get_count(s->timer2.ptimer); -+ break; -+ -+ case TIMER_1_RELOAD_REGISTER: -+ ret = s->timer1.reload; -+ break; -+ case TIMER_2_RELOAD_REGISTER: -+ ret = s->timer2.reload; -+ break; -+ -+ -+ case TIMER_1_CONTROL_REGISTER: -+ ret = s->timer1.control; -+ break; -+ case TIMER_2_CONTROL_REGISTER: -+ ret = s->timer2.control; -+ break; -+ -+ case WATCHDOG_REGISTER: -+ ret = s->wdg; -+ break; -+ -+ -+ default: -+ trace_leon_unknown_register("Timer:read", addr); -+ return 0; -+ } -+ -+ trace_leon_readl(addr, ret); -+ return ret; -+} -+ -+static void leon_timer_io_write(LeonIoState *s, hwaddr addr, -+ uint32_t val) -+{ -+ trace_leon_writel(addr, val); -+ -+ switch (addr) { -+ case PRESCALER_COUNTER_REGISTER: -+ break; -+ case PRESCALER_RELOAD_REGISTER: -+ s->scar = val & 0x3ff; -+ val = CPU_CLK / (s->scar + 1); -+ ptimer_set_freq(s->timer1.ptimer, val); -+ ptimer_set_freq(s->timer2.ptimer, val); -+ break; -+ -+ case TIMER_1_COUNTER_REGISTER: -+ s->timer1.counter = val & 0x00ffffff; -+ leon_timer_enable(&s->timer1); -+ break; -+ case TIMER_2_COUNTER_REGISTER: -+ s->timer2.counter = val & 0x00ffffff; -+ leon_timer_enable(&s->timer2); -+ break; -+ -+ case TIMER_1_RELOAD_REGISTER: -+ s->timer1.reload = val & 0x00ffffff; -+ break; -+ case TIMER_2_RELOAD_REGISTER: -+ s->timer2.reload = val & 0x00ffffff; -+ break; -+ -+ -+ case TIMER_1_CONTROL_REGISTER: -+ s->timer1.control = val & TIMCTR_MASK; -+ leon_timer_enable(&s->timer1); -+ break; -+ case TIMER_2_CONTROL_REGISTER: -+ s->timer2.control = val & TIMCTR_MASK; -+ leon_timer_enable(&s->timer2); -+ break; -+ -+ case WATCHDOG_REGISTER: -+ s->wdg = val & 0x00ffffff; -+ break; -+ -+ default: -+ trace_leon_unknown_register("Timer:write", addr); -+ break; -+ } -+} -+ -+static void leon_timer_init(struct LeonTimerState *s, qemu_irq irq, int id) -+{ -+ s->id = id; -+ s->counter = 0; -+ s->reload = 0; -+ s->control = 0; -+ s->irq = irq; -+ s->bh = qemu_bh_new(leon_timer_hit, s); -+ s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); -+ -+ ptimer_set_freq(s->ptimer, CPU_CLK); -+ -+} -+ -+static uint64_t leon_io_read(void *opaque, hwaddr addr, -+ unsigned size) -+{ -+ LeonIoState *s = opaque; -+ uint64_t ret; -+ -+ switch (addr) { -+ case MEMORY_CONFIGURATION_REGISTER_1: -+ case MEMORY_CONFIGURATION_REGISTER_2: -+ case MEMORY_CONFIGURATION_REGISTER_3: -+ ret = s->mcfg[(addr - MEMORY_CONFIGURATION_REGISTER_1) >> 2]; -+ break; -+ case FAIL_STATUS_REGISTER: -+ ret = 0; -+ break; -+ case CACHE_CONTROL_REGISTER: -+ ret = s->intctl.env->cache_control; -+ break; -+ -+ case INTERRUPT_MASK_AND_PRIORITY_REGISTER: -+ ret = s->intctl.lvl_mask; -+ break; -+ case INTERRUPT_PENDING_REGISTER: -+ ret = s->intctl.pending; -+ break; -+ case INTERRUPT_FORCE_REGISTER: -+ ret = s->intctl.force; -+ break; -+ case INTERRUPT_CLEAR_REGISTER: -+ ret = 0; -+ break; -+ -+ case UART_1_DATA_REGISTER: -+ case UART_1_DATA_REGISTER + 3: /* when only one byte read */ -+ ret = leon_uart_read_uad(&s->uart1); -+ break; -+ case UART_1_CONTROL_REGISTER: -+ ret = s->uart1.control; -+ break; -+ case UART_1_SCALER_REGISTER: -+ ret = s->uart1.scaler; -+ break; -+ case UART_1_STATUS_REGISTER: -+ ret = s->uart1.status; -+ break; -+ -+ case UART_2_DATA_REGISTER: -+ case UART_2_DATA_REGISTER + 3: /* when only one byte read */ -+ ret = leon_uart_read_uad(&s->uart2); -+ break; -+ case UART_2_CONTROL_REGISTER: -+ ret = s->uart2.control; -+ break; -+ case UART_2_SCALER_REGISTER: -+ ret = s->uart2.scaler; -+ break; -+ case UART_2_STATUS_REGISTER: -+ ret = s->uart2.status; -+ break; -+ -+ case TIMER_1_RELOAD_REGISTER ... PRESCALER_RELOAD_REGISTER: -+ ret = leon_timer_io_read(s, addr); -+ break; -+ -+ case IO_PORT_DATA_REGISTER: -+ ret = s->iodata; -+ break; -+ case IO_PORT_DIRECTION_REGISTER: -+ ret = s->iodir; -+ break; -+ case IO_PORT_INTERRUPT_REGISTER: -+ ret = s->ioit; -+ break; -+ -+ default: -+ trace_leon_unknown_register("Leon:read", addr); -+ ret = 0; -+ break; -+ } -+ -+ trace_leon_readl(addr, ret); -+ -+ return ret; -+} -+ -+static void leon_io_write(void *opaque, hwaddr addr, -+ uint64_t value, unsigned size) -+{ -+ LeonIoState *s = opaque; -+ -+ trace_leon_writel(addr, value); -+ -+ switch (addr) { -+ case MEMORY_CONFIGURATION_REGISTER_1: -+ case MEMORY_CONFIGURATION_REGISTER_2: -+ case MEMORY_CONFIGURATION_REGISTER_3: -+ s->mcfg[(addr - MEMORY_CONFIGURATION_REGISTER_1) >> 2] = value; -+ break; -+ case FAIL_STATUS_REGISTER: -+ break; -+ case CACHE_CONTROL_REGISTER: -+ /* These values must always be read as zeros */ -+ value &= ~CACHE_CTRL_FD; -+ value &= ~CACHE_CTRL_FI; -+ value &= ~CACHE_CTRL_IB; -+ value &= ~CACHE_CTRL_IP; -+ value &= ~CACHE_CTRL_DP; -+ s->intctl.env->cache_control = value; -+ break; -+ -+ case INTERRUPT_MASK_AND_PRIORITY_REGISTER: -+ s->intctl.lvl_mask = value; -+ break; -+ case INTERRUPT_PENDING_REGISTER: -+ /* Read Only */ -+ break; -+ case INTERRUPT_FORCE_REGISTER: -+ s->intctl.force = value & 0xfffe; -+ leon_check_irqs(&s->intctl); -+ break; -+ case INTERRUPT_CLEAR_REGISTER: -+ s->intctl.pending &= ~(value & 0xfffe); -+ leon_check_irqs(&s->intctl); -+ break; -+ -+ case UART_1_CONTROL_REGISTER: -+ s->uart1.control = value & 0x1ff; -+ break; -+ case UART_1_SCALER_REGISTER: -+ s->uart1.scaler = value & 0x3ff; -+ break; -+ case UART_1_DATA_REGISTER: -+ case UART_1_DATA_REGISTER + 3: /* when only one byte write */ -+ { -+ unsigned char c = value; -+ if (qemu_chr_fe_get_driver(&s->uart1.chr)) { -+ qemu_chr_fe_write(&s->uart1.chr, &c, 1); -+ } -+ } -+ break; -+ -+ case UART_2_CONTROL_REGISTER: -+ s->uart2.control = value & 0x1ff; -+ break; -+ case UART_2_SCALER_REGISTER: -+ s->uart2.scaler = value & 0x3ff; -+ break; -+ case UART_2_DATA_REGISTER: -+ case UART_2_DATA_REGISTER + 3: /* when only one byte write */ -+ { -+ unsigned char c = value; -+ if (qemu_chr_fe_get_driver(&s->uart2.chr)) { -+ qemu_chr_fe_write(&s->uart1.chr, &c, 1); -+ } -+ } -+ break; -+ -+ case TIMER_1_RELOAD_REGISTER ... PRESCALER_RELOAD_REGISTER: -+ leon_timer_io_write(s, addr, value); -+ break; -+ -+ case IO_PORT_DATA_REGISTER: -+ s->iodata = value & 0xffff; -+ break; -+ case IO_PORT_DIRECTION_REGISTER: -+ s->iodir = value & 0x3ffff; -+ break; -+ case IO_PORT_INTERRUPT_REGISTER: -+ s->ioit = value; -+ break; -+ -+ default: -+ trace_leon_unknown_register("Leon:write", addr); -+ } -+} -+ -+static const MemoryRegionOps leon_io_ops = { -+ .read = leon_io_read, -+ .write = leon_io_write, -+ .endianness = DEVICE_NATIVE_ENDIAN, -+ .valid = { -+ .min_access_size = 1, -+ .max_access_size = 4, -+ }, -+}; -+ -+static void at697_hw_init(MachineState *machine) -+{ -+ ram_addr_t ram_size = machine->ram_size; -+ const char *kernel_filename = machine->kernel_filename; -+ SPARCCPU *cpu; -+ CPUSPARCState *env; -+ MemoryRegion *address_space_mem = get_system_memory(); -+ MemoryRegion *ram = g_new(MemoryRegion, 1); -+ MemoryRegion *ram2 = g_new(MemoryRegion, 1); -+ MemoryRegion *prom = g_new(MemoryRegion, 1); -+ MemoryRegion *iomem = g_new(MemoryRegion, 1); -+ ram_addr_t ram2_size; -+ int ret; -+ char *filename; -+ qemu_irq *cpu_irqs; -+ int bios_size; -+ int aligned_bios_size; -+ LeonIoState *s; -+ ResetData *reset_info; -+ -+ cpu = SPARC_CPU(cpu_create(machine->cpu_type)); -+ if (cpu == NULL) { -+ fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); -+ exit(1); -+ } -+ env = &cpu->env; -+ -+ cpu_sparc_set_id(env, 0); -+ -+ /* Reset data */ -+ reset_info = g_malloc0(sizeof(ResetData)); -+ reset_info->cpu = cpu; -+ qemu_register_reset(main_cpu_reset, reset_info); -+ -+ s = g_malloc0(sizeof(struct LeonIoState)); -+ s->ccr = CCR_INIT; -+ s->intctl.env = env;; -+ -+ env->irq_manager = &s->intctl; -+ env->qemu_irq_ack = leon2_intctl_ack; -+ -+ cpu_irqs = qemu_allocate_irqs(leon_set_irq, &s->intctl, MAX_PILS); -+ -+ /* allocate RAM */ -+ if ((uint64_t)ram_size > (1UL << 30)) { -+ fprintf(stderr, -+ "qemu: Too much memory for this machine: %d, maximum 1G\n", -+ (unsigned int)(ram_size / (1024 * 1024))); -+ exit(1); -+ } -+ memory_region_init_ram(ram, NULL, "leon.ram", ram_size, &error_abort); -+ memory_region_add_subregion(address_space_mem, 0x40000000, ram); -+ -+ reset_info->stack_pointer = 0x40000000 + ram_size; -+ -+ /* Allocate RAM2. */ -+ ram2_size = 8 << 20; -+ memory_region_init_ram(ram2, NULL, "leon.ram2", ram2_size, &error_abort); -+ memory_region_add_subregion(address_space_mem, 0x20000000, ram2); -+ -+ /* load boot prom */ -+ if (bios_name == NULL) { -+ bios_name = PROM_FILENAME; -+ } -+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); -+ bios_size = get_image_size(filename); -+ if (bios_size > 0) { -+ aligned_bios_size = -+ (bios_size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; -+ -+ memory_region_init_ram(prom, NULL, "leon.bios", aligned_bios_size, -+ &error_abort); -+ memory_region_set_readonly(prom, true); -+ memory_region_add_subregion(address_space_mem, 0x00000000, prom); -+ -+ ret = load_image_targphys(filename, 0x00000000, bios_size); -+ if (ret < 0 || ret > bios_size) { -+ fprintf(stderr, "qemu: could not load prom '%s'\n", filename); -+ exit(1); -+ } -+ } else if (kernel_filename == NULL) { -+ fprintf(stderr, "Can't read bios image %s\n", filename); -+ exit(1); -+ } -+ -+ -+ memory_region_init_io(iomem, NULL, &leon_io_ops, s, "leon_io", 0x1000); -+ memory_region_add_subregion(get_system_memory(), 0x80000000, iomem); -+ -+ leon_timer_init(&s->timer1, cpu_irqs[8], 1 /* id */); -+ leon_timer_init(&s->timer2, cpu_irqs[9], 2 /* id */); -+ -+ if (serial_hd(0)) { -+ leon_uart_init(serial_hd(0), &s->uart1, cpu_irqs[3]); -+ } -+ if (serial_hd(1)) { -+ leon_uart_init(serial_hd(1), &s->uart2, cpu_irqs[2]); -+ } -+ -+ /* HostFS */ -+ hostfs_create(0x80001000, get_system_memory()); -+ -+ /* Initialize the GnatBus Master */ -+ gnatbus_master_init(cpu_irqs, MAX_PILS); -+ gnatbus_device_init(); -+ -+ /* Can directly load an application. */ -+ if (kernel_filename != NULL) { -+ long kernel_size; -+ uint64_t entry; -+ -+ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, -+ &entry, NULL, NULL, NULL, -+ 1 /* big endian */, EM_SPARC, 0, 0); -+ if (kernel_size < 0) { -+ fprintf(stderr, "qemu: could not load kernel '%s'\n", -+ kernel_filename); -+ exit(1); -+ } -+ if (bios_size <= 0) { -+ /* If there is no bios/monitor, start the application. */ -+ env->pc = entry; -+ env->npc = entry + 4; -+ reset_info->entry = entry; -+ } -+ } -+} -+ -+static void at697_generic_machine_init(MachineClass *mc) -+{ -+ mc->desc = "Leon-2 Atmel 697"; -+ mc->init = at697_hw_init; -+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON2"); -+} -+ -+DEFINE_MACHINE("at697", at697_generic_machine_init) -diff --git a/hw/sparc/meson.build b/hw/sparc/meson.build -index 19c442c90d..13d90572a5 100644 ---- a/hw/sparc/meson.build -+++ b/hw/sparc/meson.build -@@ -2,5 +2,6 @@ sparc_ss = ss.source_set() - sparc_ss.add(when: 'CONFIG_LEON3', if_true: files('leon3.c')) - sparc_ss.add(when: 'CONFIG_SUN4M', if_true: files('sun4m.c')) - sparc_ss.add(when: 'CONFIG_SUN4M', if_true: files('sun4m_iommu.c')) -+sparc_ss.add(files('leon.c')) - - hw_arch += {'sparc': sparc_ss} -diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events -index 355b07ae05..6c71aaf345 100644 ---- a/hw/sparc/trace-events -+++ b/hw/sparc/trace-events -@@ -19,3 +19,16 @@ sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64 - # leon3.c - leon3_set_irq(int intno) "Set CPU IRQ %d" - leon3_reset_irq(int intno) "Reset CPU IRQ %d" -+ -+# hw/leon.c -+leon_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x" -+leon_set_irq(int intno) "Set CPU IRQ %d" -+leon_reset_irq(int intno) "Reset CPU IRQ %d" -+leon_intctl_ack(int intno) "interrupt:%d" -+leon_uart_event(int event) "uart event:%d" -+leon_timer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x" -+leon_timer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run" -+leon_timer_hit(int id) "timer:%d HIT" -+leon_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64"" -+leon_readl(uint64_t addr, uint32_t val) "addr:0x%"PRIx64" val:0x%x" -+leon_writel(uint64_t addr, uint32_t val) "addr:0x%"PRIx64" val:0x%x" -diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c -index aece2c7dc8..cdac7b4329 100644 ---- a/target/sparc/cpu.c -+++ b/target/sparc/cpu.c -@@ -514,7 +514,7 @@ static const sparc_def_t sparc_defs[] = { - .iu_version = 0xf2000000, - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ - .mmu_version = 0xf2000000, -- .mmu_bm = 0x00004000, -+ .mmu_bm = 0x00000000, - .mmu_ctpr_mask = 0x007ffff0, - .mmu_cxr_mask = 0x0000003f, - .mmu_sfsr_mask = 0xffffffff, --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0006-hw-sparc-leon-Fix-compilation-errors.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0006-hw-sparc-leon-Fix-compilation-errors.patch deleted file mode 100644 index 3d656a09..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0006-hw-sparc-leon-Fix-compilation-errors.patch +++ /dev/null @@ -1,91 +0,0 @@ -From d6f7f09579a55c28fc29e57dc28ea03d3b2211ac Mon Sep 17 00:00:00 2001 -From: Yasushi SHOJI -Date: Thu, 5 Sep 2019 11:06:56 +0900 -Subject: [PATCH 06/16] hw/sparc/leon: Fix compilation errors - -The previous commit, taken from AdaCore repository as is for future -reference, depends on other commit in the AdaCore repository and fails -to build. This commit is to port it to the vanilla QEmu. - -What it does is 4 folds: - -- Remove AdaCore specific headers and function calls. -- Add necessarily headers to build. -- Use env_cpu instead of CPU() as per - 29a0af618ddd21f55df5753c3e16b0625f534b3c. -- Update for intctl_ack API change introduced by - 7922703623a989b59ce7f7b57a3c8ebe5c0f6b53. - -Signed-off-by: Yasushi SHOJI ---- - hw/sparc/leon.c | 19 +++++++------------ - 1 file changed, 7 insertions(+), 12 deletions(-) - -diff --git a/hw/sparc/leon.c b/hw/sparc/leon.c -index 316bd70288..cab394ba4b 100644 ---- a/hw/sparc/leon.c -+++ b/hw/sparc/leon.c -@@ -22,12 +22,16 @@ - * THE SOFTWARE. - */ - #include "qemu/osdep.h" -+#include "qemu-common.h" - #include "qapi/error.h" - #include "cpu.h" - #include "hw/hw.h" -+#include "hw/irq.h" - #include "qemu/timer.h" - #include "chardev/char.h" -+#include "chardev/char-fe.h" - #include "sysemu/sysemu.h" -+#include "sysemu/reset.h" - #include "hw/boards.h" - #include "hw/loader.h" - #include "elf.h" -@@ -35,8 +39,6 @@ - #include "hw/ptimer.h" - #include "exec/memory.h" - #include "exec/address-spaces.h" --#include "hw/adacore/gnat-bus.h" --#include "hw/adacore/hostfs.h" - - /* Default system clock. */ - #define CPU_CLK (50 * 1000 * 1000) -@@ -220,7 +222,7 @@ static void leon_check_irqs(struct LeonIntState *s) - uint32_t level0 = 0; - uint32_t level1 = 0; - CPUSPARCState *env = s->env; -- CPUState *cs = CPU(sparc_env_get_cpu(env)); -+ CPUState *cs = env_cpu(env); - - pend = (s->pending | s->force) & (s->lvl_mask & 0xfffe); - -@@ -260,9 +262,9 @@ static void leon_check_irqs(struct LeonIntState *s) - } - } - --static void leon2_intctl_ack(CPUSPARCState *env, int intno) -+static void leon2_intctl_ack(CPUSPARCState *env, void *irq_manager, int intno) - { -- struct LeonIntState *intctl = env->irq_manager; -+ struct LeonIntState *intctl = (struct LeonIntState *)irq_manager; - uint32_t mask; - uint32_t state = 0; - -@@ -839,13 +841,6 @@ static void at697_hw_init(MachineState *machine) - leon_uart_init(serial_hd(1), &s->uart2, cpu_irqs[2]); - } - -- /* HostFS */ -- hostfs_create(0x80001000, get_system_memory()); -- -- /* Initialize the GnatBus Master */ -- gnatbus_master_init(cpu_irqs, MAX_PILS); -- gnatbus_device_init(); -- - /* Can directly load an application. */ - if (kernel_filename != NULL) { - long kernel_size; --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0007-hw-sparc-leon-timer-Call-leon_timer_io_read-for-TIME.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0007-hw-sparc-leon-timer-Call-leon_timer_io_read-for-TIME.patch deleted file mode 100644 index a52e9abd..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0007-hw-sparc-leon-timer-Call-leon_timer_io_read-for-TIME.patch +++ /dev/null @@ -1,47 +0,0 @@ -From bdd73723d04fa722c56659e0bd2ed44a1ce4c108 Mon Sep 17 00:00:00 2001 -From: Yasushi SHOJI -Date: Fri, 17 May 2019 21:42:30 +0900 -Subject: [PATCH 07/16] hw/sparc/leon: timer: Call leon_timer_io_read() for - TIMER_1_COUNTER_REGISTER - -Accessing timer1 counter register (offset 0x40) always returned 0 -because the address range check for leon_timer_io_read() was -insufficient. Add TIMER_1_COUNTER_REGISTER at the case statement. - -We don't need to add TIMER_1_COUNTER_REGISTER for -leon_timer_io_write() because timer1 counter register isn't -writable. But, this commit also changes the range check for -leon_timer_io_write() as well for consistency. The given address is -checked in leon_timer_io_write() again, thus the change is effectively -no-op for non-writable registers. - -Signed-off-by: Yasushi SHOJI ---- - hw/sparc/leon.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/hw/sparc/leon.c b/hw/sparc/leon.c -index cab394ba4b..d2dc8e55c8 100644 ---- a/hw/sparc/leon.c -+++ b/hw/sparc/leon.c -@@ -616,7 +616,7 @@ static uint64_t leon_io_read(void *opaque, hwaddr addr, - ret = s->uart2.status; - break; - -- case TIMER_1_RELOAD_REGISTER ... PRESCALER_RELOAD_REGISTER: -+ case TIMER_1_COUNTER_REGISTER ... PRESCALER_RELOAD_REGISTER: - ret = leon_timer_io_read(s, addr); - break; - -@@ -713,7 +713,7 @@ static void leon_io_write(void *opaque, hwaddr addr, - } - break; - -- case TIMER_1_RELOAD_REGISTER ... PRESCALER_RELOAD_REGISTER: -+ case TIMER_1_COUNTER_REGISTER ... PRESCALER_RELOAD_REGISTER: - leon_timer_io_write(s, addr, value); - break; - --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0008-hw-sparc-leon-Switch-to-transaction-based-ptimer-API.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0008-hw-sparc-leon-Switch-to-transaction-based-ptimer-API.patch deleted file mode 100644 index ae865b65..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0008-hw-sparc-leon-Switch-to-transaction-based-ptimer-API.patch +++ /dev/null @@ -1,103 +0,0 @@ -From a64a2a59b1637d1d06b1286802f756241f6e5546 Mon Sep 17 00:00:00 2001 -From: Yasushi SHOJI -Date: Mon, 9 Dec 2019 11:56:20 +0900 -Subject: [PATCH 08/16] hw/sparc/leon: Switch to transaction-based ptimer API - -Switch the leon code away from old ptimers to the new -transaction-based ptimer API. This requires adding begin/commit calls -around the various places that modify the ptimer state, and not -calling leon_timer_enable() from leon_timer_hit() since -leon_timer_hit() is called within a transcation enabled ptimer_tick(). - -Signed-off-by: Yasushi SHOJI ---- - hw/sparc/leon.c | 22 +++++++++++++++++----- - 1 file changed, 17 insertions(+), 5 deletions(-) - -diff --git a/hw/sparc/leon.c b/hw/sparc/leon.c -index d2dc8e55c8..384dde035b 100644 ---- a/hw/sparc/leon.c -+++ b/hw/sparc/leon.c -@@ -156,7 +156,6 @@ typedef struct LeonUartState { - } LeonUartState; - - struct LeonTimerState { -- QEMUBH *bh; - struct ptimer_state *ptimer; - - qemu_irq irq; -@@ -404,6 +403,7 @@ static void leon_uart_init(Chardev *chr, - - static void leon_timer_enable(struct LeonTimerState *s) - { -+ ptimer_transaction_begin(s->ptimer); - ptimer_stop(s->ptimer); - - if (s->control & TIMCTR_LD) { -@@ -424,6 +424,7 @@ static void leon_timer_enable(struct LeonTimerState *s) - - ptimer_set_count(s->ptimer, s->counter + 1); - ptimer_run(s->ptimer, 1); -+ ptimer_transaction_commit(s->ptimer); - } - - static void leon_timer_hit(void *opaque) -@@ -437,7 +438,10 @@ static void leon_timer_hit(void *opaque) - if (s->control & TIMCTR_RL) { - /* reload */ - s->control |= TIMCTR_LD; -- leon_timer_enable(s); -+ ptimer_stop(s->ptimer); -+ s->counter = s->reload; -+ ptimer_set_count(s->ptimer, s->counter + 1); -+ ptimer_run(s->ptimer, 1); - } - } - -@@ -455,11 +459,15 @@ static uint32_t leon_timer_io_read(void *opaque, hwaddr addr) - break; - - case TIMER_1_COUNTER_REGISTER: -+ ptimer_transaction_begin(s->timer1.ptimer); - ret = ptimer_get_count(s->timer1.ptimer); -+ ptimer_transaction_commit(s->timer1.ptimer); - break; - - case TIMER_2_COUNTER_REGISTER: -+ ptimer_transaction_begin(s->timer2.ptimer); - ret = ptimer_get_count(s->timer2.ptimer); -+ ptimer_transaction_commit(s->timer2.ptimer); - break; - - case TIMER_1_RELOAD_REGISTER: -@@ -502,8 +510,12 @@ static void leon_timer_io_write(LeonIoState *s, hwaddr addr, - case PRESCALER_RELOAD_REGISTER: - s->scar = val & 0x3ff; - val = CPU_CLK / (s->scar + 1); -+ ptimer_transaction_begin(s->timer1.ptimer); - ptimer_set_freq(s->timer1.ptimer, val); -+ ptimer_transaction_commit(s->timer1.ptimer); -+ ptimer_transaction_begin(s->timer2.ptimer); - ptimer_set_freq(s->timer2.ptimer, val); -+ ptimer_transaction_commit(s->timer2.ptimer); - break; - - case TIMER_1_COUNTER_REGISTER: -@@ -549,11 +561,11 @@ static void leon_timer_init(struct LeonTimerState *s, qemu_irq irq, int id) - s->reload = 0; - s->control = 0; - s->irq = irq; -- s->bh = qemu_bh_new(leon_timer_hit, s); -- s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); -+ s->ptimer = ptimer_init(leon_timer_hit, s, PTIMER_POLICY_DEFAULT); - -+ ptimer_transaction_begin(s->ptimer); - ptimer_set_freq(s->ptimer, CPU_CLK); -- -+ ptimer_transaction_commit(s->ptimer); - } - - static uint64_t leon_io_read(void *opaque, hwaddr addr, --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0009-hw-sparc-leon-Fix-compilation-errors-with-qemu-6-cha.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0009-hw-sparc-leon-Fix-compilation-errors-with-qemu-6-cha.patch deleted file mode 100644 index 143096b4..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0009-hw-sparc-leon-Fix-compilation-errors-with-qemu-6-cha.patch +++ /dev/null @@ -1,46 +0,0 @@ -From fb9a3921040b1115db534f88a74997bffe3204be Mon Sep 17 00:00:00 2001 -From: Kumar Gala -Date: Thu, 25 Mar 2021 18:59:10 -0500 -Subject: [PATCH 09/16] hw/sparc/leon: Fix compilation errors with qemu 6 - changes - -Make updates to build due to upstream changes in qemu 6.0.0 - -Signed-off-by: Kumar Gala ---- - hw/sparc/leon.c | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - -diff --git a/hw/sparc/leon.c b/hw/sparc/leon.c -index 384dde035b..5521452316 100644 ---- a/hw/sparc/leon.c -+++ b/hw/sparc/leon.c -@@ -23,6 +23,7 @@ - */ - #include "qemu/osdep.h" - #include "qemu-common.h" -+#include "qemu/datadir.h" - #include "qapi/error.h" - #include "cpu.h" - #include "hw/hw.h" -@@ -757,6 +758,7 @@ static const MemoryRegionOps leon_io_ops = { - static void at697_hw_init(MachineState *machine) - { - ram_addr_t ram_size = machine->ram_size; -+ const char *bios_name = machine->firmware ?: PROM_FILENAME; - const char *kernel_filename = machine->kernel_filename; - SPARCCPU *cpu; - CPUSPARCState *env; -@@ -815,9 +817,6 @@ static void at697_hw_init(MachineState *machine) - memory_region_add_subregion(address_space_mem, 0x20000000, ram2); - - /* load boot prom */ -- if (bios_name == NULL) { -- bios_name = PROM_FILENAME; -- } - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); - bios_size = get_image_size(filename); - if (bios_size > 0) { --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0010-Add-ARC-support.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0010-Add-ARC-support.patch deleted file mode 100644 index 17d453ed..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0010-Add-ARC-support.patch +++ /dev/null @@ -1,92173 +0,0 @@ -From c42894f665c808526bbec2659883e303ae15ef9b Mon Sep 17 00:00:00 2001 -From: Alexey Brodkin -Date: Fri, 16 Apr 2021 20:15:42 +0300 -Subject: [PATCH 10/16] Add ARC support - -Signed-off-by: Alexey Brodkin ---- - configure | 4 + - default-configs/arc-softmmu.mak | 5 + - default-configs/devices/arc-softmmu.mak | 7 + - default-configs/devices/arc64-softmmu.mak | 7 + - default-configs/targets/arc-softmmu.mak | 3 + - default-configs/targets/arc64-softmmu.mak | 3 + - disas.c | 2 + - disas/arc.c | 455 + - disas/meson.build | 1 + - gdb-xml/arc-core-v3.xml | 45 + - gdb-xml/arc-v2-aux.xml | 32 + - gdb-xml/arc-v2-core.xml | 45 + - gdb-xml/arc-v2-other.xml | 235 + - gdb-xml/arc64-aux-minimal.xml | 32 + - gdb-xml/arc64-aux-other.xml | 177 + - hw/Kconfig | 1 + - hw/arc/Kconfig | 9 + - hw/arc/arc_sim.c | 124 + - hw/arc/boot.c | 101 + - hw/arc/boot.h | 21 + - hw/arc/meson.build | 9 + - hw/arc/pic_cpu.c | 113 + - hw/arc/virt.c | 184 + - hw/meson.build | 1 + - include/disas/dis-asm.h | 12 +- - include/elf.h | 6 + - include/exec/poison.h | 2 + - include/hw/arc/cpudevs.h | 30 + - include/sysemu/arch_init.h | 1 + - meson.build | 4 +- - softmmu/arch_init.c | 2 + - target/arc/arc-common.h | 65 + - target/arc/cache.c | 182 + - target/arc/cache.h | 36 + - target/arc/cpu-param.h | 42 + - target/arc/cpu-qom.h | 52 + - target/arc/cpu.c | 507 + - target/arc/cpu.h | 457 + - target/arc/decoder-v3.c | 1547 ++ - target/arc/decoder-v3.h | 322 + - target/arc/decoder.c | 1297 + - target/arc/decoder.h | 351 + - target/arc/extra_mapping.def | 79 + - target/arc/flags-v3.def | 103 + - target/arc/flags.def | 85 + - target/arc/gdbstub.c | 444 + - target/arc/gdbstub.h | 167 + - target/arc/helper.c | 292 + - target/arc/helper.h | 55 + - target/arc/irq.c | 691 + - target/arc/irq.h | 44 + - target/arc/meson.build | 34 + - target/arc/mmu-v6.c | 640 + - target/arc/mmu-v6.h | 36 + - target/arc/mmu.c | 805 + - target/arc/mmu.h | 148 + - target/arc/mpu.c | 656 + - target/arc/mpu.h | 133 + - target/arc/op_helper.c | 494 + - target/arc/opcodes-v3.def | 18799 +++++++++++++++ - target/arc/opcodes.def | 19976 ++++++++++++++++ - target/arc/operands-v3.def | 133 + - target/arc/operands.def | 123 + - target/arc/regs-detail.def | 583 + - target/arc/regs-impl.c | 200 + - target/arc/regs.c | 183 + - target/arc/regs.def | 434 + - target/arc/regs.h | 139 + - target/arc/semfunc-helper.c | 427 + - target/arc/semfunc-helper.h | 324 + - target/arc/semfunc-v2_mapping.def | 321 + - target/arc/semfunc-v3.c | 14662 ++++++++++++ - target/arc/semfunc-v3.h | 55 + - target/arc/semfunc-v3_mapping.def | 468 + - target/arc/semfunc.c | 8441 +++++++ - target/arc/semfunc.h | 63 + - target/arc/semfunc_generator/Gemfile | 3 + - target/arc/semfunc_generator/README | 35 + - .../classes/CreateInternalVars.rb | 117 + - .../classes/DecomposeExpressions.rb | 45 + - .../classes/IdentifyQEmuStaticInferedParts.rb | 91 + - .../semfunc_generator/classes/QEmuCompiler.rb | 15 + - .../classes/QEmuTranslator.rb | 269 + - .../classes/SemanticFunctionAST.rb | 466 + - .../classes/SpaghettiCodePass.rb | 55 + - .../classes/SpaghettiCodePass1.rb | 66 + - .../semfunc_generator/classes/UnfoldCode.rb | 305 + - target/arc/semfunc_generator/init.rb | 15 + - .../arc/semfunc_generator/modules/Compiler.rb | 42 + - .../modules/ConstantTables.rb | 57 + - target/arc/semfunc_generator/modules/Pass.rb | 11 + - .../SemanticFunctionASTBlockOperators.rb | 145 + - .../modules/SemanticFunctionASTFactory.rb | 55 + - .../semfunc_generator/modules/Translator.rb | 102 + - .../modules/TranslatorAST.rb | 80 + - .../modules/TranslatorFinal.rb | 103 + - .../parsers/SemanticFunctionParser.tab.rb | 553 + - .../parsers/SemanticFunctionParser.y | 126 + - .../semfunc_generator/regenerate_semfunc.rb | 245 + - target/arc/semfunc_mapping.def | 25 + - target/arc/timer.c | 459 + - target/arc/timer.h | 27 + - target/arc/translate.c | 1716 ++ - target/arc/translate.h | 168 + - target/meson.build | 1 + - tests/Makefile.include | 1 + - tests/acceptance/boot_linux_console.py | 55 + - tests/tcg/arc/Makefile | 114 + - tests/tcg/arc/Makefile.softmmu-target | 43 + - tests/tcg/arc/Makefile.target | 101 + - tests/tcg/arc/check_add.S | 11 + - tests/tcg/arc/check_addx.S | 71 + - tests/tcg/arc/check_andx.S | 36 + - tests/tcg/arc/check_aslx.S | 57 + - tests/tcg/arc/check_asrx.S | 86 + - tests/tcg/arc/check_basic1.S | 30 + - tests/tcg/arc/check_basic2.S | 26 + - tests/tcg/arc/check_beq.S | 14 + - tests/tcg/arc/check_beqx.S | 26 + - tests/tcg/arc/check_bi.S | 32 + - tests/tcg/arc/check_big_tb.S | 173 + - tests/tcg/arc/check_bih.S | 29 + - tests/tcg/arc/check_bnex.S | 26 + - tests/tcg/arc/check_breqx.S | 26 + - tests/tcg/arc/check_brgex.S | 26 + - tests/tcg/arc/check_brhsx.S | 27 + - tests/tcg/arc/check_brlox.S | 26 + - tests/tcg/arc/check_brltx.S | 26 + - tests/tcg/arc/check_brnex.S | 26 + - tests/tcg/arc/check_bta.S | 294 + - tests/tcg/arc/check_carry.S | 15 + - tests/tcg/arc/check_enter_leave.S | 715 + - tests/tcg/arc/check_excp.S | 17 + - tests/tcg/arc/check_excp_1.c | 15 + - tests/tcg/arc/check_excp_jumpdl_mmu.S | 44 + - tests/tcg/arc/check_excp_mmu.S | 69 + - tests/tcg/arc/check_flags.S | 23 + - tests/tcg/arc/check_ldaw_mmu.S | 71 + - tests/tcg/arc/check_ldstx.S | 37 + - tests/tcg/arc/check_lp.S | 12 + - tests/tcg/arc/check_lp02.S | 72 + - tests/tcg/arc/check_lp03.S | 49 + - tests/tcg/arc/check_lp04.S | 48 + - tests/tcg/arc/check_lp05.S | 23 + - tests/tcg/arc/check_lp06.S | 163 + - tests/tcg/arc/check_lsrx.S | 33 + - tests/tcg/arc/check_mac.S | 228 + - tests/tcg/arc/check_manip_10_mmu.S | 173 + - tests/tcg/arc/check_manip_4_mmu.S | 158 + - tests/tcg/arc/check_manip_5_mmu.S | 166 + - tests/tcg/arc/check_manip_mmu.S | 565 + - tests/tcg/arc/check_mmu.S | 59 + - tests/tcg/arc/check_mpu.S | 703 + - tests/tcg/arc/check_mpyd.S | 543 + - tests/tcg/arc/check_mpyw.S | 41 + - tests/tcg/arc/check_norm.S | 40 + - tests/tcg/arc/check_orx.S | 34 + - tests/tcg/arc/check_prefetch.S | 37 + - tests/tcg/arc/check_rolx.S | 47 + - tests/tcg/arc/check_rorx.S | 64 + - tests/tcg/arc/check_rtc.S | 29 + - tests/tcg/arc/check_rtie_user.S | 30 + - tests/tcg/arc/check_stld.S | 10 + - tests/tcg/arc/check_subf.S | 67 + - tests/tcg/arc/check_subx.S | 43 + - tests/tcg/arc/check_swi.S | 115 + - tests/tcg/arc/check_swirq.S | 27 + - tests/tcg/arc/check_swirq1.S | 31 + - tests/tcg/arc/check_swirq3.S | 49 + - tests/tcg/arc/check_t01.S | 12 + - tests/tcg/arc/check_t02.S | 9 + - tests/tcg/arc/check_timer0.S | 36 + - tests/tcg/arc/check_timer0_loop.S | 34 + - tests/tcg/arc/check_timer0_loop3.S | 46 + - tests/tcg/arc/check_timer0_retrig.S | 29 + - tests/tcg/arc/check_timer0_sleep.S | 33 + - tests/tcg/arc/check_timerX_freq.S | 87 + - tests/tcg/arc/check_vadd.S | 510 + - tests/tcg/arc/check_vsub.S | 510 + - tests/tcg/arc/check_xorx.S | 32 + - tests/tcg/arc/ivt.S | 38 + - tests/tcg/arc/macros.inc | 261 + - tests/tcg/arc/memory.x | 12 + - tests/tcg/arc/mmu.inc | 132 + - tests/tcg/arc/mpu.inc | 269 + - tests/tcg/arc/tarc.ld | 15 + - tests/tcg/arc/tarc_mmu.ld | 15 + - tests/tcg/arc/test_macros.h | 257 + - tests/tcg/configure.sh | 3 +- - 189 files changed, 90549 insertions(+), 3 deletions(-) - create mode 100644 default-configs/arc-softmmu.mak - create mode 100644 default-configs/devices/arc-softmmu.mak - create mode 100644 default-configs/devices/arc64-softmmu.mak - create mode 100644 default-configs/targets/arc-softmmu.mak - create mode 100644 default-configs/targets/arc64-softmmu.mak - create mode 100644 disas/arc.c - create mode 100644 gdb-xml/arc-core-v3.xml - create mode 100644 gdb-xml/arc-v2-aux.xml - create mode 100644 gdb-xml/arc-v2-core.xml - create mode 100644 gdb-xml/arc-v2-other.xml - create mode 100644 gdb-xml/arc64-aux-minimal.xml - create mode 100644 gdb-xml/arc64-aux-other.xml - create mode 100644 hw/arc/Kconfig - create mode 100644 hw/arc/arc_sim.c - create mode 100644 hw/arc/boot.c - create mode 100644 hw/arc/boot.h - create mode 100644 hw/arc/meson.build - create mode 100644 hw/arc/pic_cpu.c - create mode 100644 hw/arc/virt.c - create mode 100644 include/hw/arc/cpudevs.h - create mode 100644 target/arc/arc-common.h - create mode 100644 target/arc/cache.c - create mode 100644 target/arc/cache.h - create mode 100644 target/arc/cpu-param.h - create mode 100644 target/arc/cpu-qom.h - create mode 100644 target/arc/cpu.c - create mode 100644 target/arc/cpu.h - create mode 100644 target/arc/decoder-v3.c - create mode 100644 target/arc/decoder-v3.h - create mode 100644 target/arc/decoder.c - create mode 100644 target/arc/decoder.h - create mode 100644 target/arc/extra_mapping.def - create mode 100644 target/arc/flags-v3.def - create mode 100644 target/arc/flags.def - create mode 100644 target/arc/gdbstub.c - create mode 100644 target/arc/gdbstub.h - create mode 100644 target/arc/helper.c - create mode 100644 target/arc/helper.h - create mode 100644 target/arc/irq.c - create mode 100644 target/arc/irq.h - create mode 100644 target/arc/meson.build - create mode 100644 target/arc/mmu-v6.c - create mode 100644 target/arc/mmu-v6.h - create mode 100644 target/arc/mmu.c - create mode 100644 target/arc/mmu.h - create mode 100644 target/arc/mpu.c - create mode 100644 target/arc/mpu.h - create mode 100644 target/arc/op_helper.c - create mode 100644 target/arc/opcodes-v3.def - create mode 100644 target/arc/opcodes.def - create mode 100644 target/arc/operands-v3.def - create mode 100644 target/arc/operands.def - create mode 100644 target/arc/regs-detail.def - create mode 100644 target/arc/regs-impl.c - create mode 100644 target/arc/regs.c - create mode 100644 target/arc/regs.def - create mode 100644 target/arc/regs.h - create mode 100644 target/arc/semfunc-helper.c - create mode 100644 target/arc/semfunc-helper.h - create mode 100644 target/arc/semfunc-v2_mapping.def - create mode 100644 target/arc/semfunc-v3.c - create mode 100644 target/arc/semfunc-v3.h - create mode 100644 target/arc/semfunc-v3_mapping.def - create mode 100644 target/arc/semfunc.c - create mode 100644 target/arc/semfunc.h - create mode 100644 target/arc/semfunc_generator/Gemfile - create mode 100644 target/arc/semfunc_generator/README - create mode 100644 target/arc/semfunc_generator/classes/CreateInternalVars.rb - create mode 100644 target/arc/semfunc_generator/classes/DecomposeExpressions.rb - create mode 100644 target/arc/semfunc_generator/classes/IdentifyQEmuStaticInferedParts.rb - create mode 100644 target/arc/semfunc_generator/classes/QEmuCompiler.rb - create mode 100644 target/arc/semfunc_generator/classes/QEmuTranslator.rb - create mode 100644 target/arc/semfunc_generator/classes/SemanticFunctionAST.rb - create mode 100644 target/arc/semfunc_generator/classes/SpaghettiCodePass.rb - create mode 100644 target/arc/semfunc_generator/classes/SpaghettiCodePass1.rb - create mode 100644 target/arc/semfunc_generator/classes/UnfoldCode.rb - create mode 100644 target/arc/semfunc_generator/init.rb - create mode 100644 target/arc/semfunc_generator/modules/Compiler.rb - create mode 100644 target/arc/semfunc_generator/modules/ConstantTables.rb - create mode 100644 target/arc/semfunc_generator/modules/Pass.rb - create mode 100644 target/arc/semfunc_generator/modules/SemanticFunctionASTBlockOperators.rb - create mode 100644 target/arc/semfunc_generator/modules/SemanticFunctionASTFactory.rb - create mode 100644 target/arc/semfunc_generator/modules/Translator.rb - create mode 100644 target/arc/semfunc_generator/modules/TranslatorAST.rb - create mode 100644 target/arc/semfunc_generator/modules/TranslatorFinal.rb - create mode 100644 target/arc/semfunc_generator/parsers/SemanticFunctionParser.tab.rb - create mode 100644 target/arc/semfunc_generator/parsers/SemanticFunctionParser.y - create mode 100644 target/arc/semfunc_generator/regenerate_semfunc.rb - create mode 100644 target/arc/semfunc_mapping.def - create mode 100644 target/arc/timer.c - create mode 100644 target/arc/timer.h - create mode 100644 target/arc/translate.c - create mode 100644 target/arc/translate.h - create mode 100644 tests/tcg/arc/Makefile - create mode 100644 tests/tcg/arc/Makefile.softmmu-target - create mode 100644 tests/tcg/arc/Makefile.target - create mode 100644 tests/tcg/arc/check_add.S - create mode 100644 tests/tcg/arc/check_addx.S - create mode 100644 tests/tcg/arc/check_andx.S - create mode 100644 tests/tcg/arc/check_aslx.S - create mode 100644 tests/tcg/arc/check_asrx.S - create mode 100644 tests/tcg/arc/check_basic1.S - create mode 100644 tests/tcg/arc/check_basic2.S - create mode 100644 tests/tcg/arc/check_beq.S - create mode 100644 tests/tcg/arc/check_beqx.S - create mode 100644 tests/tcg/arc/check_bi.S - create mode 100644 tests/tcg/arc/check_big_tb.S - create mode 100644 tests/tcg/arc/check_bih.S - create mode 100644 tests/tcg/arc/check_bnex.S - create mode 100644 tests/tcg/arc/check_breqx.S - create mode 100644 tests/tcg/arc/check_brgex.S - create mode 100644 tests/tcg/arc/check_brhsx.S - create mode 100644 tests/tcg/arc/check_brlox.S - create mode 100644 tests/tcg/arc/check_brltx.S - create mode 100644 tests/tcg/arc/check_brnex.S - create mode 100644 tests/tcg/arc/check_bta.S - create mode 100644 tests/tcg/arc/check_carry.S - create mode 100644 tests/tcg/arc/check_enter_leave.S - create mode 100644 tests/tcg/arc/check_excp.S - create mode 100644 tests/tcg/arc/check_excp_1.c - create mode 100644 tests/tcg/arc/check_excp_jumpdl_mmu.S - create mode 100644 tests/tcg/arc/check_excp_mmu.S - create mode 100644 tests/tcg/arc/check_flags.S - create mode 100644 tests/tcg/arc/check_ldaw_mmu.S - create mode 100644 tests/tcg/arc/check_ldstx.S - create mode 100644 tests/tcg/arc/check_lp.S - create mode 100644 tests/tcg/arc/check_lp02.S - create mode 100644 tests/tcg/arc/check_lp03.S - create mode 100644 tests/tcg/arc/check_lp04.S - create mode 100644 tests/tcg/arc/check_lp05.S - create mode 100644 tests/tcg/arc/check_lp06.S - create mode 100644 tests/tcg/arc/check_lsrx.S - create mode 100644 tests/tcg/arc/check_mac.S - create mode 100644 tests/tcg/arc/check_manip_10_mmu.S - create mode 100644 tests/tcg/arc/check_manip_4_mmu.S - create mode 100644 tests/tcg/arc/check_manip_5_mmu.S - create mode 100644 tests/tcg/arc/check_manip_mmu.S - create mode 100644 tests/tcg/arc/check_mmu.S - create mode 100644 tests/tcg/arc/check_mpu.S - create mode 100644 tests/tcg/arc/check_mpyd.S - create mode 100644 tests/tcg/arc/check_mpyw.S - create mode 100644 tests/tcg/arc/check_norm.S - create mode 100644 tests/tcg/arc/check_orx.S - create mode 100644 tests/tcg/arc/check_prefetch.S - create mode 100644 tests/tcg/arc/check_rolx.S - create mode 100644 tests/tcg/arc/check_rorx.S - create mode 100644 tests/tcg/arc/check_rtc.S - create mode 100644 tests/tcg/arc/check_rtie_user.S - create mode 100644 tests/tcg/arc/check_stld.S - create mode 100644 tests/tcg/arc/check_subf.S - create mode 100644 tests/tcg/arc/check_subx.S - create mode 100644 tests/tcg/arc/check_swi.S - create mode 100644 tests/tcg/arc/check_swirq.S - create mode 100644 tests/tcg/arc/check_swirq1.S - create mode 100644 tests/tcg/arc/check_swirq3.S - create mode 100644 tests/tcg/arc/check_t01.S - create mode 100644 tests/tcg/arc/check_t02.S - create mode 100644 tests/tcg/arc/check_timer0.S - create mode 100644 tests/tcg/arc/check_timer0_loop.S - create mode 100644 tests/tcg/arc/check_timer0_loop3.S - create mode 100644 tests/tcg/arc/check_timer0_retrig.S - create mode 100644 tests/tcg/arc/check_timer0_sleep.S - create mode 100644 tests/tcg/arc/check_timerX_freq.S - create mode 100644 tests/tcg/arc/check_vadd.S - create mode 100644 tests/tcg/arc/check_vsub.S - create mode 100644 tests/tcg/arc/check_xorx.S - create mode 100644 tests/tcg/arc/ivt.S - create mode 100644 tests/tcg/arc/macros.inc - create mode 100644 tests/tcg/arc/memory.x - create mode 100644 tests/tcg/arc/mmu.inc - create mode 100644 tests/tcg/arc/mpu.inc - create mode 100644 tests/tcg/arc/tarc.ld - create mode 100644 tests/tcg/arc/tarc_mmu.ld - create mode 100644 tests/tcg/arc/test_macros.h - -diff --git a/configure b/configure -index 4f374b4889..c5b199c3fc 100755 ---- a/configure -+++ b/configure -@@ -680,6 +680,10 @@ elif check_define __arm__ ; then - cpu="arm" - elif check_define __aarch64__ ; then - cpu="aarch64" -+elif check_define __arc__ ; then -+ cpu="arc" -+elif check_define __arc64__ ; then -+ cpu="arc64" - else - cpu=$(uname -m) - fi -diff --git a/default-configs/arc-softmmu.mak b/default-configs/arc-softmmu.mak -new file mode 100644 -index 0000000000..4300a90c93 ---- /dev/null -+++ b/default-configs/arc-softmmu.mak -@@ -0,0 +1,5 @@ -+# Default configuration for arc-softmmu -+ -+CONFIG_VIRTIO_MMIO=y -+CONFIG_SERIAL=y -+CONFIG_OPENCORES_ETH=y -diff --git a/default-configs/devices/arc-softmmu.mak b/default-configs/devices/arc-softmmu.mak -new file mode 100644 -index 0000000000..0ce4176b2d ---- /dev/null -+++ b/default-configs/devices/arc-softmmu.mak -@@ -0,0 +1,7 @@ -+# Default configuration for arc-softmmu -+ -+CONFIG_SEMIHOSTING=n -+ -+# Boards: -+# -+CONFIG_ARC_VIRT=y -diff --git a/default-configs/devices/arc64-softmmu.mak b/default-configs/devices/arc64-softmmu.mak -new file mode 100644 -index 0000000000..0ce4176b2d ---- /dev/null -+++ b/default-configs/devices/arc64-softmmu.mak -@@ -0,0 +1,7 @@ -+# Default configuration for arc-softmmu -+ -+CONFIG_SEMIHOSTING=n -+ -+# Boards: -+# -+CONFIG_ARC_VIRT=y -diff --git a/default-configs/targets/arc-softmmu.mak b/default-configs/targets/arc-softmmu.mak -new file mode 100644 -index 0000000000..a50b090b97 ---- /dev/null -+++ b/default-configs/targets/arc-softmmu.mak -@@ -0,0 +1,3 @@ -+TARGET_ARCH=arcv2 -+TARGET_BASE_ARCH=arc -+TARGET_XML_FILES= gdb-xml/arc-v2-core.xml gdb-xml/arc-v2-aux.xml gdb-xml/arc-v2-other.xml -diff --git a/default-configs/targets/arc64-softmmu.mak b/default-configs/targets/arc64-softmmu.mak -new file mode 100644 -index 0000000000..af39b7c34d ---- /dev/null -+++ b/default-configs/targets/arc64-softmmu.mak -@@ -0,0 +1,3 @@ -+TARGET_ARCH=arcv3 -+TARGET_BASE_ARCH=arc -+TARGET_XML_FILES= gdb-xml/arc-core-v3.xml gdb-xml/arc64-aux-minimal.xml gdb-xml/arc64-aux-other.xml -diff --git a/disas.c b/disas.c -index a61f95b580..a10fa41330 100644 ---- a/disas.c -+++ b/disas.c -@@ -208,6 +208,8 @@ static void initialize_debug_host(CPUDebug *s) - s->info.cap_insn_split = 6; - #elif defined(__hppa__) - s->info.print_insn = print_insn_hppa; -+#elif defined(__arc__) -+ s->info.print_insn = print_insn_arc; - #endif - } - -diff --git a/disas/arc.c b/disas/arc.c -new file mode 100644 -index 0000000000..9a9c289948 ---- /dev/null -+++ b/disas/arc.c -@@ -0,0 +1,455 @@ -+/* -+ * Disassembler code for ARC. -+ * -+ * Copyright 2020 Synopsys Inc. -+ * Contributed by Claudiu Zissulescu -+ * -+ * QEMU ARCv2 Disassembler. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2, or (at your option) any later -+ * version. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see . -+ */ -+ -+#include "qemu/osdep.h" -+#include "qemu-common.h" -+#include "disas/dis-asm.h" -+#include "target/arc/arc-common.h" -+ -+#include "target/arc/decoder.h" -+ -+#define ARRANGE_ENDIAN(info, buf) \ -+ (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32(bfd_getl32(buf)) \ -+ : bfd_getb32(buf)) -+ -+/* -+ * Helper function to convert middle-endian data to something more -+ * meaningful. -+ */ -+ -+static bfd_vma bfd_getm32(unsigned int data) -+{ -+ bfd_vma value = 0; -+ -+ value = (data & 0x0000ffff) << 16; -+ value |= (data & 0xffff0000) >> 16; -+ return value; -+} -+ -+/* Helper for printing instruction flags. */ -+ -+bool special_flag_p(const char *opname, const char *flgname); -+bool special_flag_p(const char *opname, const char *flgname) -+{ -+ const struct arc_flag_special *flg_spec; -+ unsigned i, j, flgidx; -+ -+ for (i = 0; i < arc_num_flag_special; ++i) { -+ flg_spec = &arc_flag_special_cases[i]; -+ -+ if (strcmp(opname, flg_spec->name) != 0) { -+ continue; -+ } -+ -+ /* Found potential special case instruction. */ -+ for (j = 0; ; ++j) { -+ flgidx = flg_spec->flags[j]; -+ if (flgidx == 0) { -+ break; /* End of the array. */ -+ } -+ -+ if (strcmp(flgname, arc_flag_operands[flgidx].name) == 0) { -+ return TRUE; -+ } -+ } -+ } -+ return FALSE; -+} -+ -+/* Print instruction flags. */ -+ -+static void print_flags(const struct arc_opcode *opcode, -+ uint64_t insn, -+ struct disassemble_info *info) -+{ -+ const unsigned char *flgidx; -+ unsigned int value; -+ -+ /* Now extract and print the flags. */ -+ for (flgidx = opcode->flags; *flgidx; flgidx++) { -+ /* Get a valid flag class. */ -+ const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; -+ const unsigned *flgopridx; -+ -+ /* Check first the extensions. Not supported yet. */ -+ if (cl_flags->flag_class & F_CLASS_EXTEND) { -+ value = insn & 0x1F; -+ } -+ -+ for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) { -+ const struct arc_flag_operand *flg_operand = -+ &arc_flag_operands[*flgopridx]; -+ -+ /* Implicit flags are only used for the insn decoder. */ -+ if (cl_flags->flag_class & F_CLASS_IMPLICIT) { -+ continue; -+ } -+ -+ if (!flg_operand->favail) { -+ continue; -+ } -+ -+ value = (insn >> flg_operand->shift) & -+ ((1 << flg_operand->bits) - 1); -+ if (value == flg_operand->code) { -+ /* FIXME!: print correctly nt/t flag. */ -+ if (!special_flag_p(opcode->name, flg_operand->name)) { -+ (*info->fprintf_func)(info->stream, "."); -+ } -+ (*info->fprintf_func)(info->stream, "%s", flg_operand->name); -+ } -+ } -+ } -+} -+ -+/* -+ * When dealing with auxiliary registers, output the proper name if we -+ * have it. -+ */ -+extern const char *get_auxreg(const struct arc_opcode *opcode, -+ int value, -+ unsigned isa_mask); -+ -+/* Print the operands of an instruction. */ -+ -+static void print_operands(const struct arc_opcode *opcode, -+ bfd_vma memaddr, -+ uint64_t insn, -+ uint32_t isa_mask, -+ insn_t *pinsn, -+ struct disassemble_info *info) -+{ -+ bfd_boolean need_comma = FALSE; -+ bfd_boolean open_braket = FALSE; -+ int value, vpcl = 0; -+ bfd_boolean rpcl = FALSE, rset = FALSE; -+ const unsigned char *opidx; -+ int i; -+ -+ for (i = 0, opidx = opcode->operands; *opidx; opidx++) { -+ const struct arc_operand *operand = &arc_operands[*opidx]; -+ -+ if (open_braket && (operand->flags & ARC_OPERAND_BRAKET)) { -+ (*info->fprintf_func)(info->stream, "]"); -+ open_braket = FALSE; -+ continue; -+ } -+ -+ /* Only take input from real operands. */ -+ if (ARC_OPERAND_IS_FAKE(operand)) { -+ continue; -+ } -+ -+ if (need_comma) { -+ (*info->fprintf_func)(info->stream, ","); -+ } -+ -+ if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET)) { -+ (*info->fprintf_func)(info->stream, "["); -+ open_braket = TRUE; -+ need_comma = FALSE; -+ continue; -+ } -+ -+ need_comma = TRUE; -+ -+ /* Get the decoded */ -+ value = pinsn->operands[i++].value; -+ -+ if ((operand->flags & ARC_OPERAND_IGNORE) && -+ (operand->flags & ARC_OPERAND_IR) && -+ value == -1) { -+ need_comma = FALSE; -+ continue; -+ } -+ -+ if (operand->flags & ARC_OPERAND_PCREL) { -+ rpcl = TRUE; -+ vpcl = value; -+ rset = TRUE; -+ -+ info->target = (bfd_vma) (memaddr & ~3) + value; -+ } else if (!(operand->flags & ARC_OPERAND_IR)) { -+ vpcl = value; -+ rset = TRUE; -+ } -+ -+ /* Print the operand as directed by the flags. */ -+ if (operand->flags & ARC_OPERAND_IR) { -+ const char *rname; -+ -+ assert(value >= 0 && value < 64); -+ rname = get_register_name(value); -+ (*info->fprintf_func)(info->stream, "%s", rname); -+ if (operand->flags & ARC_OPERAND_TRUNCATE) { -+ /* Make sure we print only legal register pairs. */ -+ if ((value & 0x01) == 0) { -+ rname = get_register_name(value+1); -+ } -+ (*info->fprintf_func)(info->stream, "%s", rname); -+ } -+ if (value == 63) { -+ rpcl = TRUE; -+ } else { -+ rpcl = FALSE; -+ } -+ } else if (operand->flags & ARC_OPERAND_LIMM) { -+ value = pinsn->limm; -+ const char *rname = get_auxreg(opcode, value, isa_mask); -+ -+ if (rname && open_braket) { -+ (*info->fprintf_func)(info->stream, "%s", rname); -+ } else { -+ (*info->fprintf_func)(info->stream, "%#x", value); -+ } -+ } else if (operand->flags & ARC_OPERAND_SIGNED) { -+ const char *rname = get_auxreg(opcode, value, isa_mask); -+ if (rname && open_braket) { -+ (*info->fprintf_func)(info->stream, "%s", rname); -+ } else { -+ (*info->fprintf_func)(info->stream, "%d", value); -+ } -+ } else { -+ if (operand->flags & ARC_OPERAND_TRUNCATE && -+ !(operand->flags & ARC_OPERAND_ALIGNED32) && -+ !(operand->flags & ARC_OPERAND_ALIGNED16) && -+ value >= 0 && value <= 14) { -+ /* Leave/Enter mnemonics. */ -+ switch (value) { -+ case 0: -+ need_comma = FALSE; -+ break; -+ case 1: -+ (*info->fprintf_func)(info->stream, "r13"); -+ break; -+ default: -+ (*info->fprintf_func)(info->stream, "r13-%s", -+ get_register_name(13 + value - 1)); -+ break; -+ } -+ rpcl = FALSE; -+ rset = FALSE; -+ } else { -+ const char *rname = get_auxreg(opcode, value, isa_mask); -+ if (rname && open_braket) { -+ (*info->fprintf_func)(info->stream, "%s", rname); -+ } else { -+ (*info->fprintf_func)(info->stream, "%#x", value); -+ } -+ } -+ } -+ } -+ -+ /* Pretty print extra info for pc-relative operands. */ -+ if (rpcl && rset) { -+ if (info->flags & INSN_HAS_RELOC) { -+ /* -+ * If the instruction has a reloc associated with it, then -+ * the offset field in the instruction will actually be -+ * the addend for the reloc. (We are using REL type -+ * relocs). In such cases, we can ignore the pc when -+ * computing addresses, since the addend is not currently -+ * pc-relative. -+ */ -+ memaddr = 0; -+ } -+ -+ (*info->fprintf_func)(info->stream, "\t;"); -+ (*info->print_address_func)((memaddr & ~3) + vpcl, info); -+ } -+} -+ -+/* Select the proper instructions set for the given architecture. */ -+ -+static int arc_read_mem(bfd_vma memaddr, -+ uint64_t *insn, -+ uint32_t *isa_mask, -+ struct disassemble_info *info) -+{ -+ bfd_byte buffer[8]; -+ unsigned int highbyte, lowbyte; -+ int status; -+ int insn_len = 0; -+ -+ highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0); -+ lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1); -+ -+ switch (info->mach) { -+ case bfd_mach_arc_arc700: -+ *isa_mask = ARC_OPCODE_ARC700; -+ break; -+ case bfd_mach_arc_arc601: -+ case bfd_mach_arc_arc600: -+ *isa_mask = ARC_OPCODE_ARC600; -+ break; -+ case bfd_mach_arc_arcv2em: -+ case bfd_mach_arc_arcv2: -+ *isa_mask = ARC_OPCODE_ARCv2EM; -+ break; -+ case bfd_mach_arc_arcv2hs: -+ *isa_mask = ARC_OPCODE_ARCv2HS; -+ break; -+ case bfd_mach_arcv3_64: -+ *isa_mask = ARC_OPCODE_V3_ARC64; -+ break; -+ case bfd_mach_arcv3_32: -+ *isa_mask = ARC_OPCODE_V3_ARC32; -+ break; -+ -+ default: -+ *isa_mask = ARC_OPCODE_NONE; -+ break; -+ } -+ -+ info->bytes_per_line = 8; -+ info->bytes_per_chunk = 2; -+ info->display_endian = info->endian; -+ -+ /* Read the insn into a host word. */ -+ status = (*info->read_memory_func)(memaddr, buffer, 2, info); -+ -+ if (status != 0) { -+ (*info->memory_error_func)(status, memaddr, info); -+ return -1; -+ } -+ -+ insn_len = arc_insn_length((buffer[highbyte] << 8 | -+ buffer[lowbyte]), *isa_mask); -+ -+ switch (insn_len) { -+ case 2: -+ *insn = (buffer[highbyte] << 8) | buffer[lowbyte]; -+ break; -+ -+ case 4: -+ /* This is a long instruction: Read the remaning 2 bytes. */ -+ status = (*info->read_memory_func)(memaddr + 2, &buffer[2], 2, info); -+ if (status != 0) { -+ (*info->memory_error_func)(status, memaddr + 2, info); -+ return -1; -+ } -+ *insn = (uint64_t) ARRANGE_ENDIAN(info, buffer); -+ break; -+ -+ case 6: -+ status = (*info->read_memory_func)(memaddr + 2, &buffer[2], 4, info); -+ if (status != 0) { -+ (*info->memory_error_func)(status, memaddr + 2, info); -+ return -1; -+ } -+ *insn = (uint64_t) ARRANGE_ENDIAN(info, &buffer[2]); -+ *insn |= ((uint64_t) buffer[highbyte] << 40) | -+ ((uint64_t) buffer[lowbyte] << 32); -+ break; -+ -+ case 8: -+ status = (*info->read_memory_func)(memaddr + 2, &buffer[2], 6, info); -+ if (status != 0) { -+ (*info->memory_error_func)(status, memaddr + 2, info); -+ return -1; -+ } -+ *insn = ((((uint64_t) ARRANGE_ENDIAN(info, buffer)) << 32) | -+ ((uint64_t) ARRANGE_ENDIAN(info, &buffer[4]))); -+ break; -+ -+ default: -+ /* There is no instruction whose length is not 2, 4, 6, or 8. */ -+ g_assert_not_reached(); -+ } -+ return insn_len; -+} -+ -+/* Disassembler main entry function. */ -+ -+int print_insn_arc(bfd_vma memaddr, struct disassemble_info *info) -+{ -+ const struct arc_opcode *opcode = NULL; -+ int insn_len = -1; -+ uint64_t insn; -+ uint32_t isa_mask; -+ insn_t dis_insn; -+ -+ insn_len = arc_read_mem(memaddr, &insn, &isa_mask, info); -+ -+ if (insn_len < 2) { -+ return -1; -+ } -+ -+ opcode = arc_find_format(&dis_insn, insn, insn_len, isa_mask); -+ -+ /* If limm is required, read it. */ -+ if((isa_mask & ARC_OPCODE_V3_ALL) != 0) { -+ if (dis_insn.unsigned_limm_p) { -+ bfd_byte buffer[4]; -+ int status = (*info->read_memory_func)(memaddr + insn_len, buffer, -+ 4, info); -+ if (status != 0) { -+ return -1; -+ } -+ dis_insn.limm = ARRANGE_ENDIAN (info, buffer); -+ insn_len += 4; -+ } -+ else if (dis_insn.signed_limm_p) { -+ bfd_byte buffer[4]; -+ int status = (*info->read_memory_func)(memaddr + insn_len, buffer, -+ 4, info); -+ if (status != 0) { -+ return -1; -+ } -+ dis_insn.limm = ARRANGE_ENDIAN (info, buffer); -+ if(dis_insn.limm & 0x80000000) -+ dis_insn.limm += 0xffffffff00000000; -+ insn_len += 4; -+ } -+ -+ } else { -+ if (dis_insn.limm_p) { -+ bfd_byte buffer[4]; -+ int status = (*info->read_memory_func)(memaddr + insn_len, buffer, -+ 4, info); -+ if (status != 0) { -+ return -1; -+ } -+ dis_insn.limm = ARRANGE_ENDIAN(info, buffer); -+ insn_len += 4; -+ } -+ } -+ -+ /* Print the mnemonic. */ -+ (*info->fprintf_func)(info->stream, "%s", opcode->name); -+ -+ print_flags(opcode, insn, info); -+ -+ if (opcode->operands[0] != 0) { -+ (*info->fprintf_func)(info->stream, "\t"); -+ } -+ -+ /* Now extract and print the operands. */ -+ print_operands(opcode, memaddr, insn, isa_mask, &dis_insn, info); -+ -+ /* Say how many bytes we consumed */ -+ return insn_len; -+} -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/disas/meson.build b/disas/meson.build -index 4c8da01877..c35836fa9f 100644 ---- a/disas/meson.build -+++ b/disas/meson.build -@@ -4,6 +4,7 @@ subdir('libvixl') - common_ss.add(when: 'CONFIG_ALPHA_DIS', if_true: files('alpha.c')) - common_ss.add(when: 'CONFIG_ARM_A64_DIS', if_true: files('arm-a64.cc')) - common_ss.add_all(when: 'CONFIG_ARM_A64_DIS', if_true: libvixl_ss) -+common_ss.add(when: 'CONFIG_ARC_DIS', if_true: files('arc.c')) - common_ss.add(when: 'CONFIG_ARM_DIS', if_true: files('arm.c')) - common_ss.add(when: 'CONFIG_CRIS_DIS', if_true: files('cris.c')) - common_ss.add(when: 'CONFIG_HEXAGON_DIS', if_true: files('hexagon.c')) -diff --git a/gdb-xml/arc-core-v3.xml b/gdb-xml/arc-core-v3.xml -new file mode 100644 -index 0000000000..fdca31b4c3 ---- /dev/null -+++ b/gdb-xml/arc-core-v3.xml -@@ -0,0 +1,45 @@ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/gdb-xml/arc-v2-aux.xml b/gdb-xml/arc-v2-aux.xml -new file mode 100644 -index 0000000000..e18168ad05 ---- /dev/null -+++ b/gdb-xml/arc-v2-aux.xml -@@ -0,0 +1,32 @@ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/gdb-xml/arc-v2-core.xml b/gdb-xml/arc-v2-core.xml -new file mode 100644 -index 0000000000..c925a6994c ---- /dev/null -+++ b/gdb-xml/arc-v2-core.xml -@@ -0,0 +1,45 @@ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/gdb-xml/arc-v2-other.xml b/gdb-xml/arc-v2-other.xml -new file mode 100644 -index 0000000000..9824f518cc ---- /dev/null -+++ b/gdb-xml/arc-v2-other.xml -@@ -0,0 +1,235 @@ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/gdb-xml/arc64-aux-minimal.xml b/gdb-xml/arc64-aux-minimal.xml -new file mode 100644 -index 0000000000..56c3f2f698 ---- /dev/null -+++ b/gdb-xml/arc64-aux-minimal.xml -@@ -0,0 +1,32 @@ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/gdb-xml/arc64-aux-other.xml b/gdb-xml/arc64-aux-other.xml -new file mode 100644 -index 0000000000..75a120b894 ---- /dev/null -+++ b/gdb-xml/arc64-aux-other.xml -@@ -0,0 +1,177 @@ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/hw/Kconfig b/hw/Kconfig -index ff40bd3f7b..cdc0d380a3 100644 ---- a/hw/Kconfig -+++ b/hw/Kconfig -@@ -41,6 +41,7 @@ source vfio/Kconfig - source watchdog/Kconfig - - # arch Kconfig -+source arc/Kconfig - source arm/Kconfig - source alpha/Kconfig - source avr/Kconfig -diff --git a/hw/arc/Kconfig b/hw/arc/Kconfig -new file mode 100644 -index 0000000000..b47afbcdf2 ---- /dev/null -+++ b/hw/arc/Kconfig -@@ -0,0 +1,9 @@ -+config ARC_VIRT -+ bool -+ select SERIAL -+ select VIRTIO_MMIO -+ select PCI_EXPRESS_GENERIC_BRIDGE -+ select PCI_DEVICES -+ -+config ARC -+ bool -diff --git a/hw/arc/arc_sim.c b/hw/arc/arc_sim.c -new file mode 100644 -index 0000000000..64db440454 ---- /dev/null -+++ b/hw/arc/arc_sim.c -@@ -0,0 +1,124 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "qapi/error.h" -+#include "cpu.h" -+#include "hw/hw.h" -+#include "hw/boards.h" -+#include "elf.h" -+#include "hw/char/serial.h" -+#include "net/net.h" -+#include "hw/loader.h" -+#include "exec/memory.h" -+#include "exec/address-spaces.h" -+#include "sysemu/reset.h" -+#include "sysemu/runstate.h" -+#include "sysemu/sysemu.h" -+#include "hw/sysbus.h" -+#include "hw/arc/cpudevs.h" -+#include "boot.h" -+ -+ -+static uint64_t arc_io_read(void *opaque, hwaddr addr, unsigned size) -+{ -+ return 0; -+} -+ -+static void arc_io_write(void *opaque, hwaddr addr, -+ uint64_t val, unsigned size) -+{ -+ switch (addr) { -+ case 0x08: /* board reset. */ -+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); -+ break; -+ default: -+ break; -+ } -+} -+ -+static const MemoryRegionOps arc_io_ops = { -+ .read = arc_io_read, -+ .write = arc_io_write, -+ .endianness = DEVICE_NATIVE_ENDIAN, -+}; -+ -+static void arc_sim_init(MachineState *machine) -+{ -+ static struct arc_boot_info boot_info; -+ unsigned int smp_cpus = machine->smp.cpus; -+ ram_addr_t ram_base = 0; -+ ram_addr_t ram_size = machine->ram_size; -+ ARCCPU *cpu = NULL; -+ MemoryRegion *ram, *system_io; -+ int n; -+ -+ boot_info.ram_start = ram_base; -+ boot_info.ram_size = ram_size; -+ boot_info.kernel_filename = machine->kernel_filename; -+ -+ for (n = 0; n < smp_cpus; n++) { -+ cpu = ARC_CPU(object_new(machine->cpu_type)); -+ if (cpu == NULL) { -+ fprintf(stderr, "Unable to find CPU definition!\n"); -+ exit(1); -+ } -+ -+ /* Set the initial CPU properties. */ -+ object_property_set_uint(OBJECT(cpu), "freq_hz", 1000000, &error_fatal); -+ object_property_set_bool(OBJECT(cpu), "rtc-opt", true, &error_fatal); -+ object_property_set_bool(OBJECT(cpu), "realized", true, &error_fatal); -+ -+ /* Initialize internal devices. */ -+ cpu_arc_pic_init(cpu); -+ cpu_arc_clock_init(cpu); -+ -+ qemu_register_reset(arc_cpu_reset, cpu); -+ } -+ -+ ram = g_new(MemoryRegion, 1); -+ memory_region_init_ram(ram, NULL, "arc.ram", ram_size, &error_fatal); -+ memory_region_add_subregion(get_system_memory(), ram_base, ram); -+ -+ system_io = g_new(MemoryRegion, 1); -+ memory_region_init_io(system_io, NULL, &arc_io_ops, NULL, "arc.io", -+ 1024); -+ memory_region_add_subregion(get_system_memory(), 0xf0000000, system_io); -+ -+ serial_mm_init(get_system_memory(), 0x90000000, 2, cpu->env.irq[20], -+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); -+ -+ arc_load_kernel(cpu, &boot_info); -+} -+ -+static void arc_sim_machine_init(MachineClass *mc) -+{ -+ mc->desc = "ARCxx simulation"; -+ mc->init = arc_sim_init; -+ mc->max_cpus = 1; -+ mc->is_default = false; -+ mc->default_cpu_type = ARC_CPU_TYPE_NAME("archs"); -+} -+ -+DEFINE_MACHINE("arc-sim", arc_sim_machine_init) -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/hw/arc/boot.c b/hw/arc/boot.c -new file mode 100644 -index 0000000000..0af559e44b ---- /dev/null -+++ b/hw/arc/boot.c -@@ -0,0 +1,101 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "boot.h" -+#include "elf.h" -+#include "hw/loader.h" -+#include "qemu/error-report.h" -+#include "qemu/units.h" -+ -+void arc_cpu_reset(void *opaque) -+{ -+ ARCCPU *cpu = opaque; -+ CPUARCState *env = &cpu->env; -+ const struct arc_boot_info *info = env->boot_info; -+ -+ cpu_reset(CPU(cpu)); -+ -+ /* -+ * Right before start CPU gets reset wiping out everything -+ * but PC which we set on Elf load. -+ * -+ * And if we still want to pass something like U-Boot data -+ * via CPU registers we have to do it here. -+ */ -+ -+ if (info->kernel_cmdline && strlen(info->kernel_cmdline)) { -+ /* -+ * Load "cmdline" far enough from the kernel image. -+ * Round by MAX page size for ARC - 16 KiB. -+ */ -+ hwaddr cmdline_addr = info->ram_start + -+ QEMU_ALIGN_UP(info->ram_size / 2, 16 * KiB); -+ cpu_physical_memory_write(cmdline_addr, info->kernel_cmdline, -+ strlen(info->kernel_cmdline)); -+ -+ /* We're passing "cmdline" */ -+ cpu->env.r[0] = ARC_UBOOT_CMDLINE; -+ cpu->env.r[2] = cmdline_addr; -+ } -+} -+ -+ -+void arc_load_kernel(ARCCPU *cpu, struct arc_boot_info *info) -+{ -+ hwaddr entry; -+ int elf_machine, kernel_size; -+ -+ if (!info->kernel_filename) { -+ error_report("missing kernel file"); -+ exit(EXIT_FAILURE); -+ } -+ -+ elf_machine = cpu->family > 2 ? EM_ARC_COMPACT2 : EM_ARC_COMPACT; -+ elf_machine = (cpu->family & ARC_OPCODE_V3_ALL) != 0 ? EM_ARC_COMPACT3_64 : elf_machine; -+ kernel_size = load_elf(info->kernel_filename, NULL, NULL, NULL, -+ &entry, NULL, NULL, NULL, ARC_ENDIANNESS_LE, -+ elf_machine, 1, 0); -+ -+ if (kernel_size < 0) { -+ int is_linux; -+ -+ kernel_size = load_uimage(info->kernel_filename, &entry, NULL, -+ &is_linux, NULL, NULL); -+ if (!is_linux) { -+ error_report("Wrong U-Boot image, only Linux kernel is supported"); -+ exit(EXIT_FAILURE); -+ } -+ } -+ -+ if (kernel_size < 0) { -+ error_report("No kernel image found"); -+ exit(EXIT_FAILURE); -+ } -+ -+ cpu->env.boot_info = info; -+ -+ /* Set CPU's PC to point to the entry-point */ -+ cpu->env.pc = entry; -+} -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/hw/arc/boot.h b/hw/arc/boot.h -new file mode 100644 -index 0000000000..e46aa16fc6 ---- /dev/null -+++ b/hw/arc/boot.h -@@ -0,0 +1,21 @@ -+#ifndef ARC_BOOT_H -+#define ARC_BOOT_H -+ -+#include "hw/hw.h" -+#include "cpu.h" -+ -+struct arc_boot_info { -+ hwaddr ram_start; -+ uint64_t ram_size; -+ const char *kernel_filename; -+ const char *kernel_cmdline; -+}; -+ -+void arc_cpu_reset(void *opaque); -+void arc_load_kernel(ARCCPU *cpu, struct arc_boot_info *boot_info); -+ -+#endif /* ARC_BOOT_H */ -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/hw/arc/meson.build b/hw/arc/meson.build -new file mode 100644 -index 0000000000..f3b517013d ---- /dev/null -+++ b/hw/arc/meson.build -@@ -0,0 +1,9 @@ -+arc_ss = ss.source_set() -+arc_ss.add(files( -+ 'arc_sim.c', -+ 'pic_cpu.c', -+ 'boot.c', -+)) -+arc_ss.add(when: 'CONFIG_ARC_VIRT', if_true: files('virt.c')) -+ -+hw_arch += {'arc': arc_ss} -diff --git a/hw/arc/pic_cpu.c b/hw/arc/pic_cpu.c -new file mode 100644 -index 0000000000..d41fa0fe4b ---- /dev/null -+++ b/hw/arc/pic_cpu.c -@@ -0,0 +1,113 @@ -+/* -+ * ARC Programmable Interrupt Controller support. -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+ -+#include "qemu/osdep.h" -+#include "cpu.h" -+#include "hw/hw.h" -+#include "hw/irq.h" -+#include "qemu/log.h" -+#include "hw/arc/cpudevs.h" -+ -+/* -+ * ARC pic handler -+ */ -+static void arc_pic_cpu_handler(void *opaque, int irq, int level) -+{ -+ ARCCPU *cpu = (ARCCPU *) opaque; -+ CPUState *cs = CPU(cpu); -+ CPUARCState *env = &cpu->env; -+ int i; -+ bool clear = false; -+ uint32_t irq_bit; -+ -+ /* Assert if this handler is called in a system without interrupts. */ -+ assert(cpu->cfg.has_interrupts); -+ -+ /* Assert if the IRQ is not within the cpu configuration bounds. */ -+ assert(irq >= 16 && irq < (cpu->cfg.number_of_interrupts + 15)); -+ -+ irq_bit = 1 << env->irq_bank[irq].priority; -+ if (level) { -+ /* -+ * An interrupt is enabled, update irq_priority_pendig and rise -+ * the qemu interrupt line. -+ */ -+ env->irq_bank[irq].pending = 1; -+ qatomic_or(&env->irq_priority_pending, irq_bit); -+ cpu_interrupt(cs, CPU_INTERRUPT_HARD); -+ } else { -+ env->irq_bank[irq].pending = 0; -+ -+ /* -+ * First, check if we still have any pending interrupt at the -+ * given priority. -+ */ -+ clear = true; -+ for (i = 16; i < cpu->cfg.number_of_interrupts; i++) { -+ if (env->irq_bank[i].pending -+ && env->irq_bank[i].priority == env->irq_bank[irq].priority) { -+ clear = false; -+ break; -+ } -+ } -+ -+ /* If not, update (clear) irq_priority_pending. */ -+ if (clear) { -+ qatomic_and(&env->irq_priority_pending, ~irq_bit); -+ } -+ -+ /* -+ * If we don't have any pending priority, lower the qemu irq -+ * line. N.B. we can also check more here like IE bit, but we -+ * need to add a cpu_interrupt call when we enable the -+ * interrupts (e.g., sleep, seti). -+ */ -+ if (!env->irq_priority_pending) { -+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); -+ } -+ } -+ qemu_log_mask(CPU_LOG_INT, -+ "[IRQ] level = %d, clear = %d, irq = %d, priority = " TARGET_FMT_lu ", " -+ "pending = %08x, pc = " TARGET_FMT_lx "\n", -+ level, clear, irq, env->irq_bank[irq].priority, -+ env->irq_priority_pending, env->pc); -+} -+ -+/* -+ * ARC PIC initialization helper -+ */ -+void cpu_arc_pic_init(ARCCPU *cpu) -+{ -+ CPUARCState *env = &cpu->env; -+ int i; -+ qemu_irq *qi; -+ -+ qi = qemu_allocate_irqs(arc_pic_cpu_handler, cpu, -+ 16 + cpu->cfg.number_of_interrupts); -+ -+ for (i = 0; i < cpu->cfg.number_of_interrupts; i++) { -+ env->irq[16 + i] = qi[16 + i]; -+ } -+} -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/hw/arc/virt.c b/hw/arc/virt.c -new file mode 100644 -index 0000000000..5ba05b6452 ---- /dev/null -+++ b/hw/arc/virt.c -@@ -0,0 +1,184 @@ -+/* -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see . -+ */ -+ -+#include "qemu/osdep.h" -+#include "qapi/error.h" -+#include "boot.h" -+#include "hw/boards.h" -+#include "hw/char/serial.h" -+#include "exec/address-spaces.h" -+#include "sysemu/reset.h" -+#include "sysemu/sysemu.h" -+#include "hw/arc/cpudevs.h" -+#include "hw/pci-host/gpex.h" -+#include "hw/sysbus.h" -+ -+#define VIRT_RAM_BASE 0x80000000 -+#define VIRT_RAM_SIZE 0x80000000 -+#define VIRT_IO_BASE 0xf0000000 -+#define VIRT_IO_SIZE 0x10000000 -+#define VIRT_UART0_OFFSET 0x0 -+#define VIRT_UART0_IRQ 24 -+ -+/* VirtIO */ -+#define VIRT_VIRTIO_NUMBER 5 -+#define VIRT_VIRTIO_OFFSET 0x100000 -+#define VIRT_VIRTIO_BASE (VIRT_IO_BASE + VIRT_VIRTIO_OFFSET) -+#define VIRT_VIRTIO_SIZE 0x2000 -+#define VIRT_VIRTIO_IRQ 31 -+ -+/* PCI */ -+#define VIRT_PCI_ECAM_BASE 0xe0000000 -+#define VIRT_PCI_ECAM_SIZE 0x01000000 -+#define VIRT_PCI_MMIO_BASE 0xd0000000 -+#define VIRT_PCI_MMIO_SIZE 0x10000000 -+#define VIRT_PCI_PIO_BASE 0xc0000000 -+#define VIRT_PCI_PIO_SIZE 0x00004000 -+#define PCIE_IRQ 40 /* IRQs 40-43 as GPEX_NUM_IRQS=4 */ -+ -+static void create_pcie(ARCCPU *cpu) -+{ -+ hwaddr base_ecam = VIRT_PCI_ECAM_BASE; -+ hwaddr size_ecam = VIRT_PCI_ECAM_SIZE; -+ hwaddr base_pio = VIRT_PCI_PIO_BASE; -+ hwaddr size_pio = VIRT_PCI_PIO_SIZE; -+ hwaddr base_mmio = VIRT_PCI_MMIO_BASE; -+ hwaddr size_mmio = VIRT_PCI_MMIO_SIZE; -+ -+ MemoryRegion *ecam_alias; -+ MemoryRegion *ecam_reg; -+ MemoryRegion *pio_alias; -+ MemoryRegion *pio_reg; -+ MemoryRegion *mmio_alias; -+ MemoryRegion *mmio_reg; -+ -+ DeviceState *dev; -+ int i; -+ -+ dev = qdev_new(TYPE_GPEX_HOST); -+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); -+ -+ /* Map only the first size_ecam bytes of ECAM space. */ -+ ecam_alias = g_new0(MemoryRegion, 1); -+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); -+ memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", -+ ecam_reg, 0, size_ecam); -+ memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); -+ -+ /* -+ * Map the MMIO window into system address space so as to expose -+ * the section of PCI MMIO space which starts at the same base address -+ * (ie 1:1 mapping for that part of PCI MMIO space visible through -+ * the window). -+ */ -+ mmio_alias = g_new0(MemoryRegion, 1); -+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); -+ memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", -+ mmio_reg, base_mmio, size_mmio); -+ memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); -+ -+ /* Map IO port space. */ -+ pio_alias = g_new0(MemoryRegion, 1); -+ pio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2); -+ memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio", -+ pio_reg, 0, size_pio); -+ memory_region_add_subregion(get_system_memory(), base_pio, pio_alias); -+ -+ /* Connect IRQ lines. */ -+ for (i = 0; i < GPEX_NUM_IRQS; i++) { -+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, cpu->env.irq[PCIE_IRQ + i]); -+ gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); -+ } -+} -+ -+static void virt_init(MachineState *machine) -+{ -+ static struct arc_boot_info boot_info; -+ unsigned int smp_cpus = machine->smp.cpus; -+ MemoryRegion *system_memory = get_system_memory(); -+ MemoryRegion *system_ram; -+ MemoryRegion *system_ram0; -+ MemoryRegion *system_io; -+ ARCCPU *cpu = NULL; -+ int n; -+ -+ boot_info.ram_start = VIRT_RAM_BASE; -+ boot_info.ram_size = VIRT_RAM_SIZE; -+ boot_info.kernel_filename = machine->kernel_filename; -+ boot_info.kernel_cmdline = machine->kernel_cmdline; -+ -+ for (n = 0; n < smp_cpus; n++) { -+#ifdef TARGET_ARCV2 -+ cpu = ARC_CPU(cpu_create("archs-" TYPE_ARC_CPU)); -+#else -+ cpu = ARC_CPU(cpu_create("hs6x-" TYPE_ARC_CPU)); -+#endif -+ if (cpu == NULL) { -+ fprintf(stderr, "Unable to find CPU definition!\n"); -+ exit(1); -+ } -+ -+ /* Initialize internal devices. */ -+ cpu_arc_pic_init(cpu); -+ cpu_arc_clock_init(cpu); -+ -+ qemu_register_reset(arc_cpu_reset, cpu); -+ } -+ -+ /* Init system DDR */ -+ system_ram = g_new(MemoryRegion, 1); -+ memory_region_init_ram(system_ram, NULL, "arc.ram", VIRT_RAM_SIZE, -+ &error_fatal); -+ memory_region_add_subregion(system_memory, VIRT_RAM_BASE, system_ram); -+ -+ system_ram0 = g_new(MemoryRegion, 1); -+ memory_region_init_ram(system_ram0, NULL, "arc.ram0", 0x1000000, -+ &error_fatal); -+ memory_region_add_subregion(system_memory, 0, system_ram0); -+ -+ /* Init IO area */ -+ system_io = g_new(MemoryRegion, 1); -+ memory_region_init_io(system_io, NULL, NULL, NULL, "arc.io", -+ VIRT_IO_SIZE); -+ memory_region_add_subregion(system_memory, VIRT_IO_BASE, system_io); -+ -+ serial_mm_init(system_io, VIRT_UART0_OFFSET, 2, -+ cpu->env.irq[VIRT_UART0_IRQ], 115200, serial_hd(0), -+ DEVICE_NATIVE_ENDIAN); -+ -+ for (n = 0; n < VIRT_VIRTIO_NUMBER; n++) { -+ sysbus_create_simple("virtio-mmio", -+ VIRT_VIRTIO_BASE + VIRT_VIRTIO_SIZE * n, -+ cpu->env.irq[VIRT_VIRTIO_IRQ + n]); -+ } -+ -+ create_pcie(cpu); -+ -+ arc_load_kernel(cpu, &boot_info); -+} -+ -+static void virt_machine_init(MachineClass *mc) -+{ -+ mc->desc = "ARC Virtual Machine"; -+ mc->init = virt_init; -+ mc->max_cpus = 1; -+ mc->is_default = true; -+} -+ -+DEFINE_MACHINE("virt", virt_machine_init) -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/hw/meson.build b/hw/meson.build -index 8ba79b1a52..8f1a151c68 100644 ---- a/hw/meson.build -+++ b/hw/meson.build -@@ -42,6 +42,7 @@ subdir('xen') - subdir('xenpv') - - subdir('alpha') -+subdir('arc') - subdir('arm') - subdir('avr') - subdir('cris') -diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h -index 13fa1edd41..15ec34c185 100644 ---- a/include/disas/dis-asm.h -+++ b/include/disas/dis-asm.h -@@ -206,7 +206,16 @@ enum bfd_architecture - bfd_arch_v850, /* NEC V850 */ - #define bfd_mach_v850 0 - bfd_arch_arc, /* Argonaut RISC Core */ --#define bfd_mach_arc_base 0 -+#define bfd_mach_arc_a4 0 -+#define bfd_mach_arc_a5 1 -+#define bfd_mach_arc_arc600 2 -+#define bfd_mach_arc_arc601 4 -+#define bfd_mach_arc_arc700 3 -+#define bfd_mach_arc_arcv2 5 -+#define bfd_mach_arc_arcv2em 6 -+#define bfd_mach_arc_arcv2hs 7 -+#define bfd_mach_arcv3_64 0x10 -+#define bfd_mach_arcv3_32 0x20 - bfd_arch_m32r, /* Mitsubishi M32R/D */ - #define bfd_mach_m32r 0 /* backwards compatibility */ - bfd_arch_mn10200, /* Matsushita MN10200 */ -@@ -460,6 +469,7 @@ int print_insn_riscv32 (bfd_vma, disassemble_info*); - int print_insn_riscv64 (bfd_vma, disassemble_info*); - int print_insn_rx(bfd_vma, disassemble_info *); - int print_insn_hexagon(bfd_vma, disassemble_info *); -+int print_insn_arc (bfd_vma, disassemble_info*); - - #ifdef CONFIG_CAPSTONE - bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size); -diff --git a/include/elf.h b/include/elf.h -index 78237c9a87..14643f4c17 100644 ---- a/include/elf.h -+++ b/include/elf.h -@@ -206,6 +206,12 @@ typedef struct mips_elf_abiflags_v0 { - - #define EM_AARCH64 183 - -+#define EM_TILEGX 191 /* TILE-Gx */ -+ -+#define EM_ARC_COMPACT 93 /* Synopsys ARCompact */ -+#define EM_ARC_COMPACT2 195 /* Synopsys ARCompact V2 */ -+#define EM_ARC_COMPACT3_64 253 /* Synopsys ARCompact V3 ARC64 */ -+ - #define EM_MOXIE 223 /* Moxie processor family */ - #define EM_MOXIE_OLD 0xFEED - -diff --git a/include/exec/poison.h b/include/exec/poison.h -index 4cd3f8abb4..ec04c8370b 100644 ---- a/include/exec/poison.h -+++ b/include/exec/poison.h -@@ -8,6 +8,7 @@ - #pragma GCC poison TARGET_X86_64 - #pragma GCC poison TARGET_AARCH64 - #pragma GCC poison TARGET_ALPHA -+#pragma GCC poison TARGET_ARC - #pragma GCC poison TARGET_ARM - #pragma GCC poison TARGET_CRIS - #pragma GCC poison TARGET_HEXAGON -@@ -69,6 +70,7 @@ - - #pragma GCC poison CONFIG_ALPHA_DIS - #pragma GCC poison CONFIG_ARM_A64_DIS -+#pragma GCC poison CONFIG_ARC_DIS - #pragma GCC poison CONFIG_ARM_DIS - #pragma GCC poison CONFIG_CRIS_DIS - #pragma GCC poison CONFIG_HPPA_DIS -diff --git a/include/hw/arc/cpudevs.h b/include/hw/arc/cpudevs.h -new file mode 100644 -index 0000000000..2e155b6437 ---- /dev/null -+++ b/include/hw/arc/cpudevs.h -@@ -0,0 +1,30 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef HW_ARC_CPUDEVS_H -+#define HW_ARC_CPUDEVS_H -+ -+/* Timer service routines. */ -+extern void cpu_arc_clock_init(ARCCPU *); -+ -+/* PIC service routines. */ -+extern void cpu_arc_pic_init(ARCCPU *); -+ -+#endif /* !HW_ARC_CPUDEVS_H */ -diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h -index 16da279696..ace91cd47c 100644 ---- a/include/sysemu/arch_init.h -+++ b/include/sysemu/arch_init.h -@@ -26,6 +26,7 @@ enum { - QEMU_ARCH_RISCV = (1 << 19), - QEMU_ARCH_RX = (1 << 20), - QEMU_ARCH_AVR = (1 << 21), -+ QEMU_ARCH_ARC = (1 << 22), - - QEMU_ARCH_NONE = (1 << 31), - }; -diff --git a/meson.build b/meson.build -index c6f4b0cf5e..b3e847293f 100644 ---- a/meson.build -+++ b/meson.build -@@ -57,7 +57,7 @@ python = import('python').find_installation() - - supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] - supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', -- 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] -+ 'arc', 'arc64', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] - - cpu = host_machine.cpu_family() - targetos = host_machine.system() -@@ -1190,6 +1190,8 @@ config_target_mak = {} - - disassemblers = { - 'alpha' : ['CONFIG_ALPHA_DIS'], -+ 'arc' : ['CONFIG_ARC_DIS'], -+ 'arc64' : ['CONFIG_ARC_DIS'], - 'arm' : ['CONFIG_ARM_DIS'], - 'avr' : ['CONFIG_AVR_DIS'], - 'cris' : ['CONFIG_CRIS_DIS'], -diff --git a/softmmu/arch_init.c b/softmmu/arch_init.c -index 7fd5c09b2b..27faed5edd 100644 ---- a/softmmu/arch_init.c -+++ b/softmmu/arch_init.c -@@ -92,6 +92,8 @@ int graphic_depth = 32; - #define QEMU_ARCH QEMU_ARCH_XTENSA - #elif defined(TARGET_AVR) - #define QEMU_ARCH QEMU_ARCH_AVR -+#elif defined(TARGET_ARC) -+#define QEMU_ARCH QEMU_ARCH_ARC - #endif - - const uint32_t arch_type = QEMU_ARCH; -diff --git a/target/arc/arc-common.h b/target/arc/arc-common.h -new file mode 100644 -index 0000000000..a01e3c661d ---- /dev/null -+++ b/target/arc/arc-common.h -@@ -0,0 +1,65 @@ -+/* -+ * Common header file to be used by cpu and disassembler. -+ * Copyright (C) 2017 Free Software Foundation, Inc. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with GAS or GDB; see the file COPYING3. If not, write to -+ * the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, -+ * MA 02110-1301, USA. -+ */ -+ -+#ifndef ARC_COMMON_H -+#define ARC_COMMON_H -+ -+ -+/* CPU combi. */ -+#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ -+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS \ -+ | ARC_OPCODE_V3_ARC32 | ARC_OPCODE_V3_ARC64) -+#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM) -+#define ARC_OPCODE_ARCV1 (ARC_OPCODE_ARC700 | ARC_OPCODE_ARC600) -+#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) -+#define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2) -+ -+#define ARC_OPCODE_V3_ALL (ARC_OPCODE_V3_ARC64 | ARC_OPCODE_V3_ARC32) -+ -+#define ARC_OPCODE_V2_V3 (ARC_OPCODE_V3_ALL | ARC_OPCODE_ARCV2) -+#define ARC_OPCODE_ARCv2HS_AND_V3 (ARC_OPCODE_V3_ALL | ARC_OPCODE_ARCv2HS) -+ -+enum arc_cpu_family { -+ ARC_OPCODE_NONE = 0, -+ -+ ARC_OPCODE_DEFAULT = 1 << 0, -+ ARC_OPCODE_ARC600 = 1 << 1, -+ ARC_OPCODE_ARC700 = 1 << 2, -+ ARC_OPCODE_ARCv2EM = 1 << 3, -+ ARC_OPCODE_ARCv2HS = 1 << 4, -+ ARC_OPCODE_V3_ARC32 = 1 << 5, -+ ARC_OPCODE_V3_ARC64 = 1 << 6 -+}; -+ -+typedef struct { -+ uint64_t value; -+ uint32_t type; -+} operand_t; -+ -+typedef struct { -+ uint32_t class; -+ uint64_t limm; -+ uint8_t len; -+ bool limm_p; -+#define unsigned_limm_p limm_p -+ bool signed_limm_p; -+ operand_t operands[3]; -+ uint8_t n_ops; -+ uint8_t cc; -+ uint8_t aa; -+ uint8_t zz; -+#define zz_as_data_size zz -+ bool d; -+ bool f; -+ bool di; -+ bool x; -+} insn_t; -+ -+#endif -diff --git a/target/arc/cache.c b/target/arc/cache.c -new file mode 100644 -index 0000000000..86fae84ccb ---- /dev/null -+++ b/target/arc/cache.c -@@ -0,0 +1,182 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "hw/hw.h" -+#include "cpu.h" -+#include "target/arc/regs.h" -+#include "target/arc/cache.h" -+ -+void arc_cache_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, -+ target_ulong val, void *data) -+{ -+ -+ CPUARCState *env = (CPUARCState *) data; -+ struct arc_cache *cache = &env->cache; -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_ic_ivic: -+ case AUX_ID_ic_ivil: -+ case AUX_ID_dc_ivdc: -+ case AUX_ID_dc_ivdl: -+ case AUX_ID_dc_flsh: -+ case AUX_ID_dc_fldl: -+ case AUX_ID_dc_startr: -+ /* Do nothing as we don't simulate cache memories */ -+ break; -+ -+ case AUX_ID_ic_ctrl: -+ cache->ic_disabled = val & 1; -+ break; -+ -+ case AUX_ID_ic_ivir: -+ cache->ic_ivir = val & 0xffffff00; -+ break; -+ -+ case AUX_ID_ic_endr: -+ cache->ic_endr = val & 0xffffff00; -+ break; -+ -+ case AUX_ID_ic_ptag: -+ cache->ic_ptag = val; -+ break; -+ -+ case AUX_ID_ic_ptag_hi: -+ cache->ic_ptag_hi = val & 0xff; -+ break; -+ -+/* -+ * Description of the register content in order: -+ * DC - Disable Cache: Enables/Disables the cache: 0 - Enabled, 1 - Disabled -+ * IM - Invalidate Mode: Selects the invalidate type -+ */ -+ case AUX_ID_dc_ctrl: -+ cache->dc_disabled = val & 1; /* DC */ -+ cache->dc_inv_mode = (val >> 6) & 1; /* IM */ -+ break; -+ -+ case AUX_ID_dc_endr: -+ cache->dc_endr = val & 0xffffff00; -+ break; -+ -+ case AUX_ID_dc_ptag_hi: -+ cache->dc_ptag_hi = val & 0xff; -+ break; -+ -+ default: -+ hw_error("%s@%d: Attempt to write read-only register 0x%02x!\n", -+ __func__, __LINE__, (unsigned int)aux_reg_detail->id); -+ break; -+ } -+ -+ return; -+} -+ -+target_ulong arc_cache_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, -+ void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ struct arc_cache *cache = &env->cache; -+ uint32_t reg = 0; -+ -+ switch (aux_reg_detail->id) { -+/* -+ * Description of the register content in order. -+ * Layout: -------- -DFFBBBB CCCCAAAA VVVVVVVV -+ * D - indicates that IC is disabled on reset -+ * FL - Feature level: 10b - line lock, invalidate, advanced debug features -+ * BSize - indicates the cache block size in bytes: 0011b - 64 bytes -+ * Cache capacity: 0111b - 64 Kbytes -+ * Cache Associativiy: 0010b - Four-way set associative -+ * Version number: 4 - ARCv2 -+ */ -+ case AUX_ID_i_cache_build: -+ reg = (0 << 22) | /* D */ -+ (2 << 20) | /* FL */ -+ (3 << 16) | /* BBSixe*/ -+ (7 << 12) | /* Cache capacity */ -+ (2 << 8) | /* Cache Associativiy */ -+ (4 << 0); /* Version Number */ -+ break; -+ -+ case AUX_ID_ic_ctrl: -+ reg = cache->ic_disabled & 1; -+ break; -+ -+ case AUX_ID_ic_ivir: -+ reg = cache->ic_ivir; -+ break; -+ -+ case AUX_ID_ic_endr: -+ reg = cache->ic_endr; -+ break; -+ -+ case AUX_ID_ic_ptag: -+ reg = cache->ic_ptag; -+ break; -+ -+ case AUX_ID_ic_ptag_hi: -+ reg = cache->ic_ptag_hi; -+ break; -+ -+/* -+ * Description of the register content in order: -+ * FL - Feature level: 10b - line lock, invalidate, advanced debug features -+ * BSize - indicates the cache block size in bytes: 0010b - 64 bytes -+ * Cache capacity: 0111b - 64 Kbytes -+ * Cache Associativiy: 0001b - Two-way set associative -+ * Version number: 4 - ARCv2 with fixed number of cycles -+ */ -+ case AUX_ID_d_cache_build: -+ reg = (2 << 20) | /* FL */ -+ (2 << 16) | /* BSize */ -+ (7 << 12) | /* Cache capacity */ -+ (1 << 8) | /* Cache Associativiy */ -+ (4 << 0); /* Version number */ -+ break; -+ -+/* -+ * Description of the register content in order: -+ * DC - Disable Cache: Enables/Disables the cache: 0 - Enabled, 1 - Disabled -+ * SB - Success Bit: of last cache operation: 1 - succeded (immediately) -+ * IM - Invalidate Mode: Selects the invalidate type -+ */ -+ case AUX_ID_dc_ctrl: -+ reg = (cache->dc_disabled & 1) << 0 | /* DC */ -+ (1 << 2) | /* SB */ -+ (cache->dc_inv_mode & 1) << 6; /* IM */ -+ break; -+ -+ case AUX_ID_dc_endr: -+ reg = cache->dc_endr; -+ break; -+ -+ case AUX_ID_dc_ptag_hi: -+ reg = cache->dc_ptag_hi; -+ break; -+ -+ default: -+ hw_error("%s@%d: Attempt to read write-only register 0x%02x!\n", -+ __func__, __LINE__, (unsigned int)aux_reg_detail->id); -+ break; -+ } -+ -+ return reg; -+} -diff --git a/target/arc/cache.h b/target/arc/cache.h -new file mode 100644 -index 0000000000..a1af909fa3 ---- /dev/null -+++ b/target/arc/cache.h -@@ -0,0 +1,36 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2019 Synopsys, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#ifndef __ARC_CACHE_H__ -+#define __ARC_CACHE_H__ -+ -+#include "target/arc/regs.h" -+ -+struct arc_cache { -+ bool ic_disabled; -+ bool dc_disabled; -+ bool dc_inv_mode; -+ uint32_t ic_ivir; -+ uint32_t ic_endr; -+ uint32_t ic_ptag; -+ uint32_t ic_ptag_hi; -+ uint32_t dc_endr; -+ uint32_t dc_ptag_hi; -+}; -+ -+#endif /* __ARC_CACHE_H__ */ -diff --git a/target/arc/cpu-param.h b/target/arc/cpu-param.h -new file mode 100644 -index 0000000000..9ad28fa693 ---- /dev/null -+++ b/target/arc/cpu-param.h -@@ -0,0 +1,42 @@ -+/* -+ * ARC cpu parameters for qemu. -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * Contributed by Shahab Vahedi -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#ifndef ARC_CPU_PARAM_H -+#define ARC_CPU_PARAM_H 1 -+ -+#ifdef TARGET_ARCV2 -+#define TARGET_LONG_BITS 32 -+#define TARGET_PAGE_BITS 13 -+#define TARGET_PHYS_ADDR_SPACE_BITS 32 -+#define TARGET_VIRT_ADDR_SPACE_BITS 32 -+#define NB_MMU_MODES 2 -+#endif -+ -+#ifdef TARGET_ARCV3 -+#define TARGET_LONG_BITS 64 -+#define TARGET_PAGE_BITS 12 -+#define TARGET_PHYS_ADDR_SPACE_BITS 48 -+#define TARGET_VIRT_ADDR_SPACE_BITS 64 -+#define NB_MMU_MODES 3 -+#endif -+ -+#endif -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/cpu-qom.h b/target/arc/cpu-qom.h -new file mode 100644 -index 0000000000..ee60db158d ---- /dev/null -+++ b/target/arc/cpu-qom.h -@@ -0,0 +1,52 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#ifndef QEMU_ARC_CPU_QOM_H -+#define QEMU_ARC_CPU_QOM_H -+ -+#include "hw/core/cpu.h" -+ -+#define TYPE_ARC_CPU "arc-cpu" -+ -+#define ARC_CPU_CLASS(klass) \ -+ OBJECT_CLASS_CHECK(ARCCPUClass, (klass), TYPE_ARC_CPU) -+#define ARC_CPU(obj) \ -+ OBJECT_CHECK(ARCCPU, (obj), TYPE_ARC_CPU) -+#define ARC_CPU_GET_CLASS(obj) \ -+ OBJECT_GET_CLASS(ARCCPUClass, (obj), TYPE_ARC_CPU) -+ -+/* -+ * ARCCPUClass: -+ * @parent_realize: The parent class' realize handler. -+ * @parent_reset: The parent class' reset handler. -+ * -+ * A ARC CPU model. -+ */ -+typedef struct ARCCPUClass { -+ /*< private >*/ -+ CPUClass parent_class; -+ /*< public >*/ -+ -+ DeviceRealize parent_realize; -+ DeviceReset parent_reset; -+} ARCCPUClass; -+ -+typedef struct ARCCPU ARCCPU; -+ -+#endif -diff --git a/target/arc/cpu.c b/target/arc/cpu.c -new file mode 100644 -index 0000000000..249df55613 ---- /dev/null -+++ b/target/arc/cpu.c -@@ -0,0 +1,507 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#include "qemu/osdep.h" -+#include "qapi/error.h" -+#include "cpu.h" -+#include "exec/exec-all.h" -+#include "migration/vmstate.h" -+#include "exec/log.h" -+#include "mmu.h" -+#include "mpu.h" -+#include "hw/qdev-properties.h" -+#include "irq.h" -+#include "hw/arc/cpudevs.h" -+#include "timer.h" -+#include "gdbstub.h" -+ -+static const VMStateDescription vms_arc_cpu = { -+ .name = "cpu", -+ .version_id = 0, -+ .minimum_version_id = 0, -+ .fields = (VMStateField[]) { -+ VMSTATE_END_OF_LIST() -+ } -+}; -+ -+static Property arc_cpu_properties[] = { -+ DEFINE_PROP_UINT32("address-size", ARCCPU, cfg.addr_size, 32), -+ DEFINE_PROP_BOOL("aps", ARCCPU, cfg.aps_feature, false), -+ DEFINE_PROP_BOOL("byte-order", ARCCPU, cfg.byte_order, false), -+ DEFINE_PROP_BOOL("bitscan", ARCCPU, cfg.bitscan_option, true), -+ DEFINE_PROP_UINT32("br_bc-entries", ARCCPU, cfg.br_bc_entries, -1), -+ DEFINE_PROP_UINT32("br_pt-entries", ARCCPU, cfg.br_pt_entries, -1), -+ DEFINE_PROP_BOOL("full-tag", ARCCPU, cfg.br_bc_full_tag, false), -+ DEFINE_PROP_UINT8("rs-entries", ARCCPU, cfg.br_rs_entries, -1), -+ DEFINE_PROP_UINT32("tag-size", ARCCPU, cfg.br_bc_tag_size, -1), -+ DEFINE_PROP_UINT8("tosq-entries", ARCCPU, cfg.br_tosq_entries, -1), -+ DEFINE_PROP_UINT8("fb-entries", ARCCPU, cfg.br_fb_entries, -1), -+ DEFINE_PROP_BOOL("code-density", ARCCPU, cfg.code_density, true), -+ DEFINE_PROP_BOOL("code-protect", ARCCPU, cfg.code_protect, false), -+ DEFINE_PROP_UINT8("dcc-memcyc", ARCCPU, cfg.dccm_mem_cycles, -1), -+ DEFINE_PROP_BOOL("ddcm-posedge", ARCCPU, cfg.dccm_posedge, false), -+ DEFINE_PROP_UINT8("dcc-mem-banks", ARCCPU, cfg.dccm_mem_bancks, -1), -+ DEFINE_PROP_UINT8("mem-cycles", ARCCPU, cfg.dc_mem_cycles, -1), -+ DEFINE_PROP_BOOL("dc-posedge", ARCCPU, cfg.dc_posedge, false), -+ DEFINE_PROP_BOOL("unaligned", ARCCPU, cfg.dmp_unaligned, true), -+ DEFINE_PROP_BOOL("ecc-excp", ARCCPU, cfg.ecc_exception, false), -+ DEFINE_PROP_UINT32("ext-irq", ARCCPU, cfg.external_interrupts, 128), -+ DEFINE_PROP_UINT8("ecc-option", ARCCPU, cfg.ecc_option, -1), -+ DEFINE_PROP_BOOL("firq", ARCCPU, cfg.firq_option, true), -+ DEFINE_PROP_BOOL("fpu-dp", ARCCPU, cfg.fpu_dp_option, false), -+ DEFINE_PROP_BOOL("fpu-fma", ARCCPU, cfg.fpu_fma_option, false), -+ DEFINE_PROP_BOOL("fpu-div", ARCCPU, cfg.fpu_div_option, false), -+ DEFINE_PROP_BOOL("actionpoints", ARCCPU, cfg.has_actionpoints, false), -+ DEFINE_PROP_BOOL("fpu", ARCCPU, cfg.has_fpu, false), -+ DEFINE_PROP_BOOL("has-irq", ARCCPU, cfg.has_interrupts, true), -+ DEFINE_PROP_BOOL("has-mmu", ARCCPU, cfg.has_mmu, true), -+ DEFINE_PROP_BOOL("has-mpu", ARCCPU, cfg.has_mpu, true), -+ DEFINE_PROP_BOOL("timer0", ARCCPU, cfg.has_timer_0, true), -+ DEFINE_PROP_BOOL("timer1", ARCCPU, cfg.has_timer_1, true), -+ DEFINE_PROP_BOOL("has-pct", ARCCPU, cfg.has_pct, false), -+ DEFINE_PROP_BOOL("has-rtt", ARCCPU, cfg.has_rtt, false), -+ DEFINE_PROP_BOOL("has-smart", ARCCPU, cfg.has_smart, false), -+ DEFINE_PROP_UINT32("intv-base", ARCCPU, cfg.intvbase_preset, 0x0), -+ DEFINE_PROP_UINT32("lpc-size", ARCCPU, cfg.lpc_size, 32), -+ DEFINE_PROP_UINT8("mpu-numreg", ARCCPU, cfg.mpu_num_regions, 0), -+ DEFINE_PROP_UINT8("mpy-option", ARCCPU, cfg.mpy_option, 2), -+ DEFINE_PROP_UINT32("mmu-pagesize0", ARCCPU, cfg.mmu_page_size_sel0, -1), -+ DEFINE_PROP_UINT32("mmu-pagesize1", ARCCPU, cfg.mmu_page_size_sel1, -1), -+ DEFINE_PROP_UINT32("mmu-pae", ARCCPU, cfg.mmu_pae_enabled, -1), -+ DEFINE_PROP_UINT32("ntlb-numentries", ARCCPU, cfg.ntlb_num_entries, -1), -+ DEFINE_PROP_UINT32("num-actionpoints", ARCCPU, cfg.num_actionpoints, -1), -+ DEFINE_PROP_UINT32("num-irq", ARCCPU, cfg.number_of_interrupts, 240), -+ DEFINE_PROP_UINT32("num-irqlevels", ARCCPU, cfg.number_of_levels, 15), -+ DEFINE_PROP_UINT32("pct-counters", ARCCPU, cfg.pct_counters, -1), -+ DEFINE_PROP_UINT32("pct-irq", ARCCPU, cfg.pct_interrupt, -1), -+ DEFINE_PROP_UINT32("pc-size", ARCCPU, cfg.pc_size, 32), -+ DEFINE_PROP_UINT32("num-regs", ARCCPU, cfg.rgf_num_regs, 32), -+ DEFINE_PROP_UINT32("banked-regs", ARCCPU, cfg.rgf_banked_regs, -1), -+ DEFINE_PROP_UINT32("num-banks", ARCCPU, cfg.rgf_num_banks, 0), -+ DEFINE_PROP_BOOL("rtc-opt", ARCCPU, cfg.rtc_option, false), -+ DEFINE_PROP_UINT32("rtt-featurelevel", ARCCPU, cfg.rtt_feature_level, -1), -+ DEFINE_PROP_BOOL("stack-check", ARCCPU, cfg.stack_checking, false), -+ DEFINE_PROP_BOOL("swap-option", ARCCPU, cfg.swap_option, true), -+ DEFINE_PROP_UINT32("smrt-stackentries", ARCCPU, cfg.smar_stack_entries, -1), -+ DEFINE_PROP_UINT32("smrt-impl", ARCCPU, cfg.smart_implementation, -1), -+ DEFINE_PROP_UINT32("stlb", ARCCPU, cfg.stlb_num_entries, -1), -+ DEFINE_PROP_UINT32("slc-size", ARCCPU, cfg.slc_size, -1), -+ DEFINE_PROP_UINT32("slc-linesize", ARCCPU, cfg.slc_line_size, -1), -+ DEFINE_PROP_UINT32("slc-ways", ARCCPU, cfg.slc_ways, -1), -+ DEFINE_PROP_UINT32("slc-tagbanks", ARCCPU, cfg.slc_tag_banks, -1), -+ DEFINE_PROP_UINT32("slc-tram", ARCCPU, cfg.slc_tram_delay, -1), -+ DEFINE_PROP_UINT32("slc-dbank", ARCCPU, cfg.slc_dbank_width, -1), -+ DEFINE_PROP_UINT32("slc-data", ARCCPU, cfg.slc_data_banks, -1), -+ DEFINE_PROP_UINT32("slc-delay", ARCCPU, cfg.slc_dram_delay, -1), -+ DEFINE_PROP_BOOL("slc-memwidth", ARCCPU, cfg.slc_mem_bus_width, false), -+ DEFINE_PROP_UINT32("slc-ecc", ARCCPU, cfg.slc_ecc_option, -1), -+ DEFINE_PROP_BOOL("slc-datahalf", ARCCPU, cfg.slc_data_halfcycle_steal, false), -+ DEFINE_PROP_BOOL("slc-dataadd", ARCCPU, cfg.slc_data_add_pre_pipeline, false), -+ DEFINE_PROP_BOOL("uaux", ARCCPU, cfg.uaux_option, false), -+ DEFINE_PROP_UINT32("freq_hz", ARCCPU, cfg.freq_hz, 4600000), -+ DEFINE_PROP_END_OF_LIST(), -+}; -+ -+static void arc_cpu_set_pc(CPUState *cs, vaddr value) -+{ -+ ARCCPU *cpu = ARC_CPU(cs); -+ -+ CPU_PCL(&cpu->env) = value & (~((target_ulong) 3)); -+ cpu->env.pc = value; -+} -+ -+static bool arc_cpu_has_work(CPUState *cs) -+{ -+ return cs->interrupt_request & CPU_INTERRUPT_HARD; -+} -+ -+static void arc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) -+{ -+ ARCCPU *cpu = ARC_CPU(cs); -+ CPUARCState *env = &cpu->env; -+ -+ CPU_PCL(&cpu->env) = tb->pc & (~((target_ulong) 3)); -+ env->pc = tb->pc; -+} -+ -+static void arc_cpu_reset(DeviceState *dev) -+{ -+ CPUState *s = CPU(dev); -+ ARCCPU *cpu = ARC_CPU(s); -+ ARCCPUClass *arcc = ARC_CPU_GET_CLASS(cpu); -+ CPUARCState *env = &cpu->env; -+ -+ if (qemu_loglevel_mask(CPU_LOG_RESET)) { -+ qemu_log("CPU Reset (CPU)\n"); -+ log_cpu_state(s, 0); -+ } -+ -+ /* Initialize mmu/reset it. */ -+ arc_mmu_init(env); -+ -+ arc_mpu_init(cpu); -+ -+ arc_resetTIMER(cpu); -+ arc_resetIRQ(cpu); -+ -+ arcc->parent_reset(dev); -+ -+ memset(env->r, 0, sizeof(env->r)); -+ env->lock_lf_var = 0; -+ -+ env->stat.is_delay_slot_instruction = 0; -+ /* -+ * kernel expects MPY support to check for presence of -+ * extension core regs r58/r59. -+ * -+ * VERSION32x32=0x06: ARCv2 32x32 Multiply -+ * DSP=0x1: MPY_OPTION 7 -+ */ -+ cpu->mpy_build = 0x00001006; -+} -+ -+static void arc_cpu_disas_set_info(CPUState *cs, disassemble_info *info) -+{ -+ ARCCPU *cpu = ARC_CPU(cs); -+ -+ switch (cpu->family) { -+ case ARC_OPCODE_ARC700: -+ info->mach = bfd_mach_arc_arc700; -+ break; -+ case ARC_OPCODE_ARC600: -+ info->mach = bfd_mach_arc_arc600; -+ break; -+ case ARC_OPCODE_ARCv2EM: -+ info->mach = bfd_mach_arc_arcv2em; -+ break; -+ case ARC_OPCODE_ARCv2HS: -+ info->mach = bfd_mach_arc_arcv2hs; -+ break; -+ case ARC_OPCODE_V3_ARC64: -+ info->mach = bfd_mach_arcv3_64; -+ break; -+ default: -+ info->mach = bfd_mach_arc_arcv2; -+ break; -+ } -+ -+ info->print_insn = print_insn_arc; -+ info->endian = BFD_ENDIAN_LITTLE; -+} -+ -+ -+static void arc_cpu_realizefn(DeviceState *dev, Error **errp) -+{ -+ CPUState *cs = CPU(dev); -+ ARCCPU *cpu = ARC_CPU(dev); -+ ARCCPUClass *arcc = ARC_CPU_GET_CLASS(dev); -+ Error *local_err = NULL; -+ -+ cpu_exec_realizefn(cs, &local_err); -+ if (local_err != NULL) { -+ error_propagate(errp, local_err); -+ return; -+ } -+ -+ arc_cpu_register_gdb_regs_for_features(cpu); -+ -+ qemu_init_vcpu(cs); -+ -+ /* -+ * Initialize build registers depending on the simulation -+ * parameters. -+ */ -+ cpu->freq_hz = cpu->cfg.freq_hz; -+ -+#ifdef TARGET_ARCV2 -+ cpu->isa_config = 0x02; -+ switch (cpu->cfg.pc_size) { -+ case 16: -+ break; -+ case 20: -+ cpu->isa_config |= 1 << 8; -+ break; -+ case 24: -+ cpu->isa_config |= 2 << 8; -+ break; -+ case 28: -+ cpu->isa_config |= 3 << 8; -+ break; -+ default: -+ cpu->isa_config |= 4 << 8; -+ break; -+ } -+ -+ switch (cpu->cfg.lpc_size) { -+ case 0: -+ break; -+ case 8: -+ cpu->isa_config |= 1 << 12; -+ break; -+ case 12: -+ cpu->isa_config |= 2 << 12; -+ break; -+ case 16: -+ cpu->isa_config |= 3 << 12; -+ break; -+ case 20: -+ cpu->isa_config |= 4 << 12; -+ break; -+ case 24: -+ cpu->isa_config |= 5 << 12; -+ break; -+ case 28: -+ cpu->isa_config |= 6 << 12; -+ break; -+ default: -+ cpu->isa_config |= 7 << 12; -+ break; -+ } -+ -+ switch (cpu->cfg.addr_size) { -+ case 16: -+ break; -+ case 20: -+ cpu->isa_config |= 1 << 16; -+ break; -+ case 24: -+ cpu->isa_config |= 2 << 16; -+ break; -+ case 28: -+ cpu->isa_config |= 3 << 16; -+ break; -+ default: -+ cpu->isa_config |= 4 << 16; -+ break; -+ } -+ -+ cpu->isa_config |= (cpu->cfg.byte_order ? BIT(20) : 0) | BIT(21) -+ | (cpu->cfg.dmp_unaligned ? BIT(22) : 0) | BIT(23) -+ | (cpu->cfg.code_density ? (2 << 24) : 0) | BIT(28); -+ -+#elif defined(TARGET_ARCV3) -+ cpu->isa_config = 0x03 /* ver */ -+ | (1 << 8) /* va_size: 48-bit */ -+ | (1 << 16) /* pa_size: 48-bit */ -+ | ((cpu->cfg.byte_order ? 1 : 0) << 20) /* endian */ -+ | (1 << 21) /* atomic=1: LLOCK, LLOCKL, WLFC */ -+ | ((cpu->cfg.dmp_unaligned ? 1 : 0) << 23) /* unaliged access */ -+ | (0 << 24) /* 128-bit load/store TBD */ -+ | (3 << 26) /* Code density instructions */ -+ | (0 << 28); /* 64-bit DIV/REM TBD */ -+#endif -+ -+ arc_initializeTIMER(cpu); -+ arc_initializeIRQ(cpu); -+ -+ cpu_reset(cs); -+ -+ arcc->parent_realize(dev, errp); -+} -+ -+static void arc_cpu_initfn(Object *obj) -+{ -+ ARCCPU *cpu = ARC_CPU(obj); -+ -+ /* Initialize aux-regs. */ -+ arc_aux_regs_init(); -+ -+ cpu_set_cpustate_pointers(cpu); -+} -+ -+static ObjectClass *arc_cpu_class_by_name(const char *cpu_model) -+{ -+ ObjectClass *oc; -+ char *typename; -+ char **cpuname; -+ -+ if (!cpu_model) { -+ return NULL; -+ } -+ -+ cpuname = g_strsplit(cpu_model, ",", 1); -+ typename = g_strdup_printf("%s-" TYPE_ARC_CPU, cpuname[0]); -+ oc = object_class_by_name(typename); -+ -+ g_strfreev(cpuname); -+ g_free(typename); -+ -+ if (!oc -+ || !object_class_dynamic_cast(oc, TYPE_ARC_CPU) -+ || object_class_is_abstract(oc)) { -+ return NULL; -+ } -+ -+ return oc; -+} -+ -+static gchar *arc_gdb_arch_name(CPUState *cs) -+{ -+ return g_strdup(GDB_TARGET_STRING); -+} -+ -+#include "hw/core/tcg-cpu-ops.h" -+ -+static struct TCGCPUOps arc_tcg_ops = { -+ .initialize = arc_translate_init, -+ .synchronize_from_tb = arc_cpu_synchronize_from_tb, -+ .cpu_exec_interrupt = arc_cpu_exec_interrupt, -+ .tlb_fill = arc_cpu_tlb_fill, -+ -+#ifndef CONFIG_USER_ONLY -+ .do_interrupt = arc_cpu_do_interrupt, -+#endif /* !CONFIG_USER_ONLY */ -+}; -+ -+static void arc_cpu_class_init(ObjectClass *oc, void *data) -+{ -+ DeviceClass *dc = DEVICE_CLASS(oc); -+ CPUClass *cc = CPU_CLASS(oc); -+ ARCCPUClass *arcc = ARC_CPU_CLASS(oc); -+ -+ device_class_set_parent_realize(dc, arc_cpu_realizefn, -+ &arcc->parent_realize); -+ -+ device_class_set_parent_reset(dc, arc_cpu_reset, &arcc->parent_reset); -+ -+ cc->class_by_name = arc_cpu_class_by_name; -+ -+ cc->has_work = arc_cpu_has_work; -+ cc->dump_state = arc_cpu_dump_state; -+ cc->set_pc = arc_cpu_set_pc; -+#ifndef CONFIG_USER_ONLY -+ cc->memory_rw_debug = arc_cpu_memory_rw_debug; -+ cc->get_phys_page_debug = arc_cpu_get_phys_page_debug; -+ cc->vmsd = &vms_arc_cpu; -+#endif -+ cc->disas_set_info = arc_cpu_disas_set_info; -+ cc->gdb_read_register = arc_cpu_gdb_read_register; -+ cc->gdb_write_register = arc_cpu_gdb_write_register; -+ -+ /* Core GDB support */ -+#ifdef TARGET_ARCV2 -+ cc->gdb_core_xml_file = "arc-v2-core.xml"; -+#else -+ cc->gdb_core_xml_file = "arc-core-v3.xml"; -+#endif -+ cc->gdb_num_core_regs = GDB_REG_LAST; -+ cc->gdb_arch_name = arc_gdb_arch_name; -+ -+ cc->tcg_ops = &arc_tcg_ops; -+ -+ device_class_set_props(dc, arc_cpu_properties); -+} -+ -+static void arc_any_initfn(Object *obj) -+{ -+ /* Set cpu feature flags */ -+ ARCCPU *cpu = ARC_CPU(obj); -+ cpu->family = ARC_OPCODE_ARC700; -+} -+ -+#ifdef TARGET_ARCV2 -+static void arc600_initfn(Object *obj) -+{ -+ ARCCPU *cpu = ARC_CPU(obj); -+ cpu->family = ARC_OPCODE_ARC600; -+} -+ -+static void arc700_initfn(Object *obj) -+{ -+ ARCCPU *cpu = ARC_CPU(obj); -+ cpu->family = ARC_OPCODE_ARC700; -+} -+ -+static void arcem_initfn(Object *obj) -+{ -+ ARCCPU *cpu = ARC_CPU(obj); -+ cpu->family = ARC_OPCODE_ARCv2EM; -+} -+ -+static void archs_initfn(Object *obj) -+{ -+ ARCCPU *cpu = ARC_CPU(obj); -+ cpu->family = ARC_OPCODE_ARCv2HS; -+} -+#endif -+ -+#ifdef TARGET_ARCV3 -+static void arc_hs6x_initfn(Object *obj) -+{ -+ ARCCPU *cpu = ARC_CPU(obj); -+ cpu->family = ARC_OPCODE_V3_ARC64; -+} -+#endif -+ -+typedef struct ARCCPUInfo { -+ const char *name; -+ void (*initfn)(Object *obj); -+} ARCCPUInfo; -+ -+static const ARCCPUInfo arc_cpus[] = { -+#ifdef TARGET_ARCV2 -+ { .name = "arc600", .initfn = arc600_initfn }, -+ { .name = "arc700", .initfn = arc700_initfn }, -+ { .name = "arcem", .initfn = arcem_initfn }, -+ { .name = "archs", .initfn = archs_initfn }, -+#endif -+#ifdef TARGET_ARCV3 -+ { .name = "hs6x", .initfn = arc_hs6x_initfn }, -+#endif -+ { .name = "any", .initfn = arc_any_initfn }, -+}; -+ -+static void cpu_register(const ARCCPUInfo *info) -+{ -+ TypeInfo type_info = { -+ .parent = TYPE_ARC_CPU, -+ .instance_size = sizeof(ARCCPU), -+ .instance_init = info->initfn, -+ .class_size = sizeof(ARCCPUClass), -+ }; -+ -+ type_info.name = g_strdup_printf("%s-" TYPE_ARC_CPU, info->name); -+ type_register(&type_info); -+ g_free((void *)type_info.name); -+} -+ -+static const TypeInfo arc_cpu_type_info = { -+ .name = TYPE_ARC_CPU, -+ .parent = TYPE_CPU, -+ .instance_size = sizeof(ARCCPU), -+ .instance_init = arc_cpu_initfn, -+ .class_size = sizeof(ARCCPUClass), -+ .class_init = arc_cpu_class_init, -+ .abstract = true, -+}; -+ -+static void arc_cpu_register_types(void) -+{ -+ int i; -+ type_register_static(&arc_cpu_type_info); -+ -+ for (i = 0; i < ARRAY_SIZE(arc_cpus); i++) { -+ cpu_register(&arc_cpus[i]); -+ } -+} -+ -+type_init(arc_cpu_register_types) -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/cpu.h b/target/arc/cpu.h -new file mode 100644 -index 0000000000..4fe8691d47 ---- /dev/null -+++ b/target/arc/cpu.h -@@ -0,0 +1,457 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#ifndef CPU_ARC_H -+#define CPU_ARC_H -+ -+#include "exec/cpu-defs.h" -+#include "fpu/softfloat.h" -+ -+#include "target/arc/arc-common.h" -+#include "target/arc/mmu.h" -+#include "target/arc/mmu-v6.h" -+#include "target/arc/mpu.h" -+#include "target/arc/cache.h" -+ -+#define ARC_CPU_TYPE_SUFFIX "-" TYPE_ARC_CPU -+#define ARC_CPU_TYPE_NAME(model) model ARC_CPU_TYPE_SUFFIX -+#define CPU_RESOLVING_TYPE TYPE_ARC_CPU -+ -+enum arc_features { -+ ARC_FEATURE_ARC5, -+ ARC_FEATURE_ARC600, -+ ARC_FEATURE_ARC700, -+ no_features, -+}; -+ -+enum arc_endianess { -+ ARC_ENDIANNESS_LE = 0, -+ ARC_ENDIANNESS_BE, -+}; -+ -+/* U-Boot - kernel ABI */ -+#define ARC_UBOOT_CMDLINE 1 -+#define ARC_UBOOT_DTB 2 -+ -+ -+#define CPU_GP(env) ((env)->r[26]) -+#define CPU_FP(env) ((env)->r[27]) -+#define CPU_SP(env) ((env)->r[28]) -+#define CPU_ILINK(env) ((env)->r[29]) -+#define CPU_ILINK1(env) ((env)->r[29]) -+#define CPU_ILINK2(env) ((env)->r[30]) -+#define CPU_BLINK(env) ((env)->r[31]) -+#define CPU_LP(env) ((env)->r[60]) -+#define CPU_IMM(env) ((env)->r[62]) -+#define CPU_PCL(env) ((env)->r[63]) -+ -+enum exception_code_list { -+ EXCP_NO_EXCEPTION = -1, -+ EXCP_RESET = 0, -+ EXCP_MEMORY_ERROR, -+ EXCP_INST_ERROR, -+ EXCP_MACHINE_CHECK, -+#ifdef TARGET_ARCV2 -+ EXCP_TLB_MISS_I, -+ EXCP_TLB_MISS_D, -+#elif defined(TARGET_ARCV3) -+ EXCP_IMMU_FAULT, -+ EXCP_DMMU_FAULT, -+#else -+ #error "TARGET macro not defined!" -+#endif -+ EXCP_PROTV, -+ EXCP_PRIVILEGEV, -+ EXCP_SWI, -+ EXCP_TRAP, -+ EXCP_EXTENSION, -+ EXCP_DIVZERO, -+ EXCP_DCERROR, -+ EXCP_MISALIGNED, -+ EXCP_IRQ, -+ EXCP_LPEND_REACHED = 9000, -+ EXCP_FAKE -+}; -+ -+ -+/* -+ * Status32 register bits -+ * -- Ixxx xxxx xxxU ARRR ESDL ZNCV Udae eeeH -- -+ * -+ * I = IE - Interrupt Enable -+ * x = - Reserved -+ * U = US - User sleep mode enable -+ * A = AD - Disable alignment checking -+ * R = RB - Select a register bank -+ * E = ES - EI_S table instruction pending -+ * S = SC - Enable stack checking -+ * D = DZ - RV_DivZero exception enable -+ * L = - Zero-overhead loop disable -+ * Z = - Zero status flag -+ * N = - Negative status flag -+ * C = - Cary status flag -+ * V = - Overflow status flag -+ * U = - User mode -+ * d = DE - Delayed branch is pending -+ * a = AE - Processor is in an exception -+ * e = E - Interrupt priority operating level`I -+ * H = - Halt flag -+ */ -+ -+/* Flags in pstate */ -+#define Hf_b (0) -+#define AEf_b (5) -+#define Uf_b (7) -+#define Lf_b (12) -+#define DZf_b (13) -+#define SCf_b (14) -+#define ESf_b (15) -+#define ADf_b (19) -+#define USf_b (20) -+ -+/* Flags with their on fields */ -+#define IEf_b (31) -+#define IEf_bS (1) -+ -+#define Ef_b (1) -+#define Ef_bS (4) -+ -+#define DEf_b (6) -+#define DEf_bS (1) -+ -+#define Vf_b (8) -+#define Vf_bS (1) -+#define Cf_b (9) -+#define Cf_bS (1) -+#define Nf_b (10) -+#define Nf_bS (1) -+#define Zf_b (11) -+#define Zf_bS (1) -+ -+#define RBf_b (16) -+#define RBf_bS (3) -+ -+ -+#define PSTATE_MASK \ -+ ((1 << Hf_b) \ -+ | (1 << AEf_b) \ -+ | (1 << Uf_b) \ -+ | (1 << Lf_b) \ -+ | (1 << DZf_b) \ -+ | (1 << SCf_b) \ -+ | (1 << ESf_b) \ -+ | (1 << ADf_b) \ -+ | (1 << USf_b)) -+ -+#define GET_STATUS_BIT(STAT, BIT) ((STAT.pstate >> BIT##_b) & 0x1) -+#define SET_STATUS_BIT(STAT, BIT, VALUE) { \ -+ STAT.pstate &= ~(1 << BIT##_b); \ -+ STAT.pstate |= (VALUE << BIT##_b); \ -+} -+ -+typedef struct { -+ target_ulong pstate; -+ -+ target_ulong RBf; -+ target_ulong Ef; /* irq priority treshold. */ -+ target_ulong Vf; /* overflow */ -+ target_ulong Cf; /* carry */ -+ target_ulong Nf; /* negative */ -+ target_ulong Zf; /* zero */ -+ target_ulong DEf; -+ target_ulong IEf; -+ -+ /* Reserved bits */ -+ -+ /* Next instruction is a delayslot instruction */ -+ bool is_delay_slot_instruction; -+} ARCStatus; -+ -+/* ARC processor timer module. */ -+typedef struct { -+ target_ulong T_Cntrl; -+ target_ulong T_Limit; -+ uint64_t last_clk; -+} ARCTimer; -+ -+/* ARC PIC interrupt bancked regs. */ -+typedef struct { -+ target_ulong priority; -+ target_ulong trigger; -+ target_ulong pulse_cancel; -+ target_ulong enable; -+ target_ulong pending; -+ target_ulong status; -+} ARCIrq; -+ -+typedef struct CPUARCState { -+ target_ulong r[64]; -+ -+ ARCStatus stat, stat_l1, stat_er; -+ -+ struct { -+ target_ulong S2; -+ target_ulong S1; -+ target_ulong CS; -+ } macmod; -+ -+ target_ulong intvec; -+ -+ target_ulong eret; -+ target_ulong erbta; -+ target_ulong ecr; -+ target_ulong efa; -+ target_ulong bta; -+ target_ulong bta_l1; -+ target_ulong bta_l2; -+ -+ target_ulong pc; /* program counter */ -+ target_ulong lps; /* loops start */ -+ target_ulong lpe; /* loops end */ -+ -+ target_ulong npc; /* required for LP - zero overhead loops. */ -+ -+ target_ulong lock_lf_var; -+ -+#define TMR_IE (1 << 0) -+#define TMR_NH (1 << 1) -+#define TMR_W (1 << 2) -+#define TMR_IP (1 << 3) -+#define TMR_PD (1 << 4) -+ ARCTimer timer[2]; /* ARC CPU-Timer 0/1 */ -+ -+ ARCIrq irq_bank[256]; /* IRQ register bank */ -+ uint32_t irq_select; /* AUX register */ -+ uint32_t aux_irq_act; /* AUX register */ -+ uint32_t irq_priority_pending; /* AUX register */ -+ uint32_t icause[16]; /* Banked cause register */ -+ uint32_t aux_irq_hint; /* AUX register, used to trigger soft irq */ -+ uint32_t aux_user_sp; -+ uint32_t aux_irq_ctrl; -+ uint32_t aux_rtc_ctrl; -+ uint32_t aux_rtc_low; -+ uint32_t aux_rtc_high; -+ -+ /* Fields required by exception handling. */ -+ uint32_t causecode; -+ uint32_t param; -+ -+#ifdef TARGET_ARCV2 -+ struct arc_mmu mmu; /* mmu.h */ -+#elif defined(TARGET_ARCV3) -+ struct arc_mmuv6 mmu; /* mmu.h */ -+#endif -+ ARCMPU mpu; /* mpu.h */ -+ struct arc_cache cache; /* cache.h */ -+ -+ /* used for propagatinng "hostpc/return address" to sub-functions */ -+ uintptr_t host_pc; -+ -+ bool stopped; -+ -+ /* Fields up to this point are cleared by a CPU reset */ -+ struct {} end_reset_fields; -+ -+ uint64_t last_clk_rtc; -+ -+ void *irq[256]; -+ QEMUTimer *cpu_timer[2]; /* Internal timer. */ -+ QEMUTimer *cpu_rtc; /* Internal RTC. */ -+ -+ const struct arc_boot_info *boot_info; -+ -+ bool enabled_interrupts; -+} CPUARCState; -+ -+/* -+ * ArcCPU: -+ * @env: #CPUMBState -+ * -+ * An ARC CPU. -+ */ -+struct ARCCPU { -+ /*< private >*/ -+ CPUState parent_obj; -+ -+ /*< public >*/ -+ -+ /* ARC Configuration Settings. */ -+ struct { -+ uint32_t addr_size; -+ uint32_t br_bc_entries; -+ uint32_t br_pt_entries; -+ uint32_t br_bc_tag_size; -+ uint32_t external_interrupts; -+ uint32_t intvbase_preset; -+ uint32_t lpc_size; -+ uint32_t mmu_page_size_sel0; -+ uint32_t mmu_page_size_sel1; -+ uint32_t mmu_pae_enabled; -+ uint32_t ntlb_num_entries; -+ uint32_t num_actionpoints; -+ uint32_t number_of_interrupts; -+ uint32_t number_of_levels; -+ uint32_t pct_counters; -+ uint32_t pct_interrupt; -+ uint32_t pc_size; -+ uint32_t rgf_num_regs; -+ uint32_t rgf_banked_regs; -+ uint32_t rgf_num_banks; -+ uint32_t rtt_feature_level; -+ uint32_t smar_stack_entries; -+ uint32_t smart_implementation; -+ uint32_t stlb_num_entries; -+ uint32_t slc_size; -+ uint32_t slc_line_size; -+ uint32_t slc_ways; -+ uint32_t slc_tag_banks; -+ uint32_t slc_tram_delay; -+ uint32_t slc_dbank_width; -+ uint32_t slc_data_banks; -+ uint32_t slc_dram_delay; -+ uint32_t slc_ecc_option; -+ uint32_t freq_hz; /* CPU frequency in hz, needed for timers. */ -+ uint8_t br_rs_entries; -+ uint8_t br_tosq_entries; -+ uint8_t br_fb_entries; -+ uint8_t dccm_mem_cycles; -+ uint8_t dccm_mem_bancks; -+ uint8_t dc_mem_cycles; -+ uint8_t ecc_option; -+ uint8_t mpu_num_regions; -+ uint8_t mpy_option; -+ bool aps_feature; -+ bool byte_order; -+ bool bitscan_option; -+ bool br_bc_full_tag; -+ bool code_density; -+ bool code_protect; -+ bool dccm_posedge; -+ bool dc_posedge; -+ bool dmp_unaligned; -+ bool ecc_exception; -+ bool firq_option; -+ bool fpu_dp_option; -+ bool fpu_fma_option; -+ bool fpu_div_option; -+ bool has_actionpoints; -+ bool has_fpu; -+ bool has_interrupts; -+ bool has_mmu; -+ bool has_mpu; -+ bool has_timer_0; -+ bool has_timer_1; -+ bool has_pct; -+ bool has_rtt; -+ bool has_smart; -+ bool rtc_option; -+ bool stack_checking; -+ bool swap_option; -+ bool slc_mem_bus_width; -+ bool slc_data_halfcycle_steal; -+ bool slc_data_add_pre_pipeline; -+ bool uaux_option; -+ } cfg; -+ -+ uint32_t family; -+ -+ /* Build AUX regs. */ -+#define TIMER0_IRQ 16 -+#define TIMER1_IRQ 17 -+#define TB_T0 (1 << 8) -+#define TB_T1 (1 << 9) -+#define TB_RTC (1 << 10) -+#define TB_P0_MSK (0x0f0000) -+#define TB_P1_MSK (0xf00000) -+ uint32_t freq_hz; /* CPU frequency in hz, needed for timers. */ -+ -+ uint32_t timer_build; /* Timer configuration AUX register. */ -+ uint32_t irq_build; /* Interrupt Build Configuration Register. */ -+ uint32_t vecbase_build; /* Interrupt Vector Base Address Configuration. */ -+ uint32_t mpy_build; /* Multiply configuration register. */ -+ uint32_t isa_config; /* Instruction Set Configuration Register. */ -+ -+ CPUNegativeOffsetState neg; -+ CPUARCState env; -+}; -+ -+/* are we in user mode? */ -+static inline bool is_user_mode(const CPUARCState *env) -+{ -+ return GET_STATUS_BIT(env->stat, Uf) != 0; -+} -+ -+#define cpu_list arc_cpu_list -+#define cpu_signal_handler cpu_arc_signal_handler -+#define cpu_init(cpu_model) cpu_generic_init(TYPE_ARC_CPU, cpu_model) -+ -+typedef CPUARCState CPUArchState; -+typedef ARCCPU ArchCPU; -+ -+#include "exec/cpu-all.h" -+ -+static inline int cpu_mmu_index(const CPUARCState *env, bool ifetch) -+{ -+ return GET_STATUS_BIT(env->stat, Uf) != 0 ? 1 : 0; -+} -+ -+static inline void cpu_get_tb_cpu_state(CPUARCState *env, target_ulong *pc, -+ target_ulong *cs_base, -+ uint32_t *pflags) -+{ -+ *pc = env->pc; -+ *cs_base = 0; -+#ifdef CONFIG_USER_ONLY -+ assert(0); /* Not really supported at the moment. */ -+#else -+ *pflags = cpu_mmu_index(env, 0); -+#endif -+} -+ -+void arc_translate_init(void); -+ -+void arc_cpu_list(void); -+int cpu_arc_exec(CPUState *cpu); -+int cpu_arc_signal_handler(int host_signum, void *pinfo, void *puc); -+int arc_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, -+ int len, bool is_write); -+void arc_cpu_do_interrupt(CPUState *cpu); -+ -+void arc_cpu_dump_state(CPUState *cs, FILE *f, int flags); -+hwaddr arc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -+int arc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); -+int arc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -+ -+void QEMU_NORETURN arc_raise_exception(CPUARCState *env, int32_t excp_idx); -+ -+void not_implemented_mmu_init(struct arc_mmu *mmu); -+bool not_implemented_cpu_tlb_fill(CPUState *cs, vaddr address, int size, -+ MMUAccessType access_type, int mmu_idx, -+ bool probe, uintptr_t retaddr); -+ -+void arc_mmu_init(CPUARCState *env); -+bool arc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, -+ MMUAccessType access_type, int mmu_idx, -+ bool probe, uintptr_t retaddr); -+hwaddr arc_mmu_debug_translate(CPUARCState *env, vaddr addr); -+void arc_mmu_disable(CPUARCState *env); -+ -+#include "exec/cpu-all.h" -+ -+#endif /* !defined (CPU_ARC_H) */ -diff --git a/target/arc/decoder-v3.c b/target/arc/decoder-v3.c -new file mode 100644 -index 0000000000..ae058c706d ---- /dev/null -+++ b/target/arc/decoder-v3.c -@@ -0,0 +1,1547 @@ -+/* -+ * Decoder for the ARC. -+ * Copyright (C) 2017 Free Software Foundation, Inc. -+ -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public License -+ * as published by the Free Software Foundation; either version 2.1 of -+ * the License, or (at your option) any later version. -+ -+ * This library is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License -+ * along with GAS or GDB; see the file COPYING3. If not, write to -+ * the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, -+ * MA 02110-1301, USA. -+ */ -+ -+#include "qemu/osdep.h" -+#include "target/arc/decoder.h" -+#include "qemu/osdep.h" -+#include "qemu/bswap.h" -+#include "cpu.h" -+ -+/* Register names. */ -+static const char * const regnames[64] = { -+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", -+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", -+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", -+ "r24", "r25", -+ "gp", -+ "fp", "sp", "ilink", "r30", "blink", -+ -+ "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", -+ "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", -+ "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", -+ "r56", "r57", "r58", "r59", "lp_count", "rezerved", "LIMM", "pcl" -+}; -+const char *get_register_name(int value) -+{ -+ return regnames[value]; -+} -+ -+extern bool special_flag_p(const char *opname, const char *flgname); -+ -+static long long int -+extract_rb (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); -+ -+ if (value == 0x3e && invalid) -+ *invalid = TRUE; /* A limm operand, it should be extracted in a -+ different way. */ -+ -+ return value; -+} -+ -+static long long int -+extract_rhv1 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); -+ -+ return value; -+} -+ -+static long long int -+extract_rhv2 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); -+ -+ return value; -+} -+ -+static long long int -+extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 0; -+} -+ -+static long long int -+extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 1; -+} -+ -+static long long int -+extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 2; -+} -+ -+static long long int -+extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 3; -+} -+ -+static long long int -+extract_sp (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 28; -+} -+ -+static long long int -+extract_gp (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 26; -+} -+ -+static long long int -+extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 63; -+} -+ -+static long long int -+extract_blink (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 31; -+} -+ -+static long long int -+extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 29; -+} -+ -+static long long int -+extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return 30; -+} -+ -+static long long int -+extract_ras (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = insn & 0x07; -+ if (value > 3) -+ return (value + 8); -+ else -+ return value; -+} -+ -+static long long int -+extract_rbs (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = (insn >> 8) & 0x07; -+ if (value > 3) -+ return (value + 8); -+ else -+ return value; -+} -+ -+static long long int -+extract_rcs (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = (insn >> 5) & 0x07; -+ if (value > 3) -+ return (value + 8); -+ else -+ return value; -+} -+ -+static long long int -+extract_simm3s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = (insn >> 8) & 0x07; -+ if (value == 7) -+ return -1; -+ else -+ return value; -+} -+ -+static long long int -+extract_rrange (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return (insn >> 1) & 0x0F; -+} -+ -+static long long int -+extract_fpel (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return (insn & 0x0100) ? 27 : -1; -+} -+ -+static long long int -+extract_blinkel (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return (insn & 0x0200) ? 31 : -1; -+} -+ -+static long long int -+extract_pclel (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ return (insn & 0x0400) ? 63 : -1; -+} -+ -+#define EXTRACT_W6 -+/* mask = 00000000000000000000111111000000. */ -+static long long int -+extract_w6 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ signed value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ -+ int signbit = 1 << 5; -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+#define EXTRACT_G_S -+/* mask = 0000011100022000. */ -+static long long int -+extract_g_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 8) & 0x0007) << 0; -+ value |= ((insn >> 3) & 0x0003) << 3; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (6 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+static long long int -+extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ value |= ((insn >> 0) & 0x003f) << 6; -+ -+ return value; -+} -+ -+#ifndef EXTRACT_LIMM -+#define EXTRACT_LIMM -+/* mask = 00000000000000000000000000000000. */ -+static ATTRIBUTE_UNUSED int -+extract_limm (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ return value; -+} -+#endif /* EXTRACT_LIMM */ -+ -+#ifndef EXTRACT_UIMM6_20 -+#define EXTRACT_UIMM6_20 -+/* mask = 00000000000000000000111111000000. */ -+static long long int -+extract_uimm6_20 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM6_20 */ -+ -+#ifndef EXTRACT_SIMM12_20 -+#define EXTRACT_SIMM12_20 -+/* mask = 00000000000000000000111111222222. */ -+static long long int -+extract_simm12_20 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ value |= ((insn >> 0) & 0x003f) << 6; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (12 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM12_20 */ -+ -+#ifndef EXTRACT_SIMM3_5_S -+#define EXTRACT_SIMM3_5_S -+/* mask = 0000011100000000. */ -+static ATTRIBUTE_UNUSED int -+extract_simm3_5_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 8) & 0x0007) << 0; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (3 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM3_5_S */ -+ -+#ifndef EXTRACT_LIMM_S -+#define EXTRACT_LIMM_S -+/* mask = 0000000000000000. */ -+static ATTRIBUTE_UNUSED int -+extract_limm_s (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ return value; -+} -+#endif /* EXTRACT_LIMM_S */ -+ -+#ifndef EXTRACT_UIMM7_A32_11_S -+#define EXTRACT_UIMM7_A32_11_S -+/* mask = 0000000000011111. */ -+static long long int -+extract_uimm7_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x001f) << 2; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM7_A32_11_S */ -+ -+#ifndef EXTRACT_UIMM7_9_S -+#define EXTRACT_UIMM7_9_S -+/* mask = 0000000001111111. */ -+static long long int -+extract_uimm7_9_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x007f) << 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM7_9_S */ -+ -+#ifndef EXTRACT_UIMM3_13_S -+#define EXTRACT_UIMM3_13_S -+/* mask = 0000000000000111. */ -+static long long int -+extract_uimm3_13_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x0007) << 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM3_13_S */ -+ -+#ifndef EXTRACT_SIMM11_A32_7_S -+#define EXTRACT_SIMM11_A32_7_S -+/* mask = 0000000111111111. */ -+static long long int -+extract_simm11_a32_7_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x01ff) << 2; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (11 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM11_A32_7_S */ -+ -+#ifndef EXTRACT_UIMM6_13_S -+#define EXTRACT_UIMM6_13_S -+/* mask = 0000000002220111. */ -+static long long int -+extract_uimm6_13_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x0007) << 0; -+ value |= ((insn >> 4) & 0x0007) << 3; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM6_13_S */ -+ -+#ifndef EXTRACT_UIMM5_11_S -+#define EXTRACT_UIMM5_11_S -+/* mask = 0000000000011111. */ -+static long long int -+extract_uimm5_11_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x001f) << 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM5_11_S */ -+ -+#ifndef EXTRACT_SIMM9_A16_8 -+#define EXTRACT_SIMM9_A16_8 -+/* mask = 00000000111111102000000000000000. */ -+static long long int -+extract_simm9_a16_8 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 17) & 0x007f) << 1; -+ value |= ((insn >> 15) & 0x0001) << 8; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (9 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM9_A16_8 */ -+ -+#ifndef EXTRACT_UIMM6_8 -+#define EXTRACT_UIMM6_8 -+/* mask = 00000000000000000000111111000000. */ -+static long long int -+extract_uimm6_8 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM6_8 */ -+ -+#ifndef EXTRACT_SIMM21_A16_5 -+#define EXTRACT_SIMM21_A16_5 -+/* mask = 00000111111111102222222222000000. */ -+static long long int -+extract_simm21_a16_5 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 17) & 0x03ff) << 1; -+ value |= ((insn >> 6) & 0x03ff) << 11; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (21 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM21_A16_5 */ -+ -+#ifndef EXTRACT_SIMM25_A16_5 -+#define EXTRACT_SIMM25_A16_5 -+/* mask = 00000111111111102222222222003333. */ -+static long long int -+extract_simm25_a16_5 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 17) & 0x03ff) << 1; -+ value |= ((insn >> 6) & 0x03ff) << 11; -+ value |= ((insn >> 0) & 0x000f) << 21; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (25 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM25_A16_5 */ -+ -+#ifndef EXTRACT_SIMM10_A16_7_S -+#define EXTRACT_SIMM10_A16_7_S -+/* mask = 0000000111111111. */ -+static long long int -+extract_simm10_a16_7_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x01ff) << 1; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (10 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM10_A16_7_S */ -+ -+#ifndef EXTRACT_SIMM7_A16_10_S -+#define EXTRACT_SIMM7_A16_10_S -+/* mask = 0000000000111111. */ -+static long long int -+extract_simm7_a16_10_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x003f) << 1; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (7 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM7_A16_10_S */ -+ -+#ifndef EXTRACT_SIMM21_A32_5 -+#define EXTRACT_SIMM21_A32_5 -+/* mask = 00000111111111002222222222000000. */ -+static long long int -+extract_simm21_a32_5 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 18) & 0x01ff) << 2; -+ value |= ((insn >> 6) & 0x03ff) << 11; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (21 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM21_A32_5 */ -+ -+#ifndef EXTRACT_SIMM25_A32_5 -+#define EXTRACT_SIMM25_A32_5 -+/* mask = 00000111111111002222222222003333. */ -+static long long int -+extract_simm25_a32_5 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 18) & 0x01ff) << 2; -+ value |= ((insn >> 6) & 0x03ff) << 11; -+ value |= ((insn >> 0) & 0x000f) << 21; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (25 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM25_A32_5 */ -+ -+#ifndef EXTRACT_SIMM13_A32_5_S -+#define EXTRACT_SIMM13_A32_5_S -+/* mask = 0000011111111111. */ -+static long long int -+extract_simm13_a32_5_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x07ff) << 2; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (13 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM13_A32_5_S */ -+ -+#ifndef EXTRACT_SIMM8_A16_9_S -+#define EXTRACT_SIMM8_A16_9_S -+/* mask = 0000000001111111. */ -+static long long int -+extract_simm8_a16_9_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x007f) << 1; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (8 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM8_A16_9_S */ -+ -+#ifndef EXTRACT_UIMM3_23 -+#define EXTRACT_UIMM3_23 -+/* mask = 00000000000000000000000111000000. */ -+static long long int -+extract_uimm3_23 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x0007) << 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM3_23 */ -+ -+#ifndef EXTRACT_UIMM10_6_S -+#define EXTRACT_UIMM10_6_S -+/* mask = 0000001111111111. */ -+static long long int -+extract_uimm10_6_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x03ff) << 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM10_6_S */ -+ -+#ifndef EXTRACT_UIMM6_11_S -+#define EXTRACT_UIMM6_11_S -+/* mask = 0000002200011110. */ -+static long long int -+extract_uimm6_11_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 1) & 0x000f) << 0; -+ value |= ((insn >> 8) & 0x0003) << 4; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM6_11_S */ -+ -+#ifndef EXTRACT_SIMM9_8 -+#define EXTRACT_SIMM9_8 -+/* mask = 00000000111111112000000000000000. */ -+static long long int -+extract_simm9_8 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 16) & 0x00ff) << 0; -+ value |= ((insn >> 15) & 0x0001) << 8; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (9 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM9_8 */ -+ -+#ifndef EXTRACT_UIMM10_A32_8_S -+#define EXTRACT_UIMM10_A32_8_S -+/* mask = 0000000011111111. */ -+static long long int -+extract_uimm10_a32_8_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x00ff) << 2; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM10_A32_8_S */ -+ -+#ifndef EXTRACT_SIMM9_7_S -+#define EXTRACT_SIMM9_7_S -+/* mask = 0000000111111111. */ -+static long long int -+extract_simm9_7_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x01ff) << 0; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (9 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM9_7_S */ -+ -+#ifndef EXTRACT_UIMM6_A16_11_S -+#define EXTRACT_UIMM6_A16_11_S -+/* mask = 0000000000011111. */ -+static long long int -+extract_uimm6_a16_11_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x001f) << 1; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM6_A16_11_S */ -+ -+ -+#ifndef EXTRACT_UIMM5_A32_11_S -+#define EXTRACT_UIMM5_A32_11_S -+/* mask = 0000020000011000. */ -+static long long int -+extract_uimm5_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 3) & 0x0003) << 2; -+ value |= ((insn >> 10) & 0x0001) << 4; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM5_A32_11_S */ -+ -+#ifndef EXTRACT_SIMM11_A32_13_S -+#define EXTRACT_SIMM11_A32_13_S -+/* mask = 0000022222200111. */ -+static long long int -+extract_simm11_a32_13_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x0007) << 2; -+ value |= ((insn >> 5) & 0x003f) << 5; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (11 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM11_A32_13_S */ -+ -+#ifndef EXTRACT_UIMM7_13_S -+#define EXTRACT_UIMM7_13_S -+/* mask = 0000000022220111. */ -+static long long int -+extract_uimm7_13_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x0007) << 0; -+ value |= ((insn >> 4) & 0x000f) << 3; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM7_13_S */ -+ -+#ifndef EXTRACT_UIMM6_A16_21 -+#define EXTRACT_UIMM6_A16_21 -+/* mask = 00000000000000000000011111000000. */ -+static long long int -+extract_uimm6_a16_21 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x001f) << 1; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM6_A16_21 */ -+ -+#ifndef EXTRACT_UIMM7_11_S -+#define EXTRACT_UIMM7_11_S -+/* mask = 0000022200011110. */ -+static long long int -+extract_uimm7_11_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 1) & 0x000f) << 0; -+ value |= ((insn >> 8) & 0x0007) << 4; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM7_11_S */ -+ -+#ifndef EXTRACT_UIMM7_A16_20 -+#define EXTRACT_UIMM7_A16_20 -+/* mask = 00000000000000000000111111000000. */ -+static long long int -+extract_uimm7_a16_20 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 1; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM7_A16_20 */ -+ -+#ifndef EXTRACT_SIMM13_A16_20 -+#define EXTRACT_SIMM13_A16_20 -+/* mask = 00000000000000000000111111222222. */ -+static long long int -+extract_simm13_a16_20 (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 1; -+ value |= ((insn >> 0) & 0x003f) << 7; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (13 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+#endif /* EXTRACT_SIMM13_A16_20 */ -+ -+ -+#ifndef EXTRACT_UIMM8_8_S -+#define EXTRACT_UIMM8_8_S -+/* mask = 0000000011111111. */ -+static long long int -+extract_uimm8_8_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x00ff) << 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM8_8_S */ -+ -+#ifndef EXTRACT_UIMM6_5_S -+#define EXTRACT_UIMM6_5_S -+/* mask = 0000011111100000. */ -+static long long int -+extract_uimm6_5_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 5) & 0x003f) << 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM6_5_S */ -+ -+#ifndef EXTRACT_UIMM6_AXX_ -+#define EXTRACT_UIMM6_AXX_ -+/* mask = 00000000000000000000000000000000. */ -+static ATTRIBUTE_UNUSED int -+extract_uimm6_axx_ (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean * invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM6_AXX_ */ -+ -+/* mask = 0000022000011111. */ -+#ifndef EXTRACT_UIMM9_A32_11_S -+#define EXTRACT_UIMM9_A32_11_S -+ATTRIBUTE_UNUSED static long long int -+extract_uimm9_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ value |= ((insn >> 0) & 0x001f) << 2; -+ value |= ((insn >> 9) & 0x0003) << 7; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM9_A32_11_S */ -+ -+/* mask = 0000022222220111. */ -+#ifndef EXTRACT_UIMM10_13_S -+#define EXTRACT_UIMM10_13_S -+ATTRIBUTE_UNUSED static long long int -+extract_uimm10_13_s (unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ value |= ((insn >> 0) & 0x0007) << 0; -+ value |= ((insn >> 4) & 0x007f) << 3; -+ -+ return value; -+} -+#endif /* EXTRACT_UIMM10_13_S */ -+ -+static long long -+extract_rbb (unsigned long long insn, -+ bfd_boolean * invalid) -+{ -+ int value = (((insn >> 1) & 0x07) << 3) | ((insn >> 8) & 0x07); -+ -+ if (value == 0x3e && invalid) -+ *invalid = TRUE; /* A limm operand, it should be extracted in a -+ different way. */ -+ -+ return value; -+} -+ -+/* -+ * The operands table. -+ * -+ * The format of the operands table is: -+ * -+ * BITS SHIFT FLAGS EXTRACT_FUN. -+ */ -+const struct arc_operand arc_operands[] = { -+ { 0, 0, 0, 0 }, -+#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN) \ -+ { BITS, SHIFT, FLAGS, FUN }, -+#include "target/arc/operands-v3.def" -+#undef ARC_OPERAND -+ { 0, 0, 0, 0} -+}; -+ -+enum arc_operands_map { -+ OPERAND_UNUSED = 0, -+#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN) OPERAND_##NAME, -+#include "target/arc/operands-v3.def" -+#undef ARC_OPERAND -+ OPERAND_LAST -+}; -+ -+/* -+ * The flag operands table. -+ * -+ * The format of the table is -+ * NAME CODE BITS SHIFT FAVAIL. -+ */ -+const struct arc_flag_operand arc_flag_operands[] = { -+ { 0, 0, 0, 0, 0}, -+#define ARC_FLAG(NAME, MNEMONIC, CODE, BITS, SHIFT, AVAIL) \ -+ { MNEMONIC, CODE, BITS, SHIFT, AVAIL }, -+#include "target/arc/flags-v3.def" -+#undef ARC_FLAG -+ { 0, 0, 0, 0, 0} -+}; -+ -+enum arc_flags_map { -+ F_NULL = 0, -+#define ARC_FLAG(NAME, MNEMONIC, CODE, BITS, SHIFT, AVAIL) F_##NAME, -+#include "target/arc/flags-v3.def" -+#undef ARC_FLAG -+ F_LAST -+}; -+ -+/* -+ * Table of the flag classes. -+ * -+ * The format of the table is -+ * CLASS {FLAG_CODE}. -+ */ -+const struct arc_flag_class arc_flag_classes[] = -+{ -+#define C_EMPTY 0 -+ { F_CLASS_NONE, { F_NULL } }, -+ -+#define C_CC_EQ (C_EMPTY + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} }, -+ -+#define C_CC_GE (C_CC_EQ + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} }, -+ -+#define C_CC_GT (C_CC_GE + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} }, -+ -+#define C_CC_HI (C_CC_GT + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} }, -+ -+#define C_CC_HS (C_CC_HI + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} }, -+ -+#define C_CC_LE (C_CC_HS + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} }, -+ -+#define C_CC_LO (C_CC_LE + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} }, -+ -+#define C_CC_LS (C_CC_LO + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} }, -+ -+#define C_CC_LT (C_CC_LS + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} }, -+ -+#define C_CC_NE (C_CC_LT + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} }, -+ -+#define C_AA_AB (C_CC_NE + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} }, -+ -+#define C_AA_AW (C_AA_AB + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} }, -+ -+#define C_ZZ_D (C_AA_AW + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} }, -+ -+#define C_ZZ_L (C_ZZ_D + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEL, F_NULL} }, -+ -+#define C_ZZ_W (C_ZZ_L + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEW, F_NULL} }, -+ -+#define C_ZZ_H (C_ZZ_W + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} }, -+ -+#define C_ZZ_B (C_ZZ_H + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} }, -+ -+#define C_CC (C_ZZ_B + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, -+ { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, -+ F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, -+ F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, -+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, -+ F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, -+ F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } }, -+ -+#define C_AA_ADDR3 (C_CC + 1) -+#define C_AA27 (C_CC + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, -+#define C_AA_ADDR9 (C_AA_ADDR3 + 1) -+#define C_AA21 (C_AA_ADDR3 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, -+#define C_AA_ADDR22 (C_AA_ADDR9 + 1) -+#define C_AA8 (C_AA_ADDR9 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, -+ -+#define C_F (C_AA_ADDR22 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_F, { F_FLAG, F_NULL } }, -+#define C_FHARD (C_F + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_F, { F_FFAKE, F_NULL } }, -+#define C_AQ (C_FHARD + 1) -+ { F_CLASS_OPTIONAL, { F_AQ, F_NULL } }, -+ -+#define C_ATOP (C_AQ + 1) -+ { F_CLASS_REQUIRED, {F_ATO_ADD, F_ATO_OR, F_ATO_AND, F_ATO_XOR, F_ATO_MINU, -+ F_ATO_MAXU, F_ATO_MIN, F_ATO_MAX, F_NULL}}, -+ -+#define C_T (C_ATOP + 1) -+ { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } }, -+#define C_D (C_T + 1) -+ { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } }, -+#define C_DNZ_D (C_D + 1) -+ { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } }, -+ -+#define C_DHARD (C_DNZ_D + 1) -+ { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } }, -+ -+#define C_DI20 (C_DHARD + 1) -+ { F_CLASS_OPTIONAL, { F_DI11, F_NULL }}, -+#define C_DI14 (C_DI20 + 1) -+ { F_CLASS_OPTIONAL, { F_DI14, F_NULL }}, -+#define C_DI16 (C_DI14 + 1) -+ { F_CLASS_OPTIONAL, { F_DI15, F_NULL }}, -+#define C_DI26 (C_DI16 + 1) -+ { F_CLASS_OPTIONAL, { F_DI5, F_NULL }}, -+ -+#define C_X25 (C_DI26 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_X, { F_SIGN6, F_NULL }}, -+#define C_X15 (C_X25 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_X, { F_SIGN16, F_NULL }}, -+#define C_XHARD (C_X15 + 1) -+#define C_X (C_X15 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_X, { F_SIGNX, F_NULL }}, -+ -+#define C_ZZ13 (C_X + 1) -+ { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_D17 , F_NULL}}, -+#define C_ZZ23 (C_ZZ13 + 1) -+ { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_D7, F_NULL}}, -+#define C_ZZ29 (C_ZZ23 + 1) -+ { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}}, -+ -+#define C_AS (C_ZZ29 + 1) -+#define C_AAHARD13 (C_ZZ29 + 1) -+ { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}}, -+ -+#define C_NE (C_AS + 1) -+ { F_CLASS_REQUIRED, { F_NE, F_NULL}} -+}; -+ -+/* List with special cases instructions and the applicable flags. */ -+const struct arc_flag_special arc_flag_special_cases[] = -+{ -+ { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, -+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, -+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, -+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, -+ F_NO_T, F_NULL } }, -+ { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, -+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, -+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, -+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, -+ { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, -+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, -+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, -+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, -+ { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, -+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, -+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, -+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, -+ { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, -+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, -+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, -+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, -+ { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, -+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, -+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, -+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, -+ { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, -+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, -+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, -+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, -+ { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, -+ { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } -+}; -+ -+const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases); -+ -+/* -+ * The opcode table. -+ * -+ * The format of the opcode table is: -+ * -+ * NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. -+ * -+ * The table is organised such that, where possible, all instructions with -+ * the same mnemonic are together in a block. When the assembler searches -+ * for a suitable instruction the entries are checked in table order, so -+ * more specific, or specialised cases should appear earlier in the table. -+ * -+ * As an example, consider two instructions 'add a,b,u6' and 'add -+ * a,b,limm'. The first takes a 6-bit immediate that is encoded within the -+ * 32-bit instruction, while the second takes a 32-bit immediate that is -+ * encoded in a follow-on 32-bit, making the total instruction length -+ * 64-bits. In this case the u6 variant must appear first in the table, as -+ * all u6 immediates could also be encoded using the 'limm' extension, -+ * however, we want to use the shorter instruction wherever possible. -+ * -+ * It is possible though to split instructions with the same mnemonic into -+ * multiple groups. However, the instructions are still checked in table -+ * order, even across groups. The only time that instructions with the -+ * same mnemonic should be split into different groups is when different -+ * variants of the instruction appear in different architectures, in which -+ * case, grouping all instructions from a particular architecture together -+ * might be preferable to merging the instruction into the main instruction -+ * table. -+ * -+ * An example of this split instruction groups can be found with the 'sync' -+ * instruction. The core arc architecture provides a 'sync' instruction, -+ * while the nps instruction set extension provides 'sync.rd' and -+ * 'sync.wr'. The rd/wr flags are instruction flags, not part of the -+ * mnemonic, so we end up with two groups for the sync instruction, the -+ * first within the core arc instruction table, and the second within the -+ * nps extension instructions. -+ */ -+const struct arc_opcode arc_opcodes[] = -+{ -+#define FASTMATH NONE -+#include "opcodes-v3.def" -+ { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } -+#undef FASTMATH -+}; -+ -+/* Return length of an opcode in bytes. */ -+static uint8_t arc_opcode_len(const struct arc_opcode *opcode) -+{ -+ if (opcode->mask < 0x10000ull) { -+ return 2; -+ } -+ -+ if (opcode->mask < 0x100000000ull) { -+ return 4; -+ } -+ -+ if (opcode->mask < 0x1000000000000ull) { -+ return 6; -+ } -+ -+ return 8; -+} -+ -+/* -+ * Calculate the instruction length for an instruction starting with -+ * MSB and LSB, the most and least significant byte. The ISA_MASK is -+ * used to filter the instructions considered to only those that are -+ * part of the current architecture. -+ * -+ * The instruction lengths are calculated from the ARC_OPCODE table, -+ * and cached for later use. -+ */ -+unsigned int arc_insn_length(uint16_t insn, uint16_t cpu_type) -+{ -+ uint8_t major_opcode; -+ uint8_t msb; -+ -+ msb = (uint8_t)(insn >> 8); -+ major_opcode = msb >> 3; -+ -+ switch (cpu_type) { -+ case ARC_OPCODE_V3_ARC64: -+ if(major_opcode == 0x0b) -+ return 4; -+ return (major_opcode > 0x7) ? 2 : 4; -+ break; -+ -+ default: -+ g_assert_not_reached(); -+ } -+} -+ -+static enum dis_insn_type -+arc_opcode_to_insn_type (const struct arc_opcode *opcode) -+{ -+ enum dis_insn_type insn_type; -+ -+ switch (opcode->insn_class) -+ { -+ case BRANCH: -+ case BBIT0: -+ case BBIT1: -+ case BI: -+ case BIH: -+ case BRCC: -+ case EI: -+ case JLI: -+ case JUMP: -+ case LOOP: -+ if (!strncmp (opcode->name, "bl", 2) -+ || !strncmp (opcode->name, "jl", 2)) -+ { -+ if (opcode->subclass == COND) -+ insn_type = dis_condjsr; -+ else -+ insn_type = dis_jsr; -+ } -+ else -+ { -+ if (opcode->subclass == COND) -+ insn_type = dis_condbranch; -+ else -+ insn_type = dis_branch; -+ } -+ break; -+ case LOAD: -+ case STORE: -+ case MEMORY: -+ case ENTER: -+ case PUSH: -+ case POP: -+ insn_type = dis_dref; -+ break; -+ case LEAVE: -+ insn_type = dis_branch; -+ break; -+ default: -+ insn_type = dis_nonbranch; -+ break; -+ } -+ -+ return insn_type; -+} -+ -+#define REG_PCL 63 -+#define REG_LIMM 62 -+#define REG_LIMM_S 30 -+#define REG_U32 62 -+#define REG_S32 60 -+ -+static const struct arc_opcode *find_format(insn_t *pinsn, -+ uint64_t insn, -+ uint8_t insn_len, -+ uint32_t isa_mask) -+{ -+ uint32_t i = 0; -+ const struct arc_opcode *opcode = NULL; -+ const uint8_t *opidx; -+ const uint8_t *flgidx; -+ bool has_limm_signed = false; -+ bool has_limm_unsigned = false; -+ -+ const struct arc_opcode *ret = NULL; -+ -+ do { -+ bool invalid = false; -+ uint32_t noperands = 0; -+ -+ opcode = &arc_opcodes[i++]; -+ -+ if (!(opcode->cpu & isa_mask)) { -+ continue; -+ } -+ -+ if (arc_opcode_len(opcode) != (int) insn_len) { -+ continue; -+ } -+ -+ if ((insn & opcode->mask) != opcode->opcode) { -+ continue; -+ } -+ -+ if(ret != NULL) -+ continue; -+ -+ memset(pinsn, 0, sizeof (*pinsn)); -+ -+ has_limm_signed = false; -+ has_limm_unsigned = false; -+ -+ /* Possible candidate, check the operands. */ -+ for (opidx = opcode->operands; *opidx; ++opidx) { -+ int value, slimmind; -+ const struct arc_operand *operand = &arc_operands[*opidx]; -+ -+ if (operand->flags & ARC_OPERAND_FAKE) { -+ continue; -+ } -+ -+ if (operand->extract) { -+ value = (*operand->extract)(insn, &invalid); -+ } -+ else { -+ value = (insn >> operand->shift) & ((1 << operand->bits) - 1); -+ } -+ -+ /* Check for (short) LIMM indicator. If it is there, then -+ make sure we pick the right format. */ -+ slimmind = (isa_mask & (ARC_OPCODE_ARCV2 | ARC_OPCODE_V3_ARC64)) ? -+ REG_LIMM_S : REG_LIMM; -+ if (operand->flags & ARC_OPERAND_IR -+ && !(operand->flags & ARC_OPERAND_LIMM)) -+ if ((value == REG_LIMM && insn_len == 4) -+ || (value == slimmind && insn_len == 2) -+ || (isa_mask & ARC_OPCODE_V3_ARC64 -+ && (value == REG_S32) && (insn_len == 4))) -+ { -+ invalid = TRUE; -+ break; -+ } -+ -+ -+ -+ if (operand->flags & ARC_OPERAND_LIMM && -+ !(operand->flags & ARC_OPERAND_DUPLICATE)) { -+ if(operand->flags & ARC_OPERAND_SIGNED) -+ has_limm_signed = true; -+ else -+ has_limm_unsigned = true; -+ } -+ -+ pinsn->operands[noperands].value = value; -+ pinsn->operands[noperands].type = operand->flags; -+ noperands += 1; -+ pinsn->n_ops = noperands; -+ } -+ -+ /* Preselect the insn class. */ -+ enum dis_insn_type insn_type = arc_opcode_to_insn_type (opcode); -+ -+ /* Check the flags. */ -+ for (flgidx = opcode->flags; *flgidx; ++flgidx) { -+ /* Get a valid flag class. */ -+ const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; -+ const unsigned *flgopridx; -+ bool foundA = false, foundB = false; -+ unsigned int value; -+ -+ /* FIXME! Add check for EXTENSION flags. */ -+ -+ for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) { -+ const struct arc_flag_operand *flg_operand = -+ &arc_flag_operands[*flgopridx]; -+ -+ /* Check for the implicit flags. */ -+ if (cl_flags->flag_class & F_CLASS_IMPLICIT) { -+ if (cl_flags->flag_class & F_CLASS_COND) { -+ pinsn->cc = flg_operand->code; -+ } -+ else if (cl_flags->flag_class & F_CLASS_WB) { -+ pinsn->aa = flg_operand->code; -+ } -+ else if (cl_flags->flag_class & F_CLASS_ZZ) { -+ pinsn->zz_as_data_size = flg_operand->code; -+ } -+ continue; -+ } -+ -+ value = (insn >> flg_operand->shift) & -+ ((1 << flg_operand->bits) - 1); -+ if (value == flg_operand->code) { -+ if (!special_flag_p (opcode->name, flg_operand->name)) -+ { } -+ else if (insn_type == dis_dref) -+ { -+ switch (flg_operand->name[0]) { -+ case 'b': -+ pinsn->zz_as_data_size = 1; -+ break; -+ case 'h': -+ case 'w': -+ pinsn->zz_as_data_size = 2; -+ break; -+ default: -+ pinsn->zz_as_data_size = 0; -+ break; -+ } -+ } -+ -+ /* -+ * TODO: This has a problem: instruction "b label" -+ * sets this to true. -+ */ -+ if (cl_flags->flag_class & F_CLASS_D) { -+ pinsn->d = value ? true : false; -+ if (cl_flags->flags[0] == F_DFAKE) { -+ pinsn->d = true; -+ } -+ } -+ if (flg_operand->name[0] == 'd' -+ && flg_operand->name[1] == 0) -+ pinsn->d = true; -+ -+ if (cl_flags->flag_class & F_CLASS_COND) { -+ pinsn->cc = value; -+ } -+ -+ if (cl_flags->flag_class & F_CLASS_WB) { -+ pinsn->aa = value; -+ } -+ -+ if (cl_flags->flag_class & F_CLASS_F) { -+ pinsn->f = true; -+ } -+ -+ if (cl_flags->flag_class & F_CLASS_DI) { -+ pinsn->di = true; -+ } -+ -+ if (cl_flags->flag_class & F_CLASS_X) { -+ pinsn->x = true; -+ } -+ -+ foundA = true; -+ } -+ if (value) { -+ foundB = true; -+ } -+ } -+ -+ if (!foundA && foundB) { -+ invalid = TRUE; -+ break; -+ } -+ } -+ -+ if (invalid) { -+ continue; -+ } -+ -+ /* The instruction is valid. */ -+ pinsn->signed_limm_p = has_limm_signed; -+ pinsn->unsigned_limm_p = has_limm_unsigned; -+ pinsn->class = (uint32_t) opcode->insn_class; -+ -+ /* -+ * FIXME: here add extra info about the instruction -+ * e.g. delay slot, data size, write back, etc. -+ */ -+ if(ret == NULL) -+ ret = opcode; -+ -+ } while (opcode->mask); -+ -+ if(ret != NULL) -+ return ret; -+ -+ memset(pinsn, 0, sizeof (*pinsn)); -+ return NULL; -+} -+ -+/* Helper to be used by the disassembler. */ -+const struct arc_opcode *arc_find_format(insn_t *insnd, -+ uint64_t insn, -+ uint8_t insn_len, -+ uint32_t isa_mask) -+{ -+ memset(insnd, 0, sizeof (*insnd)); -+ return find_format(insnd, insn, insn_len, isa_mask); -+} -+ -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/decoder-v3.h b/target/arc/decoder-v3.h -new file mode 100644 -index 0000000000..7131218f35 ---- /dev/null -+++ b/target/arc/decoder-v3.h -@@ -0,0 +1,322 @@ -+/* Decoder for the ARC. -+ Copyright (C) 2017 Free Software Foundation, Inc. -+ -+ You should have received a copy of the GNU General Public License -+ along with GAS or GDB; see the file COPYING3. If not, write to -+ the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+#ifndef ARC_DECODER_V3_H -+#define ARC_DECODER_V3_H -+ -+#include "arc-common.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#ifndef MAX_INSN_ARGS -+#define MAX_INSN_ARGS 16 -+#endif -+ -+#ifndef MAX_INSN_FLGS -+#define MAX_INSN_FLGS 4 -+#endif -+ -+/* Instruction Class. */ -+typedef enum { -+ NADA = 0, -+ ARC_ACL, -+ ARITH, -+ AUXREG, -+ BBIT0, -+ BBIT1, -+ BI, -+ BIH, -+ BITOP, -+ BITSTREAM, -+ BMU, -+ BRANCH, -+ BRCC, -+ CONTROL, -+ DIVREM, -+ DPI, -+ DSP, -+ EI, -+ ENTER, -+ ARC_FLOAT, -+ INVALID, -+ JLI, -+ JUMP, -+ KERNEL, -+ LEAVE, -+ LOAD, -+ LOGICAL, -+ LOOP, -+ MEMORY, -+ MOVE, -+ MPY, -+ NET, -+ PROTOCOL_DECODE, -+ PMU, -+ POP, -+ PUSH, -+ SJLI, -+ STORE, -+ SUB, -+ XY -+} insn_class_t; -+ -+/* Instruction Subclass. */ -+typedef enum { -+ NONE = 0, -+ CVT = (1U << 1), -+ BTSCN = (1U << 2), -+ CD = (1U << 3), -+ CD1 = CD, -+ CD2 = CD, -+ COND = (1U << 4), -+ DIV = (1U << 5), -+ DP = (1U << 6), -+ DPA = (1U << 7), -+ DPX = (1U << 8), -+ MPY1E = (1U << 9), -+ MPY6E = (1U << 10), -+ MPY7E = (1U << 11), -+ MPY8E = (1U << 12), -+ MPY9E = (1U << 13), -+ QUARKSE1 = (1U << 15), -+ QUARKSE2 = (1U << 16), -+ SHFT1 = (1U << 17), -+ SHFT2 = (1U << 18), -+ SWAP = (1U << 19), -+ SP = (1U << 20), -+ SPX = (1U << 21) -+} insn_subclass_t; -+ -+/* Flags class. */ -+typedef enum { -+ F_CLASS_NONE = 0, -+ -+ /* -+ * At most one flag from the set of flags can appear in the -+ * instruction. -+ */ -+ F_CLASS_OPTIONAL = (1 << 0), -+ -+ /* Exactly one from from the set of flags must appear in the -+ instruction. */ -+ F_CLASS_REQUIRED = (1 << 1), -+ -+ /* The conditional code can be extended over the standard variants -+ via .extCondCode pseudo-op. */ -+ F_CLASS_EXTEND = (1 << 2), -+ -+ /* Condition code flag. */ -+ F_CLASS_COND = (1 << 3), -+ -+ /* Write back mode. */ -+ F_CLASS_WB = (1 << 4), -+ -+ /* Data size. */ -+ F_CLASS_ZZ = (1 << 5), -+ -+ /* Implicit flag. */ -+ F_CLASS_IMPLICIT = (1 << 6), -+ -+ F_CLASS_F = (1 << 7), -+ -+ F_CLASS_DI = (1 << 8), -+ -+ F_CLASS_X = (1 << 9), -+ F_CLASS_D = (1 << 10), -+ -+} flag_class_t; -+ -+/* The opcode table is an array of struct arc_opcode. */ -+struct arc_opcode { -+ /* The opcode name. */ -+ const char *name; -+ -+ /* The opcode itself. Those bits which will be filled in with -+ operands are zeroes. */ -+ unsigned long long opcode; -+ -+ /* The opcode mask. This is used by the disassembler. This is a -+ mask containing ones indicating those bits which must match the -+ opcode field, and zeroes indicating those bits which need not -+ match (and are presumably filled in by operands). */ -+ unsigned long long mask; -+ -+ /* One bit flags for the opcode. These are primarily used to -+ indicate specific processors and environments support the -+ instructions. The defined values are listed below. */ -+ unsigned cpu; -+ -+ /* The instruction class. This is used by gdb. */ -+ insn_class_t insn_class; -+ -+ /* The instruction subclass. */ -+ insn_subclass_t subclass; -+ -+ /* An array of operand codes. Each code is an index into the -+ operand table. They appear in the order which the operands must -+ appear in assembly code, and are terminated by a zero. */ -+ unsigned char operands[MAX_INSN_ARGS + 1]; -+ -+ /* An array of flag codes. Each code is an index into the flag -+ table. They appear in the order which the flags must appear in -+ assembly code, and are terminated by a zero. */ -+ unsigned char flags[MAX_INSN_FLGS + 1]; -+}; -+ -+/* The operands table is an array of struct arc_operand. */ -+struct arc_operand { -+ /* The number of bits in the operand. */ -+ unsigned int bits; -+ -+ /* How far the operand is left shifted in the instruction. */ -+ unsigned int shift; -+ -+ /* One bit syntax flags. */ -+ unsigned int flags; -+ -+ /* Extraction function. This is used by the disassembler. To -+ extract this operand type from an instruction, check this field. -+ -+ If it is NULL, compute -+ op = ((i) >> o->shift) & ((1 << o->bits) - 1); -+ if ((o->flags & ARC_OPERAND_SIGNED) != 0 -+ && (op & (1 << (o->bits - 1))) != 0) -+ op -= 1 << o->bits; -+ (i is the instruction, o is a pointer to this structure, and op -+ is the result; this assumes twos complement arithmetic). -+ -+ If this field is not NULL, then simply call it with the -+ instruction value. It will return the value of the operand. If -+ the INVALID argument is not NULL, *INVALID will be set to -+ TRUE if this operand type can not actually be extracted from -+ this operand (i.e., the instruction does not match). If the -+ operand is valid, *INVALID will not be changed. */ -+ long long int (*extract) (unsigned long long instruction, -+ bool *invalid); -+}; -+ -+extern const struct arc_operand arc_operands[]; -+ -+/* Values defined for the flags field of a struct arc_operand. */ -+ -+/* -+ * This operand does not actually exist in the assembler input. This -+ * is used to support extended mnemonics, for which two operands fields -+ * are identical. The assembler should call the insert function with -+ * any op value. The disassembler should call the extract function, -+ * ignore the return value, and check the value placed in the invalid -+ * argument. -+ */ -+#define ARC_OPERAND_FAKE 0x0001 -+ -+/* This operand names an integer register. */ -+#define ARC_OPERAND_IR 0x0002 -+ -+/* This operand takes signed values. */ -+#define ARC_OPERAND_SIGNED 0x0004 -+ -+/* This operand takes unsigned values. This exists primarily so that -+ a flags value of 0 can be treated as end-of-arguments. */ -+#define ARC_OPERAND_UNSIGNED 0x0008 -+ -+/* This operand takes long immediate values. */ -+#define ARC_OPERAND_LIMM 0x0010 -+ -+/* This operand is identical like the previous one. */ -+#define ARC_OPERAND_DUPLICATE 0x0020 -+ -+/* This operand is PC relative. Used for internal relocs. */ -+#define ARC_OPERAND_PCREL 0x0040 -+ -+/* This operand is truncated. The truncation is done accordingly to -+ operand alignment attribute. */ -+#define ARC_OPERAND_TRUNCATE 0x0080 -+ -+/* This operand is 16bit aligned. */ -+#define ARC_OPERAND_ALIGNED16 0x0100 -+ -+/* This operand is 32bit aligned. */ -+#define ARC_OPERAND_ALIGNED32 0x0200 -+ -+/* This operand can be ignored by matching process if it is not -+ present. */ -+#define ARC_OPERAND_IGNORE 0x0400 -+ -+/* Don't check the range when matching. */ -+#define ARC_OPERAND_NCHK 0x0800 -+ -+/* Mark the braket possition. */ -+#define ARC_OPERAND_BRAKET 0x1000 -+ -+/* Mask for selecting the type for typecheck purposes. */ -+#define ARC_OPERAND_TYPECHECK_MASK \ -+ (ARC_OPERAND_IR \ -+ | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \ -+ | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET) -+ -+/* Macro to determine if an operand is a fake operand. */ -+#define ARC_OPERAND_IS_FAKE(op) \ -+ ((operand->flags & ARC_OPERAND_FAKE) \ -+ && !(operand->flags & ARC_OPERAND_BRAKET)) -+ -+/* The flags structure. */ -+struct arc_flag_operand -+{ -+ /* The flag name. */ -+ const char *name; -+ -+ /* The flag code. */ -+ unsigned code; -+ -+ /* The number of bits in the operand. */ -+ unsigned int bits; -+ -+ /* How far the operand is left shifted in the instruction. */ -+ unsigned int shift; -+ -+ /* Available for disassembler. */ -+ unsigned char favail; -+}; -+ -+extern const struct arc_flag_operand arc_flag_operands[]; -+ -+/* The flag's class structure. */ -+struct arc_flag_class -+{ -+ /* Flag class. */ -+ flag_class_t flag_class; -+ -+ /* List of valid flags (codes). */ -+ unsigned flags[256]; -+}; -+ -+extern const struct arc_flag_class arc_flag_classes[]; -+ -+/* Structure for special cases. */ -+struct arc_flag_special -+{ -+ /* Name of special case instruction. */ -+ const char *name; -+ -+ /* List of flags applicable for special case instruction. */ -+ unsigned flags[32]; -+}; -+ -+extern const struct arc_flag_special arc_flag_special_cases[]; -+extern const unsigned arc_num_flag_special; -+ -+const struct arc_opcode *arc_find_format (insn_t*, uint64_t, uint8_t, uint32_t); -+unsigned int arc_insn_length (uint16_t, uint16_t); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* ARC_DECODER_V3_H */ -diff --git a/target/arc/decoder.c b/target/arc/decoder.c -new file mode 100644 -index 0000000000..5f1baabaef ---- /dev/null -+++ b/target/arc/decoder.c -@@ -0,0 +1,1297 @@ -+/* -+ * QEMU Decoder for the ARC. -+ * Copyright (C) 2020 Free Software Foundation, Inc. -+ -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public License -+ * as published by the Free Software Foundation; either version 2.1 of -+ * the License, or (at your option) any later version. -+ -+ * This library is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License -+ * along with GAS or GDB; see the file COPYING3. If not, write to -+ * the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, -+ * MA 02110-1301, USA. -+ */ -+ -+#include "qemu/osdep.h" -+#include "target/arc/decoder.h" -+#include "qemu/osdep.h" -+#include "qemu/bswap.h" -+#include "cpu.h" -+ -+/* Register names. */ -+static const char * const regnames[64] = { -+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", -+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", -+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", -+ "r24", "r25", -+ "r26", -+ "fp", "sp", "ilink", "r30", "blink", -+ -+ "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", -+ "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", -+ "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", -+ "r56", "r57", "r58", "r59", "lp_count", "rezerved", "LIMM", "pcl" -+}; -+ -+const char *get_register_name(int value) -+{ -+ return regnames[value]; -+} -+ -+/* Extract functions. */ -+static ATTRIBUTE_UNUSED int -+extract_limm(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ return value; -+} -+ -+/* mask = 00000000000000000000111111000000. */ -+static long long int -+extract_uimm6_20(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ -+ return value; -+} -+ -+/* mask = 00000000000000000000111111222222. */ -+static long long int -+extract_simm12_20(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ value |= ((insn >> 0) & 0x003f) << 6; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (12 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000011100000000. */ -+static ATTRIBUTE_UNUSED int -+extract_simm3_5_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 8) & 0x0007) << 0; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (3 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+static ATTRIBUTE_UNUSED int -+extract_limm_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ return value; -+} -+ -+/* mask = 0000000000011111. */ -+static long long int -+extract_uimm7_a32_11_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x001f) << 2; -+ -+ return value; -+} -+ -+/* mask = 0000000001111111. */ -+static long long int -+extract_uimm7_9_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x007f) << 0; -+ -+ return value; -+} -+ -+/* mask = 0000000000000111. */ -+static long long int -+extract_uimm3_13_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x0007) << 0; -+ -+ return value; -+} -+ -+/* mask = 0000000111111111. */ -+static long long int -+extract_simm11_a32_7_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x01ff) << 2; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (11 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000000002220111. */ -+static long long int -+extract_uimm6_13_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x0007) << 0; -+ value |= ((insn >> 4) & 0x0007) << 3; -+ -+ return value; -+} -+ -+/* mask = 0000000000011111. */ -+static long long int -+extract_uimm5_11_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x001f) << 0; -+ -+ return value; -+} -+ -+/* mask = 00000000111111102000000000000000. */ -+static long long int -+extract_simm9_a16_8(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 17) & 0x007f) << 1; -+ value |= ((insn >> 15) & 0x0001) << 8; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (9 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 00000000000000000000111111000000. */ -+static long long int -+extract_uimm6_8(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ -+ return value; -+} -+ -+/* mask = 00000111111111102222222222000000. */ -+static long long int -+extract_simm21_a16_5(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 17) & 0x03ff) << 1; -+ value |= ((insn >> 6) & 0x03ff) << 11; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (21 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 00000111111111102222222222003333. */ -+static long long int -+extract_simm25_a16_5(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 17) & 0x03ff) << 1; -+ value |= ((insn >> 6) & 0x03ff) << 11; -+ value |= ((insn >> 0) & 0x000f) << 21; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (25 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000000111111111. */ -+static long long int -+extract_simm10_a16_7_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x01ff) << 1; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (10 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000000000111111. */ -+static long long int -+extract_simm7_a16_10_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x003f) << 1; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (7 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 00000111111111002222222222000000. */ -+static long long int -+extract_simm21_a32_5(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 18) & 0x01ff) << 2; -+ value |= ((insn >> 6) & 0x03ff) << 11; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (21 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 00000111111111002222222222003333. */ -+static long long int -+extract_simm25_a32_5(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 18) & 0x01ff) << 2; -+ value |= ((insn >> 6) & 0x03ff) << 11; -+ value |= ((insn >> 0) & 0x000f) << 21; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (25 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000011111111111. */ -+static long long int -+extract_simm13_a32_5_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x07ff) << 2; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (13 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000000001111111. */ -+static long long int -+extract_simm8_a16_9_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x007f) << 1; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (8 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 00000000000000000000000111000000. */ -+static long long int -+extract_uimm3_23(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x0007) << 0; -+ -+ return value; -+} -+ -+/* mask = 0000001111111111. */ -+static long long int -+extract_uimm10_6_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x03ff) << 0; -+ -+ return value; -+} -+ -+/* mask = 0000002200011110. */ -+static long long int -+extract_uimm6_11_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 1) & 0x000f) << 0; -+ value |= ((insn >> 8) & 0x0003) << 4; -+ -+ return value; -+} -+ -+/* mask = 00000000111111112000000000000000. */ -+static long long int -+extract_simm9_8(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 16) & 0x00ff) << 0; -+ value |= ((insn >> 15) & 0x0001) << 8; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (9 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000000011111111. */ -+static long long int -+extract_uimm10_a32_8_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x00ff) << 2; -+ -+ return value; -+} -+ -+/* mask = 0000000111111111. */ -+static long long int -+extract_simm9_7_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x01ff) << 0; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (9 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000000000011111. */ -+static long long int -+extract_uimm6_a16_11_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x001f) << 1; -+ -+ return value; -+} -+ -+/* mask = 0000020000011000. */ -+static long long int -+extract_uimm5_a32_11_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 3) & 0x0003) << 2; -+ value |= ((insn >> 10) & 0x0001) << 4; -+ -+ return value; -+} -+ -+/* mask = 0000022222200111. */ -+static long long int -+extract_simm11_a32_13_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 0) & 0x0007) << 2; -+ value |= ((insn >> 5) & 0x003f) << 5; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (11 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000000022220111. */ -+static long long int -+extract_uimm7_13_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x0007) << 0; -+ value |= ((insn >> 4) & 0x000f) << 3; -+ -+ return value; -+} -+ -+/* mask = 00000000000000000000011111000000. */ -+static long long int -+extract_uimm6_a16_21(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x001f) << 1; -+ -+ return value; -+} -+ -+/* mask = 0000022200011110. */ -+static long long int -+extract_uimm7_11_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 1) & 0x000f) << 0; -+ value |= ((insn >> 8) & 0x0007) << 4; -+ -+ return value; -+} -+ -+/* mask = 00000000000000000000111111000000. */ -+static long long int -+extract_uimm7_a16_20(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 1; -+ -+ return value; -+} -+ -+/* mask = 00000000000000000000111111222222. */ -+static long long int -+extract_simm13_a16_20(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 1; -+ value |= ((insn >> 0) & 0x003f) << 7; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (13 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+/* mask = 0000000011111111. */ -+static long long int -+extract_uimm8_8_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 0) & 0x00ff) << 0; -+ -+ return value; -+} -+ -+/* mask = 0000011111100000. */ -+static long long int -+extract_uimm6_5_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ value |= ((insn >> 5) & 0x003f) << 0; -+ -+ return value; -+} -+ -+/* mask = 00000000000000000000000000000000. */ -+static ATTRIBUTE_UNUSED int -+extract_uimm6_axx_(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ unsigned value = 0; -+ -+ return value; -+} -+ -+static long long int extract_rb(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); -+ -+ if (value == 0x3e && invalid) { -+ *invalid = TRUE; -+ } -+ -+ return value; -+} -+ -+static long long int extract_rhv1(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); -+ -+ return value; -+} -+ -+static long long int extract_rhv2(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); -+ -+ return value; -+} -+ -+static long long int extract_r0(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 0; -+} -+ -+static long long int extract_r1(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 1; -+} -+ -+static long long int extract_r2(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 2; -+} -+ -+static long long int extract_r3(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 3; -+} -+ -+static long long int extract_sp(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 28; -+} -+ -+static long long int extract_gp(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 26; -+} -+ -+static long long int extract_pcl(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 63; -+} -+ -+static long long int extract_blink(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 31; -+} -+ -+static long long int extract_ilink1(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 29; -+} -+ -+static long long int extract_ilink2(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return 30; -+} -+ -+static long long int extract_ras(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = insn & 0x07; -+ if (value > 3) { -+ return value + 8; -+ } else { -+ return value; -+ } -+} -+ -+static long long int extract_rbs(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = (insn >> 8) & 0x07; -+ if (value > 3) { -+ return value + 8; -+ } else { -+ return value; -+ } -+} -+ -+static long long int extract_rcs(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = (insn >> 5) & 0x07; -+ if (value > 3) { -+ return value + 8; -+ } else { -+ return value; -+ } -+} -+ -+static long long int extract_simm3s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = (insn >> 8) & 0x07; -+ if (value == 7) { -+ return -1; -+ } else { -+ return value; -+ } -+} -+ -+static long long int extract_rrange(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return (insn >> 1) & 0x0F; -+} -+ -+static long long int extract_fpel(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return (insn & 0x0100) ? 27 : -1; -+} -+ -+static long long int extract_blinkel(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return (insn & 0x0200) ? 31 : -1; -+} -+ -+static long long int extract_pclel(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ return (insn & 0x0400) ? 63 : -1; -+} -+ -+static long long int extract_w6(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ signed value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ -+ int signbit = 1 << 5; -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+static long long int extract_g_s(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 8) & 0x0007) << 0; -+ value |= ((insn >> 3) & 0x0003) << 3; -+ -+ /* Extend the sign. */ -+ int signbit = 1 << (6 - 1); -+ value = (value ^ signbit) - signbit; -+ -+ return value; -+} -+ -+static long long int extract_uimm12_20(unsigned long long insn ATTRIBUTE_UNUSED, -+ bfd_boolean *invalid ATTRIBUTE_UNUSED) -+{ -+ int value = 0; -+ -+ value |= ((insn >> 6) & 0x003f) << 0; -+ value |= ((insn >> 0) & 0x003f) << 6; -+ -+ return value; -+} -+ -+/* -+ * The operands table. -+ * -+ * The format of the operands table is: -+ * -+ * BITS SHIFT FLAGS EXTRACT_FUN. -+ */ -+const struct arc_operand arc_operands[] = { -+ { 0, 0, 0, 0 }, -+#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN) \ -+ { BITS, SHIFT, FLAGS, FUN }, -+#include "target/arc/operands.def" -+#undef ARC_OPERAND -+ { 0, 0, 0, 0} -+}; -+ -+enum arc_operands_map { -+ OPERAND_UNUSED = 0, -+#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN) OPERAND_##NAME, -+#include "target/arc/operands.def" -+#undef ARC_OPERAND -+ OPERAND_LAST -+}; -+ -+/* -+ * The flag operands table. -+ * -+ * The format of the table is -+ * NAME CODE BITS SHIFT FAVAIL. -+ */ -+const struct arc_flag_operand arc_flag_operands[] = { -+ { 0, 0, 0, 0, 0}, -+#define ARC_FLAG(NAME, MNEMONIC, CODE, BITS, SHIFT, AVAIL) \ -+ { MNEMONIC, CODE, BITS, SHIFT, AVAIL }, -+#include "target/arc/flags.def" -+#undef ARC_FLAG -+ { 0, 0, 0, 0, 0} -+}; -+ -+enum arc_flags_map { -+ F_NULL = 0, -+#define ARC_FLAG(NAME, MNEMONIC, CODE, BITS, SHIFT, AVAIL) F_##NAME, -+#include "target/arc/flags.def" -+#undef ARC_FLAG -+ F_LAST -+}; -+ -+/* -+ * Table of the flag classes. -+ * -+ * The format of the table is -+ * CLASS {FLAG_CODE}. -+ */ -+const struct arc_flag_class arc_flag_classes[] = { -+#define C_EMPTY 0 -+ { F_CLASS_NONE, { F_NULL } }, -+ -+#define C_CC_EQ (C_EMPTY + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} }, -+ -+#define C_CC_GE (C_CC_EQ + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} }, -+ -+#define C_CC_GT (C_CC_GE + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} }, -+ -+#define C_CC_HI (C_CC_GT + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} }, -+ -+#define C_CC_HS (C_CC_HI + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} }, -+ -+#define C_CC_LE (C_CC_HS + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} }, -+ -+#define C_CC_LO (C_CC_LE + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} }, -+ -+#define C_CC_LS (C_CC_LO + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} }, -+ -+#define C_CC_LT (C_CC_LS + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} }, -+ -+#define C_CC_NE (C_CC_LT + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} }, -+ -+#define C_AA_AB (C_CC_NE + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} }, -+ -+#define C_AA_AW (C_AA_AB + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} }, -+ -+#define C_ZZ_D (C_AA_AW + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} }, -+ -+#define C_ZZ_H (C_ZZ_D + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} }, -+ -+#define C_ZZ_B (C_ZZ_H + 1) -+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} }, -+ -+#define C_CC (C_ZZ_B + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, -+ { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, -+ F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, -+ F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, -+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, -+ F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, -+ F_LE, F_HI, F_LS, F_PNZ, F_NULL -+ } -+ }, -+ -+#define C_AA_ADDR3 (C_CC + 1) -+#define C_AA27 (C_CC + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, -+#define C_AA_ADDR9 (C_AA_ADDR3 + 1) -+#define C_AA21 (C_AA_ADDR3 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, -+#define C_AA_ADDR22 (C_AA_ADDR9 + 1) -+#define C_AA8 (C_AA_ADDR9 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_WB, -+ { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } -+ }, -+ -+#define C_F (C_AA_ADDR22 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_F, { F_FLAG, F_NULL } }, -+#define C_FHARD (C_F + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_F, { F_FFAKE, F_NULL } }, -+ -+#define C_T (C_FHARD + 1) -+ { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } }, -+#define C_D (C_T + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_D, { F_ND, F_D, F_NULL } }, -+#define C_DNZ_D (C_D + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_D, { F_DNZ_ND, F_DNZ_D, F_NULL } }, -+ -+#define C_DHARD (C_DNZ_D + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_D, { F_DFAKE, F_NULL } }, -+ -+#define C_DI20 (C_DHARD + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_DI, { F_DI11, F_NULL } }, -+#define C_DI14 (C_DI20 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_DI, { F_DI14, F_NULL } }, -+#define C_DI16 (C_DI14 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_DI, { F_DI15, F_NULL } }, -+#define C_DI26 (C_DI16 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_DI, { F_DI5, F_NULL } }, -+ -+#define C_X25 (C_DI26 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_X, { F_SIGN6, F_NULL } }, -+#define C_X15 (C_X25 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_X, { F_SIGN16, F_NULL } }, -+#define C_XHARD (C_X15 + 1) -+#define C_X (C_X15 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_X, { F_SIGNX, F_NULL } }, -+ -+#define C_ZZ13 (C_X + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_ZZ, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL} }, -+#define C_ZZ23 (C_ZZ13 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_ZZ, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL} }, -+#define C_ZZ29 (C_ZZ23 + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_ZZ, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL} }, -+ -+#define C_AS (C_ZZ29 + 1) -+ { F_CLASS_IMPLICIT | F_CLASS_OPTIONAL | F_CLASS_WB, { F_ASFAKE, F_NULL} }, -+ -+#define C_NE (C_AS + 1) -+ { F_CLASS_OPTIONAL | F_CLASS_COND, { F_NE, F_NULL} }, -+}; -+ -+/* List with special cases instructions and the applicable flags. */ -+const struct arc_flag_special arc_flag_special_cases[] = { -+ { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, -+ F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, -+ F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, -+ F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, -+ F_LE, F_HI, F_LS, F_PNZ, F_NULL -+ } -+ }, -+ { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, -+ F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, -+ F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, -+ F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, -+ F_LE, F_HI, F_LS, F_PNZ, F_NULL -+ } -+ }, -+ { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, -+ F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, -+ F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, -+ F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, -+ F_LE, F_HI, F_LS, F_PNZ, F_NULL -+ } -+ }, -+ { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, -+ F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, -+ F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, -+ F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, -+ F_LE, F_HI, F_LS, F_PNZ, F_NULL -+ } -+ }, -+ { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, -+ F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, -+ F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, -+ F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, -+ F_LE, F_HI, F_LS, F_PNZ, F_NULL -+ } -+ }, -+ { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, -+ F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, -+ F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, -+ F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, -+ F_LE, F_HI, F_LS, F_PNZ, F_NULL -+ } -+ }, -+ { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, -+ F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, -+ F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, -+ F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, -+ F_LE, F_HI, F_LS, F_PNZ, F_NULL -+ } -+ }, -+ { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, -+ { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } -+}; -+ -+const unsigned arc_num_flag_special = ARRAY_SIZE(arc_flag_special_cases); -+ -+/* -+ * The opcode table. -+ * -+ * The format of the opcode table is: -+ * -+ * NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. -+ * -+ * The table is organised such that, where possible, all instructions with -+ * the same mnemonic are together in a block. When the assembler searches -+ * for a suitable instruction the entries are checked in table order, so -+ * more specific, or specialised cases should appear earlier in the table. -+ * -+ * As an example, consider two instructions 'add a,b,u6' and 'add -+ * a,b,limm'. The first takes a 6-bit immediate that is encoded within the -+ * 32-bit instruction, while the second takes a 32-bit immediate that is -+ * encoded in a follow-on 32-bit, making the total instruction length -+ * 64-bits. In this case the u6 variant must appear first in the table, as -+ * all u6 immediates could also be encoded using the 'limm' extension, -+ * however, we want to use the shorter instruction wherever possible. -+ * -+ * It is possible though to split instructions with the same mnemonic into -+ * multiple groups. However, the instructions are still checked in table -+ * order, even across groups. The only time that instructions with the -+ * same mnemonic should be split into different groups is when different -+ * variants of the instruction appear in different architectures, in which -+ * case, grouping all instructions from a particular architecture together -+ * might be preferable to merging the instruction into the main instruction -+ * table. -+ * -+ * An example of this split instruction groups can be found with the 'sync' -+ * instruction. The core arc architecture provides a 'sync' instruction, -+ * while the nps instruction set extension provides 'sync.rd' and -+ * 'sync.wr'. The rd/wr flags are instruction flags, not part of the -+ * mnemonic, so we end up with two groups for the sync instruction, the -+ * first within the core arc instruction table, and the second within the -+ * nps extension instructions. -+ */ -+static const struct arc_opcode arc_opcodes[] = { -+#include "target/arc/opcodes.def" -+ { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } -+}; -+ -+/* Return length of an opcode in bytes. */ -+static uint8_t arc_opcode_len(const struct arc_opcode *opcode) -+{ -+ if (opcode->mask < 0x10000ull) { -+ return 2; -+ } -+ -+ if (opcode->mask < 0x100000000ull) { -+ return 4; -+ } -+ -+ if (opcode->mask < 0x1000000000000ull) { -+ return 6; -+ } -+ -+ return 8; -+} -+ -+/*Helper for arc_find_format. */ -+static const struct arc_opcode *find_format(insn_t *pinsn, -+ uint64_t insn, -+ uint8_t insn_len, -+ uint32_t isa_mask) -+{ -+ uint32_t i = 0; -+ const struct arc_opcode *opcode = NULL; -+ const uint8_t *opidx; -+ const uint8_t *flgidx; -+ bool has_limm = false; -+ -+ do { -+ bool invalid = false; -+ uint32_t noperands = 0; -+ -+ opcode = &arc_opcodes[i++]; -+ memset(pinsn, 0, sizeof(*pinsn)); -+ -+ if (!(opcode->cpu & isa_mask)) { -+ continue; -+ } -+ -+ if (arc_opcode_len(opcode) != (int) insn_len) { -+ continue; -+ } -+ -+ if ((insn & opcode->mask) != opcode->opcode) { -+ continue; -+ } -+ -+ has_limm = false; -+ -+ /* Possible candidate, check the operands. */ -+ for (opidx = opcode->operands; *opidx; ++opidx) { -+ int value, limmind; -+ const struct arc_operand *operand = &arc_operands[*opidx]; -+ -+ if (operand->flags & ARC_OPERAND_FAKE) { -+ continue; -+ } -+ -+ if (operand->extract) { -+ value = (*operand->extract)(insn, &invalid); -+ } else { -+ value = (insn >> operand->shift) & ((1 << operand->bits) - 1); -+ } -+ -+ /* -+ * Check for LIMM indicator. If it is there, then make sure -+ * we pick the right format. -+ */ -+ limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E; -+ if (operand->flags & ARC_OPERAND_IR && -+ !(operand->flags & ARC_OPERAND_LIMM)) { -+ if ((value == 0x3E && insn_len == 4) || -+ (value == limmind && insn_len == 2)) { -+ invalid = TRUE; -+ break; -+ } -+ } -+ -+ if (operand->flags & ARC_OPERAND_LIMM && -+ !(operand->flags & ARC_OPERAND_DUPLICATE)) { -+ has_limm = true; -+ } -+ -+ pinsn->operands[noperands].value = value; -+ pinsn->operands[noperands].type = operand->flags; -+ noperands += 1; -+ pinsn->n_ops = noperands; -+ } -+ -+ /* Check the flags. */ -+ for (flgidx = opcode->flags; *flgidx; ++flgidx) { -+ /* Get a valid flag class. */ -+ const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; -+ const unsigned *flgopridx; -+ bool foundA = false, foundB = false; -+ unsigned int value; -+ -+ /* FIXME! Add check for EXTENSION flags. */ -+ -+ for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) { -+ const struct arc_flag_operand *flg_operand = -+ &arc_flag_operands[*flgopridx]; -+ -+ /* Check for the implicit flags. */ -+ if (cl_flags->flag_class & F_CLASS_IMPLICIT) { -+ if (cl_flags->flag_class & F_CLASS_COND) { -+ pinsn->cc = flg_operand->code; -+ } else if (cl_flags->flag_class & F_CLASS_WB) { -+ pinsn->aa = flg_operand->code; -+ } else if (cl_flags->flag_class & F_CLASS_ZZ) { -+ pinsn->zz = flg_operand->code; -+ } -+ continue; -+ } -+ -+ value = (insn >> flg_operand->shift) & -+ ((1 << flg_operand->bits) - 1); -+ if (value == flg_operand->code) { -+ if (cl_flags->flag_class & F_CLASS_ZZ) { -+ switch (flg_operand->name[0]) { -+ case 'b': -+ pinsn->zz = 1; -+ break; -+ case 'h': -+ case 'w': -+ pinsn->zz = 2; -+ break; -+ default: -+ pinsn->zz = 4; -+ break; -+ } -+ } -+ -+ /* -+ * TODO: This has a problem: instruction "b label" -+ * sets this to true. -+ */ -+ if (cl_flags->flag_class & F_CLASS_D) { -+ pinsn->d = value ? true : false; -+ if (cl_flags->flags[0] == F_DFAKE) { -+ pinsn->d = true; -+ } -+ } -+ -+ if (cl_flags->flag_class & F_CLASS_COND) { -+ pinsn->cc = value; -+ } -+ -+ if (cl_flags->flag_class & F_CLASS_WB) { -+ pinsn->aa = value; -+ } -+ -+ if (cl_flags->flag_class & F_CLASS_F) { -+ pinsn->f = true; -+ } -+ -+ if (cl_flags->flag_class & F_CLASS_DI) { -+ pinsn->di = true; -+ } -+ -+ if (cl_flags->flag_class & F_CLASS_X) { -+ pinsn->x = true; -+ } -+ -+ foundA = true; -+ } -+ if (value) { -+ foundB = true; -+ } -+ } -+ -+ if (!foundA && foundB) { -+ invalid = TRUE; -+ break; -+ } -+ } -+ -+ if (invalid) { -+ continue; -+ } -+ -+ /* The instruction is valid. */ -+ pinsn->limm_p = has_limm; -+ pinsn->class = (uint32_t) opcode->insn_class; -+ -+ /* -+ * FIXME: here add extra info about the instruction -+ * e.g. delay slot, data size, write back, etc. -+ */ -+ return opcode; -+ } while (opcode->mask); -+ -+ memset(pinsn, 0, sizeof(*pinsn)); -+ return NULL; -+} -+ -+/* Main entry point for this file. */ -+const struct arc_opcode *arc_find_format(insn_t *insnd, -+ uint64_t insn, -+ uint8_t insn_len, -+ uint32_t isa_mask) -+{ -+ memset(insnd, 0, sizeof(*insnd)); -+ return find_format(insnd, insn, insn_len, isa_mask); -+} -+ -+/* -+ * Calculate the instruction length for an instruction starting with -+ * MSB and LSB, the most and least significant byte. The ISA_MASK is -+ * used to filter the instructions considered to only those that are -+ * part of the current architecture. -+ * -+ * The instruction lengths are calculated from the ARC_OPCODE table, -+ * and cached for later use. -+ */ -+unsigned int arc_insn_length(uint16_t insn, uint16_t cpu_type) -+{ -+ uint8_t major_opcode; -+ uint8_t msb, lsb; -+ -+ msb = (uint8_t)(insn >> 8); -+ lsb = (uint8_t)(insn & 0xFF); -+ major_opcode = msb >> 3; -+ -+ switch (cpu_type) { -+ case ARC_OPCODE_ARC700: -+ if (major_opcode == 0xb) { -+ uint8_t minor_opcode = lsb & 0x1f; -+ -+ if (minor_opcode < 4) { -+ return 6; -+ } else if (minor_opcode == 0x10 || minor_opcode == 0x11) { -+ return 8; -+ } -+ } -+ if (major_opcode == 0xa) { -+ return 8; -+ } -+ /* Fall through. */ -+ case ARC_OPCODE_ARC600: -+ return (major_opcode > 0xb) ? 2 : 4; -+ break; -+ -+ case ARC_OPCODE_ARCv2EM: -+ case ARC_OPCODE_ARCv2HS: -+ return (major_opcode > 0x7) ? 2 : 4; -+ break; -+ -+ default: -+ g_assert_not_reached(); -+ } -+} -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/decoder.h b/target/arc/decoder.h -new file mode 100644 -index 0000000000..9a4c91d57d ---- /dev/null -+++ b/target/arc/decoder.h -@@ -0,0 +1,351 @@ -+/* -+ * Decoder for the ARC. -+ * Copyright 2020 Free Software Foundation, Inc. -+ * -+ * QEMU ARCv2 Decoder. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2, or (at your option) any later -+ * version. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see . -+ */ -+ -+#ifndef ARC_DECODER_H -+#define ARC_DECODER_H -+ -+#include "arc-common.h" -+ -+#ifndef MAX_INSN_ARGS -+#define MAX_INSN_ARGS 16 -+#endif -+ -+#ifndef MAX_INSN_FLGS -+#define MAX_INSN_FLGS 4 -+#endif -+ -+const char *get_register_name(int value); -+ -+/* Instruction Class. */ -+typedef enum { -+ NADA = 0, -+ ARC_ACL, -+ ARITH, -+ AUXREG, -+ BBIT0, -+ BBIT1, -+ BI, -+ BIH, -+ BITOP, -+ BITSTREAM, -+ BMU, -+ BRANCH, -+ BRCC, -+ CONTROL, -+ DIVREM, -+ DPI, -+ DSP, -+ EI, -+ ENTER, -+ ARC_FLOAT, -+ INVALID, -+ JLI, -+ JUMP, -+ KERNEL, -+ LEAVE, -+ LOAD, -+ LOGICAL, -+ LOOP, -+ MEMORY, -+ MOVE, -+ MPY, -+ NET, -+ PROTOCOL_DECODE, -+ PMU, -+ POP, -+ PUSH, -+ SJLI, -+ STORE, -+ SUB, -+ XY -+} insn_class_t; -+ -+/* Instruction Subclass. */ -+typedef enum { -+ NONE = 0, -+ CVT = (1U << 1), -+ BTSCN = (1U << 2), -+ CD = (1U << 3), -+ CD1 = CD, -+ CD2 = CD, -+ COND = (1U << 4), -+ DIV = (1U << 5), -+ DP = (1U << 6), -+ DPA = (1U << 7), -+ DPX = (1U << 8), -+ MPY1E = (1U << 9), -+ MPY6E = (1U << 10), -+ MPY7E = (1U << 11), -+ MPY8E = (1U << 12), -+ MPY9E = (1U << 13), -+ QUARKSE1 = (1U << 15), -+ QUARKSE2 = (1U << 16), -+ SHFT1 = (1U << 17), -+ SHFT2 = (1U << 18), -+ SWAP = (1U << 19), -+ SP = (1U << 20), -+ SPX = (1U << 21) -+} insn_subclass_t; -+ -+/* Flags class. */ -+typedef enum { -+ F_CLASS_NONE = 0, -+ -+ /* -+ * At most one flag from the set of flags can appear in the -+ * instruction. -+ */ -+ F_CLASS_OPTIONAL = (1 << 0), -+ -+ /* -+ * Exactly one from from the set of flags must appear in the -+ * instruction. -+ */ -+ F_CLASS_REQUIRED = (1 << 1), -+ -+ /* -+ * The conditional code can be extended over the standard variants -+ * via .extCondCode pseudo-op. -+ */ -+ F_CLASS_EXTEND = (1 << 2), -+ -+ /* Condition code flag. */ -+ F_CLASS_COND = (1 << 3), -+ -+ /* Write back mode. */ -+ F_CLASS_WB = (1 << 4), -+ -+ /* Data size. */ -+ F_CLASS_ZZ = (1 << 5), -+ -+ /* Implicit flag. */ -+ F_CLASS_IMPLICIT = (1 << 6), -+ -+ F_CLASS_F = (1 << 7), -+ -+ F_CLASS_DI = (1 << 8), -+ -+ F_CLASS_X = (1 << 9), -+ F_CLASS_D = (1 << 10), -+ -+} flag_class_t; -+ -+/* The opcode table is an array of struct arc_opcode. */ -+struct arc_opcode { -+ /* The opcode name. */ -+ const char *name; -+ -+ /* -+ * The opcode itself. Those bits which will be filled in with -+ * operands are zeroes. -+ */ -+ unsigned long long opcode; -+ -+ /* -+ * The opcode mask. This is used by the disassembler. This is a -+ * mask containing ones indicating those bits which must match the -+ * opcode field, and zeroes indicating those bits which need not -+ * match (and are presumably filled in by operands). -+ */ -+ unsigned long long mask; -+ -+ /* -+ * One bit flags for the opcode. These are primarily used to -+ * indicate specific processors and environments support the -+ * instructions. The defined values are listed below. -+ */ -+ unsigned cpu; -+ -+ /* The instruction class. */ -+ insn_class_t insn_class; -+ -+ /* The instruction subclass. */ -+ insn_subclass_t subclass; -+ -+ /* -+ * An array of operand codes. Each code is an index into the -+ * operand table. They appear in the order which the operands must -+ * appear in assembly code, and are terminated by a zero. -+ */ -+ unsigned char operands[MAX_INSN_ARGS + 1]; -+ -+ /* -+ * An array of flag codes. Each code is an index into the flag -+ * table. They appear in the order which the flags must appear in -+ * assembly code, and are terminated by a zero. -+ */ -+ unsigned char flags[MAX_INSN_FLGS + 1]; -+}; -+ -+/* The operands table is an array of struct arc_operand. */ -+struct arc_operand { -+ /* The number of bits in the operand. */ -+ unsigned int bits; -+ -+ /* How far the operand is left shifted in the instruction. */ -+ unsigned int shift; -+ -+ /* One bit syntax flags. */ -+ unsigned int flags; -+ -+ /* -+ * Extraction function. This is used by the disassembler. To -+ * extract this operand type from an instruction, check this -+ * field. -+ * -+ * If it is NULL, compute -+ * op = ((i) >> o->shift) & ((1 << o->bits) - 1); -+ * if ((o->flags & ARC_OPERAND_SIGNED) != 0 -+ * && (op & (1 << (o->bits - 1))) != 0) -+ * op -= 1 << o->bits; -+ * (i is the instruction, o is a pointer to this structure, and op -+ * is the result; this assumes twos complement arithmetic). -+ * -+ * If this field is not NULL, then simply call it with the -+ * instruction value. It will return the value of the operand. -+ * If the INVALID argument is not NULL, *INVALID will be set to -+ * TRUE if this operand type can not actually be extracted from -+ * this operand (i.e., the instruction does not match). If the -+ * operand is valid, *INVALID will not be changed. -+ */ -+ long long int (*extract) (unsigned long long instruction, -+ bool *invalid); -+}; -+ -+extern const struct arc_operand arc_operands[]; -+ -+/* Values defined for the flags field of a struct arc_operand. */ -+ -+/* -+ * This operand does not actually exist in the assembler input. This -+ * is used to support extended mnemonics, for which two operands -+ * fields are identical. The assembler should call the insert -+ * function with any op value. The disassembler should call the -+ * extract function, ignore the return value, and check the value -+ * placed in the invalid argument. -+ */ -+#define ARC_OPERAND_FAKE 0x0001 -+ -+/* This operand names an integer register. */ -+#define ARC_OPERAND_IR 0x0002 -+ -+/* This operand takes signed values. */ -+#define ARC_OPERAND_SIGNED 0x0004 -+ -+/* -+ * This operand takes unsigned values. This exists primarily so that -+ * a flags value of 0 can be treated as end-of-arguments. -+ */ -+#define ARC_OPERAND_UNSIGNED 0x0008 -+ -+/* This operand takes short immediate values. */ -+#define ARC_OPERAND_SHIMM (ARC_OPERAND_SIGNED | ARC_OPERAND_UNSIGNED) -+ -+/* This operand takes long immediate values. */ -+#define ARC_OPERAND_LIMM 0x0010 -+ -+/* This operand is identical like the previous one. */ -+#define ARC_OPERAND_DUPLICATE 0x0020 -+ -+/* This operand is PC relative. Used for internal relocs. */ -+#define ARC_OPERAND_PCREL 0x0040 -+ -+/* -+ * This operand is truncated. The truncation is done accordingly to -+ * operand alignment attribute. -+ */ -+#define ARC_OPERAND_TRUNCATE 0x0080 -+ -+/* This operand is 16bit aligned. */ -+#define ARC_OPERAND_ALIGNED16 0x0100 -+ -+/* This operand is 32bit aligned. */ -+#define ARC_OPERAND_ALIGNED32 0x0200 -+ -+/* -+ * This operand can be ignored by matching process if it is not -+ * present. -+ */ -+#define ARC_OPERAND_IGNORE 0x0400 -+ -+/* Don't check the range when matching. */ -+#define ARC_OPERAND_NCHK 0x0800 -+ -+/* Mark the braket possition. */ -+#define ARC_OPERAND_BRAKET 0x1000 -+ -+/* Mask for selecting the type for typecheck purposes. */ -+#define ARC_OPERAND_TYPECHECK_MASK \ -+ (ARC_OPERAND_IR \ -+ | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \ -+ | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET) -+ -+/* Macro to determine if an operand is a fake operand. */ -+#define ARC_OPERAND_IS_FAKE(op) \ -+ ((operand->flags & ARC_OPERAND_FAKE) \ -+ && !(operand->flags & ARC_OPERAND_BRAKET)) -+ -+/* The flags structure. */ -+struct arc_flag_operand { -+ /* The flag name. */ -+ const char *name; -+ -+ /* The flag code. */ -+ unsigned code; -+ -+ /* The number of bits in the operand. */ -+ unsigned int bits; -+ -+ /* How far the operand is left shifted in the instruction. */ -+ unsigned int shift; -+ -+ /* Available for disassembler. */ -+ unsigned char favail; -+}; -+ -+extern const struct arc_flag_operand arc_flag_operands[]; -+ -+/* The flag's class structure. */ -+struct arc_flag_class { -+ /* Flag class. */ -+ flag_class_t flag_class; -+ -+ /* List of valid flags (codes). */ -+ unsigned flags[256]; -+}; -+ -+extern const struct arc_flag_class arc_flag_classes[]; -+ -+/* Structure for special cases. */ -+struct arc_flag_special { -+ /* Name of special case instruction. */ -+ const char *name; -+ -+ /* List of flags applicable for special case instruction. */ -+ unsigned flags[32]; -+}; -+ -+extern const struct arc_flag_special arc_flag_special_cases[]; -+extern const unsigned arc_num_flag_special; -+ -+const struct arc_opcode *arc_find_format(insn_t*, uint64_t, uint8_t, uint32_t); -+unsigned int arc_insn_length(uint16_t, uint16_t); -+ -+#endif -diff --git a/target/arc/extra_mapping.def b/target/arc/extra_mapping.def -new file mode 100644 -index 0000000000..527a70f304 ---- /dev/null -+++ b/target/arc/extra_mapping.def -@@ -0,0 +1,79 @@ -+/* -+ * QEMU ARC EXTRA MAPPING -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+SEMANTIC_FUNCTION(ENTER, 0) -+SEMANTIC_FUNCTION(LEAVE, 0) -+MAPPING(enter_s, ENTER, 0) -+MAPPING(leave_s, LEAVE, 0) -+ -+SEMANTIC_FUNCTION(SR, 2) -+SEMANTIC_FUNCTION(SRL, 2) -+SEMANTIC_FUNCTION(SYNC, 0) -+MAPPING(sr, SR, 2, 1, 0) -+MAPPING(srl, SRL, 2, 1, 0) -+MAPPING(sync, SYNC, 0) -+ -+SEMANTIC_FUNCTION(TRAP, 1) -+SEMANTIC_FUNCTION(RTIE, 0) -+SEMANTIC_FUNCTION(SLEEP, 1) -+MAPPING(trap_s, TRAP, 1, 0) -+MAPPING(rtie, RTIE, 0) -+MAPPING(sleep, SLEEP, 1, 0) -+ -+SEMANTIC_FUNCTION(SWI, 1) -+CONSTANT(SWI, swi, 0, 0) -+MAPPING(swi, SWI, 1, 0) -+CONSTANT(SWI, swi_s, 0, 0) -+MAPPING(swi_s, SWI, 1, 0) -+ -+#ifdef TARGET_ARCV2 -+SEMANTIC_FUNCTION(VADD2, 3) -+SEMANTIC_FUNCTION(VADD2H, 3) -+SEMANTIC_FUNCTION(VADD4H, 3) -+SEMANTIC_FUNCTION(VSUB2, 3) -+SEMANTIC_FUNCTION(VSUB2H, 3) -+SEMANTIC_FUNCTION(VSUB4H, 3) -+SEMANTIC_FUNCTION(MPYD, 3) -+SEMANTIC_FUNCTION(MPYDU, 3) -+ -+ -+MAPPING(vadd2, VADD2, 3, 0, 1, 2) -+MAPPING(vadd2h, VADD2H, 3, 0, 1, 2) -+MAPPING(vadd4h, VADD4H, 3, 0, 1, 2) -+MAPPING(vsub2, VSUB2, 3, 0, 1, 2) -+MAPPING(vsub2h, VSUB2H, 3, 0, 1, 2) -+MAPPING(vsub4h, VSUB4H, 3, 0, 1, 2) -+MAPPING(mpyd, MPYD, 3, 0, 1, 2) -+MAPPING(mpydu, MPYDU, 3, 0, 1, 2) -+#endif -+ -+#ifdef TARGET_ARCV3 -+SEMANTIC_FUNCTION(MPYL, 3) -+SEMANTIC_FUNCTION(MPYML, 3) -+SEMANTIC_FUNCTION(MPYMUL, 3) -+SEMANTIC_FUNCTION(MPYMSUL, 3) -+SEMANTIC_FUNCTION(ADDHL, 3) -+ -+MAPPING(mpyl, MPYL, 3, 0, 1, 2) -+MAPPING(mpyml, MPYML, 3, 0, 1, 2) -+MAPPING(mpymul, MPYMUL, 3, 0, 1, 2) -+MAPPING(mpymsul, MPYMSUL, 3, 0, 1, 2) -+MAPPING(addhl, ADDHL, 3, 0, 1, 2) -+#endif -diff --git a/target/arc/flags-v3.def b/target/arc/flags-v3.def -new file mode 100644 -index 0000000000..0c04286dea ---- /dev/null -+++ b/target/arc/flags-v3.def -@@ -0,0 +1,103 @@ -+/* -+ * QEMU ARCv3 flags -+ * -+ * Copyright (c) 2020 Synopsys, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+ARC_FLAG(ALWAYS , "al", 0, 0, 0, 0) -+ARC_FLAG(RA, "ra", 0, 0, 0, 0) -+ARC_FLAG(EQUAL, "eq", 1, 5, 0, 1) -+ARC_FLAG(ZERO, "z", 1, 5, 0, 0) -+ARC_FLAG(NOTEQUAL, "ne", 2, 5, 0, 1) -+ARC_FLAG(NOTZERO , "nz", 2, 5, 0, 0) -+ARC_FLAG(POZITIVE, "p", 3, 5, 0, 1) -+ARC_FLAG(PL, "pl", 3, 5, 0, 0) -+ARC_FLAG(NEGATIVE, "n", 4, 5, 0, 1) -+ARC_FLAG(MINUS, "mi", 4, 5, 0, 0) -+ARC_FLAG(CARRY, "c", 5, 5, 0, 1) -+ARC_FLAG(CARRYSET, "cs", 5, 5, 0, 0) -+ARC_FLAG(LOWER, "lo", 5, 5, 0, 0) -+ARC_FLAG(CARRYCLR, "cc", 6, 5, 0, 0) -+ARC_FLAG(NOTCARRY, "nc", 6, 5, 0, 1) -+ARC_FLAG(HIGHER , "hs", 6, 5, 0, 0) -+ARC_FLAG(OVERFLOWSET, "vs", 7, 5, 0, 0) -+ARC_FLAG(OVERFLOW, "v", 7, 5, 0, 1) -+ARC_FLAG(NOTOVERFLOW, "nv", 8, 5, 0, 1) -+ARC_FLAG(OVERFLOWCLR, "vc", 8, 5, 0, 0) -+ARC_FLAG(GT, "gt", 9, 5, 0, 1) -+ARC_FLAG(GE, "ge", 10, 5, 0, 1) -+ARC_FLAG(LT, "lt", 11, 5, 0, 1) -+ARC_FLAG(LE, "le", 12, 5, 0, 1) -+ARC_FLAG(HI, "hi", 13, 5, 0, 1) -+ARC_FLAG(LS, "ls", 14, 5, 0, 1) -+ARC_FLAG(PNZ, "pnz", 15, 5, 0, 1) -+ARC_FLAG(NJ, "nj", 21, 5, 0, 1) -+ARC_FLAG(NM, "nm", 23, 5, 0, 1) -+ARC_FLAG(NO_T, "nt", 24, 5, 0, 1) -+ARC_FLAG(FLAG , "f", 1, 1, 15, 1) -+ARC_FLAG(FFAKE , "f", 0, 0, 0, 1) -+ARC_FLAG(AQ , "aq", 1, 1, 15, 1) -+ARC_FLAG(RL , "rl", 1, 1, 15, 1) -+ARC_FLAG(ATO_ADD , "add", 0, 3, 0, 1) -+ARC_FLAG(ATO_OR , "or", 1, 3, 0, 1) -+ARC_FLAG(ATO_AND , "and", 2, 3, 0, 1) -+ARC_FLAG(ATO_XOR , "xor", 3, 3, 0, 1) -+ARC_FLAG(ATO_MINU , "minu", 4, 3, 0, 1) -+ARC_FLAG(ATO_MAXU , "maxu", 5, 3, 0, 1) -+ARC_FLAG(ATO_MIN , "min", 6, 3, 0, 1) -+ARC_FLAG(ATO_MAX , "max", 7, 3, 0, 1) -+ARC_FLAG(ND, "nd", 0, 1, 5, 0) -+ARC_FLAG(D, "d", 1, 1, 5, 1) -+ARC_FLAG(DFAKE, "d", 0, 0, 0, 1) -+ARC_FLAG(DNZ_ND , "nd", 0, 1, 16, 0) -+ARC_FLAG(DNZ_D, "d", 1, 1, 16, 1) -+ARC_FLAG(SIZEB1 , "b", 1, 2, 1, 1) -+ARC_FLAG(SIZEB7 , "b", 1, 2, 7, 1) -+ARC_FLAG(SIZEB17, "b", 1, 2, 17, 1) -+ARC_FLAG(SIZEW1 , "w", 2, 2, 1, 0) -+ARC_FLAG(SIZEW7 , "w", 2, 2, 7, 0) -+ARC_FLAG(SIZEW17, "w", 2, 2, 17, 0) -+ARC_FLAG(SIGN6 , "x", 1, 1, 6, 1) -+ARC_FLAG(SIGN16, "x", 1, 1, 16, 1) -+ARC_FLAG(SIGNX , "x", 0, 0, 0, 1) -+ARC_FLAG(A3 , "a", 1, 2, 3, 0) -+ARC_FLAG(A9 , "a", 1, 2, 9, 0) -+ARC_FLAG(A22 , "a", 1, 2, 22, 0) -+ARC_FLAG(AW3 , "aw", 1, 2, 3, 1) -+ARC_FLAG(AW9 , "aw", 1, 2, 9, 1) -+ARC_FLAG(AW22 , "aw", 1, 2, 22, 1) -+ARC_FLAG(AB3 , "ab", 2, 2, 3, 1) -+ARC_FLAG(AB9 , "ab", 2, 2, 9, 1) -+ARC_FLAG(AB22 , "ab", 2, 2, 22, 1) -+ARC_FLAG(AS3 , "as", 3, 2, 3, 1) -+ARC_FLAG(AS9 , "as", 3, 2, 9, 1) -+ARC_FLAG(AS22 , "as", 3, 2, 22, 1) -+ARC_FLAG(ASFAKE , "as", 0, 0, 0, 1) -+ARC_FLAG(DI5, "di", 1, 1, 5, 1) -+ARC_FLAG(DI11, "di", 1, 1, 11, 1) -+ARC_FLAG(DI14, "di", 1, 1, 14, 1) -+ARC_FLAG(DI15, "di", 1, 1, 15, 1) -+ARC_FLAG(NT, "nt", 0, 1, 3, 1) -+ARC_FLAG(T, "t", 1, 1, 3, 1) -+ARC_FLAG(H1, "h", 2, 2, 1, 1) -+ARC_FLAG(H7, "h", 2, 2, 7, 1) -+ARC_FLAG(H17, "h", 2, 2, 17, 1) -+ARC_FLAG(D1, "d", 3, 2, 1, 1) -+ARC_FLAG(D7, "d", 3, 2, 7, 1) -+ARC_FLAG(D17, "d", 3, 2, 17, 1) -+ARC_FLAG(SIZED, "dd", 3, 0, 0, 0) -+ARC_FLAG(SIZEL, "dl", 3, 0, 0, 0) -+ARC_FLAG(SIZEW, "xx", 0, 0, 0, 0) -+ARC_FLAG(NE, "ne", 0, 0, 0, 1) -diff --git a/target/arc/flags.def b/target/arc/flags.def -new file mode 100644 -index 0000000000..455ce20bbf ---- /dev/null -+++ b/target/arc/flags.def -@@ -0,0 +1,85 @@ -+/* -+ * QEMU ARC flags -+ * -+ * Copyright (c) 2020 Synopsys, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+ARC_FLAG(ALWAYS, "al", 0, 0, 0, 0) -+ARC_FLAG(RA, "ra", 0, 0, 0, 0) -+ARC_FLAG(EQUAL, "eq", 1, 5, 0, 1) -+ARC_FLAG(ZERO, "z", 1, 5, 0, 0) -+ARC_FLAG(NOTEQUAL, "ne", 2, 5, 0, 1) -+ARC_FLAG(NOTZERO, "nz", 2, 5, 0, 0) -+ARC_FLAG(POZITIVE, "p", 3, 5, 0, 1) -+ARC_FLAG(PL, "pl", 3, 5, 0, 0) -+ARC_FLAG(NEGATIVE, "n", 4, 5, 0, 1) -+ARC_FLAG(MINUS, "mi", 4, 5, 0, 0) -+ARC_FLAG(CARRY, "c", 5, 5, 0, 1) -+ARC_FLAG(CARRYSET, "cs", 5, 5, 0, 0) -+ARC_FLAG(LOWER, "lo", 5, 5, 0, 0) -+ARC_FLAG(CARRYCLR, "cc", 6, 5, 0, 0) -+ARC_FLAG(NOTCARRY, "nc", 6, 5, 0, 1) -+ARC_FLAG(HIGHER, "hs", 6, 5, 0, 0) -+ARC_FLAG(OVERFLOWSET, "vs", 7, 5, 0, 0) -+ARC_FLAG(OVERFLOW, "v", 7, 5, 0, 1) -+ARC_FLAG(NOTOVERFLOW, "nv", 8, 5, 0, 1) -+ARC_FLAG(OVERFLOWCLR, "vc", 8, 5, 0, 0) -+ARC_FLAG(GT, "gt", 9, 5, 0, 1) -+ARC_FLAG(GE, "ge", 10, 5, 0, 1) -+ARC_FLAG(LT, "lt", 11, 5, 0, 1) -+ARC_FLAG(LE, "le", 12, 5, 0, 1) -+ARC_FLAG(HI, "hi", 13, 5, 0, 1) -+ARC_FLAG(LS, "ls", 14, 5, 0, 1) -+ARC_FLAG(PNZ, "pnz", 15, 5, 0, 1) -+ARC_FLAG(FLAG, "f", 1, 1, 15, 1) -+ARC_FLAG(FFAKE, "f", 0, 0, 0, 1) -+ARC_FLAG(ND, "nd", 0, 1, 5, 0) -+ARC_FLAG(D, "d", 1, 1, 5, 1) -+ARC_FLAG(DFAKE, "d", 0, 0, 0, 1) -+ARC_FLAG(DNZ_ND, "nd", 0, 1, 16, 0) -+ARC_FLAG(DNZ_D, "d", 1, 1, 16, 1) -+ARC_FLAG(SIZEB1, "b", 1, 2, 1, 1) -+ARC_FLAG(SIZEB7, "b", 1, 2, 7, 1) -+ARC_FLAG(SIZEB17, "b", 1, 2, 17, 1) -+ARC_FLAG(SIZEW1, "w", 2, 2, 1, 0) -+ARC_FLAG(SIZEW7, "w", 2, 2, 7, 0) -+ARC_FLAG(SIZEW17, "w", 2, 2, 17, 0) -+ARC_FLAG(SIGN6, "x", 1, 1, 6, 1) -+ARC_FLAG(SIGN16, "x", 1, 1, 16, 1) -+ARC_FLAG(SIGNX, "x", 0, 0, 0, 1) -+ARC_FLAG(A3, "a", 1, 2, 3, 0) -+ARC_FLAG(A9, "a", 1, 2, 9, 0) -+ARC_FLAG(A22, "a", 1, 2, 22, 0) -+ARC_FLAG(AW3, "aw", 1, 2, 3, 1) -+ARC_FLAG(AW9, "aw", 1, 2, 9, 1) -+ARC_FLAG(AW22, "aw", 1, 2, 22, 1) -+ARC_FLAG(AB3, "ab", 2, 2, 3, 1) -+ARC_FLAG(AB9, "ab", 2, 2, 9, 1) -+ARC_FLAG(AB22, "ab", 2, 2, 22, 1) -+ARC_FLAG(AS3, "as", 3, 2, 3, 1) -+ARC_FLAG(AS9, "as", 3, 2, 9, 1) -+ARC_FLAG(AS22, "as", 3, 2, 22, 1) -+ARC_FLAG(ASFAKE, "as", 3, 0, 0, 1) -+ARC_FLAG(DI5, "di", 1, 1, 5, 1) -+ARC_FLAG(DI11, "di", 1, 1, 11, 1) -+ARC_FLAG(DI14, "di", 1, 1, 14, 1) -+ARC_FLAG(DI15, "di", 1, 1, 15, 1) -+ARC_FLAG(NT, "nt", 0, 1, 3, 1) -+ARC_FLAG(T, "t", 1, 1, 3, 1) -+ARC_FLAG(H1, "h", 2, 2, 1, 1) -+ARC_FLAG(H7, "h", 2, 2, 7, 1) -+ARC_FLAG(H17, "h", 2, 2, 17, 1) -+ARC_FLAG(SIZED, "dd", 3, 0, 0, 0) -+ARC_FLAG(NE, "ne", 0, 0, 0, 1) -diff --git a/target/arc/gdbstub.c b/target/arc/gdbstub.c -new file mode 100644 -index 0000000000..0d11652546 ---- /dev/null -+++ b/target/arc/gdbstub.c -@@ -0,0 +1,444 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "exec/gdbstub.h" -+#include "arc-common.h" -+#include "target/arc/regs.h" -+#include "irq.h" -+#include "gdbstub.h" -+#include "exec/helper-proto.h" -+ -+/* gets the register address for a particular processor */ -+#define REG_ADDR(reg, processor_type) \ -+ arc_aux_reg_address_for((reg), (processor_type)) -+ -+#ifdef TARGET_ARCV2 -+#define GDB_GET_REG gdb_get_reg32 -+#elif defined(TARGET_ARCV3) -+#define GDB_GET_REG gdb_get_reg64 -+#else -+ #error No target is selected. -+#endif -+ -+int arc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) -+{ -+ ARCCPU *cpu = ARC_CPU(cs); -+ CPUARCState *env = &cpu->env; -+ target_ulong regval = 0; -+ -+ switch (n) { -+ case 0 ... 31: -+ regval = env->r[n]; -+ break; -+ case GDB_REG_58: -+ regval = env->r[58]; -+ break; -+ case GDB_REG_59: -+ regval = env->r[59]; -+ break; -+ case GDB_REG_60: -+ regval = env->r[60]; -+ break; -+ case GDB_REG_63: -+ regval = env->r[63]; -+ break; -+ default: -+ assert(!"Unsupported register is being read."); -+ } -+ -+ return GDB_GET_REG(mem_buf, regval); -+} -+ -+int arc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) -+{ -+ ARCCPU *cpu = ARC_CPU(cs); -+ CPUARCState *env = &cpu->env; -+ target_ulong regval = ldl_p(mem_buf); -+ -+ switch (n) { -+ case 0 ... 31: -+ env->r[n] = regval; -+ break; -+ case GDB_REG_58: -+ env->r[58] = regval; -+ break; -+ case GDB_REG_59: -+ env->r[59] = regval; -+ break; -+ case GDB_REG_60: -+ env->r[60] = regval; -+ break; -+ case GDB_REG_63: -+ env->r[63] = regval; -+ break; -+ default: -+ assert(!"Unsupported register is being written."); -+ } -+ -+ return 4; -+} -+ -+ -+static int -+arc_aux_minimal_gdb_get_reg(CPUARCState *env, GByteArray *mem_buf, int regnum) -+{ -+ ARCCPU *cpu = env_archcpu(env); -+ target_ulong regval = 0; -+ -+ switch (regnum) { -+ case GDB_AUX_MIN_REG_PC: -+ regval = env->pc & ((target_ulong) 0xfffffffffffffffe); -+ break; -+ case GDB_AUX_MIN_REG_LPS: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_lp_start, cpu->family)); -+ break; -+ case GDB_AUX_MIN_REG_LPE: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_lp_end, cpu->family)); -+ break; -+ case GDB_AUX_MIN_REG_STATUS: -+ regval = pack_status32(&env->stat); -+ break; -+ default: -+ assert(!"Unsupported minimal auxiliary register is being read."); -+ } -+ return GDB_GET_REG(mem_buf, regval); -+} -+ -+ -+static int -+arc_aux_minimal_gdb_set_reg(CPUARCState *env, uint8_t *mem_buf, int regnum) -+{ -+ ARCCPU *cpu = env_archcpu(env); -+ target_ulong regval = ldl_p(mem_buf); -+ switch (regnum) { -+ case GDB_AUX_MIN_REG_PC: -+ env->pc = regval & ((target_ulong) 0xfffffffffffffffe); -+ break; -+ case GDB_AUX_MIN_REG_LPS: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_lp_start, cpu->family)); -+ break; -+ case GDB_AUX_MIN_REG_LPE: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_lp_end, cpu->family)); -+ break; -+ case GDB_AUX_MIN_REG_STATUS: -+ unpack_status32(&env->stat, regval); -+ break; -+ default: -+ assert(!"Unsupported minimal auxiliary register is being written."); -+ } -+ return 4; -+} -+ -+ -+static int -+arc_aux_other_gdb_get_reg(CPUARCState *env, GByteArray *mem_buf, int regnum) -+{ -+ ARCCPU *cpu = env_archcpu(env); -+ target_ulong regval = 0; -+ switch (regnum) { -+ case GDB_AUX_OTHER_REG_TIMER_BUILD: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_timer_build, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_BUILD: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_irq_build, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_MPY_BUILD: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_mpy_build, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_VECBASE_BUILD: -+ regval = cpu->vecbase_build; -+ break; -+ case GDB_AUX_OTHER_REG_ISA_CONFIG: -+ regval = cpu->isa_config; -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_CNT0: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_count0, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_CTRL0: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_control0, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_LIM0: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_limit0, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_CNT1: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_count1, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_CTRL1: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_control1, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_LIM1: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_limit1, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_PID: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_pid, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TLBPD0: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_tlbpd0, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TLBPD1: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_tlbpd1, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TLB_INDEX: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_tlbindex, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TLB_CMD: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_tlbcommand, cpu->family)); -+ break; -+ /* MPU */ -+ case GDB_AUX_OTHER_REG_MPU_BUILD: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_mpu_build, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_MPU_EN: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_mpuen, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_MPU_ECR: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_mpuic, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_MPU_BASE0 ... GDB_AUX_OTHER_REG_MPU_BASE15: { -+ const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_BASE0; -+ regval = helper_lr(env, REG_ADDR(AUX_ID_mpurdb0 + index, cpu->family)); -+ break; -+ } -+ case GDB_AUX_OTHER_REG_MPU_PERM0 ... GDB_AUX_OTHER_REG_MPU_PERM15: { -+ const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_PERM0; -+ regval = helper_lr(env, REG_ADDR(AUX_ID_mpurdp0 + index, cpu->family)); -+ break; -+ } -+ /* exceptions */ -+ case GDB_AUX_OTHER_REG_ERSTATUS: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_erstatus, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_ERBTA: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_erbta, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_ECR: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_ecr, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_ERET: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_eret, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_EFA: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_efa, cpu->family)); -+ break; -+ /* interrupt */ -+ case GDB_AUX_OTHER_REG_ICAUSE: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_icause, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_CTRL: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_aux_irq_ctrl, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_ACT: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_aux_irq_act, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_PRIO_PEND: -+ regval = env->irq_priority_pending; -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_HINT: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_aux_irq_hint, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_SELECT: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_irq_select, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_ENABLE: -+ regval = env->irq_bank[env->irq_select & 0xff].enable; -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_TRIGGER: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_irq_trigger, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_STATUS: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_irq_status, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_PULSE: -+ regval = 0; /* write only for clearing the pulse triggered interrupt */ -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_PENDING: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_irq_pending, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_PRIO: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_irq_priority, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_BTA: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_bta, cpu->family)); -+ break; -+#ifdef TARGET_ARCV3 -+ /* MMUv6 */ -+ case GDB_AUX_OTHER_REG_MMU_CTRL: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_mmu_ctrl, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_RTP0: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_mmu_rtp0, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_RTP1: -+ regval = helper_lr(env, REG_ADDR(AUX_ID_mmu_rtp1, cpu->family)); -+ break; -+#endif -+ default: -+ assert(!"Unsupported other auxiliary register is being read."); -+ } -+ return GDB_GET_REG(mem_buf, regval); -+} -+ -+ -+static int -+arc_aux_other_gdb_set_reg(CPUARCState *env, uint8_t *mem_buf, int regnum) -+{ -+ ARCCPU *cpu = env_archcpu(env); -+ target_ulong regval = ldl_p(mem_buf); -+ switch (regnum) { -+ case GDB_AUX_OTHER_REG_TIMER_BUILD: -+ case GDB_AUX_OTHER_REG_IRQ_BUILD: -+ case GDB_AUX_OTHER_REG_MPY_BUILD: -+ case GDB_AUX_OTHER_REG_VECBASE_BUILD: -+ case GDB_AUX_OTHER_REG_ISA_CONFIG: -+ case GDB_AUX_OTHER_REG_MPU_BUILD: -+ case GDB_AUX_OTHER_REG_MPU_ECR: -+ case GDB_AUX_OTHER_REG_ICAUSE: -+ case GDB_AUX_OTHER_REG_IRQ_PRIO_PEND: -+ case GDB_AUX_OTHER_REG_IRQ_STATUS: -+ case GDB_AUX_OTHER_REG_IRQ_PENDING: -+ /* builds/configs/exceptions/irqs cannot be changed */ -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_CNT0: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_count0, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_CTRL0: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_control0, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_LIM0: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_limit0, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_CNT1: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_count1, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_CTRL1: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_control1, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TIMER_LIM1: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_limit1, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_PID: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_pid, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TLBPD0: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_tlbpd0, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TLBPD1: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_tlbpd1, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TLB_INDEX: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_tlbindex, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_TLB_CMD: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_tlbcommand, cpu->family)); -+ break; -+ /* MPU */ -+ case GDB_AUX_OTHER_REG_MPU_EN: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_mpuen, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_MPU_BASE0 ... GDB_AUX_OTHER_REG_MPU_BASE15: { -+ const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_BASE0; -+ helper_sr(env, regval, REG_ADDR(AUX_ID_mpurdb0 + index, cpu->family)); -+ break; -+ } -+ case GDB_AUX_OTHER_REG_MPU_PERM0 ... GDB_AUX_OTHER_REG_MPU_PERM15: { -+ const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_PERM0; -+ helper_sr(env, regval, REG_ADDR(AUX_ID_mpurdp0 + index, cpu->family)); -+ break; -+ } -+ /* exceptions */ -+ case GDB_AUX_OTHER_REG_ERSTATUS: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_erstatus, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_ERBTA: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_erbta, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_ECR: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_ecr, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_ERET: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_eret, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_EFA: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_efa, cpu->family)); -+ break; -+ /* interrupt */ -+ case GDB_AUX_OTHER_REG_IRQ_CTRL: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_ctrl, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_ACT: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_act, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_HINT: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_hint, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_SELECT: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_irq_select, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_ENABLE: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_irq_enable, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_TRIGGER: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_irq_trigger, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_PULSE: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_irq_pulse_cancel, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_IRQ_PRIO: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_irq_priority, cpu->family)); -+ break; -+ case GDB_AUX_OTHER_REG_BTA: -+ helper_sr(env, regval, REG_ADDR(AUX_ID_bta, cpu->family)); -+ break; -+ default: -+ assert(!"Unsupported other auxiliary register is being written."); -+ } -+ return 4; -+} -+ -+#ifdef TARGET_ARCV2 -+#define GDB_TARGET_MINIMAL_XML "arc-v2-aux.xml" -+#define GDB_TARGET_AUX_XML "arc-v2-other.xml" -+#else -+#define GDB_TARGET_MINIMAL_XML "arc64-aux-minimal.xml" -+#define GDB_TARGET_AUX_XML "arc64-aux-other.xml" -+#endif -+ -+void arc_cpu_register_gdb_regs_for_features(ARCCPU *cpu) -+{ -+ CPUState *cs = CPU(cpu); -+ -+ gdb_register_coprocessor(cs, -+ arc_aux_minimal_gdb_get_reg, /* getter */ -+ arc_aux_minimal_gdb_set_reg, /* setter */ -+ GDB_AUX_MIN_REG_LAST, /* number of registers */ -+ GDB_TARGET_MINIMAL_XML, /* feature file */ -+ 0); /* position in g packet */ -+ -+ gdb_register_coprocessor(cs, -+ arc_aux_other_gdb_get_reg, -+ arc_aux_other_gdb_set_reg, -+ GDB_AUX_OTHER_REG_LAST, -+ GDB_TARGET_AUX_XML, -+ 0); -+} -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/gdbstub.h b/target/arc/gdbstub.h -new file mode 100644 -index 0000000000..ff00c592e1 ---- /dev/null -+++ b/target/arc/gdbstub.h -@@ -0,0 +1,167 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#ifndef ARC_GDBSTUB_H -+#define ARC_GDBSTUB_H -+ -+#ifdef TARGET_ARCV2 -+#define GDB_TARGET_STRING "arc:ARCv2" -+#else -+#define GDB_TARGET_STRING "arc:ARCv3_64" -+#endif -+ -+enum gdb_regs { -+ GDB_REG_0 = 0, -+ GDB_REG_1, -+ GDB_REG_2, -+ GDB_REG_3, -+ GDB_REG_4, -+ GDB_REG_5, -+ GDB_REG_6, -+ GDB_REG_7, -+ GDB_REG_8, -+ GDB_REG_9, -+ GDB_REG_10, -+ GDB_REG_11, -+ GDB_REG_12, -+ GDB_REG_13, -+ GDB_REG_14, -+ GDB_REG_15, -+ GDB_REG_16, -+ GDB_REG_17, -+ GDB_REG_18, -+ GDB_REG_19, -+ GDB_REG_20, -+ GDB_REG_21, -+ GDB_REG_22, -+ GDB_REG_23, -+ GDB_REG_24, -+ GDB_REG_25, -+ GDB_REG_26, /* GP */ -+ GDB_REG_27, /* FP */ -+ GDB_REG_28, /* SP */ -+ GDB_REG_29, /* ILINK */ -+ GDB_REG_30, /* R30 */ -+ GDB_REG_31, /* BLINK */ -+ GDB_REG_58, /* little_endian? ACCL : ACCH */ -+ GDB_REG_59, /* little_endian? ACCH : ACCL */ -+ GDB_REG_60, /* LP */ -+ GDB_REG_63, /* Immediate */ -+ GDB_REG_LAST -+}; -+ -+enum gdb_aux_min_regs { -+ GDB_AUX_MIN_REG_PC = 0, /* program counter */ -+ GDB_AUX_MIN_REG_LPS, /* loop body start */ -+ GDB_AUX_MIN_REG_LPE, /* loop body end */ -+ GDB_AUX_MIN_REG_STATUS, /* status flag */ -+ GDB_AUX_MIN_REG_LAST -+}; -+ -+enum gdb_aux_other_regs { -+ /* builds */ -+ GDB_AUX_OTHER_REG_TIMER_BUILD = 0, /* timer build */ -+ GDB_AUX_OTHER_REG_IRQ_BUILD, /* irq build */ -+ GDB_AUX_OTHER_REG_MPY_BUILD, /* multiply configuration */ -+ GDB_AUX_OTHER_REG_VECBASE_BUILD, /* vector base address config */ -+ GDB_AUX_OTHER_REG_ISA_CONFIG, /* isa config */ -+ /* timers */ -+ GDB_AUX_OTHER_REG_TIMER_CNT0, /* timer 0 counter */ -+ GDB_AUX_OTHER_REG_TIMER_CTRL0, /* timer 0 control */ -+ GDB_AUX_OTHER_REG_TIMER_LIM0, /* timer 0 limit */ -+ GDB_AUX_OTHER_REG_TIMER_CNT1, /* timer 1 counter */ -+ GDB_AUX_OTHER_REG_TIMER_CTRL1, /* timer 1 control */ -+ GDB_AUX_OTHER_REG_TIMER_LIM1, /* timer 1 limit */ -+ /* mpu */ -+ GDB_AUX_OTHER_REG_MPU_BUILD, /* MPU build */ -+ GDB_AUX_OTHER_REG_MPU_EN, /* MPU enable */ -+ GDB_AUX_OTHER_REG_MPU_ECR, /* MPU exception cause */ -+ GDB_AUX_OTHER_REG_MPU_BASE0, /* MPU base 0 */ -+ GDB_AUX_OTHER_REG_MPU_BASE1, /* MPU base 1 */ -+ GDB_AUX_OTHER_REG_MPU_BASE2, /* MPU base 2 */ -+ GDB_AUX_OTHER_REG_MPU_BASE3, /* MPU base 3 */ -+ GDB_AUX_OTHER_REG_MPU_BASE4, /* MPU base 4 */ -+ GDB_AUX_OTHER_REG_MPU_BASE5, /* MPU base 5 */ -+ GDB_AUX_OTHER_REG_MPU_BASE6, /* MPU base 6 */ -+ GDB_AUX_OTHER_REG_MPU_BASE7, /* MPU base 7 */ -+ GDB_AUX_OTHER_REG_MPU_BASE8, /* MPU base 8 */ -+ GDB_AUX_OTHER_REG_MPU_BASE9, /* MPU base 9 */ -+ GDB_AUX_OTHER_REG_MPU_BASE10, /* MPU base 10 */ -+ GDB_AUX_OTHER_REG_MPU_BASE11, /* MPU base 11 */ -+ GDB_AUX_OTHER_REG_MPU_BASE12, /* MPU base 12 */ -+ GDB_AUX_OTHER_REG_MPU_BASE13, /* MPU base 13 */ -+ GDB_AUX_OTHER_REG_MPU_BASE14, /* MPU base 14 */ -+ GDB_AUX_OTHER_REG_MPU_BASE15, /* MPU base 15 */ -+ GDB_AUX_OTHER_REG_MPU_PERM0, /* MPU permission 0 */ -+ GDB_AUX_OTHER_REG_MPU_PERM1, /* MPU permission 1 */ -+ GDB_AUX_OTHER_REG_MPU_PERM2, /* MPU permission 2 */ -+ GDB_AUX_OTHER_REG_MPU_PERM3, /* MPU permission 3 */ -+ GDB_AUX_OTHER_REG_MPU_PERM4, /* MPU permission 4 */ -+ GDB_AUX_OTHER_REG_MPU_PERM5, /* MPU permission 5 */ -+ GDB_AUX_OTHER_REG_MPU_PERM6, /* MPU permission 6 */ -+ GDB_AUX_OTHER_REG_MPU_PERM7, /* MPU permission 7 */ -+ GDB_AUX_OTHER_REG_MPU_PERM8, /* MPU permission 8 */ -+ GDB_AUX_OTHER_REG_MPU_PERM9, /* MPU permission 9 */ -+ GDB_AUX_OTHER_REG_MPU_PERM10, /* MPU permission 10 */ -+ GDB_AUX_OTHER_REG_MPU_PERM11, /* MPU permission 11 */ -+ GDB_AUX_OTHER_REG_MPU_PERM12, /* MPU permission 12 */ -+ GDB_AUX_OTHER_REG_MPU_PERM13, /* MPU permission 13 */ -+ GDB_AUX_OTHER_REG_MPU_PERM14, /* MPU permission 14 */ -+ GDB_AUX_OTHER_REG_MPU_PERM15, /* MPU permission 15 */ -+ /* excpetions */ -+ GDB_AUX_OTHER_REG_ERSTATUS, /* exception return status */ -+ GDB_AUX_OTHER_REG_ERBTA, /* exception return BTA */ -+ GDB_AUX_OTHER_REG_ECR, /* exception cause register */ -+ GDB_AUX_OTHER_REG_ERET, /* exception return address */ -+ GDB_AUX_OTHER_REG_EFA, /* exception fault address */ -+ /* irq */ -+ GDB_AUX_OTHER_REG_ICAUSE, /* interrupt cause */ -+ GDB_AUX_OTHER_REG_IRQ_CTRL, /* context saving control */ -+ GDB_AUX_OTHER_REG_IRQ_ACT, /* active */ -+ GDB_AUX_OTHER_REG_IRQ_PRIO_PEND, /* priority pending */ -+ GDB_AUX_OTHER_REG_IRQ_HINT, /* hint */ -+ GDB_AUX_OTHER_REG_IRQ_SELECT, /* select */ -+ GDB_AUX_OTHER_REG_IRQ_ENABLE, /* enable */ -+ GDB_AUX_OTHER_REG_IRQ_TRIGGER, /* trigger */ -+ GDB_AUX_OTHER_REG_IRQ_STATUS, /* status */ -+ GDB_AUX_OTHER_REG_IRQ_PULSE, /* pulse cancel */ -+ GDB_AUX_OTHER_REG_IRQ_PENDING, /* pending */ -+ GDB_AUX_OTHER_REG_IRQ_PRIO, /* priority */ -+ /* miscellaneous */ -+ GDB_AUX_OTHER_REG_BTA, /* branch target address */ -+ /* mmu */ -+ GDB_AUX_OTHER_REG_PID, /* process identity */ -+ GDB_AUX_OTHER_REG_TLBPD0, /* page descriptor 0 */ -+ GDB_AUX_OTHER_REG_TLBPD1, /* page descriptor 1 */ -+ GDB_AUX_OTHER_REG_TLB_INDEX, /* tlb index */ -+ GDB_AUX_OTHER_REG_TLB_CMD, /* tlb command */ -+#ifdef TARGET_ARCV3 -+ /* mmuv6 */ -+ GDB_AUX_OTHER_REG_MMU_CTRL, /* mmuv6 control */ -+ GDB_AUX_OTHER_REG_RTP0, /* region 0 ptr */ -+ GDB_AUX_OTHER_REG_RTP1, /* region 1 ptr */ -+#endif -+ -+ GDB_AUX_OTHER_REG_LAST -+}; -+ -+/* add auxiliary registers to set of supported registers for GDB */ -+void arc_cpu_register_gdb_regs_for_features(ARCCPU *cpu); -+ -+#endif /* ARC_GDBSTUB_H */ -diff --git a/target/arc/helper.c b/target/arc/helper.c -new file mode 100644 -index 0000000000..9e59cabbb3 ---- /dev/null -+++ b/target/arc/helper.c -@@ -0,0 +1,292 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+ -+#include "cpu.h" -+#include "hw/irq.h" -+#include "include/hw/sysbus.h" -+#include "include/sysemu/sysemu.h" -+#include "qemu/qemu-print.h" -+#include "exec/exec-all.h" -+#include "exec/cpu_ldst.h" -+#include "qemu/host-utils.h" -+#include "exec/helper-proto.h" -+#include "irq.h" -+ -+void arc_cpu_do_interrupt(CPUState *cs) -+{ -+ ARCCPU *cpu = ARC_CPU(cs); -+ CPUARCState *env = &cpu->env; -+ uint32_t offset = 0; -+ uint32_t vectno; -+ const char *name; -+ MemTxResult txres; -+ -+ /* -+ * NOTE: Special LP_END exception. Immediately return code execution to -+ * lp_start. -+ * Now also used for delayslot MissI cases. -+ * This special exception should not execute any of the exception -+ * handling code. Instead it returns immediately after setting PC to the -+ * address passed as exception parameter. -+ */ -+ if (cs->exception_index == EXCP_LPEND_REACHED -+ || cs->exception_index == EXCP_FAKE) { -+ env->pc = env->param; -+ CPU_PCL(env) = env->pc & 0xfffffffe; -+ return; -+ } -+ -+ /* If we take an exception within an exception => fatal Machine Check. */ -+ if (GET_STATUS_BIT(env->stat, AEf) == 1) { -+ cs->exception_index = EXCP_MACHINE_CHECK; -+ env->causecode = 0; -+ env->param = 0; -+ arc_mmu_disable(env); -+ env->mpu.enabled = false; /* no more MPU */ -+ } -+ vectno = cs->exception_index & 0x0F; -+ offset = OFFSET_FOR_VECTOR(vectno); -+ -+ /* Generic computation for exceptions. */ -+ switch (cs->exception_index) { -+ case EXCP_RESET: -+ name = "Reset"; -+ break; -+ case EXCP_MEMORY_ERROR: -+ name = "Memory Error"; -+ break; -+ case EXCP_INST_ERROR: -+ name = "Instruction Error"; -+ break; -+ case EXCP_MACHINE_CHECK: -+ name = "Machine Check"; -+ break; -+#ifdef TARGET_ARCV2 -+ case EXCP_TLB_MISS_I: -+ name = "TLB Miss Instruction"; -+ break; -+ case EXCP_TLB_MISS_D: -+ name = "TLB Miss Data"; -+ break; -+#elif defined(TARGET_ARCV3) -+ case EXCP_IMMU_FAULT: -+ name = "Instruction MMU Fault"; -+ break; -+ case EXCP_DMMU_FAULT: -+ name = "Data MMU Fault"; -+ break; -+#else -+#error -+#endif -+ case EXCP_PROTV: -+ name = "Protection Violation"; -+ break; -+ case EXCP_PRIVILEGEV: -+ name = "Privilege Violation"; -+ break; -+ case EXCP_SWI: -+ name = "SWI"; -+ break; -+ case EXCP_TRAP: -+ name = "Trap"; -+ break; -+ case EXCP_EXTENSION: -+ name = "Extension"; -+ break; -+ case EXCP_DIVZERO: -+ name = "DIV by Zero"; -+ break; -+ case EXCP_DCERROR: -+ name = "DCError"; -+ break; -+ case EXCP_MISALIGNED: -+ name = "Misaligned"; -+ break; -+ case EXCP_IRQ: -+ default: -+ cpu_abort(cs, "unhandled exception/irq type=%d\n", -+ cs->exception_index); -+ break; -+ } -+ -+ qemu_log_mask(CPU_LOG_INT, "[EXCP] exception %d (%s) at pc=0x" -+ TARGET_FMT_lx "\n", -+ cs->exception_index, name, env->pc); -+ -+ /* -+ * 3. exception status register is loaded with the contents -+ * of STATUS32. -+ */ -+ env->stat_er = env->stat; -+ -+ /* 4. exception return branch target address register. */ -+ env->erbta = env->bta; -+ -+ /* -+ * 5. eception cause register is loaded with a code to indicate -+ * the cause of the exception. -+ */ -+ env->ecr = (vectno & 0xFF) << 16; -+ env->ecr |= (env->causecode & 0xFF) << 8; -+ env->ecr |= (env->param & 0xFF); -+ -+ /* 6. Set the EFA if available. */ -+ if (cpu->cfg.has_mmu || cpu->cfg.has_mpu) { -+ switch (cs->exception_index) { -+ case EXCP_DCERROR: -+ case EXCP_DIVZERO: -+ case EXCP_EXTENSION: -+ case EXCP_TRAP: -+ case EXCP_SWI: -+ case EXCP_PRIVILEGEV: -+ case EXCP_MACHINE_CHECK: -+ case EXCP_INST_ERROR: -+ case EXCP_RESET: -+ /* TODO: this should move to the place raising the exception */ -+ env->efa = env->pc; -+ break; -+ default: -+ break; -+ } -+ } -+ -+ /* 7. CPU is switched to kernel mode. */ -+ SET_STATUS_BIT(env->stat, Uf, 0); -+ -+ if (GET_STATUS_BIT(env->stat_er, Uf)) { -+ switchSP(env); -+ } -+ -+ /* 8. Interrupts are disabled. */ -+ env->stat.IEf = 0; -+ -+ /* 9. The active exception flag is set. */ -+ SET_STATUS_BIT(env->stat, AEf, 1); -+ -+ /* 10-14. Other flags sets. */ -+ env->stat.Zf = GET_STATUS_BIT(env->stat_er, Uf); -+ SET_STATUS_BIT(env->stat, Lf, 1); -+ env->stat.DEf = 0; -+ SET_STATUS_BIT(env->stat, ESf, 0); -+ SET_STATUS_BIT(env->stat, DZf, 0); -+ SET_STATUS_BIT(env->stat, SCf, 0); -+ -+ /* 15. The PC is set with the appropriate exception vector. */ -+ env->pc = address_space_ldl(cs->as, env->intvec + offset, -+ MEMTXATTRS_UNSPECIFIED, &txres); -+ assert(txres == MEMTX_OK); -+ CPU_PCL(env) = env->pc & 0xfffffffe; -+ -+ qemu_log_mask(CPU_LOG_INT, "[EXCP] isr=0x" TARGET_FMT_lx -+ " vec=0x%x ecr=0x" TARGET_FMT_lx "\n", -+ env->pc, offset, env->ecr); -+ -+ /* Make sure that exception code decodes corectly */ -+ env->stat.is_delay_slot_instruction = 0; -+ -+ cs->exception_index = -1; -+} -+ -+static gint arc_cpu_list_compare(gconstpointer a, gconstpointer b) -+{ -+ ObjectClass *class_a = (ObjectClass *)a; -+ ObjectClass *class_b = (ObjectClass *)b; -+ const char *name_a; -+ const char *name_b; -+ -+ name_a = object_class_get_name(class_a); -+ name_b = object_class_get_name(class_b); -+ if (strcmp(name_a, "any-" TYPE_ARC_CPU) == 0) { -+ return 1; -+ } else if (strcmp(name_b, "any-" TYPE_ARC_CPU) == 0) { -+ return -1; -+ } else { -+ return strcmp(name_a, name_b); -+ } -+} -+ -+static void arc_cpu_list_entry(gpointer data, gpointer user_data) -+{ -+ ObjectClass *oc = data; -+ const char *typename; -+ char *name; -+ -+ typename = object_class_get_name(oc); -+ name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARC_CPU)); -+ qemu_printf(" %s\n", name); -+ g_free(name); -+} -+ -+void arc_cpu_list(void) -+{ -+ GSList *list; -+ -+ list = object_class_get_list(TYPE_ARC_CPU, false); -+ list = g_slist_sort(list, arc_cpu_list_compare); -+ qemu_printf("Available CPUs:\n"); -+ g_slist_foreach(list, arc_cpu_list_entry, NULL); -+ g_slist_free(list); -+} -+ -+int arc_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, -+ int len, bool is_write) -+{ -+ return cpu_memory_rw_debug(cs, addr, buf, len, is_write); -+} -+ -+hwaddr arc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -+{ -+ ARCCPU *cpu = ARC_CPU(cs); -+ CPUARCState *env = &cpu->env; -+ -+ return arc_mmu_debug_translate(env, addr); -+} -+ -+void helper_debug(CPUARCState *env) -+{ -+ CPUState *cs = env_cpu(env); -+ -+ cs->exception_index = EXCP_DEBUG; -+ cpu_loop_exit(cs); -+} -+ -+/* -+ * raises a simple exception with causecode and parameter set to 0. -+ * it also considers "pc" as the exception return address. this is -+ * not true for a software trap. -+ * it is very important that "env->host_pc" holds the recent value, -+ * else the cpu_restore_state() will not be helpful and we end up -+ * with incorrect registers in env. -+ */ -+void QEMU_NORETURN arc_raise_exception(CPUARCState *env, int32_t excp_idx) -+{ -+ CPUState *cs = env_cpu(env); -+ cpu_restore_state(cs, env->host_pc, true); -+ cs->exception_index = excp_idx; -+ env->causecode = env->param = 0x0; -+ env->eret = env->pc; -+ env->erbta = env->bta; -+ cpu_loop_exit(cs); -+} -+ -+ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/helper.h b/target/arc/helper.h -new file mode 100644 -index 0000000000..2d93fc3a96 ---- /dev/null -+++ b/target/arc/helper.h -@@ -0,0 +1,55 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * href="http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+DEF_HELPER_1(debug, void, env) -+DEF_HELPER_2(lr, tl, env, tl) -+DEF_HELPER_3(sr, void, env, tl, tl) -+DEF_HELPER_2(halt, noreturn, env, tl) -+DEF_HELPER_1(rtie, void, env) -+DEF_HELPER_1(flush, void, env) -+DEF_HELPER_4(raise_exception, noreturn, env, tl, tl, tl) -+DEF_HELPER_2(zol_verify, void, env, tl) -+DEF_HELPER_2(fake_exception, void, env, tl) -+DEF_HELPER_2(set_status32, void, env, tl) -+DEF_HELPER_1(get_status32, tl, env) -+DEF_HELPER_3(set_status32_bit, void, env, tl, tl) -+ -+DEF_HELPER_FLAGS_3(carry_add_flag, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) -+DEF_HELPER_FLAGS_3(overflow_add_flag, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) -+DEF_HELPER_FLAGS_3(overflow_sub_flag, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) -+DEF_HELPER_FLAGS_3(mpymu, TCG_CALL_NO_RWG_SE, tl, env, tl, tl) -+DEF_HELPER_FLAGS_3(mpym, TCG_CALL_NO_RWG_SE, tl, env, tl, tl) -+DEF_HELPER_FLAGS_3(repl_mask, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) -+ -+/* ARCV3 helpers */ -+#ifdef TARGET_ARCV3 -+DEF_HELPER_FLAGS_2(ffs32, TCG_CALL_NO_RWG_SE, tl, env, tl) -+ -+DEF_HELPER_FLAGS_3(carry_add_flag32, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) -+DEF_HELPER_FLAGS_3(carry_sub_flag32, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) -+DEF_HELPER_FLAGS_3(overflow_add_flag32, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) -+DEF_HELPER_FLAGS_3(overflow_sub_flag32, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) -+ -+DEF_HELPER_FLAGS_2(rotate_left32, TCG_CALL_NO_RWG_SE, i64, i64, i64) -+DEF_HELPER_FLAGS_2(rotate_right32, TCG_CALL_NO_RWG_SE, i64, i64, i64) -+DEF_HELPER_FLAGS_2(asr_32, TCG_CALL_NO_RWG_SE, i64, i64, i64) -+ -+DEF_HELPER_2(norml, i64, env, i64) -+#endif -diff --git a/target/arc/irq.c b/target/arc/irq.c -new file mode 100644 -index 0000000000..398ee8f011 ---- /dev/null -+++ b/target/arc/irq.c -@@ -0,0 +1,691 @@ -+/* -+ * QEMU ARC CPU - IRQ subsystem -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "qemu/log.h" -+#include "qemu/error-report.h" -+#include "hw/irq.h" -+#include "cpu.h" -+#include "qemu/main-loop.h" -+#include "irq.h" -+#include "exec/cpu_ldst.h" -+#include "translate.h" -+#include "qemu/host-utils.h" -+ -+#define CACHE_ENTRY_SIZE (TARGET_LONG_BITS / 8) -+#ifdef TARGET_ARCV2 -+#define TARGET_LONG_LOAD(ENV, ADDR) cpu_ldl_data(ENV, ADDR) -+#define TARGET_LONG_STORE(ENV, ADDR, VALUE) cpu_stl_data(ENV, ADDR, VALUE) -+#elif defined(TARGET_ARCV3) -+#define TARGET_LONG_LOAD(ENV, ADDR) cpu_ldq_data(ENV, ADDR) -+#define TARGET_LONG_STORE(ENV, ADDR, VALUE) cpu_stq_data(ENV, ADDR, VALUE) -+#else -+#error "This should never happen !!!!" -+#endif -+ -+/* Static functions and variables. */ -+ -+static uint32_t save_reg_pair_32[] = { -+ 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 -+}; -+ -+static uint32_t save_reg_pair_16[] = { -+ 0, 2, 10, 12, 14, 26, 28, 30 -+}; -+ -+/* Given a struct STATUS_R, pack it to 32 bit. */ -+uint32_t pack_status32(ARCStatus *status_r) -+{ -+ uint32_t res = 0x0; -+ -+ res |= status_r->pstate & PSTATE_MASK; -+ res |= (status_r->RBf & ((1 << RBf_bS)-1)) << RBf_b; -+ res |= (status_r->Zf & ((1 << Zf_bS)-1)) << Zf_b; -+ res |= (status_r->Nf & ((1 << Nf_bS)-1)) << Nf_b; -+ res |= (status_r->Cf & ((1 << Cf_bS)-1)) << Cf_b; -+ res |= (status_r->Vf & ((1 << Vf_bS)-1)) << Vf_b; -+ res |= (status_r->DEf & ((1 << DEf_bS)-1)) << DEf_b; -+ res |= (status_r->Ef & ((1 << Ef_bS)-1)) << Ef_b; -+ res |= (status_r->IEf & ((1 << IEf_bS)-1)) << IEf_b; -+ -+ /* For debug purposes only. */ -+ /* -+ * assert((status_r->pstate & ~PSTATE_MASK) == 0); -+ * assert((status_r->RBf & (~((1 << RBf_bS) - 1))) == 0); -+ * assert((status_r->Zf & (~((1 << Zf_bS) - 1))) == 0); -+ * assert((status_r->Nf & (~((1 << Cf_bS) - 1))) == 0); -+ * assert((status_r->Cf & (~((1 << Cf_bS) - 1))) == 0); -+ * assert((status_r->Vf & (~((1 << Vf_bS) - 1))) == 0); -+ * assert((status_r->DEf & (~((1 << DEf_bS) - 1))) == 0); -+ * assert((status_r->Ef & (~((1 << Ef_bS) - 1))) == 0); -+ * assert((status_r->IEf & (~((1 << IEf_bS) - 1))) == 0); -+ */ -+ -+ return res; -+} -+ -+/* Reverse of the above function. */ -+void unpack_status32(ARCStatus *status_r, uint32_t value) -+{ -+ status_r->pstate = value; -+ status_r->RBf = ((value >> RBf_b)&((1 << RBf_bS)-1)); -+ status_r->Zf = ((value >> Zf_b)&((1 << Zf_bS)-1)); -+ status_r->Nf = ((value >> Nf_b)&((1 << Nf_bS)-1)); -+ status_r->Cf = ((value >> Cf_b)&((1 << Cf_bS)-1)); -+ status_r->Vf = ((value >> Vf_b)&((1 << Vf_bS)-1)); -+ status_r->DEf = ((value >> DEf_b)&((1 << DEf_bS)-1)); -+ status_r->Ef = ((value >> Ef_b)&((1 << Ef_bS)-1)); -+ status_r->IEf = ((value >> IEf_b)&((1 << IEf_bS)-1)); -+} -+ -+/* Return from fast interrupts. */ -+ -+static void arc_rtie_firq(CPUARCState *env) -+{ -+ assert(GET_STATUS_BIT(env->stat, AEf) == 0); -+ -+ qemu_log_mask(CPU_LOG_INT, "[IRQ] exit firq: U=" TARGET_FMT_ld -+ ", AUX_IRQ_ACT.U=%d\n", -+ GET_STATUS_BIT(env->stat, Uf), env->aux_irq_act >> 31); -+ -+ /* Clear currently active interrupt. */ -+ env->aux_irq_act &= (~1); -+ -+ /* Check if we need to restore userland SP. */ -+ if (((env->aux_irq_act & 0xFFFF) == 0) && (env->aux_irq_act & 0x80000000)) { -+ switchSP(env); -+ } -+ -+ env->stat = env->stat_l1; /* FIXME use status32_p0 reg. */ -+ /* Keep U-bit in sync. */ -+ env->aux_irq_act &= ~(GET_STATUS_BIT(env->stat, Uf) << 31); -+ -+ /* FIXME! fix current reg bank if RB bit is changed. */ -+ -+ CPU_PCL(env) = CPU_ILINK(env); -+ env->pc = CPU_ILINK(env); -+} -+ -+/* Implements a pop operation from the CPU stack. */ -+static target_ulong irq_pop(CPUARCState *env, const char *str) -+{ -+ target_ulong rval; -+ rval = TARGET_LONG_LOAD(env, CPU_SP(env)); -+ -+ qemu_log_mask(CPU_LOG_INT, "[IRQ] Pop [SP:0x" TARGET_FMT_lx -+ "] => 0x" TARGET_FMT_lx " (%s)\n", -+ CPU_SP(env), rval, str ? str : "unk"); -+ CPU_SP(env) += CACHE_ENTRY_SIZE; -+ return rval; -+} -+ -+/* Return from regular interrupts. */ -+ -+static void arc_rtie_irq(CPUARCState *env) -+{ -+ uint32_t tmp; -+ ARCCPU *cpu = env_archcpu(env); -+ -+ assert((env->aux_irq_act & 0xFFFF) != 0); -+ assert(GET_STATUS_BIT(env->stat, AEf) == 0); -+ -+ /* Clear currently active interrupt. */ -+ tmp = ctz32(env->aux_irq_act & 0xffff); -+ -+ qemu_log_mask(CPU_LOG_INT, -+ "[IRQ] exit irq:%d IRQ_ACT:0x%08x PRIO:%d\n", -+ env->icause[tmp], env->aux_irq_act, tmp); -+ -+ /* -+ * FIXME! I assume the current active interrupt is the one which is -+ * the highest in the aux_irq_act register. -+ */ -+ env->aux_irq_act &= ~(1 << tmp); -+ -+ qemu_log_mask(CPU_LOG_INT, -+ "[IRQ] exit irq:%d U:" TARGET_FMT_ld " AE:" TARGET_FMT_ld -+ " IE:" TARGET_FMT_ld " E:" TARGET_FMT_ld " IRQ_ACT:0x%08x\n", -+ env->icause[tmp], GET_STATUS_BIT(env->stat, Uf), -+ GET_STATUS_BIT(env->stat, AEf), env->stat.IEf, -+ env->stat.Ef, env->aux_irq_act); -+ -+ if (((env->aux_irq_act & 0xffff) == 0) && -+ (env->aux_irq_act & 0x80000000) && (env->aux_irq_ctrl & (1 << 11))) { -+ switchSP(env); -+ } -+ -+ /* Pop requested number of registers. */ -+ /* FIXME! select rf16 when needed. */ -+ uint32_t *save_reg_pair = save_reg_pair_32; -+ char regname[6]; -+ uint32_t i; -+ for (i = 0; i < (env->aux_irq_ctrl & 0x1F); ++i) { -+ sprintf(regname, "r%d", save_reg_pair[i]); -+ env->r[save_reg_pair[i]] = irq_pop(env, (const char *) regname); -+ sprintf(regname, "r%d", save_reg_pair[i] + 1); -+ env->r[save_reg_pair[i] + 1] = irq_pop(env, (const char *) regname); -+ } -+ -+ /* Pop BLINK */ -+ if (env->aux_irq_ctrl & (1 << 9) && ((env->aux_irq_ctrl & 0x1F) != 16)) { -+ CPU_BLINK(env) = irq_pop(env, "blink"); -+ } -+ -+#ifdef TARGET_ARCV2 -+ /* Pop lp_end, lp_start, lp_count if aux_irq_ctrl.l bit is set. */ -+ if (env->aux_irq_ctrl & (1 << 10)) { -+ env->lpe = irq_pop(env, "LP_END"); -+ env->lps = irq_pop(env, "LP_START"); -+ CPU_LP(env) = irq_pop(env, "lp"); -+ } -+#endif -+ -+ /* -+ * Pop EI_BASE, JLI_BASE, LDI_BASE if LP bit is set and Code -+ * Density feature is enabled. FIXME! -+ */ -+ if (cpu->cfg.code_density && (env->aux_irq_ctrl & (1 << 13))) { -+ /* FIXME! env->aux_ei_base = irq_pop(env); */ -+ /* FIXME! env->aux_ldi_base = irq_pop(env); */ -+ /* FIXME! env->aux_jli_base = irq_pop(env); */ -+ irq_pop(env, "dummy EI_BASE"); -+ irq_pop(env, "dummy LDI_BASE"); -+ irq_pop(env, "dummy JLI_BASE"); -+ } -+ -+ CPU_ILINK(env) = irq_pop(env, "PC"); /* CPU PC*/ -+ uint32_t tmp_stat = irq_pop(env, "STATUS32"); /* status. */ -+ unpack_status32(&env->stat, tmp_stat); -+ -+ /* Late switch to Kernel SP if previously in User thread. */ -+ if (((env->aux_irq_act & 0xffff) == 0) -+ && GET_STATUS_BIT(env->stat, Uf) && !(env->aux_irq_ctrl & (1 << 11))) { -+ switchSP(env); -+ } -+ -+ /* Keep U-bit in sync. */ -+ env->aux_irq_act &= ~(GET_STATUS_BIT(env->stat, Uf) << 31); -+ CPU_PCL(env) = CPU_ILINK(env); -+ env->pc = CPU_ILINK(env); -+} -+ -+/* Helper, implements entering in a fast irq. */ -+static void arc_enter_firq(ARCCPU *cpu, uint32_t vector) -+{ -+ CPUARCState *env = &cpu->env; -+ -+ assert(env->stat.DEf == 0); -+ assert(env->stat.is_delay_slot_instruction == 0); -+ -+ /* Reset RTC state machine -> AUX_RTC_CTRL &= 0x3fffffff */ -+ qemu_log_mask(CPU_LOG_INT, -+ "[IRQ] enter firq:%d U:" TARGET_FMT_ld " AE:" TARGET_FMT_ld -+ " IE:" TARGET_FMT_ld " E:" TARGET_FMT_ld "\n", -+ vector, GET_STATUS_BIT(env->stat, Uf), -+ GET_STATUS_BIT(env->stat, AEf), env->stat.IEf, -+ env->stat.Ef); -+ -+ /* Switch SP with AUX_SP. */ -+ if (GET_STATUS_BIT(env->stat, Uf)) { -+ switchSP(env); -+ } -+ -+ /* Clobber ILINK with address of interrupting instruction. */ -+ CPU_ILINK(env) = env->pc; -+ assert((env->pc & 0x1) == 0); -+ env->stat_l1 = env->stat; -+ -+ /* Set stat {Z = U; U = 0; L = 1; ES = 0; DZ = 0; DE = 0;} */ -+ SET_STATUS_BIT(env->stat, Lf, 1); -+ env->stat.Zf = GET_STATUS_BIT(env->stat, Uf); /* Old User/Kernel bit. */ -+ SET_STATUS_BIT(env->stat, Uf, 0); -+ SET_STATUS_BIT(env->stat, ESf, 0); -+ SET_STATUS_BIT(env->stat, DZf, 0); -+ env->stat.DEf = 0; -+ env->stat.is_delay_slot_instruction = 0; -+ -+ /* Set .RB to 1 if additional register banks are specified. */ -+ if (cpu->cfg.rgf_num_banks > 0) { -+ env->stat.RBf = 1; -+ /* FIXME! Switch to first register bank. */ -+ } -+} -+ -+/* Implements a push operation to the CPU stack. */ -+static void irq_push(CPUARCState *env, target_ulong regval, const char *str) -+{ -+ CPU_SP(env) -= CACHE_ENTRY_SIZE; -+ qemu_log_mask(CPU_LOG_INT, "[IRQ] Push [SP:0x" TARGET_FMT_lx -+ "] <= 0x" TARGET_FMT_lx " (%s)\n", -+ CPU_SP(env), regval, str ? str : "unk"); -+ uint32_t uf = GET_STATUS_BIT(env->stat, Uf); -+ SET_STATUS_BIT(env->stat, Uf, 0); -+ TARGET_LONG_STORE(env, CPU_SP(env), regval); -+ SET_STATUS_BIT(env->stat, Uf, uf); -+} -+ -+/* Helper, implements the steps required to enter a simple interrupt. */ -+static void arc_enter_irq(ARCCPU *cpu, uint32_t vector) -+{ -+ CPUARCState *env = &cpu->env; -+ -+ assert(env->stat.DEf == 0); -+ assert(env->stat.is_delay_slot_instruction == 0); -+ -+ /* Reset RTC state machine -> AUX_RTC_CTRL &= 0x3fffffff */ -+ qemu_log_mask(CPU_LOG_INT, "[IRQ] enter irq:%d U:" TARGET_FMT_ld -+ " AE:" TARGET_FMT_ld " IE:" TARGET_FMT_ld -+ " E:" TARGET_FMT_ld "\n", -+ vector, GET_STATUS_BIT(env->stat, Uf), -+ GET_STATUS_BIT(env->stat, AEf), env->stat.IEf, -+ env->stat.Ef); -+ -+ /* Early switch to kernel sp if previously in user thread */ -+ if (GET_STATUS_BIT(env->stat, Uf) && !(env->aux_irq_ctrl & (1 << 11))) { -+ switchSP(env); -+ } -+ -+ /* Clobber ILINK with address of interrupting instruction. */ -+ CPU_ILINK(env) = env->pc; -+ -+ /* Start pushing regs and stat. */ -+ irq_push(env, pack_status32(&env->stat), "STATUS32"); -+ irq_push(env, env->pc, "PC"); -+ -+ /* -+ * Push EI_BASE, JLI_BASE, LDI_BASE if LP bit is set and Code -+ * Density feature is enabled. -+ */ -+ if (cpu->cfg.code_density && (env->aux_irq_ctrl & (1 << 13))) { -+ /* FIXME! irq_push(env, env->aux_jli_base, "JLI_BASE"); */ -+ /* FIXME! irq_push(env, env->aux_ldi_base, "LDI_BASE""); */ -+ /* FIXME! irq_push(env, env->aux_ei_base, "EI_BASE"); */ -+ irq_push(env, 0xdeadbeef, "dummy JLI_BASE"); -+ irq_push(env, 0xdeadbeef, "dummy LDI_BASE"); -+ irq_push(env, 0xdeadbeef, "dummy EI_BASE"); -+ } -+ -+#ifdef TARGET_ARCV2 -+ /* Push LP_COUNT, LP_START, LP_END registers if required. */ -+ if (env->aux_irq_ctrl & (1 << 10)) { -+ irq_push(env, CPU_LP(env), "lp"); -+ irq_push(env, env->lps, "LP_START"); -+ irq_push(env, env->lpe, "LP_END"); -+ } -+#endif -+ -+ /* Push BLINK register if required */ -+ if (env->aux_irq_ctrl & (1 << 9) && ((env->aux_irq_ctrl & 0x1F) != 16)) { -+ irq_push(env, CPU_BLINK(env), "blink"); -+ } -+ -+ /* Push selected AUX_IRQ_CTRL.NR of registers onto stack. */ -+ uint32_t *save_reg_pair = cpu->cfg.rgf_num_regs == 32 ? -+ save_reg_pair_32 : save_reg_pair_16; -+ const uint32_t regspair = (cpu->cfg.rgf_num_regs == 32 ? 16 : 8); -+ const uint32_t upperlimit = (env->aux_irq_ctrl & 0x1F) < regspair ? -+ env->aux_irq_ctrl & 0x1F : regspair; -+ char regname[6]; -+ uint32_t i; -+ -+ for (i = upperlimit; i > 0; --i) { -+ sprintf(regname, "r%d", save_reg_pair[i - 1] + 1); -+ irq_push(env, env->r[save_reg_pair[i - 1] + 1], (const char *) regname); -+ sprintf(regname, "r%d", save_reg_pair[i - 1]); -+ irq_push(env, env->r[save_reg_pair[i - 1]], (const char *) regname); -+ } -+ -+ /* Late switch to Kernel SP if previously in User thread. */ -+ if (GET_STATUS_BIT(env->stat, Uf) && (env->aux_irq_ctrl & (1 << 11))) { -+ switchSP(env); -+ } -+ -+ /* Set STATUS bits */ -+ env->stat.Zf = GET_STATUS_BIT(env->stat, Uf); /* Old User/Kernel mode. */ -+ SET_STATUS_BIT(env->stat, Lf, 1); -+ SET_STATUS_BIT(env->stat, ESf, 0); -+ SET_STATUS_BIT(env->stat, DZf, 0); -+ env->stat.DEf = 0; -+ SET_STATUS_BIT(env->stat, Uf, 0); -+} -+ -+/* Function implementation for reading the IRQ related aux regs. */ -+target_ulong aux_irq_get(const struct arc_aux_reg_detail *aux_reg_detail, -+ void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ ARCCPU *cpu = env_archcpu(env); -+ uint32_t tmp; -+ -+ /* extract selected IRQ. */ -+ const uint32_t irq = env->irq_select; -+ const ARCIrq *irq_bank = &env->irq_bank[irq]; -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_irq_pending: -+ return irq_bank->pending | (irq > 15 ? (env->aux_irq_hint == irq) : 0); -+ -+ case AUX_ID_irq_select: -+ return env->irq_select; -+ -+ case AUX_ID_irq_priority: -+ return irq_bank->priority; -+ -+ case AUX_ID_irq_trigger: -+ return irq_bank->trigger; -+ -+ case AUX_ID_irq_status: -+ return (irq_bank->priority -+ | irq_bank->enable << 4 -+ | irq_bank->trigger << 5 -+ | (irq_bank->pending -+ | (irq > 15 ? ((env->aux_irq_hint == irq) << 31) : 0))); -+ -+ case AUX_ID_aux_irq_act: -+ return env->aux_irq_act; -+ -+ case AUX_ID_aux_irq_ctrl: -+ return env->aux_irq_ctrl; -+ -+ case AUX_ID_icause: -+ if ((env->aux_irq_act & 0xffff) == 0) { -+ return 0; -+ } -+ tmp = ctz32(env->aux_irq_act & 0xffff); -+ return env->icause[tmp]; -+ -+ case AUX_ID_irq_build: -+ return cpu->irq_build; -+ -+ case AUX_ID_int_vector_base: -+ return env->intvec; -+ -+ case AUX_ID_vecbase_ac_build: -+ return cpu->vecbase_build; -+ break; -+ -+ case AUX_ID_aux_user_sp: -+ return env->aux_user_sp; -+ -+ case AUX_ID_aux_irq_hint: -+ return env->aux_irq_hint; -+ -+ default: -+ break; -+ } -+ return 0; -+} -+ -+/* Function implementation for writing the IRQ related aux regs. */ -+void aux_irq_set(const struct arc_aux_reg_detail *aux_reg_detail, -+ target_ulong val, void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ ARCCPU *cpu = env_archcpu(env); -+ const uint32_t irq = env->irq_select; -+ ARCIrq *irq_bank = &env->irq_bank[irq]; -+ -+ qemu_log_mask(CPU_LOG_INT, "[IRQ] set aux_reg: %s, with 0x" -+ TARGET_FMT_lx "\n", -+ arc_aux_reg_name[aux_reg_detail->id], -+ val); -+ -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_irq_select: -+ if (val <= (16 + ((cpu->irq_build >> 8) & 0xff))) -+ env->irq_select = val; -+ else -+ qemu_log_mask(LOG_UNIMP, -+ "[IRQ] Invalid write 0x" TARGET_FMT_lx -+ " to IRQ_SELECT aux reg.\n", -+ val); -+ break; -+ -+ case AUX_ID_aux_irq_hint: -+ qemu_mutex_lock_iothread(); -+ if (val == 0) { -+ qemu_irq_lower(env->irq[env->aux_irq_hint]); -+ } else if (val >= 16) { -+ qemu_irq_raise(env->irq[val]); -+ env->aux_irq_hint = val; -+ } -+ qemu_mutex_unlock_iothread(); -+ break; -+ -+ case AUX_ID_irq_pulse_cancel: -+ irq_bank->pending = irq_bank->trigger ? (val & 0x01) : 0; -+ break; -+ -+ case AUX_ID_irq_trigger: -+ irq_bank->trigger = val & 0x01; -+ break; -+ -+ case AUX_ID_irq_priority: -+ if (val <= ((cpu->irq_build >> 24) & 0x0f)) { -+ irq_bank->priority = val & 0x0f; -+ } else { -+ qemu_log_mask(LOG_UNIMP, -+ "[IRQ] Invalid write 0x" TARGET_FMT_lx -+ " to IRQ_PRIORITY aux reg.\n", -+ val); -+ } -+ break; -+ -+ case AUX_ID_aux_irq_ctrl: -+ env->aux_irq_ctrl = val & 0x2e1f; -+ break; -+ -+ case AUX_ID_irq_enable: -+ irq_bank->enable = val & 0x01; -+ break; -+ -+ case AUX_ID_aux_irq_act: -+ env->aux_irq_act = val & 0x8000ffff; -+ break; -+ -+ case AUX_ID_int_vector_base: -+ env->intvec = val; -+ break; -+ -+ case AUX_ID_aux_user_sp: -+ env->aux_user_sp = val; -+ break; -+ -+ default: -+ break; -+ } -+} -+ -+/* Check if we can interrupt the cpu. */ -+ -+bool arc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -+{ -+ ARCCPU *cpu = ARC_CPU(cs); -+ CPUARCState *env = &cpu->env; -+ bool found = false; -+ uint32_t vectno = 0; -+ uint32_t offset, priority; -+ -+ /* Check if we should execute this interrupt. */ -+ if (GET_STATUS_BIT(env->stat, Hf) -+ /* The interrupts are enabled. */ -+ || env->stat.IEf == 0 -+ /* We are not in an exception. */ -+ || GET_STATUS_BIT(env->stat, AEf) -+ /* Disable interrupts to happen after MissI exceptions. */ -+ || env->enabled_interrupts == false -+ /* In a delay slot of branch */ -+ || env->stat.is_delay_slot_instruction -+ || env->stat.DEf -+ || (!(interrupt_request & CPU_INTERRUPT_HARD))) { -+ return false; -+ } -+ -+ /* Check if any interrupts are pending. */ -+ if (!env->irq_priority_pending -+ /* Or we are serving at the same priority level. */ -+ || (ctz32(env->irq_priority_pending) >= ctz32(env->aux_irq_act))) { -+ return false; -+ } -+ -+ /* Find the first IRQ to serve. */ -+ priority = 0; -+ do { -+ for (vectno = 0; -+ vectno < cpu->cfg.number_of_interrupts; vectno++) { -+ if (env->irq_bank[16 + vectno].priority == priority -+ && env->irq_bank[16 + vectno].enable -+ && env->irq_bank[16 + vectno].pending) { -+ found = true; -+ break; -+ } -+ } -+ } while (!found && ((++priority) <= env->stat.Ef)); -+ -+ /* No valid interrupt has been found. */ -+ if (!found) { -+ return false; -+ } -+ -+ qemu_log_mask(CPU_LOG_INT, "[IRQ] interrupt at pc=0x" TARGET_FMT_lx -+ "\n", env->pc); -+ -+ /* Adjust vector number. */ -+ vectno += 16; -+ -+ /* Set the AUX_IRQ_ACT. */ -+ if ((env->aux_irq_act & 0xffff) == 0) { -+ env->aux_irq_act |= GET_STATUS_BIT(env->stat, Uf) << 31; -+ } -+ env->aux_irq_act |= 1 << priority; -+ -+ /* Set ICAUSE register. */ -+ env->icause[priority] = vectno; -+ -+ /* Do FIRQ if possible. */ -+ if (cpu->cfg.firq_option && priority == 0) { -+ arc_enter_firq(cpu, vectno); -+ } else { -+ arc_enter_irq(cpu, vectno); -+ } -+ -+ /* XX. The PC is set with the appropriate exception vector. */ -+ offset = OFFSET_FOR_VECTOR(vectno); -+ env->pc = TARGET_LONG_LOAD(env, env->intvec + offset); -+ CPU_PCL(env) = env->pc & (~1); -+ -+ qemu_log_mask(CPU_LOG_INT, "[IRQ] isr=0x" TARGET_FMT_lx -+ " vec=0x%08x, priority=0x%04x\n", -+ env->pc, offset, priority); -+ -+ return true; -+} -+ -+/* To be called in the RTIE helper. */ -+ -+bool arc_rtie_interrupts(CPUARCState *env) -+{ -+ ARCCPU *cpu = env_archcpu(env); -+ -+ if (GET_STATUS_BIT(env->stat, AEf) || ((env->aux_irq_act & 0xffff) == 0)) { -+ return false; -+ } -+ -+ /* FIXME! Reset RTC state. */ -+ -+ if ((env->aux_irq_act & 0xffff) == 1 && cpu->cfg.firq_option) { -+ arc_rtie_firq(env); -+ } else { -+ arc_rtie_irq(env); -+ } -+ return true; -+} -+ -+/* Switch between AUX USER SP and CPU's SP. */ -+void switchSP(CPUARCState *env) -+{ -+ uint32_t tmp; -+ qemu_log_mask(CPU_LOG_INT, -+ "[%s] swap: r28 = 0x" TARGET_FMT_lx -+ " AUX_USER_SP = 0x%08x\n", -+ (env->aux_irq_act & 0xFFFF) ? "IRQ" : "EXCP", -+ CPU_SP(env), env->aux_user_sp); -+ -+ tmp = env->aux_user_sp; -+ env->aux_user_sp = CPU_SP(env); -+ CPU_SP(env) = tmp; -+ /* -+ * TODO: maybe we need to flush the tcg buffer to switch into -+ * kernel mode. -+ */ -+} -+ -+/* Reset the IRQ subsytem. */ -+void arc_resetIRQ(ARCCPU *cpu) -+{ -+ CPUARCState *env = &cpu->env; -+ uint32_t i; -+ -+ if (!cpu->cfg.has_interrupts) { -+ return; -+ } -+ -+ for (i = 0; i < (cpu->cfg.number_of_interrupts & 0xff); i++) { -+ env->irq_bank[16 + i].enable = 1; -+ } -+ -+ if (cpu->cfg.has_timer_0) { -+ /* FIXME! add build default timer0 priority. */ -+ env->irq_bank[16].priority = 0; -+ } -+ -+ if (cpu->cfg.has_timer_1) { -+ /* FIXME! add build default timer1 priority. */ -+ env->irq_bank[17].priority = 0; -+ } -+ -+ qemu_log_mask(CPU_LOG_RESET, "[IRQ] Reset the IRQ subsystem."); -+} -+ -+/* Initializing the IRQ subsystem. */ -+void arc_initializeIRQ(ARCCPU *cpu) -+{ -+ CPUARCState *env = &cpu->env; -+ uint32_t i; -+ -+ if (cpu->cfg.has_interrupts) { -+ /* FIXME! add N (NMI) bit. */ -+ cpu->irq_build = 0x01 | ((cpu->cfg.number_of_interrupts & 0xff) << 8) | -+ ((cpu->cfg.external_interrupts & 0xff) << 16) | -+ ((cpu->cfg.number_of_levels & 0x0f) << 24) | -+ (cpu->cfg.firq_option ? (1 << 28) : 0); -+ -+ for (i = 0; i < (cpu->cfg.number_of_interrupts & 0xff); i++) { -+ env->irq_bank[16 + i].enable = 1; -+ } -+ -+ cpu->vecbase_build = (cpu->cfg.intvbase_preset & (~0x3ffff)) -+ | (0x04 << 2); -+ env->intvec = cpu->cfg.intvbase_preset & (~0x3ffff); -+ } else { -+ cpu->irq_build = 0; -+ } -+} -diff --git a/target/arc/irq.h b/target/arc/irq.h -new file mode 100644 -index 0000000000..fdd1b84843 ---- /dev/null -+++ b/target/arc/irq.h -@@ -0,0 +1,44 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef __IRQ_H__ -+#define __IRQ_H__ -+ -+#include "target/arc/regs.h" -+#include "cpu.h" -+ -+bool arc_cpu_exec_interrupt(CPUState *, int); -+bool arc_rtie_interrupts(CPUARCState *); -+void switchSP(CPUARCState *); -+void arc_initializeIRQ(ARCCPU *); -+void arc_resetIRQ(ARCCPU *); -+uint32_t pack_status32(ARCStatus *); -+void unpack_status32(ARCStatus *, uint32_t); -+ -+#ifdef TARGET_ARCV2 -+#define OFFSET_FOR_VECTOR(VECNO) (VECNO << 2) -+#elif defined(TARGET_ARCV3) -+#define OFFSET_FOR_VECTOR(VECNO) (VECNO << 3) -+#else -+#error Should never be reached -+#endif -+ -+ -+#endif -diff --git a/target/arc/meson.build b/target/arc/meson.build -new file mode 100644 -index 0000000000..9d633553a8 ---- /dev/null -+++ b/target/arc/meson.build -@@ -0,0 +1,34 @@ -+dir = meson.current_source_dir() -+ -+gen32 = [ -+ dir + '/decoder.c', -+ dir + '/semfunc.c', -+ dir + '/mmu.c', -+] -+gen64 = [ -+ dir + '/decoder-v3.c', -+ dir + '/semfunc-v3.c', -+ dir + '/mmu-v6.c', -+] -+ -+arc_softmmu_ss = ss.source_set() -+arc_softmmu_ss.add(when: 'TARGET_ARCV2', if_true: gen32) -+arc_softmmu_ss.add(when: 'TARGET_ARCV3', if_true: gen64) -+ -+arc_softmmu_ss.add(files( -+ 'translate.c', -+ 'helper.c', -+ 'cpu.c', -+ 'op_helper.c', -+ 'gdbstub.c', -+ 'regs.c', -+ 'regs-impl.c', -+ 'semfunc-helper.c', -+ 'mpu.c', -+ 'timer.c', -+ 'irq.c', -+ 'cache.c', -+)) -+ -+target_arch += {'arc': arc_softmmu_ss} -+target_softmmu_arch += {'arc': arc_softmmu_ss} -diff --git a/target/arc/mmu-v6.c b/target/arc/mmu-v6.c -new file mode 100644 -index 0000000000..525ef640d6 ---- /dev/null -+++ b/target/arc/mmu-v6.c -@@ -0,0 +1,640 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Cupertino Miranda (cmiranda@synopsys.com) -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "mmu-v6.h" -+#include "target/arc/regs.h" -+#include "qemu/osdep.h" -+#include "cpu.h" -+#include "exec/exec-all.h" -+ -+#define LOAD_DATA_IN(ADDR) (address_space_ldq(((CPUState *) cpu)->as, ADDR, MEMTXATTRS_UNSPECIFIED, NULL)) -+ -+#define SET_MMU_EXCEPTION(ENV, N, C, P) { \ -+ ENV->mmu.exception.number = N; \ -+ ENV->mmu.exception.causecode = C; \ -+ ENV->mmu.exception.parameter = P; \ -+} -+ -+uint32_t mmu_ctrl; -+ -+static void disable_mmuv6(void) -+{ -+ mmu_ctrl &= 0xFFFFFFFE; -+} -+ -+#define MMU_ENABLED ((mmu_ctrl & 1) != 0) -+#define MMU_IN_USER_KERNEL_MODE ((mmu_ctrl >> 1) & 1) -+ -+int mmuv6_enabled(void) -+{ -+ return MMU_ENABLED; -+} -+ -+ -+uint32_t mmu_ttbcr; -+ -+#define MMU_TTBCR_TNSZ(I) ((mmu_ttbcr >> (I * 16)) & 0x1f) -+#define MMU_TTBCR_TNSH(I) (((mmu_ttbcr >> 4) >> (I * 16)) & 0x3) -+ -+#define MMU_TTBCR_A1 ((mmu_ttbcr >> 15) & 0x1) -+ -+/* -+static void init_mmu_ttbcr(void) -+{ -+ // TODO BE DONE -+} -+*/ -+ -+uint64_t mmu_rtp0; -+uint64_t mmu_rtp1; -+ -+uint64_t mmu_fault_status; -+ -+#define MASK_FOR_ROOT_ADDRESS(X) \ -+ (0x0000ffffffffffff & (~((1 << X) - 1))) -+ -+/* TODO: This is for MMU48 only. */ -+#define X_FOR_BCR_ZR(I) \ -+ (12) -+ -+// Grab Root Table Address for RTPN -+#define MMU_RTPN_ROOT_ADDRESS(VADDR, N) \ -+ (mmu_rtp##N & MASK_FOR_ROOT_ADDRESS(X_FOR_BCR_ZR(1))) -+ -+#define MMU_RTP0_ROOT_ADDRESS(VADDR) MMU_RTPN_ROOT_ADDRESS(VADDR, 0) -+#define MMU_RTP1_ROOT_ADDRESS(VADDR) MMU_RTPN_ROOT_ADDRESS(VADDR, 1) -+ -+/* TODO: This is for MMU48/52 only. */ -+#define MMU_RTPN_ASID(VADDR, N) \ -+ ((mmu_rtp##N >> 48) & 0xffff) -+ -+/* Table descriptors accessor macros */ -+ -+#define PTE_TBL_NEXT_LEVEL_TABLE_ADDRESS(PTE) (PTE & 0x0000fffffffff000) -+#define PTE_TBL_ATTRIBUTES(PTE) ((PTE & 0xf800000000000000) >> 59) -+ -+#define PTE_TBL_KERNEL_EXECUTE_NEVER_NEXT(PTE) (PTE_TBL_ATTRIBUTES(PTE) & 0x1) -+#define PTE_TBL_USER_EXECUTE_NEVER_NEXT(PTE) (PTE_TBL_ATTRIBUTES(PTE) & 0x2) -+ -+#define PTE_TBL_ACCESS_PERMITIONS_NEXT(PTE) ((PTE_TBL_ATTRIBUTES(PTE) & 0xc) >> 2) -+#define PTE_TBL_AP_NO_EFFECT(PTE) (PTE_TBL_ACCESS_PERMITIONS_NEXT(PTE) == 0) -+#define PTE_TBL_AP_NO_USER_MODE(PTE) (PTE_TBL_ACCESS_PERMITIONS_NEXT(PTE) == 1) -+#define PTE_TBL_AP_NO_WRITES(PTE) (PTE_TBL_ACCESS_PERMITIONS_NEXT(PTE) == 2) -+#define PTE_TBL_AP_NO_USER_READS_OR_WRITES(PTE) (PTE_TBL_ACCESS_PERMITIONS_NEXT(PTE) == 3) -+ -+/* Block descriptors accessor macros */ -+ -+#define PTE_BLK_LOWER_ATTRS(PTE) ((PTE >> 2) & ((1 << 10) - 1)) -+#define PTE_BLK_UPPER_ATTRS(PTE) ((PTE >> 51) & ((1 << 13) - 1)) -+ -+#define PTE_BLK_IS_READ_ONLY(PTE) ((PTE_BLK_LOWER_ATTRS(PTE) & 0x20) != 0) // bit 7 in PTE, 5 in attrs -+#define PTE_BLK_IS_KERNEL_ONLY(PTE) ((PTE_BLK_LOWER_ATTRS(PTE) & 0x10) == 0) // bit 6 in PTE, 4 in attrs -+#define PTE_BLK_AF(PTE) ((PTE_BLK_LOWER_ATTRS(PTE) & 0x100) != 0) // AF flag -+// We also need to verify MMU_CTRL.KU. Don't know what it means for now. :( -+ -+#define PTE_BLK_KERNEL_EXECUTE_NEVER(PTE) ((PTE_BLK_UPPER_ATTRS(PTE) & 0x4) != 0) -+#define PTE_BLK_USER_EXECUTE_NEVER(PTE) ((PTE_BLK_UPPER_ATTRS(PTE) & 0x8) != 0) -+ -+#define PTE_IS_BLOCK_DESCRIPTOR(PTE, LEVEL) \ -+ (((PTE & 0x3) == 1) && (LEVEL < (max_levels() - 1))) -+#define PTE_IS_PAGE_DESCRIPTOR(PTE, LEVEL) \ -+ ((PTE & 0x3) == 3 && (LEVEL == (max_levels() - 1))) -+#define PTE_IS_TABLE_DESCRIPTOR(PTE, LEVEL) \ -+ (!PTE_IS_PAGE_DESCRIPTOR(PTE, LEVEL) && ((PTE & 0x3) == 3)) -+ -+#define PTE_IS_INVALID(PTE, LEVEL) \ -+ (((PTE & 0x3) == 0) \ -+ || ((PTE & 0x3) != 3 && LEVEL == 0) \ -+ || ((PTE & 0x3) != 3 && LEVEL == 3)) -+ -+ -+enum MMUv6_TLBCOMMAND { -+ TLBInvalidateAll = 0x1, -+ TLBRead, -+ TLBInvalidateASID, -+ TLBInvalidateAddr, -+ TLBInvalidateRegion, -+ TLBInvalidateRegionASID -+}; -+ -+static void -+mmuv6_tlb_command(CPUARCState *env, enum MMUv6_TLBCOMMAND command) -+{ -+ CPUState *cs = env_cpu(env); -+ -+ switch(command) { -+ case TLBInvalidateAll: -+ case TLBInvalidateASID: -+ case TLBInvalidateAddr: -+ case TLBInvalidateRegion: -+ case TLBInvalidateRegionASID: -+ /* For now we flush all entries all the time. */ -+ qemu_log_mask(CPU_LOG_MMU, "\n[MMUV3] TLB Flush cmd %d\n\n", command); -+ tlb_flush(cs); -+ break; -+ -+ case TLBRead: -+ qemu_log_mask(LOG_UNIMP, "TLBRead command is not implemented for MMUv6."); -+ break; -+ } -+} -+ -+target_ulong -+arc_mmuv6_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data) -+{ -+ target_ulong reg = 0; -+ switch(aux_reg_detail->id) -+ { -+ case AUX_ID_mmuv6_build: -+ /* -+ * DTLB: 2 (8 entries) -+ * ITLB: 1 (4 entries) -+ * L2TLB: 0 (256 entries) -+ * TC: 0 (no translation cache) -+ * Type: 1 (MMUv48) -+ * Version: 6 (MMUv6) -+ */ -+ reg = (6 << 24) | (1 << 21) | (0 << 9) | (0 << 6) | (1 << 3) | 2; -+ break; -+ case AUX_ID_mmu_rtp0: -+ reg = mmu_rtp0; -+ qemu_log_mask(CPU_LOG_MMU, "\n[MMUV3] RTP0 read %lx\n\n", mmu_rtp0); -+ break; -+ case AUX_ID_mmu_rtp0hi: -+ reg = (mmu_rtp0 >> 32); -+ break; -+ case AUX_ID_mmu_rtp1: -+ reg = mmu_rtp1; -+ break; -+ case AUX_ID_mmu_rtp1hi: -+ reg = (mmu_rtp1 >> 32); -+ break; -+ case AUX_ID_mmu_ctrl: -+ reg = mmu_ctrl; -+ break; -+ case AUX_ID_mmu_ttbcr: -+ reg = mmu_ttbcr; -+ break; -+ case AUX_ID_mmu_fault_status: -+ reg = mmu_fault_status; -+ break; -+ default: -+ break; -+ } -+ return reg; -+} -+ -+void -+arc_mmuv6_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, -+ target_ulong val, void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ CPUState *cs = env_cpu(env); -+ -+ switch(aux_reg_detail->id) -+ { -+ case AUX_ID_mmu_rtp0: -+ qemu_log_mask(CPU_LOG_MMU, "\n[MMUV3] RTP0 update %lx ==> %lx\n\n", mmu_rtp0, val); -+ if (mmu_rtp0 != val) -+ tlb_flush(cs); -+ mmu_rtp0 = val; -+ break; -+ case AUX_ID_mmu_rtp0hi: -+ if ((mmu_rtp0 >> 32) != val) -+ tlb_flush(cs); -+ mmu_rtp0 &= ~0xffffffff00000000; -+ mmu_rtp0 |= (val << 32); -+ break; -+ case AUX_ID_mmu_rtp1: -+ if (mmu_rtp1 != val) -+ tlb_flush(cs); -+ mmu_rtp1 = val; -+ break; -+ case AUX_ID_mmu_rtp1hi: -+ if ((mmu_rtp1 >> 32) != val) -+ tlb_flush(cs); -+ mmu_rtp1 &= ~0xffffffff00000000; -+ mmu_rtp1 |= (val << 32); -+ break; -+ case AUX_ID_mmu_ctrl: -+ if (mmu_ctrl != val) -+ tlb_flush(cs); -+ mmu_ctrl = val; -+ qemu_log_mask(CPU_LOG_MMU, "mmu_ctrl = 0x%08lx\n", val); -+ break; -+ case AUX_ID_mmu_ttbcr: -+ mmu_ttbcr = val; -+ break; -+ case AUX_ID_tlbcommand: -+ mmuv6_tlb_command(env, val); -+ break; -+ case AUX_ID_mmu_fault_status: -+ assert(0); -+ break; -+ default: -+ break; -+ } -+} -+ -+#define ALL1_64BIT (0xffffffffffffffff) -+ -+static uint64_t -+root_ptr_for_vaddr(uint64_t vaddr, bool *valid) -+{ -+ /* TODO: This is only for MMUv48 */ -+ assert(MMU_TTBCR_TNSZ(0) == MMU_TTBCR_TNSZ(1) -+ && (MMU_TTBCR_TNSZ(0) == 16 || MMU_TTBCR_TNSZ(0) == 25)); -+ -+ if ((vaddr >> (64-MMU_TTBCR_TNSZ(0))) == 0) -+ return MMU_RTP0_ROOT_ADDRESS(vaddr); -+ -+ if ((vaddr >> (64-MMU_TTBCR_TNSZ(1))) == ((1 << MMU_TTBCR_TNSZ(1)) - 1)) -+ return MMU_RTP1_ROOT_ADDRESS(vaddr); -+ -+ *valid = false; -+ return 0; -+} -+ -+static int n_bits_on_level(int level) { return 9; } -+static int max_levels(void) { return 4; } -+static int vaddr_size(void) { return 48; } -+ -+#define V6_PAGE_OFFSET_MASK ((((target_ulong) 1) << remainig_bits) - 1) -+#define V6_PTE_PADDR_MASK (((((target_ulong) 1) << vaddr_size()) - 1) & (~V6_PAGE_OFFSET_MASK)) -+#define V6_PADDR(PTE, VADDR) \ -+ ((PTE & V6_PTE_PADDR_MASK) | (VADDR & V6_PAGE_OFFSET_MASK)) -+ -+#define RESTRICT_TBL_NO_USER_MODE (1 << 4) -+#define RESTRICT_TBL_NO_WRITE_ACCESS (1 << 3) -+#define RESTRICT_TBL_NO_USER_READ_WRITE_ACCESS (1 << 2) -+#define RESTRICT_TBL_USER_EXECUTE_NEVER (1 << 1) -+#define RESTRICT_TBL_KERNEL_EXECUTE_NEVER (1 << 0) -+ -+static bool -+protv_violation(struct CPUARCState *env, uint64_t pte, int level, int table_perm_overwride, enum mmu_access_type rwe) -+{ -+ bool in_kernel_mode = !(GET_STATUS_BIT(env->stat, Uf)); /* Read status for user mode. */ -+ bool trigger_prot_v = false; -+ -+ /* FIXME: user write access if Kr needs to trigger priv_v not prot v */ -+ if(rwe == MMU_MEM_WRITE && PTE_BLK_IS_READ_ONLY(pte)) { -+ trigger_prot_v = true; -+ } -+ -+ /* TODO: Isn't it a little bit tool late for this guard check? */ -+ if(PTE_IS_BLOCK_DESCRIPTOR(pte, level) -+ || PTE_IS_PAGE_DESCRIPTOR(pte, level)) -+ { -+ if (in_kernel_mode == true) { -+ if (rwe == MMU_MEM_FETCH && -+ (PTE_BLK_KERNEL_EXECUTE_NEVER(pte) || -+ (table_perm_overwride & -+ RESTRICT_TBL_KERNEL_EXECUTE_NEVER))) { -+ trigger_prot_v = true; -+ } -+ } else { -+ if((rwe == MMU_MEM_READ || rwe == MMU_MEM_WRITE) -+ && (table_perm_overwride & RESTRICT_TBL_NO_USER_READ_WRITE_ACCESS) != 0) { -+ trigger_prot_v = true; -+ } -+ -+ if (rwe == MMU_MEM_FETCH && -+ (PTE_BLK_USER_EXECUTE_NEVER(pte) || -+ (table_perm_overwride & RESTRICT_TBL_USER_EXECUTE_NEVER))) { -+ trigger_prot_v = true; -+ } -+ -+ if((table_perm_overwride & RESTRICT_TBL_NO_USER_MODE) != 0) { -+ trigger_prot_v = true; -+ } -+ -+ if(PTE_BLK_IS_KERNEL_ONLY(pte)) { -+ trigger_prot_v = true; -+ } -+ } -+ } -+ -+ return trigger_prot_v; -+} -+ -+static int -+get_prot_for_pte(struct CPUARCState *env, uint64_t pte, -+ int overwrite_permitions) -+{ -+ int ret = PAGE_READ | PAGE_WRITE | PAGE_EXEC; -+ -+ bool in_kernel_mode = !(GET_STATUS_BIT(env->stat, Uf)); /* Read status for user mode. */ -+ -+ if(in_kernel_mode -+ && ((overwrite_permitions & RESTRICT_TBL_KERNEL_EXECUTE_NEVER) != 0 -+ || PTE_BLK_KERNEL_EXECUTE_NEVER(pte))) { -+ ret &= ~PAGE_EXEC; -+ } -+ -+ if(!in_kernel_mode -+ && ((overwrite_permitions & RESTRICT_TBL_USER_EXECUTE_NEVER) != 0 -+ || PTE_BLK_USER_EXECUTE_NEVER(pte))) { -+ ret &= ~PAGE_EXEC; -+ } -+ -+ if(!in_kernel_mode -+ && ((overwrite_permitions & RESTRICT_TBL_NO_USER_MODE) != 0 -+ || PTE_BLK_IS_KERNEL_ONLY(pte))) { -+ ret &= ~PAGE_WRITE; -+ ret &= ~PAGE_READ; -+ ret &= ~PAGE_EXEC; -+ } -+ -+ if((overwrite_permitions & RESTRICT_TBL_NO_WRITE_ACCESS) != 0) { -+ ret &= ~PAGE_WRITE; -+ } -+ -+ if(!in_kernel_mode -+ && (overwrite_permitions & RESTRICT_TBL_NO_USER_READ_WRITE_ACCESS) != 0) { -+ ret &= ~PAGE_WRITE; -+ ret &= ~PAGE_READ; -+ } -+ -+ if (PTE_BLK_IS_READ_ONLY(pte)) { -+ ret &= ~PAGE_WRITE; -+ } -+ -+ if ((!in_kernel_mode && PTE_BLK_USER_EXECUTE_NEVER(pte)) || -+ (in_kernel_mode && PTE_BLK_KERNEL_EXECUTE_NEVER(pte))) { -+ ret &= ~PAGE_EXEC; -+ } -+ -+ return ret; -+} -+ -+static target_ulong -+page_table_traverse(struct CPUARCState *env, -+ target_ulong vaddr, enum mmu_access_type rwe, -+ int *prot) -+{ -+ bool found_block_descriptor = false; -+ uint64_t pte, pte_addr; -+ int l; -+ int overwrite_permitions = 0; -+ bool valid_root = true; -+ uint64_t root = root_ptr_for_vaddr(vaddr, &valid_root); -+ ARCCPU *cpu = env_archcpu (env); -+ unsigned char remainig_bits = vaddr_size(); -+ -+ qemu_log_mask(CPU_LOG_MMU, "[MMUV3] [PC %lx] PageWalking for %lx [%s]\n", env->pc, vaddr, RWE_STRING(rwe)); -+ -+ if(valid_root == false) { -+ if(rwe == MMU_MEM_FETCH || rwe == MMU_MEM_IRRELEVANT_TYPE) { -+ SET_MMU_EXCEPTION(env, EXCP_IMMU_FAULT, 0x00, 0x00); -+ return -1; -+ } else if(rwe == MMU_MEM_READ || rwe == MMU_MEM_WRITE) { -+ SET_MMU_EXCEPTION(env, EXCP_DMMU_FAULT, CAUSE_CODE(rwe), 0x00); -+ return -1; -+ } -+ } -+ -+ for(l = 0; l < max_levels(); l++) { -+ unsigned char bits_to_compare = n_bits_on_level(l); -+ remainig_bits = remainig_bits - bits_to_compare; -+ unsigned offset = (vaddr >> remainig_bits) & ((1< %lx\n", l, offset, pte_addr, pte); -+ -+ if(PTE_IS_INVALID(pte, l)) { -+ qemu_log_mask(CPU_LOG_MMU, "[MMUV3] PTE seems invalid\n"); -+ -+ mmu_fault_status = (l & 0x7); -+ if(rwe == MMU_MEM_FETCH || rwe == MMU_MEM_IRRELEVANT_TYPE) { -+ SET_MMU_EXCEPTION(env, EXCP_IMMU_FAULT, 0x00, 0x00); -+ return -1; -+ } else if(rwe == MMU_MEM_READ || rwe == MMU_MEM_WRITE) { -+ SET_MMU_EXCEPTION(env, EXCP_DMMU_FAULT, CAUSE_CODE(rwe), 0x00); -+ return -1; -+ } -+ } -+ -+ -+ if(PTE_IS_BLOCK_DESCRIPTOR(pte, l) || PTE_IS_PAGE_DESCRIPTOR(pte, l)) { -+ if(PTE_BLK_AF(pte) != 0) { -+ found_block_descriptor = true; -+ break; -+ } else { -+ qemu_log_mask(CPU_LOG_MMU, "[MMUV3] PTE AF is not set\n"); -+ mmu_fault_status = (l & 0x7); -+ if(rwe == MMU_MEM_FETCH || rwe == MMU_MEM_IRRELEVANT_TYPE) { -+ SET_MMU_EXCEPTION(env, EXCP_IMMU_FAULT, 0x10, 0x00); -+ return -1; -+ } else if(rwe == MMU_MEM_READ || rwe == MMU_MEM_WRITE) { -+ SET_MMU_EXCEPTION(env, EXCP_DMMU_FAULT, 0x10 | CAUSE_CODE(rwe), 0x00); -+ return -1; -+ } -+ } -+ } -+ -+ if(PTE_IS_TABLE_DESCRIPTOR(pte, l)) { -+ if(PTE_TBL_KERNEL_EXECUTE_NEVER_NEXT(pte)) { -+ overwrite_permitions |= RESTRICT_TBL_KERNEL_EXECUTE_NEVER; -+ } -+ if(PTE_TBL_USER_EXECUTE_NEVER_NEXT(pte)) { -+ overwrite_permitions |= RESTRICT_TBL_USER_EXECUTE_NEVER; -+ } -+ if(PTE_TBL_AP_NO_USER_MODE(pte)) { -+ overwrite_permitions |= RESTRICT_TBL_NO_USER_MODE; -+ } -+ if(PTE_TBL_AP_NO_WRITES(pte)) { -+ overwrite_permitions |= RESTRICT_TBL_NO_WRITE_ACCESS; -+ } -+ if(PTE_TBL_AP_NO_USER_READS_OR_WRITES(pte)) { -+ overwrite_permitions |= RESTRICT_TBL_NO_USER_READ_WRITE_ACCESS; -+ } -+ } -+ -+ if(PTE_IS_INVALID(pte, l)) { -+ if(rwe == MMU_MEM_FETCH || rwe == MMU_MEM_IRRELEVANT_TYPE) { -+ SET_MMU_EXCEPTION(env, EXCP_IMMU_FAULT, 0x00, 0x00); -+ return -1; -+ } else if(rwe == MMU_MEM_READ || rwe == MMU_MEM_WRITE) { -+ SET_MMU_EXCEPTION(env, EXCP_DMMU_FAULT, CAUSE_CODE(rwe), 0x00); -+ return -1; -+ } -+ } -+ -+ root = PTE_TBL_NEXT_LEVEL_TABLE_ADDRESS(pte); -+ } -+ -+ if(found_block_descriptor) { -+ -+ if(protv_violation(env, pte, l, overwrite_permitions, rwe)) { -+ qemu_log_mask(CPU_LOG_MMU, "\n[MMUV3] [PC %lx] PTE Protection violation: vaddr %lx pte [addr %lx val %lx]\n", env->pc, vaddr, pte_addr, pte); -+ found_block_descriptor = false; -+ SET_MMU_EXCEPTION(env, EXCP_PROTV, CAUSE_CODE(rwe), 0x08); -+ return -1; -+ } -+ -+ if(prot != NULL) { -+ *prot = get_prot_for_pte(env, pte, overwrite_permitions); -+ } -+ return V6_PADDR(pte, vaddr); -+ } -+ return -1; -+} -+ -+#undef PAGE_OFFSET_MASK -+#undef PTE_PADDR_MASK -+#undef PADDR -+ -+static target_ulong -+arc_mmuv6_translate(struct CPUARCState *env, -+ target_ulong vaddr, enum mmu_access_type rwe, -+ int *prot) -+{ -+ target_ulong paddr; -+ -+ /* This is really required. Fail in non singlestep without in_asm. */ -+ env->mmu.exception.number = EXCP_NO_EXCEPTION; -+ -+ if(!MMU_ENABLED) { -+ paddr = vaddr; -+ } -+ -+ paddr = (target_ulong) page_table_traverse(env, vaddr, rwe, prot); -+ -+ // TODO: Check if address is valid -+ // Still need to know what it means ... -+ -+ return paddr; -+} -+ -+typedef enum { -+ DIRECT_ACTION, -+ MMU_ACTION, -+} ACTION; -+ -+static int mmuv6_decide_action(const struct CPUARCState *env, -+ target_ulong addr, -+ int mmu_idx) -+{ -+ // TODO: Remove this later -+ //if((addr >= 0x80000000) && (addr < 0x90000000)) -+ // return DIRECT_ACTION; -+ -+ if (MMU_ENABLED) -+ return MMU_ACTION; -+ else -+ return DIRECT_ACTION; -+} -+ -+void arc_mmu_init(CPUARCState *env) -+{ -+ return; -+} -+ -+ -+#ifndef CONFIG_USER_ONLY -+ -+static void QEMU_NORETURN raise_mem_exception( -+ CPUState *cs, target_ulong addr, uintptr_t host_pc, -+ int32_t excp_idx, uint8_t excp_cause_code, uint8_t excp_param) -+{ -+ CPUARCState *env = &(ARC_CPU(cs)->env); -+ if (excp_idx != EXCP_IMMU_FAULT) { -+ cpu_restore_state(cs, host_pc, true); -+ } -+ -+ env->efa = addr; -+ env->eret = env->pc; -+ env->erbta = env->bta; -+ -+ cs->exception_index = excp_idx; -+ env->causecode = excp_cause_code; -+ env->param = excp_param; -+ cpu_loop_exit(cs); -+} -+ -+/* Softmmu support function for MMU. */ -+bool arc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, -+ MMUAccessType access_type, int mmu_idx, -+ bool probe, uintptr_t retaddr) -+{ -+ /* TODO: this rwe should go away when the TODO below is done */ -+ enum mmu_access_type rwe = (char) access_type; -+ ARCCPU *cpu = ARC_CPU(cs); -+ CPUARCState *env = &(cpu->env); -+ int prot; -+ -+ int action = mmuv6_decide_action(env, address, mmu_idx); -+ -+ switch (action) { -+ case DIRECT_ACTION: -+ tlb_set_page(cs, address & PAGE_MASK, address & PAGE_MASK, -+ PAGE_READ | PAGE_WRITE | PAGE_EXEC, -+ mmu_idx, TARGET_PAGE_SIZE); -+ break; -+ case MMU_ACTION: { -+ /* -+ * TODO: these lines must go inside arc_mmu_translate and it -+ * should only signal a failure or success --> generate an -+ * exception or not -+ */ -+ -+ target_ulong paddr; -+ paddr = arc_mmuv6_translate(env, address, rwe, &prot); -+ -+ if ((enum exception_code_list) env->mmu.exception.number != EXCP_NO_EXCEPTION) { -+ if (probe) { -+ return false; -+ } -+ const struct mmuv6_exception *mmu_excp = &(env->mmu.exception); -+ raise_mem_exception(cs, address, retaddr, -+ mmu_excp->number, mmu_excp->causecode, mmu_excp->parameter); -+ } -+ else { -+ tlb_set_page(cs, address, paddr & PAGE_MASK, prot, -+ mmu_idx, TARGET_PAGE_SIZE); -+ } -+ break; -+ } -+ default: -+ g_assert_not_reached(); -+ } -+ -+ return true; -+} -+#endif /* CONFIG_USER_ONLY */ -+ -+hwaddr arc_mmu_debug_translate(CPUARCState *env, vaddr addr) -+{ -+ if(mmuv6_enabled()) { -+ return arc_mmuv6_translate(env, addr, MMU_MEM_IRRELEVANT_TYPE, NULL); -+ } else { -+ return addr; -+ } -+} -+ -+void arc_mmu_disable(CPUARCState *env) { -+ disable_mmuv6(); -+} -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/mmu-v6.h b/target/arc/mmu-v6.h -new file mode 100644 -index 0000000000..7745fe2139 ---- /dev/null -+++ b/target/arc/mmu-v6.h -@@ -0,0 +1,36 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Cupertino Miranda (cmiranda@synopsys.com) -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef ARC64_MMUV3_H -+#define ARC64_MMUV3_H -+ -+#include "target/arc/regs.h" -+ -+struct arc_mmuv6 { -+ struct mmuv6_exception { -+ int32_t number; -+ uint8_t causecode; -+ uint8_t parameter; -+ } exception; -+}; -+ -+int mmuv6_enabled(void); -+ -+#endif /* ARC64_MMUV3_H */ -diff --git a/target/arc/mmu.c b/target/arc/mmu.c -new file mode 100644 -index 0000000000..f79c910d80 ---- /dev/null -+++ b/target/arc/mmu.c -@@ -0,0 +1,805 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "mmu.h" -+#include "target/arc/regs.h" -+#include "qemu/osdep.h" -+#include "cpu.h" -+#include "exec/exec-all.h" -+ -+target_ulong -+arc_mmu_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ struct arc_mmu *mmu = &env->mmu; -+ uint32_t reg = 0; -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_mmu_build: -+ /* -+ * For now hardcode the TLB geometry and canonical page sizes -+ * MMUv4: 2M Super Page, 8k Page, 4 way set associative, -+ * 1K entries (256x4), 4 uITLB, 8 uDTLB -+ */ -+ reg = 0x04e21a4a; -+ break; -+ case AUX_ID_tlbindex: -+ reg = mmu->tlbindex; -+ break; -+ case AUX_ID_tlbpd0: -+ reg = mmu->tlbpd0; -+ break; -+ case AUX_ID_tlbpd1: -+ reg = mmu->tlbpd1; -+ break; -+ case AUX_ID_tlbpd1_hi: -+ reg = mmu->tlbpd1_hi; -+ break; -+ case AUX_ID_scratch_data0: -+ reg = mmu->scratch_data0; -+ break; -+ case AUX_ID_tlbcommand: -+ reg = mmu->tlbcmd; -+ break; -+ case AUX_ID_pid: -+ reg = (mmu->enabled << 31) | mmu->pid_asid; -+ break; -+ case AUX_ID_sasid0: -+ reg = mmu->sasid0; -+ break; -+ case AUX_ID_sasid1: -+ reg = mmu->sasid1; -+ break; -+ default: -+ break; -+ } -+ -+ return reg; -+} -+ -+void -+arc_mmu_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, -+ target_ulong val, void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ CPUState *cs = env_cpu(env); -+ struct arc_mmu *mmu = &env->mmu; -+ -+ switch (aux_reg_detail->id) { -+ /* AUX_ID_tlbcommand is more involved and handled seperately */ -+ case AUX_ID_tlbindex: -+ mmu->tlbindex = val; -+ break; -+ case AUX_ID_tlbpd0: -+ mmu->tlbpd0 = val; -+ break; -+ case AUX_ID_tlbpd1: -+ mmu->tlbpd1 = val; -+ break; -+ case AUX_ID_tlbpd1_hi: -+ mmu->tlbpd1_hi = val; -+ break; -+ case AUX_ID_scratch_data0: -+ mmu->scratch_data0 = val; -+ break; -+ case AUX_ID_pid: -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] Writing PID_ASID with value 0x" TARGET_FMT_lx -+ " at 0x" TARGET_FMT_lx "\n", -+ val, env->pc); -+ mmu->enabled = (val >> 31); -+ mmu->pid_asid = val & 0xff; -+ tlb_flush(cs); -+ break; -+ case AUX_ID_sasid0: -+ mmu->sasid0 = val; -+ break; -+ case AUX_ID_sasid1: -+ mmu->sasid1 = val; -+ break; -+ default: -+ break; -+ } -+} -+ -+/* vaddr can't have top bit */ -+#define VPN(addr) ((addr) & (PAGE_MASK & (~0x80000000))) -+#define PFN(addr) ((addr) & PAGE_MASK) -+ -+static void -+arc_mmu_debug_tlb_for_set(CPUARCState *env, int set) -+{ -+ int j; -+ bool set_printed = false; -+ -+ for (j = 0; j < N_WAYS; j++) { -+ struct arc_tlb_e *tlb = &env->mmu.nTLB[set][j]; -+ -+ if ((tlb->pd0 & PD0_V) != 0) { -+ if (set_printed == false) { -+ printf("set %d\n", set); -+ set_printed = true; -+ } -+ if (set_printed == true) { -+ printf(" way %d\n", j); -+ } -+ printf(" tlppd0: %08x: vaddr=\t%08x %s %s%s asid=%02x\n", -+ tlb->pd0, VPN(tlb->pd0), -+ (char *) ((tlb->pd0 & PD0_SZ) != 0 ? "sz1" : "sz0"), -+ (char *) ((tlb->pd0 & PD0_V) != 0 ? "V" : ""), -+ (char *) ((tlb->pd0 & PD0_G) != 0 ? "g" : ""), -+ tlb->pd0 & PD0_ASID); -+ -+ printf(" tlppd1: %08x: paddr=\t%08x k:%s%s%s u:%s%s%s f:%s\n", -+ (unsigned int) tlb->pd1, (unsigned int) PFN(tlb->pd1), -+ (char *) ((tlb->pd1 & PD1_RK) != 0 ? "R" : "r"), -+ (char *) ((tlb->pd1 & PD1_WK) != 0 ? "W" : "w"), -+ (char *) ((tlb->pd1 & PD1_XK) != 0 ? "X" : "x"), -+ (char *) ((tlb->pd1 & PD1_RU) != 0 ? "R" : "r"), -+ (char *) ((tlb->pd1 & PD1_WU) != 0 ? "W" : "w"), -+ (char *) ((tlb->pd1 & PD1_XU) != 0 ? "X" : "x"), -+ (char *) ((tlb->pd1 & PD1_FC) != 0 ? "C" : "c")); -+ } -+ } -+} -+ -+void -+arc_mmu_debug_tlb(CPUARCState *env) -+{ -+ int i; -+ -+ for (i = 0; i < N_SETS; i++) { -+ arc_mmu_debug_tlb_for_set(env, i); -+ } -+} -+ -+void -+arc_mmu_debug_tlb_for_vaddr(CPUARCState *env, uint32_t vaddr) -+{ -+ uint32_t set = (vaddr >> PAGE_SHIFT) & (N_SETS - 1); -+ arc_mmu_debug_tlb_for_set(env, set); -+} -+ -+ -+static struct arc_tlb_e * -+arc_mmu_get_tlb_at_index(uint32_t index, struct arc_mmu *mmu) -+{ -+ uint32_t set = index / N_WAYS; -+ uint32_t bank = index % N_WAYS; -+ return &mmu->nTLB[set][bank]; -+} -+ -+static inline bool -+match_sasid(struct arc_tlb_e *tlb, struct arc_mmu *mmu) -+{ -+ /* Match to a shared library. */ -+ uint8_t position = tlb->pd0 & PD0_ASID_MATCH; -+ uint64_t pos = 1ULL << position; -+ uint64_t sasid = ((uint64_t) mmu->sasid1 << 32) | mmu->sasid0; -+ if ((pos & sasid) == 0) { -+ return false; -+ } -+ return true; -+} -+ -+static struct arc_tlb_e * -+arc_mmu_lookup_tlb(uint32_t vaddr, uint32_t compare_mask, struct arc_mmu *mmu, -+ int *num_finds, uint32_t *index) -+{ -+ struct arc_tlb_e *ret = NULL; -+ uint32_t set = (vaddr >> PAGE_SHIFT) & (N_SETS - 1); -+ struct arc_tlb_e *tlb = &mmu->nTLB[set][0]; -+ int w; -+ -+ if (num_finds != NULL) { -+ *num_finds = 0; -+ } -+ -+ bool general_match = true; -+ for (w = 0; w < N_WAYS; w++, tlb++) { -+ uint32_t match = vaddr & compare_mask; -+ uint32_t final_compare_mask = compare_mask; -+ -+ if ((tlb->pd0 & PD0_G) == 0) { -+ if ((tlb->pd0 & PD0_S) != 0) { -+ /* Match to a shared library. */ -+ if (match_sasid(tlb, mmu) == false) { -+ general_match = false; -+ } -+ } else { -+ /* Match to a process. */ -+ match |= mmu->pid_asid & PD0_PID_MATCH; -+ final_compare_mask |= PD0_PID_MATCH; -+ } -+ } -+ -+ if (match == (tlb->pd0 & final_compare_mask) && general_match) { -+ ret = tlb; -+ if (num_finds != NULL) { -+ *num_finds += 1; -+ } -+ if (index != NULL) { -+ *index = (set * N_WAYS) + w; -+ } -+ } -+ } -+ -+ if (ret == NULL) { -+ uint32_t way = mmu->way_sel[set]; -+ ret = &mmu->nTLB[set][way]; -+ -+ /* TODO: Replace by something more significant. */ -+ if (index != NULL) { -+ *index = (set * N_WAYS) + way; -+ } -+ -+ mmu->way_sel[set] = (mmu->way_sel[set] + 1) & (N_WAYS - 1); -+ } -+ -+ return ret; -+} -+ -+/* -+ * TLB Insert/Delete triggered by writing the cmd to TLBCommand Aux -+ * - Requires PD0 and PD1 be setup apriori -+ */ -+void -+arc_mmu_aux_set_tlbcmd(const struct arc_aux_reg_detail *aux_reg_detail, -+ target_ulong val, void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ CPUState *cs = env_cpu(env); -+ struct arc_mmu *mmu = &env->mmu; -+ uint32_t pd0 = mmu->tlbpd0; -+ uint32_t pd1 = mmu->tlbpd1; -+ int num_finds = 4; -+ uint32_t index; -+ struct arc_tlb_e *tlb; -+ -+ mmu->tlbcmd = val; -+ uint32_t matching_mask = (PD0_VPN | PD0_SZ | PD0_G | PD0_S | PD0_ASID); -+ -+ if ((pd0 & PD0_G) != 0) { -+ /* -+ * When Global do not check for asid match. -+ */ -+ matching_mask &= ~(PD0_S | PD0_ASID); -+ } -+ -+ /* -+ * NOTE: Write and WriteNI commands are the same because we do not model -+ * uTLBs in QEMU. -+ */ -+ if (val == TLB_CMD_WRITE || val == TLB_CMD_WRITENI) { -+ /* -+ * TODO: Include index verification. We are always clearing the index as -+ * we assume it is always valid. -+ */ -+ tlb = arc_mmu_get_tlb_at_index(mmu->tlbindex & TLBINDEX_INDEX, mmu); -+ tlb->pd0 = mmu->tlbpd0; -+ tlb->pd1 = mmu->tlbpd1; -+ -+ /* -+ * don't try to optimize this: upon ASID rollover the entire TLB is -+ * unconditionally flushed for any ASID -+ */ -+ tlb_flush(cs); -+ } -+ if (val == TLB_CMD_READ) { -+ /* -+ * TODO: Include index verification. We are always clearing the index as -+ * we assume it is always valid. -+ */ -+ -+ tlb = arc_mmu_get_tlb_at_index(mmu->tlbindex & TLBINDEX_INDEX, mmu); -+ mmu->tlbpd0 = tlb->pd0; -+ mmu->tlbpd1 = tlb->pd1; -+ -+ mmu->tlbindex &= ~(TLBINDEX_E | TLBINDEX_RC); -+ } -+ if (val == TLB_CMD_DELETE || val == TLB_CMD_INSERT) { -+ tlb_flush_page_by_mmuidx(cs, VPN(pd0), 3); -+ -+ if ((pd0 & PD0_G) != 0) { -+ /* -+ * When Global do not check for asid match. -+ */ -+ matching_mask &= ~(PD0_S | PD0_ASID); -+ } -+ -+ matching_mask &= (VPN(PD0_VPN) | (~PD0_VPN)) ; -+ tlb = arc_mmu_lookup_tlb(pd0, -+ matching_mask | PD0_V, -+ &env->mmu, &num_finds, &index); -+ -+ if (num_finds == 0) { -+ mmu->tlbindex = 0x80000000; /* No entry to delete */ -+ } else if (num_finds == 1) { -+ mmu->tlbindex = index; /* Entry is deleted set index */ -+ tlb->pd0 &= ~PD0_V; -+ num_finds--; -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] Delete at 0x" TARGET_FMT_lx -+ ", pd0 = 0x%08x, pd1 = 0x%08x\n", -+ env->pc, tlb->pd0, tlb->pd1); -+ } else { -+ while (num_finds > 0) { -+ tlb->pd0 &= ~PD0_V; -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] Delete at 0x" TARGET_FMT_lx -+ ", pd0 = 0x%08x, pd1 = 0x%08x\n", -+ env->pc, tlb->pd0, tlb->pd1); -+ tlb = arc_mmu_lookup_tlb(pd0, -+ (VPN(PD0_VPN) | PD0_V -+ | PD0_SZ | PD0_G | PD0_S), -+ mmu, &num_finds, NULL); -+ } -+ } -+ } -+ -+ if (val == TLB_CMD_INSERT) { -+ if ((pd0 & PD0_V) == 0) { -+ mmu->tlbindex = 0x80000000; -+ } else { -+ tlb->pd0 = pd0; -+ tlb->pd1 = pd1; -+ -+ /* Set index for latest inserted element. */ -+ mmu->tlbindex |= index; -+ -+ /* TODO: More verifications needed. */ -+ -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] Insert at 0x" TARGET_FMT_lx -+ ", PID = %d, VPN = 0x%08x, " -+ "PFN = 0x%08x, pd0 = 0x%08x, pd1 = 0x%08x\n", -+ env->pc, -+ pd0 & 0xff, -+ VPN(pd0), PFN(pd1), -+ pd0, pd1); -+ } -+ } -+ -+ /* NOTE: We do not implement IVUTLB as we do not model uTLBs. */ -+ assert(val == TLB_CMD_INSERT -+ || val == TLB_CMD_DELETE -+ || val == TLB_CMD_WRITE -+ || val == TLB_CMD_READ -+ || val == TLB_CMD_WRITENI -+ || val == TLB_CMD_IVUTLB -+ ); -+} -+ -+/* Function to verify if we have permission to use MMU TLB entry. */ -+static bool -+arc_mmu_have_permission(CPUARCState *env, -+ struct arc_tlb_e *tlb, -+ enum mmu_access_type type) -+{ -+ bool ret = false; -+ /* Read status for user mode. */ -+ bool in_kernel_mode = !GET_STATUS_BIT(env->stat, Uf); -+ switch (type) { -+ case MMU_MEM_READ: -+ ret = in_kernel_mode ? tlb->pd1 & PD1_RK : tlb->pd1 & PD1_RU; -+ break; -+ case MMU_MEM_WRITE: -+ ret = in_kernel_mode ? tlb->pd1 & PD1_WK : tlb->pd1 & PD1_WU; -+ break; -+ case MMU_MEM_FETCH: -+ ret = in_kernel_mode ? tlb->pd1 & PD1_XK : tlb->pd1 & PD1_XU; -+ break; -+ case MMU_MEM_ATTOMIC: -+ ret = in_kernel_mode ? tlb->pd1 & PD1_RK : tlb->pd1 & PD1_RU; -+ ret = ret & (in_kernel_mode ? tlb->pd1 & PD1_WK : tlb->pd1 & PD1_WU); -+ break; -+ case MMU_MEM_IRRELEVANT_TYPE: -+ ret = true; -+ break; -+ } -+ -+ return ret; -+} -+ -+#define SET_MMU_EXCEPTION(ENV, N, C, P) { \ -+ ENV->mmu.exception.number = N; \ -+ ENV->mmu.exception.causecode = C; \ -+ ENV->mmu.exception.parameter = P; \ -+} -+ -+/* Translation function to get physical address from virtual address. */ -+static uint32_t -+arc_mmu_translate(struct CPUARCState *env, -+ uint32_t vaddr, enum mmu_access_type rwe, -+ uint32_t *index) -+{ -+ struct arc_mmu *mmu = &(env->mmu); -+ struct arc_tlb_e *tlb = NULL; -+ int num_matching_tlb = 0; -+ -+ SET_MMU_EXCEPTION(env, EXCP_NO_EXCEPTION, 0, 0); -+ -+ if (rwe != MMU_MEM_IRRELEVANT_TYPE -+ && GET_STATUS_BIT(env->stat, Uf) != 0 && vaddr >= 0x80000000) { -+ goto protv_exception; -+ } -+ -+ /* -+ * Check that we are not addressing an address above 0x80000000. -+ * Return the same address in that case. -+ */ -+ if ((vaddr >= 0x80000000) || mmu->enabled == false) { -+ return vaddr; -+ } -+ -+ if (rwe != MMU_MEM_IRRELEVANT_TYPE) { -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] Translate at 0x" TARGET_FMT_lx -+ ", vaddr 0x%08x, pid %d, rwe = %s\n", -+ env->pc, vaddr, mmu->pid_asid, RWE_STRING(rwe)); -+ } -+ -+ uint32_t match_pd0 = (VPN(vaddr) | PD0_V); -+ tlb = arc_mmu_lookup_tlb(match_pd0, (VPN(PD0_VPN) | PD0_V), mmu, -+ &num_matching_tlb, index); -+ -+ /* -+ * Check for multiple matches in nTLB, and return machine check -+ * exception. -+ */ -+ if (num_matching_tlb > 1) { -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] Machine Check exception. num_matching_tlb = %d\n", -+ num_matching_tlb); -+ SET_MMU_EXCEPTION(env, EXCP_MACHINE_CHECK, 0x01, 0x00); -+ return 0; -+ } -+ -+ -+ bool match = true; -+ -+ if (num_matching_tlb == 0) { -+ match = false; -+ } -+ -+ /* Check if entry if related to this address */ -+ if (VPN(vaddr) != VPN(tlb->pd0) || (tlb->pd0 & PD0_V) == 0) { -+ /* Call the interrupt. */ -+ match = false; -+ } -+ -+ if (match == true) { -+ if ((tlb->pd0 & PD0_G) == 0) { -+ if ((tlb->pd0 & PD0_S) != 0) { -+ /* Match to a shared library. */ -+ if (match_sasid(tlb, mmu) == false) { -+ match = false; -+ } -+ } else if ((tlb->pd0 & PD0_PID_MATCH) != -+ (mmu->pid_asid & PD0_PID_MATCH)) { -+ /* Match to a process. */ -+ match = false; -+ } -+ } -+ } -+ -+ if (match == true && !arc_mmu_have_permission(env, tlb, rwe)) { -+ protv_exception: -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] ProtV exception at 0x" TARGET_FMT_lx -+ " for 0x%08x. rwe = %s, " -+ "tlb->pd0 = %08x, tlb->pd1 = %08x\n", -+ env->pc, -+ vaddr, -+ RWE_STRING(rwe), -+ tlb->pd0, tlb->pd1); -+ -+ SET_MMU_EXCEPTION(env, EXCP_PROTV, CAUSE_CODE(rwe), 0x08); -+ return 0; -+ } -+ -+ if (match == true) { -+ if (rwe != MMU_MEM_IRRELEVANT_TYPE) { -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] Translated to 0x%08x, pd0=0x%08x, pd1=0x%08x\n", -+ (tlb->pd1 & PAGE_MASK) | (vaddr & (~PAGE_MASK)), -+ tlb->pd0, tlb->pd1); -+ } -+ return (tlb->pd1 & PAGE_MASK) | (vaddr & (~PAGE_MASK)); -+ } else { -+ if (rwe != MMU_MEM_IRRELEVANT_TYPE) { -+ /* To remove eventually, just fail safe to check kernel. */ -+ if (mmu->sasid0 != 0 || mmu->sasid1 != 0) { -+ assert(0); -+ } else { -+ mmu->tlbpd0 = (vaddr & (VPN(PD0_VPN))) -+ | PD0_V | (mmu->pid_asid & PD0_ASID); -+ } -+ if (rwe == MMU_MEM_FETCH) { -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] TLB_MissI exception at 0x" -+ TARGET_FMT_lx ". rwe = %s, " -+ "vaddr = %08x, tlb->pd0 = %08x, tlb->pd1 = %08x\n", -+ env->pc, -+ RWE_STRING(rwe), -+ vaddr, tlb->pd0, tlb->pd1); -+ SET_MMU_EXCEPTION(env, EXCP_TLB_MISS_I, 0x00, 0x00); -+ } else { -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] TLB_MissD exception at 0x" TARGET_FMT_lx -+ ". rwe = %s, " -+ "vaddr = %08x, tlb->pd0 = %08x, tlb->pd1 = %08x\n", -+ env->pc, -+ RWE_STRING(rwe), -+ vaddr, tlb->pd0, tlb->pd1); -+ SET_MMU_EXCEPTION(env, EXCP_TLB_MISS_D, CAUSE_CODE(rwe), -+ 0x00); -+ } -+ } else if (rwe != MMU_MEM_IRRELEVANT_TYPE) { -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MMU] Failed to translate to 0x%08x\n", -+ vaddr); -+ } -+ return 0; -+ } -+} -+ -+uint32_t arc_mmu_page_address_for(uint32_t vaddr) -+{ -+ uint32_t ret = VPN(vaddr); -+ if (vaddr >= 0x80000000) { -+ ret |= 0x80000000; -+ } -+ return ret; -+} -+ -+static int -+arc_mmu_get_prot_for_index(uint32_t index, CPUARCState *env) -+{ -+ struct arc_tlb_e *tlb; -+ int ret = 0; -+ /* Read status for user mode. */ -+ bool in_kernel_mode = !GET_STATUS_BIT(env->stat, Uf); -+ -+ tlb = arc_mmu_get_tlb_at_index( -+ index, -+ &env->mmu); -+ -+ if ((in_kernel_mode && (tlb->pd1 & PD1_RK) != 0) -+ || (!in_kernel_mode && (tlb->pd1 & PD1_RU) != 0)) { -+ ret |= PAGE_READ; -+ } -+ -+ if ((in_kernel_mode && (tlb->pd1 & PD1_WK) != 0) -+ || (!in_kernel_mode && (tlb->pd1 & PD1_WU) != 0)) { -+ ret |= PAGE_WRITE; -+ } -+ -+ if ((in_kernel_mode && (tlb->pd1 & PD1_XK) != 0) -+ || (!in_kernel_mode && (tlb->pd1 & PD1_XU) != 0)) { -+ ret |= PAGE_EXEC; -+ } -+ -+ return ret; -+} -+ -+static void QEMU_NORETURN raise_mem_exception( -+ CPUState *cs, target_ulong addr, uintptr_t host_pc, -+ int32_t excp_idx, uint8_t excp_cause_code, uint8_t excp_param) -+{ -+ CPUARCState *env = &(ARC_CPU(cs)->env); -+ if (excp_idx != EXCP_TLB_MISS_I) { -+ cpu_restore_state(cs, host_pc, true); -+ } -+ -+ env->efa = addr; -+ env->eret = env->pc; -+ env->erbta = env->bta; -+ -+ cs->exception_index = excp_idx; -+ env->causecode = excp_cause_code; -+ env->param = excp_param; -+ cpu_loop_exit(cs); -+} -+ -+/* MMU range */ -+static const uint32_t MMU_VA_START = 0x00000000; /* inclusive */ -+static const uint32_t MMU_VA_END = 0x80000000; /* exclusive */ -+ -+typedef enum { -+ DIRECT_ACTION, -+ MPU_ACTION, -+ MMU_ACTION, -+ EXCEPTION_ACTION -+} ACTION; -+ -+/* -+ * Applying the following logic -+ * ,-----.-----.-----------.---------.---------------. -+ * | MMU | MPU | MMU range | mmu_idx | action | -+ * |-----+-----+-----------+---------+---------------| -+ * | dis | dis | x | x | phys = virt | -+ * |-----+-----+-----------+---------+---------------| -+ * | dis | ena | x | x | mpu_translate | -+ * |-----+-----+-----------+---------+---------------| -+ * | ena | dis | true | x | mmu_translate | -+ * |-----+-----+-----------+---------+---------------| -+ * | ena | dis | false | 0 | phys = virt | -+ * |-----+-----+-----------+---------+---------------| -+ * | ena | dis | false | 1 | exception | -+ * |-----+-----+-----------+---------+---------------| -+ * | ena | ena | false | x | mpu_translate | -+ * |-----+-----+-----------+---------+---------------| -+ * | ena | ena | true | x | mmu_translate | -+ * `-----^-----^-----------^---------^---------------' -+ */ -+static int decide_action(const CPUARCState *env, -+ target_ulong addr, -+ int mmu_idx) -+{ -+ static ACTION table[2][2][2][2] = { }; -+ static bool is_initialized; -+ const bool is_user = (mmu_idx == 1); -+ const bool is_mmu_range = ((addr >= MMU_VA_START) && (addr < MMU_VA_END)); -+ -+ if (!is_initialized) { -+ /* Both MMU and MPU disabled */ -+#define T true -+#define F false -+ -+ table[F][F][F][F] = DIRECT_ACTION; -+ table[F][F][F][T] = DIRECT_ACTION; -+ table[F][F][T][F] = DIRECT_ACTION; -+ table[F][F][T][T] = DIRECT_ACTION; -+ -+ /* Only MPU */ -+ table[F][T][F][F] = MPU_ACTION; -+ table[F][T][F][T] = MPU_ACTION; -+ table[F][T][T][F] = MPU_ACTION; -+ table[F][T][T][T] = MPU_ACTION; -+ -+ /* Only MMU; non-mmu range; kernel access */ -+ table[T][F][F][F] = DIRECT_ACTION; -+ /* Only MMU; non-mmu range; user access */ -+ table[T][F][F][T] = EXCEPTION_ACTION; -+ -+ /* Only MMU; mmu range; both modes access */ -+ table[T][F][T][F] = MMU_ACTION; -+ table[T][F][T][T] = MMU_ACTION; -+ -+ /* Both MMU and MPU enabled; non-mmu range */ -+ table[T][T][F][F] = MPU_ACTION; -+ table[T][T][F][T] = MPU_ACTION; -+ -+ /* Both MMU and MPU enabled; mmu range */ -+ table[T][T][T][F] = MMU_ACTION; -+ table[T][T][T][T] = MMU_ACTION; -+ -+#undef T -+#undef F -+ -+ is_initialized = true; -+ } -+ -+ return table[env->mmu.enabled][env->mpu.enabled][is_mmu_range][is_user]; -+} -+ -+void arc_mmu_init(CPUARCState *env) -+{ -+ env->mmu.enabled = 0; -+ env->mmu.pid_asid = 0; -+ env->mmu.sasid0 = 0; -+ env->mmu.sasid1 = 0; -+ -+ env->mmu.tlbpd0 = 0; -+ env->mmu.tlbpd1 = 0; -+ env->mmu.tlbpd1_hi = 0; -+ env->mmu.tlbindex = 0; -+ env->mmu.tlbcmd = 0; -+ env->mmu.scratch_data0 = 0; -+ -+ memset(env->mmu.nTLB, 0, sizeof(env->mmu.nTLB)); -+} -+ -+ -+#ifndef CONFIG_USER_ONLY -+/* Softmmu support function for MMU. */ -+bool arc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, -+ MMUAccessType access_type, int mmu_idx, -+ bool probe, uintptr_t retaddr) -+{ -+ /* TODO: this rwe should go away when the TODO below is done */ -+ enum mmu_access_type rwe = (char) access_type; -+ CPUARCState *env = &((ARC_CPU(cs))->env); -+ int action = decide_action(env, address, mmu_idx); -+ -+ switch (action) { -+ case DIRECT_ACTION: -+ tlb_set_page(cs, address & PAGE_MASK, address & PAGE_MASK, -+ PAGE_READ | PAGE_WRITE | PAGE_EXEC, -+ mmu_idx, TARGET_PAGE_SIZE); -+ break; -+ case MPU_ACTION: -+ if (arc_mpu_translate(env, address, access_type, mmu_idx)) { -+ if (probe) { -+ return false; -+ } -+ MPUException *mpu_excp = &env->mpu.exception; -+ raise_mem_exception(cs, address, retaddr, -+ mpu_excp->number, mpu_excp->code, mpu_excp->param); -+ } -+ break; -+ case MMU_ACTION: { -+ /* -+ * TODO: these lines must go inside arc_mmu_translate and it -+ * should only signal a failure or success --> generate an -+ * exception or not -+ */ -+ uint32_t index; -+ target_ulong paddr = arc_mmu_translate(env, address, rwe, &index); -+ if ((enum exception_code_list) env->mmu.exception.number != -+ EXCP_NO_EXCEPTION) { -+ if (probe) { -+ return false; -+ } -+ const struct mmu_exception *mmu_excp = &env->mmu.exception; -+ raise_mem_exception(cs, address, retaddr, -+ mmu_excp->number, mmu_excp->causecode, mmu_excp->parameter); -+ } else { -+ int prot = arc_mmu_get_prot_for_index(index, env); -+ address = arc_mmu_page_address_for(address); -+ tlb_set_page(cs, address, paddr & PAGE_MASK, prot, -+ mmu_idx, TARGET_PAGE_SIZE); -+ } -+ break; -+ } -+ case EXCEPTION_ACTION: -+ if (probe) { -+ return false; -+ } -+ /* TODO: like TODO above, this must move inside mmu */ -+ qemu_log_mask(CPU_LOG_MMU, "[MMU_TLB_FILL] ProtV " -+ "exception at 0x" TARGET_FMT_lx ". rwe = %s\n", -+ env->pc, RWE_STRING(rwe)); -+ raise_mem_exception(cs, address, retaddr, -+ EXCP_PROTV, CAUSE_CODE(rwe), 0x08); -+ break; -+ default: -+ g_assert_not_reached(); -+ } -+ -+ return true; -+} -+ -+hwaddr arc_mmu_debug_translate(CPUARCState *env, vaddr addr) -+{ -+ return arc_mmu_translate(env, addr, MMU_MEM_IRRELEVANT_TYPE, -+ NULL); -+} -+ -+ -+#endif /* ifndef CONFIG_USER_ONLY */ -+ -+void arc_mmu_disable(CPUARCState *env) -+{ -+ env->mmu.enabled = false; -+} -diff --git a/target/arc/mmu.h b/target/arc/mmu.h -new file mode 100644 -index 0000000000..00a26e828c ---- /dev/null -+++ b/target/arc/mmu.h -@@ -0,0 +1,148 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef ARC_MMU_H -+#define ARC_MMU_H -+ -+#include "target/arc/regs.h" -+ -+/* PD0 flags */ -+#define PD0_VPN 0x7ffff000 -+#define PD0_ASID 0x000000ff -+#define PD0_G 0x00000100 /* Global */ -+#define PD0_V 0x00000200 /* Valid */ -+#define PD0_SZ 0x00000400 /* Size: Normal or Super Page */ -+#define PD0_L 0x00000800 /* Lock */ -+#define PD0_S 0x80000000 /* Shared Library ASID */ -+#define PD0_FLG (PD0_G | PD0_V | PD0_SZ | PD0_L) -+ -+#define PD0_ASID_MATCH 0x0000003f -+#define PD0_PID_MATCH 0x000000ff -+ -+/* PD1 permission bits */ -+#define PD1_PPN 0xfffff000 /* Cached */ -+#define PD1_FC 0x00000001 /* Cached */ -+#define PD1_XU 0x00000002 /* User Execute */ -+#define PD1_WU 0x00000004 /* User Write */ -+#define PD1_RU 0x00000008 /* User Read */ -+#define PD1_XK 0x00000010 /* Kernel Execute */ -+#define PD1_WK 0x00000020 /* Kernel Write */ -+#define PD1_RK 0x00000040 /* Kernel Read */ -+#define PD1_FLG (PD1_FC | PD1_XU | PD1_WU | PD1_RU | PD1_XK | PD1_WK | PD1_RK) -+ -+#define TLBINDEX_INDEX 0x00001fff -+#define TLBINDEX_E 0x80000000 -+#define TLBINDEX_RC 0x70000000 -+ -+#define TLB_CMD_WRITE 0x1 -+#define TLB_CMD_WRITENI 0x5 -+#define TLB_CMD_READ 0x2 -+#define TLB_CMD_INSERT 0x7 -+#define TLB_CMD_DELETE 0x8 -+#define TLB_CMD_IVUTLB 0x6 -+ -+#define N_SETS 256 -+#define N_WAYS 4 -+#define TLB_ENTRIES (N_SETS * N_WAYS) -+ -+#define PAGE_SHIFT TARGET_PAGE_BITS -+#define PAGE_SIZE (1 << PAGE_SHIFT) -+#define PAGE_MASK (~(PAGE_SIZE - 1)) -+ -+/* NOTE: Do not reorder, this is casted in tbl_fill function. */ -+enum mmu_access_type { -+ MMU_MEM_READ = 0, -+ MMU_MEM_WRITE, -+ MMU_MEM_FETCH, /* Read for execution. */ -+ MMU_MEM_ATTOMIC, -+ MMU_MEM_IRRELEVANT_TYPE, -+}; -+ -+#define RWE_STRING(RWE) \ -+ (RWE == MMU_MEM_READ ? "MEM_READ" : \ -+ (RWE == MMU_MEM_WRITE ? "MEM_WRITE" : \ -+ (RWE == MMU_MEM_ATTOMIC ? "MEM_ATTOMIC" : \ -+ (RWE == MMU_MEM_FETCH ? "MEM_FETCH" : \ -+ (RWE == MMU_MEM_IRRELEVANT_TYPE ? "MEM_IRRELEVANT" \ -+ : "NOT_VALID_RWE"))))) -+ -+ -+#define CAUSE_CODE(ENUM) \ -+ ((ENUM == MMU_MEM_FETCH) ? 0 : \ -+ ((ENUM == MMU_MEM_READ) ? 1 : \ -+ ((ENUM == MMU_MEM_WRITE) ? 2 : 3))) -+ -+ -+struct arc_tlb_e { -+ /* -+ * TLB entry is {PD0,PD1} tuple, kept "unpacked" to avoid bit fiddling -+ * flags includes both PD0 flags and PD1 permissions. -+ */ -+ uint32_t pd0, pd1; -+}; -+ -+#define RAISE_MMU_EXCEPTION(ENV) { \ -+ do_exception_no_delayslot(ENV, \ -+ ENV->mmu.exception.number, \ -+ ENV->mmu.exception.causecode, \ -+ ENV->mmu.exception.parameter); \ -+} -+ -+struct arc_mmu { -+ uint32_t enabled; -+ struct mmu_exception { -+ int32_t number; -+ uint8_t causecode; -+ uint8_t parameter; -+ } exception; -+ -+ struct arc_tlb_e nTLB[N_SETS][N_WAYS]; -+ -+ /* insert uses vaddr to find set; way selection could be random/rr/lru */ -+ uint32_t way_sel[N_SETS]; -+ -+ /* -+ * Current Address Space ID (in whose context mmu lookups done) -+ * Note that it is actually present in AUX PID reg, which we don't -+ * explicitly maintain, but {re,de}construct as needed by LR/SR insns -+ * respectively. -+ */ -+ uint32_t pid_asid; -+ uint32_t sasid0; -+ uint32_t sasid1; -+ -+ uint32_t tlbpd0; -+ uint32_t tlbpd1; -+ uint32_t tlbpd1_hi; -+ uint32_t tlbindex; -+ uint32_t tlbcmd; -+ uint32_t scratch_data0; -+}; -+ -+ -+struct CPUARCState; -+ -+void arc_mmu_debug_tlb(struct CPUARCState *env); -+void arc_mmu_debug_tlb_for_vaddr(struct CPUARCState *env, uint32_t vaddr); -+ -+uint32_t arc_mmu_page_address_for(uint32_t vaddr); -+ -+#endif /* ARC_MMU_H */ -diff --git a/target/arc/mpu.c b/target/arc/mpu.c -new file mode 100644 -index 0000000000..256ff12bfc ---- /dev/null -+++ b/target/arc/mpu.c -@@ -0,0 +1,656 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * Contributed by Shahab Vahedi (Synopsys) -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "mpu.h" -+#include "cpu.h" -+#include "exec/exec-all.h" -+#include "mmu.h" -+ -+/* -+ * In case of exception, this signals the effective region -+ * was the default one -+ */ -+#define MPU_DEFAULT_REGION_NR 0xff -+ -+/* Defines used by in-house functions */ -+#define MPU_EN_EN_BIT 30 -+#define MPU_EN_KR_BIT 8 -+#define MPU_EN_KW_BIT 7 -+#define MPU_EN_KE_BIT 6 -+#define MPU_EN_UR_BIT 5 -+#define MPU_EN_UW_BIT 4 -+#define MPU_EN_UE_BIT 3 -+ -+#define MPU_ECR_EC_CODE_BIT 16 -+#define MPU_ECR_VT_BIT 8 -+ -+#define MPU_BASE_ADDR_MASK 0xffffffe0 /* ignore least 5 bits */ -+#define MPU_BASE_VALID_MASK 0x00000001 /* bit #0 */ -+ -+/* -+ * Given a number of bits as width, calc the mask to -+ * "and" with. e.g.: 3 bits --> 8 - 1 --> 7 (111b) -+ */ -+#define MPU_WIDTH_TO_MASK(w) ((1 << (w)) - 1) -+#define MPU_PERMS_REG_LOWER_SIZE_WIDTH 2 -+#define MPU_PERMS_REG_HIGHER_SIZE_WIDTH 3 -+#define MPU_PERMS_REG_HIGHER_SIZE_POS 9 -+ -+/* -+ * After knowing the operating mode (user/kernel), -+ * this struct represents the effective permissions. -+ */ -+typedef struct MPUEffectPerm { -+ bool read; -+ bool write; -+ bool exec; -+} MPUEffectPerm; -+ -+/* Packer and unpackers (local to this translation unit) */ -+static inline uint32_t pack_enable(const bool ena) -+{ -+ return ena << MPU_EN_EN_BIT; -+} -+ -+static inline void unpack_enable(bool *enabled, uint32_t value) -+{ -+ *enabled = (value >> MPU_EN_EN_BIT) & 1; -+} -+ -+static inline uint32_t pack_permissions(const MPUPermissions *perms) -+{ -+ return perms->KR << MPU_EN_KR_BIT | -+ perms->KW << MPU_EN_KW_BIT | -+ perms->KE << MPU_EN_KE_BIT | -+ perms->UR << MPU_EN_UR_BIT | -+ perms->UW << MPU_EN_UW_BIT | -+ perms->UE << MPU_EN_UE_BIT; -+} -+ -+static inline void unpack_permissions(MPUPermissions *perms, uint32_t value) -+{ -+ perms->KR = (value >> MPU_EN_KR_BIT) & 1; -+ perms->KW = (value >> MPU_EN_KW_BIT) & 1; -+ perms->KE = (value >> MPU_EN_KE_BIT) & 1; -+ perms->UR = (value >> MPU_EN_UR_BIT) & 1; -+ perms->UW = (value >> MPU_EN_UW_BIT) & 1; -+ perms->UE = (value >> MPU_EN_UE_BIT) & 1; -+} -+ -+static inline uint32_t pack_enable_reg(const MPUEnableReg *mpuen) -+{ -+ return pack_enable(mpuen->enabled) | -+ pack_permissions(&mpuen->permission); -+} -+ -+static inline void unpack_enable_reg(MPUEnableReg *mpuen, uint32_t value) -+{ -+ unpack_enable(&mpuen->enabled, value); -+ unpack_permissions(&mpuen->permission, value); -+} -+ -+static inline uint32_t pack_ecr(const MPUECR *mpuecr) -+{ -+ return ARC_MPU_ECR_VEC_NUM << MPU_ECR_EC_CODE_BIT | -+ (mpuecr->violation & 3) << MPU_ECR_VT_BIT | -+ mpuecr->region; -+} -+ -+static inline uint32_t pack_base_reg(const MPUBaseReg *mpurdb) -+{ -+ return mpurdb->addr | mpurdb->valid; -+} -+ -+static inline void unpack_base_reg(MPUBaseReg *mpurdb, uint32_t value) -+{ -+ mpurdb->addr = value & MPU_BASE_ADDR_MASK; -+ mpurdb->valid = value & MPU_BASE_VALID_MASK; -+} -+ -+ -+/* -+ * Break the "size" field into "higher" and "lower" parts -+ * e.g.: a b c d e --> a b c . . . d e -+ * higher lower -+ */ -+static uint32_t pack_region_size_bits(uint8_t size_bits) -+{ -+ uint32_t lower = -+ size_bits & MPU_WIDTH_TO_MASK(MPU_PERMS_REG_LOWER_SIZE_WIDTH); -+ uint32_t higher = size_bits >> MPU_PERMS_REG_LOWER_SIZE_WIDTH; -+ higher &= MPU_WIDTH_TO_MASK(MPU_PERMS_REG_HIGHER_SIZE_WIDTH); -+ return (higher << MPU_PERMS_REG_HIGHER_SIZE_POS) | lower; -+} -+ -+/* -+ * Put the higher and lower parts of "size" field together -+ * e.g.: a b c . . . d e ---> abcde -+ * higher lower -+ */ -+static void unpack_region_size_bits(uint8_t *size_bits, uint32_t value) -+{ -+ uint8_t lower = -+ value & MPU_WIDTH_TO_MASK(MPU_PERMS_REG_LOWER_SIZE_WIDTH); -+ uint8_t higher = value >> MPU_PERMS_REG_HIGHER_SIZE_POS; -+ higher &= MPU_WIDTH_TO_MASK(MPU_PERMS_REG_HIGHER_SIZE_WIDTH); -+ *size_bits = (higher << MPU_PERMS_REG_LOWER_SIZE_WIDTH) | lower; -+} -+ -+static void set_region_mask(uint32_t *mask, uint8_t size_bits) -+{ -+ uint32_t region_offset_mask = 0; -+ /* -+ * size_bits: 00100b (4) --> 32 bytes --> least 5 bits are 0 -+ * size_bits: 00101b (5) --> 64 bytes --> least 6 bits are 0 -+ * ... -+ * size_bits: 11111b (31) --> 4 gb --> least 32 bits are 0 -+ */ -+ if (size_bits >= 4 && size_bits < 31) { -+ region_offset_mask = (2 << size_bits) - 1; -+ } else if (size_bits == 31) { -+ region_offset_mask = 0xffffffff; -+ } else { -+ qemu_log_mask(LOG_GUEST_ERROR, "[MPU] %hu as size of a region is " -+ "undefined behaviour.\n", size_bits); -+ } -+ *mask = ~region_offset_mask; -+} -+ -+static inline uint32_t pack_perm_reg(const MPUPermReg *mpurdp) -+{ -+ return pack_region_size_bits(mpurdp->size_bits) | -+ pack_permissions(&mpurdp->permission); -+} -+ -+static void unpack_perm_reg(MPUPermReg *mpurdp, uint32_t value) -+{ -+ unpack_region_size_bits(&mpurdp->size_bits, value); -+ /* size_bits of below 4 are undefined --> Assuming min region size. */ -+ mpurdp->size = (mpurdp->size_bits < 4) ? 32 : (2ul << mpurdp->size_bits); -+ unpack_permissions(&mpurdp->permission, value); -+ /* The mask is a facilitator to find the corresponding region easier */ -+ set_region_mask(&mpurdp->mask, mpurdp->size_bits); -+} -+ -+ -+/* Extern function: To be called at reset() */ -+void arc_mpu_init(struct ARCCPU *cpu) -+{ -+ static const MPUPermissions INITIAL_PERMS = {0}; -+ ARCMPU *mpu = &cpu->env.mpu; -+ size_t idx = 0; -+ -+ /* Maybe the version must be determinded also based on CPU type */ -+ mpu->reg_bcr.version = cpu->cfg.has_mpu ? ARC_MPU_VERSION : 0; -+ mpu->reg_bcr.regions = cpu->cfg.has_mpu ? cpu->cfg.mpu_num_regions : 0; -+ switch (mpu->reg_bcr.regions) { -+ case 0 ... 2: -+ case 4: -+ case 8: -+ case 16: -+ break; -+ default: -+ assert(!"Invalid number of MPU regions."); -+ } -+ -+ /* -+ * We use this flag to determine if MPU is in motion or not. -+ * This is most of the time the same as reg_enable.enabled, -+ * However, in case of a double exception (Machine Check) -+ * this becomes false while reg_enable.enabled holds its -+ * value. As a result, there is no MPU anymore after a -+ * Machine Check is raised. -+ */ -+ mpu->enabled = false; -+ -+ mpu->reg_enable.enabled = false; -+ mpu->reg_enable.permission = INITIAL_PERMS; -+ -+ mpu->reg_ecr.region = 0; -+ mpu->reg_ecr.violation = 0; -+ mpu->exception.number = ARC_MPU_ECR_VEC_NUM; -+ mpu->exception.code = 0; -+ mpu->exception.param = ARC_MPU_ECR_PARAM; -+ -+ for (idx = 0; idx < ARC_MPU_MAX_NR_REGIONS; ++idx) { -+ mpu->reg_base[idx].valid = false; -+ mpu->reg_base[idx].addr = 0; -+ -+ mpu->reg_perm[idx].size_bits = 0; -+ mpu->reg_perm[idx].mask = 0xffffffff; -+ mpu->reg_perm[idx].permission = INITIAL_PERMS; -+ } -+} -+ -+/* Checking the sanity of situation before accessing MPU registers */ -+static void validate_mpu_regs_access(CPUARCState *env) -+{ -+ /* MPU registers are only accessible in kernel mode */ -+ if (is_user_mode(env)) { -+ arc_raise_exception(env, EXCP_PRIVILEGEV); -+ } -+ /* No MPU, no getting any */ -+ else if ((env_archcpu(env))->cfg.has_mpu == false) { -+ arc_raise_exception(env, EXCP_INST_ERROR); -+ } -+} -+ -+/* If 'rgn' is higher than configured region number, throw an exception */ -+static inline void validate_region_number(const ARCMPU *mpu, uint8_t rgn) -+{ -+ if (!(rgn < mpu->reg_bcr.regions)) { -+ arc_raise_exception(container_of(mpu, CPUARCState, mpu), /* env */ -+ EXCP_INST_ERROR); -+ } -+} -+ -+/* Extern function: Getter for MPU registers */ -+target_ulong -+arc_mpu_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data) -+{ -+ validate_mpu_regs_access((CPUARCState *) data); -+ ARCMPU *mpu = &(((CPUARCState *) data)->mpu); -+ uint32_t reg = 0; -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_mpu_build: -+ reg = (mpu->reg_bcr.regions << 8) | mpu->reg_bcr.version; -+ break; -+ case AUX_ID_mpuen: -+ reg = pack_enable_reg(&mpu->reg_enable); -+ break; -+ case AUX_ID_mpuic: -+ reg = pack_ecr(&mpu->reg_ecr); -+ break; -+ case AUX_ID_mpurdb0 ... AUX_ID_mpurdb15: { -+ const uint8_t rgn = aux_reg_detail->id - AUX_ID_mpurdb0; -+ validate_region_number(mpu, rgn); -+ reg = pack_base_reg(&mpu->reg_base[rgn]); -+ break; -+ } -+ case AUX_ID_mpurdp0 ... AUX_ID_mpurdp15: { -+ const uint8_t rgn = aux_reg_detail->id - AUX_ID_mpurdp0; -+ validate_region_number(mpu, rgn); -+ reg = pack_perm_reg(&mpu->reg_perm[rgn]); -+ break; -+ } -+ default: -+ g_assert_not_reached(); -+ } -+ return reg; -+} -+ -+/* Log the MPU sensitive information */ -+static void log_mpu_data(const ARCMPU *mpu) -+{ -+ char suffix[4] = " B"; -+ uint32_t size; -+ /* Log header */ -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MPU] ,--------.-------.------------.--------.---" -+ "--------------------.--------------.------------.\n"); -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MPU] | region | valid | address | size | " -+ "effective address | kernel perm. | user perm. |\n"); -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MPU] |--------+-------+------------+--------+---" -+ "--------------------+--------------+------------|\n"); -+ /* Now its every regions turn */ -+ for (uint8_t r = 0; r < mpu->reg_bcr.regions; ++r) { -+ const MPUBaseReg *rb = &mpu->reg_base[r]; -+ const MPUPermReg *rp = &mpu->reg_perm[r]; -+ const MPUPermissions *p = &rp->permission; -+ if (rp->size >= 0x40000000) { -+ suffix[0] = 'G'; -+ size = rp->size >> 30; -+ } else if (rp->size >= 0x00100000) { -+ suffix[0] = 'M'; -+ size = rp->size >> 20; -+ } else if (rp->size >= 0x00000400) { -+ suffix[0] = 'K'; -+ size = rp->size >> 10; -+ } else { -+ suffix[0] = ' '; -+ size = rp->size & 0x3FF; -+ } -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MPU] | %02u | %s | 0x%08x | %3u %s | 0x%08x-0x%08x " -+ "| %c%c%c | %c%c%c |\n", -+ r, rb->valid ? "true " : "false", rb->addr, size, suffix, -+ rb->addr & rp->mask, -+ (rb->addr & rp->mask) + ((uint32_t) rp->size), -+ p->KR ? 'r' : '-', p->KW ? 'w' : '-', p->KE ? 'x' : '-', -+ p->UR ? 'r' : '-', p->UW ? 'w' : '-', p->UE ? 'x' : '-'); -+ } -+ /* Default region */ -+ const MPUPermissions *defp = &mpu->reg_enable.permission; -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MPU] | def. | | | | " -+ " | %c%c%c | %c%c%c |\n", -+ defp->KR ? 'r' : '-', defp->KW ? 'w' : '-', defp->KE ? 'x' : '-', -+ defp->UR ? 'r' : '-', defp->UW ? 'w' : '-', defp->UE ? 'x' : '-'); -+ /* Wrap it up */ -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MPU] `--------^-------^------------^--------^---" -+ "--------------------^--------------^------------'\n"); -+} -+ -+/* Extern function: Setter for MPU registers */ -+void -+arc_mpu_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, -+ const target_ulong value, void *data) -+{ -+ validate_mpu_regs_access((CPUARCState *) data); -+ ARCMPU *mpu = &(((CPUARCState *) data)->mpu); -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_mpuen: -+ unpack_enable_reg(&mpu->reg_enable, value); -+ mpu->enabled = mpu->reg_enable.enabled; -+ break; -+ case AUX_ID_mpurdb0 ... AUX_ID_mpurdb15: { -+ const uint8_t rgn = aux_reg_detail->id - AUX_ID_mpurdb0; -+ validate_region_number(mpu, rgn); -+ unpack_base_reg(&mpu->reg_base[rgn], value); -+ break; -+ } -+ case AUX_ID_mpurdp0 ... AUX_ID_mpurdp15: { -+ const uint8_t rgn = aux_reg_detail->id - AUX_ID_mpurdp0; -+ validate_region_number(mpu, rgn); -+ unpack_perm_reg(&mpu->reg_perm[rgn], value); -+ break; -+ } -+ default: -+ g_assert_not_reached(); -+ } -+ /* Invalidate the entries in qemu's translation buffer */ -+ tlb_flush(env_cpu((CPUARCState *) data)); -+ /* If MPU is enabled, log its data */ -+ if (mpu->enabled) { -+ log_mpu_data(mpu); -+ } -+} -+ -+/* -+ * If user mode, return the user permission only. -+ * If kernel mode, return the aggregation of both permissions. -+ */ -+static void get_effective_rwe(const MPUPermissions *perm, -+ bool user_mode, MPUEffectPerm *effective) -+{ -+ effective->read = user_mode ? perm->UR : perm->KR | perm->UR; -+ effective->write = user_mode ? perm->UW : perm->KW | perm->UW; -+ effective->exec = user_mode ? perm->UE : perm->KE | perm->UE; -+} -+ -+/* Translate internal QEMU's access type to an MPU violation type */ -+static inline uint8_t qemu_access_to_violation(MMUAccessType access) -+{ -+ uint8_t vt = 0; -+ switch (access) { -+ case MMU_INST_FETCH: -+ vt = MPU_CAUSE_FETCH; -+ break; -+ case MMU_DATA_LOAD: -+ vt = MPU_CAUSE_READ; -+ break; -+ case MMU_DATA_STORE: -+ vt = MPU_CAUSE_WRITE; -+ break; -+ /* TODO: there must be an MPU_CAUSE_RW as well, but how? */ -+ default: -+ g_assert_not_reached(); -+ } -+ return vt; -+} -+ -+/* Translate MPU's permission to QEMU's tlb permission */ -+static inline uint8_t mpu_permission_to_qemu(const MPUPermissions *perm, -+ bool user_mode) -+{ -+ MPUEffectPerm effective = { }; -+ get_effective_rwe(perm, user_mode, &effective); -+ return (effective.read ? PAGE_READ : 0) | -+ (effective.write ? PAGE_WRITE : 0) | -+ (effective.exec ? PAGE_EXEC : 0); -+} -+ -+/* -+ * Check if the 'access' is according to 'perm'ission. -+ * Note that a user mode permission is also implied for kernel. -+ */ -+static bool allowed(MMUAccessType access, bool user_mode, -+ const MPUPermissions *perm) -+{ -+ MPUEffectPerm effective_perm = { }; -+ get_effective_rwe(perm, user_mode, &effective_perm); -+ -+ switch (access) { -+ case MMU_INST_FETCH: -+ return effective_perm.exec; -+ case MMU_DATA_LOAD: -+ return effective_perm.read; -+ case MMU_DATA_STORE: -+ return effective_perm.write; -+ default: -+ g_assert_not_reached(); -+ } -+} -+ -+/* Used for logging purposes */ -+static inline const char *log_violation_to_str(uint8_t violation) -+{ -+ return (violation == MPU_CAUSE_FETCH) ? "fetch" : -+ (violation == MPU_CAUSE_READ) ? "read" : -+ (violation == MPU_CAUSE_WRITE) ? "write" : -+ (violation == MPU_CAUSE_RW) ? "read-write" : -+ "unknown"; -+} -+ -+/* Sets the exception data */ -+static void set_exception(CPUARCState *env, uint32_t addr, -+ uint8_t region, MMUAccessType access) -+{ -+ MPUECR *ecr = &env->mpu.reg_ecr; -+ ecr->violation = qemu_access_to_violation(access); -+ ecr->region = region; -+ -+ /* this info is used by the caller to trigger the exception */ -+ MPUException *excp = &env->mpu.exception; -+ excp->number = EXCP_PROTV; -+ excp->code = ecr->violation; -+ excp->param = ARC_MPU_ECR_PARAM; -+ -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MPU] exception: region=%hu, addr=0x%08x, violation=%s\n", -+ region, addr, log_violation_to_str(ecr->violation)); -+} -+ -+/* -+ * Given an 'addr', finds the region it belongs to. If no match -+ * is found, then it signals this by returning MPU_DEFAULT_REGION_NR. -+ * Since regions with lower index has higher priority, the first match -+ * is the correct one even if there is overlap among regions. -+ */ -+static uint8_t get_matching_region(const ARCMPU *mpu, uint32_t addr) -+{ -+ qemu_log_mask(CPU_LOG_MMU, "[MPU] looking up: addr=0x%08x\n", addr); -+ for (uint8_t r = 0; r < mpu->reg_bcr.regions; ++r) { -+ if (!mpu->reg_base[r].valid) { -+ continue; -+ } -+ const uint32_t mask = mpu->reg_perm[r].mask; -+ /* 'addr' falls under the current region? */ -+ if ((mpu->reg_base[r].addr & mask) == (addr & mask)) { -+ qemu_log_mask(CPU_LOG_MMU, -+ "[MPU] region match: region=%u, base=0x%08x\n", -+ r, mpu->reg_base[r].addr); -+ return r; -+ } -+ } -+ /* If we are here, then no corresponding region is found */ -+ qemu_log_mask(CPU_LOG_MMU, "[MPU] default region will be used.\n"); -+ return MPU_DEFAULT_REGION_NR; -+} -+ -+/* -+ * Returns the corresponding permission for the given 'region'. -+ * If 'region' is MPU_DEFAULT_REGION_NR, then the default permission -+ * from MPU_EN register is returned. -+ */ -+static const MPUPermissions *get_permission(const ARCMPU *mpu, -+ uint8_t region) -+{ -+ if (region < mpu->reg_bcr.regions) { -+ return &mpu->reg_perm[region].permission; -+ } else if (region == MPU_DEFAULT_REGION_NR) { -+ return &mpu->reg_enable.permission; -+ } -+ g_assert_not_reached(); -+} -+ -+/* -+ * Have the following example in mind: -+ * ,------------. -+ * | region 5 | -+ * | | -+ * | | first page of region 5 -+ * | | -+ * |............| -+ * | | -+ * |,----------.| second page of region 5 -+ * || region 4 || -+ * |`----------'| -+ * `------------' -+ * Here region four's size is half a page size. -+ * -+ * This function checks if the page that the address belongs to, -+ * overlaps with another higher priority region. regions with lower -+ * priority don't matter because they cannot influence the permission. -+ * -+ * The logic is to check if any of the valid regions is contained in -+ * the page that 'addr' belongs to. -+ */ -+static bool is_overlap_free(const ARCMPU *mpu, target_ulong addr, -+ uint8_t current_region) -+{ -+ /* Nothing has higher priority than region 0 */ -+ if (current_region == 0) { -+ return true; -+ } else if (current_region == MPU_DEFAULT_REGION_NR) { -+ /* Make the "default region number" fit in this function */ -+ current_region = mpu->reg_bcr.regions; -+ } -+ -+ assert(current_region <= mpu->reg_bcr.regions); -+ -+ target_ulong page_addr = addr & PAGE_MASK; -+ /* -+ * Going through every region that has higher priority than -+ * the current one. -+ */ -+ for (uint8_t r = 0; r < current_region; ++r) { -+ if (mpu->reg_base[r].valid && -+ page_addr == (mpu->reg_base[r].addr & PAGE_MASK)) { -+ return false; -+ } -+ } -+ /* No overlap with a higher priority region */ -+ return true; -+} -+ -+/* -+ * Update QEMU's TLB with region's permission. -+ * One thing to remember is that if the region size -+ * is smaller than TARGET_PAGE_SIZE, QEMU will always -+ * consult tlb_fill() for any access to that region. -+ * So there is no point in fine tunning TLB entry sizes -+ * to reflect the real region size. On the other hand, -+ * if the region size is big ( > TARGET_PAGE_SIZE), we -+ * still go with TARGET_PAGE_SIZE, because it can be -+ * memory demanding for host process. -+ */ -+static void update_tlb_page(CPUARCState *env, uint8_t region, -+ target_ulong addr, int mmu_idx) -+{ -+ CPUState *cs = env_cpu(env); -+ /* By default, only add entry for 'addr' */ -+ target_ulong tlb_addr = addr; -+ target_ulong tlb_size = 1; -+ bool check_for_overlap = true; -+ int prot = 0; -+ -+ if (region != MPU_DEFAULT_REGION_NR) { -+ MPUPermReg *perm = &env->mpu.reg_perm[region]; -+ prot = mpu_permission_to_qemu( -+ &perm->permission, is_user_mode(env)); -+ /* -+ * If the region's size is big enough, we'll check for overlap. -+ * Later if we find no overlap, then we add the permission for -+ * the whole page to qemu's tlb. -+ */ -+ check_for_overlap = (perm->size >= TARGET_PAGE_SIZE); -+ } -+ /* Default region */ -+ else { -+ prot = mpu_permission_to_qemu( -+ &env->mpu.reg_enable.permission, is_user_mode(env)); -+ } -+ -+ /* -+ * If the region completely covers the 'page' that 'addr' -+ * belongs to, _and_ is not overlapping with any other region -+ * then add a 'page'wise entry. -+ */ -+ if (check_for_overlap && -+ is_overlap_free(&env->mpu, addr, region)) { -+ tlb_addr = addr & PAGE_MASK; -+ tlb_size = TARGET_PAGE_SIZE; -+ } -+ -+ tlb_set_page(cs, tlb_addr, tlb_addr, prot, mmu_idx, tlb_size); -+ qemu_log_mask(CPU_LOG_MMU, "[MPU] TLB update: addr=0x" TARGET_FMT_lx ", " -+ "prot=%c%c%c, mmu_idx=%u, page_size=" TARGET_FMT_lu "\n", tlb_addr, -+ (prot & PAGE_READ) ? 'r' : '-', (prot & PAGE_WRITE) ? 'w' : '-', -+ (prot & PAGE_EXEC) ? 'x' : '-', mmu_idx, tlb_size); -+} -+ -+/* The MPU entry point for any memory access */ -+int -+arc_mpu_translate(CPUARCState *env, target_ulong addr, -+ MMUAccessType access, int mmu_idx) -+{ -+ ARCMPU *mpu = &env->mpu; -+ -+ uint8_t region = get_matching_region(mpu, addr); -+ const MPUPermissions *perms = get_permission(mpu, region); -+ if (!allowed(access, is_user_mode(env), perms)) { -+ set_exception(env, addr, region, access); -+ return MPU_FAULT; -+ } -+ update_tlb_page(env, region, addr, mmu_idx); -+ -+ return MPU_SUCCESS; -+} -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/mpu.h b/target/arc/mpu.h -new file mode 100644 -index 0000000000..5894221197 ---- /dev/null -+++ b/target/arc/mpu.h -@@ -0,0 +1,133 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * Contributed by Shahab Vahedi (Synopsys) -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef ARC_MPU_H -+#define ARC_MPU_H -+ -+#include "target/arc/regs.h" -+#include "cpu-qom.h" -+ -+/* These values are based on ARCv2 ISA PRM for ARC HS processors */ -+#define ARC_MPU_VERSION 0x03 /* MPU version supported */ -+#define ARC_MPU_MAX_NR_REGIONS 16 /* Number of regions to protect */ -+#define ARC_MPU_ECR_VEC_NUM 0x06 /* EV_ProtV: Protection Violation */ -+#define ARC_MPU_ECR_PARAM 0x04 /* MPU (as opposed to MMU, ...) */ -+ -+/* MPU Build Configuration Register */ -+typedef struct MPUBCR { -+ uint8_t version; /* 0 (disabled), 0x03 */ -+ uint8_t regions; /* 0, 1, 2, 4, 8, 16 */ -+} MPUBCR; -+ -+typedef struct MPUPermissions { -+ bool KR; /* Kernel read */ -+ bool KW; /* Kernel write */ -+ bool KE; /* Kernel execute */ -+ bool UR; /* User read */ -+ bool UW; /* User write */ -+ bool UE; /* User execute */ -+} MPUPermissions; -+ -+/* MPU Enable Register */ -+typedef struct MPUEnableReg { -+ bool enabled; /* Is MPU enabled? */ -+ MPUPermissions permission; /* Default region permissions */ -+} MPUEnableReg; -+ -+/* Determines during which type of operation a violation occurred */ -+enum MPUCauseCode { -+ MPU_CAUSE_FETCH = 0x00, -+ MPU_CAUSE_READ = 0x01, -+ MPU_CAUSE_WRITE = 0x02, -+ MPU_CAUSE_RW = 0x03 -+}; -+ -+/* The exception to be set */ -+typedef struct MPUException { -+ uint8_t number; /* Exception vector number: 0x06 -> EV_ProtV */ -+ uint8_t code; /* Cause code: fetch, read, write, read/write */ -+ uint8_t param; /* Always 0x04 to represent MPU */ -+} MPUException; -+ -+/* MPU Exception Cause Register */ -+typedef struct MPUECR { -+ uint8_t region; -+ uint8_t violation; /* Fetch, read, write, read/write */ -+} MPUECR; -+ -+/* MPU Region Descriptor Base Register */ -+typedef struct MPUBaseReg { -+ bool valid; /* Is this region valid? */ -+ uint32_t addr; /* Minimum size is 32 bytes --> bits[4:0] are 0 */ -+} MPUBaseReg; -+ -+/* MPU Region Descriptor Permissions Register */ -+typedef struct MPUPermReg { -+ /* size_bits: 00100b ... 11111b */ -+ uint8_t size_bits; -+ /* -+ * We need normal notation of size to set qemu's tlb page size later. -+ * Region's size: 32 bytes, 64 bytes, ..., 4 gigabytes -+ */ -+ uint64_t size; /* 2 << size_bits */ -+ /* -+ * Region offset: 0x1f, 0x3f, ..., 0xffffffff -+ * Hence region mask: 0xffffffe0, 0xfffffc0, ..., 0x00000000 -+ */ -+ uint32_t mask; -+ MPUPermissions permission; /* region's permissions */ -+} MPUPermReg; -+ -+typedef struct ARCMPU { -+ bool enabled; -+ -+ MPUBCR reg_bcr; -+ MPUEnableReg reg_enable; -+ MPUECR reg_ecr; -+ /* Base and permission registers are paired */ -+ MPUBaseReg reg_base[ARC_MPU_MAX_NR_REGIONS]; -+ MPUPermReg reg_perm[ARC_MPU_MAX_NR_REGIONS]; -+ -+ MPUException exception; -+} ARCMPU; -+ -+enum ARCMPUVerifyRet { -+ MPU_SUCCESS, -+ MPU_FAULT -+}; -+ -+struct ARCCPU; -+struct CPUARCState; -+ -+/* Used during a reset */ -+extern void arc_mpu_init(struct ARCCPU *cpu); -+ -+/* -+ * Verifies if 'access' to 'addr' is allowed or not. -+ * possible return values: -+ * MPU_SUCCESS - allowed; 'prot' holds permissions -+ * MPU_FAULT - not allowed; corresponding exception parameters are set -+ */ -+extern int -+arc_mpu_translate(struct CPUARCState *env, target_ulong addr, -+ MMUAccessType access, int mmu_idx); -+ -+#endif /* ARC_MPU_H */ -diff --git a/target/arc/op_helper.c b/target/arc/op_helper.c -new file mode 100644 -index 0000000000..6d68018334 ---- /dev/null -+++ b/target/arc/op_helper.c -@@ -0,0 +1,494 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synopsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "qemu/error-report.h" -+#include "cpu.h" -+#include "sysemu/runstate.h" -+#include "exec/helper-proto.h" -+#include "exec/cpu_ldst.h" -+#include "exec/ioport.h" -+#include "target/arc/regs.h" -+#include "mmu.h" -+#include "hw/arc/cpudevs.h" -+#include "qemu/main-loop.h" -+#include "irq.h" -+#include "sysemu/sysemu.h" -+#include "exec/exec-all.h" -+ -+ -+static target_ulong get_status32(CPUARCState *env) -+{ -+ target_ulong value = pack_status32(&env->stat); -+ -+ /* TODO: Implement debug mode */ -+ if (GET_STATUS_BIT(env->stat, Uf) == 1) { -+ value &= 0x00000f00; -+ } -+ -+ if (env->stopped) { -+ value |= BIT(0); -+ } -+ -+ return value; -+} -+ -+static void set_status32(CPUARCState *env, target_ulong value) -+{ -+ /* TODO: Implement debug mode. */ -+ bool debug_mode = false; -+ if (GET_STATUS_BIT(env->stat, Uf) == 1) { -+ value &= 0x00000f00; -+ } else if (!debug_mode) { -+ value &= 0xffff6f3f; -+ } -+ -+ if (GET_STATUS_BIT(env->stat, Uf) != ((value >> 7) & 0x1)) { -+ tlb_flush(env_cpu(env)); -+ } -+ -+ unpack_status32(&env->stat, value); -+ -+ /* Implement HALT functionality. */ -+ if (value & 0x01) { -+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); -+ } -+} -+ -+static void report_aux_reg_error(target_ulong aux) -+{ -+ if (((aux >= ARC_BCR1_START) && (aux <= ARC_BCR1_END)) || -+ ((aux >= ARC_BCR2_START) && (aux <= ARC_BCR2_END))) { -+ qemu_log_mask(LOG_UNIMP, "Undefined BCR 0x" TARGET_FMT_lx "\n", aux); -+ } -+ -+ qemu_log_mask(LOG_UNIMP, "Undefined aux register with id 0x" TARGET_FMT_lx -+ "\n", aux); -+} -+ -+void helper_sr(CPUARCState *env, target_ulong val, target_ulong aux) -+{ -+ /* saving return address in case an exception must be raised later */ -+ env->host_pc = GETPC(); -+ ARCCPU *cpu = env_archcpu(env); -+ struct arc_aux_reg_detail *aux_reg_detail = -+ arc_aux_reg_struct_for_address(aux, cpu->family); -+ -+ g_assert(aux_reg_detail != NULL); -+ if (aux_reg_detail == NULL) { -+ report_aux_reg_error(aux); -+ arc_raise_exception(env, EXCP_INST_ERROR); -+ } -+ -+ if (aux_reg_detail->aux_reg->set_func != NULL) { -+ aux_reg_detail->aux_reg->set_func(aux_reg_detail, val, -+ (void *) env); -+ } else { -+ arc_raise_exception(env, EXCP_INST_ERROR); -+ } -+ cpu_outl(aux, val); -+} -+ -+ -+target_ulong helper_lr(CPUARCState *env, target_ulong aux) -+{ -+ ARCCPU *cpu = env_archcpu(env); -+ target_ulong result = 0; -+ -+ /* saving return address in case an exception must be raised later */ -+ env->host_pc = GETPC(); -+ -+ struct arc_aux_reg_detail *aux_reg_detail = -+ arc_aux_reg_struct_for_address(aux, cpu->family); -+ -+ if (aux_reg_detail == NULL) { -+ report_aux_reg_error(aux); -+ arc_raise_exception(env, EXCP_INST_ERROR); -+ } -+ -+ if (aux_reg_detail->aux_reg->get_func != NULL) { -+ result = aux_reg_detail->aux_reg->get_func(aux_reg_detail, -+ (void *) env); -+ } else { -+ arc_raise_exception(env, EXCP_INST_ERROR); -+ } -+ -+ return result; -+} -+ -+void QEMU_NORETURN helper_halt(CPUARCState *env, target_ulong npc) -+{ -+ CPUState *cs = env_cpu(env); -+ if (GET_STATUS_BIT(env->stat, Uf)) { -+ cs->exception_index = EXCP_PRIVILEGEV; -+ env->causecode = 0; -+ env->param = 0; -+ /* Restore PC such that we point at the faulty instruction. */ -+ env->eret = env->pc; -+ } else { -+ env->pc = npc; -+ cs->halted = 1; -+ cs->exception_index = EXCP_HLT; -+ } -+ cpu_loop_exit(cs); -+} -+ -+void helper_rtie(CPUARCState *env) -+{ -+ CPUState *cs = env_cpu(env); -+ if (GET_STATUS_BIT(env->stat, Uf)) { -+ cs->exception_index = EXCP_PRIVILEGEV; -+ env->causecode = 0; -+ env->param = 0; -+ /* Restore PC such that we point at the faulty instruction. */ -+ env->eret = env->pc; -+ cpu_loop_exit(cs); -+ return; -+ } -+ -+ if (GET_STATUS_BIT(env->stat, AEf) || (env->aux_irq_act & 0xFFFF) == 0) { -+ assert(GET_STATUS_BIT(env->stat, Uf) == 0); -+ -+ CPU_PCL(env) = env->eret; -+ env->pc = env->eret; -+ -+ env->stat = env->stat_er; -+ env->bta = env->erbta; -+ -+ /* If returning to userland, restore SP. */ -+ if (GET_STATUS_BIT(env->stat, Uf)) { -+ switchSP(env); -+ } -+ -+ qemu_log_mask(CPU_LOG_INT, "[EXCP] RTIE @0x" TARGET_FMT_lx -+ " ECR:0x" TARGET_FMT_lx "\n", -+ (target_ulong) env->r[63], (target_ulong) env->ecr); -+ } else { -+ arc_rtie_interrupts(env); -+ qemu_log_mask(CPU_LOG_INT, "[IRQ] RTIE @0x" TARGET_FMT_lx -+ " STATUS32:0x" TARGET_FMT_lx "\n", -+ (target_ulong) env->r[63], -+ (target_ulong) pack_status32(&env->stat)); -+ } -+ -+#ifdef TARGET_ARCV2 -+ helper_zol_verify(env, env->pc); -+#endif -+} -+ -+void helper_flush(CPUARCState *env) -+{ -+ tb_flush((CPUState *) env_cpu(env)); -+} -+ -+/* -+ * This should only be called from translate, via gen_raise_exception. -+ * We expect that ENV->PC has already been updated. -+ */ -+ -+void QEMU_NORETURN helper_raise_exception(CPUARCState *env, -+ target_ulong index, -+ target_ulong causecode, -+ target_ulong param) -+{ -+ CPUState *cs = env_cpu(env); -+ cs->exception_index = index; -+ env->causecode = causecode; -+ env->param = param; -+ cpu_loop_exit(cs); -+} -+ -+void helper_zol_verify(CPUARCState *env, target_ulong npc) -+{ -+ CPUState *cs = env_cpu(env); -+ if (npc == env->lpe) { -+ if (env->r[60] > 1) { -+ env->r[60] -= 1; -+ -+ /* -+ * Raise exception in case where Zero-overhead-loops needs -+ * to jump. -+ */ -+ cs->exception_index = EXCP_LPEND_REACHED; -+ env->causecode = 0; -+ env->param = env->lps; -+ cpu_loop_exit(cs); -+ } else { -+ env->r[60] = 0; -+ } -+ } -+} -+void helper_fake_exception(CPUARCState *env, target_ulong pc) -+{ -+ helper_raise_exception(env, (target_ulong) EXCP_FAKE, 0, pc); -+} -+ -+target_ulong helper_get_status32(CPUARCState *env) -+{ -+ return get_status32(env); -+} -+ -+void helper_set_status32(CPUARCState *env, target_ulong value) -+{ -+ set_status32(env, value); -+} -+ -+void helper_set_status32_bit(CPUARCState *env, target_ulong bit, -+ target_ulong value) -+{ -+ target_ulong bit_mask = (1 << bit); -+ /* Verify i changing bit is in pstate. Assert otherwise. */ -+ assert((bit_mask & PSTATE_MASK) == 0); -+ -+ env->stat.pstate &= ~bit_mask; -+ env->stat.pstate |= (value << bit); -+} -+ -+static inline target_ulong -+carry_add_flag(target_ulong dest, target_ulong b, target_ulong c, uint8_t size) -+{ -+ target_ulong t1, t2, t3; -+ -+ t1 = b & c; -+ t2 = b & (~dest); -+ t3 = c & (~dest); -+ t1 = t1 | t2 | t3; -+ return (t1 >> (size - 1)) & 1; -+} -+ -+target_ulong helper_carry_add_flag(target_ulong dest, target_ulong b, -+ target_ulong c) { -+ return carry_add_flag(dest, b, c, TARGET_LONG_BITS); -+} -+ -+static inline target_ulong -+overflow_add_flag(target_ulong dest, target_ulong b, target_ulong c, -+ uint8_t size) -+{ -+ dest >>= (size - 1); -+ b >>= (size - 1); -+ c >>= (size - 1); -+ if ((dest == 0 && b == 1 && c == 1) -+ || (dest == 1 && b == 0 && c == 0)) { -+ return 1; -+ } else { -+ return 0; -+ } -+} -+target_ulong helper_overflow_add_flag(target_ulong dest, target_ulong b, -+ target_ulong c) { -+ return overflow_add_flag(dest, b, c, TARGET_LONG_BITS); -+} -+ -+static inline target_ulong -+overflow_sub_flag(target_ulong dest, target_ulong b, target_ulong c, -+ uint8_t size) -+{ -+ dest >>= (size - 1); -+ b >>= (size - 1); -+ c >>= (size - 1); -+ if ((dest == 1 && b == 0 && c == 1) -+ || (dest == 0 && b == 1 && c == 0)) { -+ return 1; -+ } else { -+ return 0; -+ } -+} -+target_ulong helper_overflow_sub_flag(target_ulong dest, target_ulong b, -+ target_ulong c) { -+ return overflow_sub_flag(dest, b, c, TARGET_LONG_BITS); -+} -+ -+target_ulong helper_repl_mask(target_ulong dest, target_ulong src, -+ target_ulong mask) -+{ -+ target_ulong ret = dest & (~mask); -+ ret |= (src & mask); -+ -+ return ret; -+} -+ -+target_ulong helper_mpymu(CPUARCState *env, target_ulong b, target_ulong c) -+{ -+ uint64_t _b = (uint64_t) b; -+ uint64_t _c = (uint64_t) c; -+ -+ return (uint32_t) ((_b * _c) >> 32); -+} -+ -+target_ulong helper_mpym(CPUARCState *env, target_ulong b, target_ulong c) -+{ -+ int64_t _b = (int64_t) ((int32_t) b); -+ int64_t _c = (int64_t) ((int32_t) c); -+ -+ /* -+ * fprintf(stderr, "B = 0x%llx, C = 0x%llx, result = 0x%llx\n", -+ * _b, _c, _b * _c); -+ */ -+ return (_b * _c) >> 32; -+} -+ -+target_ulong -+arc_status_regs_get(const struct arc_aux_reg_detail *aux_reg_detail, -+ void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ target_ulong reg = 0; -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_status32: -+ reg = get_status32(env); -+ break; -+ -+ case AUX_ID_erstatus: -+ if (is_user_mode(env)) { -+ arc_raise_exception(env, EXCP_PRIVILEGEV); -+ } -+ reg = pack_status32(&env->stat_er); -+ break; -+ -+ default: -+ break; -+ } -+ -+ return reg; -+} -+ -+void -+arc_status_regs_set(const struct arc_aux_reg_detail *aux_reg_detail, -+ target_ulong val, void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ -+ switch (aux_reg_detail->id) { -+ -+ case AUX_ID_status32: -+ set_status32(env, val); -+ break; -+ -+ case AUX_ID_erstatus: -+ unpack_status32(&env->stat_er, val); -+ break; -+ -+ default: -+ break; -+ } -+} -+ -+#ifdef TARGET_ARCV3 -+uint64_t helper_carry_add_flag32(uint64_t dest, uint64_t b, uint64_t c) { -+ return carry_add_flag(dest, b, c, 32); -+} -+ -+target_ulong helper_overflow_add_flag32(target_ulong dest, target_ulong b, target_ulong c) { -+ return overflow_add_flag(dest, b, c, 32); -+} -+ -+target_ulong helper_overflow_sub_flag32(target_ulong dest, target_ulong b, target_ulong c) { -+ dest = dest & 0xffffffff; -+ b = b & 0xffffffff; -+ c = c & 0xffffffff; -+ return overflow_sub_flag(dest, b, c, 32); -+} -+ -+uint64_t helper_carry_sub_flag32(uint64_t dest, uint64_t b, uint64_t c) -+{ -+ uint32_t t1, t2, t3; -+ -+ t1 = ~b; -+ t2 = t1 & c; -+ t3 = (t1 | c) & dest; -+ -+ t2 = t2 | t3; -+ return (t2 >> 31) & 1; -+} -+ -+uint64_t helper_rotate_left32(uint64_t orig, uint64_t n) -+{ -+ uint64_t t; -+ uint64_t dest = (orig << n) & ((0xffffffff << n) & 0xffffffff); -+ -+ t = (orig >> (32 - n)) & ((1 << n) - 1); -+ dest |= t; -+ -+ return dest; -+} -+ -+uint64_t helper_rotate_right32(uint64_t orig, uint64_t n) -+{ -+ uint64_t t; -+ uint64_t dest = (orig >> n) & (0xffffffff >> n); -+ -+ t = ((orig & ((1 << n) - 1)) << (32 - n)); -+ dest |= t; -+ -+ return dest; -+} -+ -+uint64_t helper_asr_32(uint64_t b, uint64_t c) -+{ -+ uint64_t t; -+ c = c & 31; -+ t = b; -+ for(int i = 0; i < c; i++) { -+ t >>= 1; -+ if((b & 0x80000000) != 0) -+ t |= 0x80000000; -+ } -+ //t |= ((1 << (c+1)) - 1) << (32 - c); -+ -+ return t; -+} -+ -+target_ulong helper_ffs32(CPUARCState *env, uint64_t src) -+{ -+ int i; -+ if (src == 0) { -+ return 31; -+ } -+ for (i = 0; i <= 31; i++) { -+ if (((src >> i) & 1) != 0) { -+ break; -+ } -+ } -+ return i; -+} -+ -+target_ulong helper_norml(CPUARCState *env, uint64_t src1) -+{ -+ int i; -+ int64_t tmp = (int64_t) src1; -+ if (tmp == 0 || tmp == -1) { -+ return 0; -+ } -+ for (i = 0; i <= 63; i++) { -+ if ((tmp >> i) == 0) { -+ break; -+ } -+ if ((tmp >> i) == -1) { -+ break; -+ } -+ } -+ return i; -+} -+#endif -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/opcodes-v3.def b/target/arc/opcodes-v3.def -new file mode 100644 -index 0000000000..a4f2734553 ---- /dev/null -+++ b/target/arc/opcodes-v3.def -@@ -0,0 +1,18799 @@ -+ -+/* abs<.f> b,c 00100bbb00101111FBBBCCCCCC001001. */ -+{ "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* abs<.f> 0,c 0010011000101111F111CCCCCC001001. */ -+{ "abs", 0x262F7009, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* abs<.f> b,u6 00100bbb01101111FBBBuuuuuu001001. */ -+{ "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abs<.f> 0,u6 0010011001101111F111uuuuuu001001. */ -+{ "abs", 0x266F7009, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abs<.f> b,limm 00100bbb00101111FBBB111110001001. */ -+{ "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* abs<.f> 0,limm 0010011000101111F111111110001001. */ -+{ "abs", 0x262F7F89, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* absl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc001001. */ -+{ "absl", 0x582F0009, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* absl<.f> 0,RC 0101111000101111F111cccccc001001. */ -+{ "absl", 0x5E2F7009, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* absl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu001001. */ -+{ "absl", 0x586F0009, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* absl<.f> 0,u6 0101111001101111F111uuuuuu001001. */ -+{ "absl", 0x5E6F7009, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* absl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100001001. */ -+{ "absl", 0x582F0F09, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* absl<.f> 0,ximm 0101111000101111F111111100001001. */ -+{ "absl", 0x5E2F7F09, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* absl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110001001. */ -+{ "absl", 0x582F0F89, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* absl<.f> 0,limm 0101111000101111F111111110001001. */ -+{ "absl", 0x5E2F7F89, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* abss<.f> b,c 00101bbb00101111FBBBCCCCCC000101. */ -+{ "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* abss<.f> 0,c 0010111000101111F111CCCCCC000101. */ -+{ "abss", 0x2E2F7005, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* abss<.f> b,u6 00101bbb01101111FBBBuuuuuu000101. */ -+{ "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abss<.f> 0,u6 0010111001101111F111uuuuuu000101. */ -+{ "abss", 0x2E6F7005, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abss<.f> b,limm 00101bbb00101111FBBB111110000101. */ -+{ "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* abss<.f> 0,limm 0010111000101111F111111110000101. */ -+{ "abss", 0x2E2F7F85, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* abssh<.f> b,c 00101bbb00101111FBBBCCCCCC000100. */ -+{ "abssh", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* abssh<.f> 0,c 0010111000101111F111CCCCCC000100. */ -+{ "abssh", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* abssh<.f> b,u6 00101bbb01101111FBBBuuuuuu000100. */ -+{ "abssh", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abssh<.f> 0,u6 0010111001101111F111uuuuuu000100. */ -+{ "abssh", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abssh<.f> b,limm 00101bbb00101111FBBB111110000100. */ -+{ "abssh", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* abssh<.f> 0,limm 0010111000101111F111111110000100. */ -+{ "abssh", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* abs_s b,c 01111bbbccc10001. */ -+{ "abs_s", 0x00007811, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* adc<.f> a,b,c 00100bbb00000001FBBBCCCCCCAAAAAA. */ -+{ "adc", 0x20010000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adc<.f> 0,b,c 00100bbb00000001FBBBCCCCCC111110. */ -+{ "adc", 0x2001003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adc<.f><.cc> b,b,c 00100bbb11000001FBBBCCCCCC0QQQQQ. */ -+{ "adc", 0x20C10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adc<.f> a,b,u6 00100bbb01000001FBBBuuuuuuAAAAAA. */ -+{ "adc", 0x20410000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adc<.f> 0,b,u6 00100bbb01000001FBBBuuuuuu111110. */ -+{ "adc", 0x2041003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adc<.f><.cc> b,b,u6 00100bbb11000001FBBBuuuuuu1QQQQQ. */ -+{ "adc", 0x20C10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adc<.f> b,b,s12 00100bbb10000001FBBBssssssSSSSSS. */ -+{ "adc", 0x20810000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adc<.f> a,limm,c 0010011000000001F111CCCCCCAAAAAA. */ -+{ "adc", 0x26017000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adc<.f> a,b,limm 00100bbb00000001FBBB111110AAAAAA. */ -+{ "adc", 0x20010F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adc<.f> 0,limm,c 0010011000000001F111CCCCCC111110. */ -+{ "adc", 0x2601703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adc<.f> 0,b,limm 00100bbb00000001FBBB111110111110. */ -+{ "adc", 0x20010FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adc<.f><.cc> b,b,limm 00100bbb11000001FBBB1111100QQQQQ. */ -+{ "adc", 0x20C10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* adc<.f><.cc> 0,limm,c 0010011011000001F111CCCCCC0QQQQQ. */ -+{ "adc", 0x26C17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adc<.f> a,limm,u6 0010011001000001F111uuuuuuAAAAAA. */ -+{ "adc", 0x26417000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adc<.f> 0,limm,u6 0010011001000001F111uuuuuu111110. */ -+{ "adc", 0x2641703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adc<.f><.cc> 0,limm,u6 0010011011000001F111uuuuuu1QQQQQ. */ -+{ "adc", 0x26C17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adc<.f> 0,limm,s12 0010011010000001F111ssssssSSSSSS. */ -+{ "adc", 0x26817000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA. */ -+{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adc<.f> 0,limm,limm 0010011000000001F111111110111110. */ -+{ "adc", 0x26017FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ. */ -+{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* adcl<.f> OPERAND_RA,RB,RC 01011bbb00000001FBBBccccccaaaaaa. */ -+{ "adcl", 0x58010000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adcl<.f> 0,RB,RC 01011bbb00000001FBBBcccccc111110. */ -+{ "adcl", 0x5801003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adcl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11000001FBBBcccccc0QQQQQ. */ -+{ "adcl", 0x58C10000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adcl<.f> OPERAND_RA,RB,u6 01011bbb01000001FBBBuuuuuuaaaaaa. */ -+{ "adcl", 0x58410000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcl<.f> 0,RB,u6 01011bbb01000001FBBBuuuuuu111110. */ -+{ "adcl", 0x5841003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11000001FBBBuuuuuu1QQQQQ. */ -+{ "adcl", 0x58C10020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adcl<.f> OPERAND_RB,RB,s12 01011bbb10000001FBBBssssssSSSSSS. */ -+{ "adcl", 0x58810000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adcl<.f> OPERAND_RA,ximm,RC 0101110000000001F111ccccccaaaaaa. */ -+{ "adcl", 0x5C017000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* adcl<.f> OPERAND_RA,RB,ximm 01011bbb00000001FBBB111100aaaaaa. */ -+{ "adcl", 0x58010F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* adcl<.f> 0,ximm,RC 0101110000000001F111cccccc111110. */ -+{ "adcl", 0x5C01703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* adcl<.f> 0,RB,ximm 01011bbb00000001FBBB111100111110. */ -+{ "adcl", 0x58010F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* adcl<.f><.cc> 0,ximm,RC 0101110011000001F111cccccc0QQQQQ. */ -+{ "adcl", 0x5CC17000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adcl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11000001FBBB1111000QQQQQ. */ -+{ "adcl", 0x58C10F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* adcl<.f> OPERAND_RA,ximm,u6 0101110001000001F111uuuuuuaaaaaa. */ -+{ "adcl", 0x5C417000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcl<.f> 0,ximm,u6 0101110001000001F111uuuuuu111110. */ -+{ "adcl", 0x5C41703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcl<.f><.cc> 0,ximm,u6 0101110011000001F111uuuuuu1QQQQQ. */ -+{ "adcl", 0x5CC17020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adcl<.f> OPERAND_RA,limm,RC 0101111000000001F111ccccccaaaaaa. */ -+{ "adcl", 0x5E017000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adcl<.f> OPERAND_RA,RB,limm 01011bbb00000001FBBB111110aaaaaa. */ -+{ "adcl", 0x58010F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adcl<.f> 0,limm,RC 0101111000000001F111cccccc111110. */ -+{ "adcl", 0x5E01703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adcl<.f> 0,RB,limm 01011bbb00000001FBBB111110111110. */ -+{ "adcl", 0x58010FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adcl<.f><.cc> 0,limm,RC 0101111011000001F111cccccc0QQQQQ. */ -+{ "adcl", 0x5EC17000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adcl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11000001FBBB1111100QQQQQ. */ -+{ "adcl", 0x58C10F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* adcl<.f> OPERAND_RA,limm,u6 0101111001000001F111uuuuuuaaaaaa. */ -+{ "adcl", 0x5E417000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcl<.f> 0,limm,u6 0101111001000001F111uuuuuu111110. */ -+{ "adcl", 0x5E41703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcl<.f><.cc> 0,limm,u6 0101111011000001F111uuuuuu1QQQQQ. */ -+{ "adcl", 0x5EC17020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adcl<.f> 0,ximm,s12 0101110010000001F111ssssssSSSSSS. */ -+{ "adcl", 0x5C817000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adcl<.f> 0,limm,s12 0101111010000001F111ssssssSSSSSS. */ -+{ "adcl", 0x5E817000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adcl<.f> OPERAND_RA,ximm,ximm 0101110000000001F111111100aaaaaa. */ -+{ "adcl", 0x5C017F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* adcl<.f> 0,ximm,ximm 0101110000000001F111111100111110. */ -+{ "adcl", 0x5C017F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* adcl<.f><.cc> 0,ximm,ximm 0101110011000001F1111111000QQQQQ. */ -+{ "adcl", 0x5CC17F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* adcl<.f> OPERAND_RA,limm,limm 0101111000000001F111111110aaaaaa. */ -+{ "adcl", 0x5E017F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adcl<.f> 0,limm,limm 0101111000000001F111111110111110. */ -+{ "adcl", 0x5E017FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adcl<.f><.cc> 0,limm,limm 0101111011000001F1111111100QQQQQ. */ -+{ "adcl", 0x5EC17F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* adcs<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA. */ -+{ "adcs", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adcs<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110. */ -+{ "adcs", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adcs<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ. */ -+{ "adcs", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adcs<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA. */ -+{ "adcs", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcs<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110. */ -+{ "adcs", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcs<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ. */ -+{ "adcs", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adcs<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS. */ -+{ "adcs", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adcs<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA. */ -+{ "adcs", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adcs<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA. */ -+{ "adcs", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adcs<.f> 0,limm,c 0010111001100110F111CCCCCC111110. */ -+{ "adcs", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adcs<.f> 0,b,limm 00101bbb00100110FBBB111110111110. */ -+{ "adcs", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adcs<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ. */ -+{ "adcs", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* adcs<.f><.cc> 0,limm,c 0010111011100110F111CCCCCC0QQQQQ. */ -+{ "adcs", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adcs<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA. */ -+{ "adcs", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcs<.f> 0,limm,u6 0010111001100110F111uuuuuu111110. */ -+{ "adcs", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcs<.f><.cc> 0,limm,u6 0010111011100110F111uuuuuu1QQQQQ. */ -+{ "adcs", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adcs<.f> 0,limm,s12 0010111010100110F111ssssssSSSSSS. */ -+{ "adcs", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adcs<.f> a,limm,limm 0010111000100110F111111110AAAAAA. */ -+{ "adcs", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adcs<.f> 0,limm,limm 0010111000100110F111111110111110. */ -+{ "adcs", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adcs<.f><.cc> 0,limm,limm 0010111011100110F1111111100QQQQQ. */ -+{ "adcs", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add<.f> a,b,c 00100bbb00000000FBBBCCCCCCAAAAAA. */ -+{ "add", 0x20000000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add<.f> 0,b,c 00100bbb00000000FBBBCCCCCC111110. */ -+{ "add", 0x2000003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add<.f><.cc> b,b,c 00100bbb11000000FBBBCCCCCC0QQQQQ. */ -+{ "add", 0x20C00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */ -+{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add<.f> 0,b,u6 00100bbb01000000FBBBuuuuuu111110. */ -+{ "add", 0x2040003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */ -+{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add<.f> b,b,s12 00100bbb10000000FBBBssssssSSSSSS. */ -+{ "add", 0x20800000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add<.f> a,limm,c 0010011000000000F111CCCCCCAAAAAA. */ -+{ "add", 0x26007000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ -+{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add<.f> 0,limm,c 0010011000000000F111CCCCCC111110. */ -+{ "add", 0x2600703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add<.f> 0,b,limm 00100bbb00000000FBBB111110111110. */ -+{ "add", 0x20000FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ -+{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add<.f><.cc> 0,limm,c 0010011011000000F111CCCCCC0QQQQQ. */ -+{ "add", 0x26C07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add<.f> a,limm,u6 0010011001000000F111uuuuuuAAAAAA. */ -+{ "add", 0x26407000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add<.f> 0,limm,u6 0010011001000000F111uuuuuu111110. */ -+{ "add", 0x2640703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add<.f><.cc> 0,limm,u6 0010011011000000F111uuuuuu1QQQQQ. */ -+{ "add", 0x26C07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add<.f> 0,limm,s12 0010011010000000F111ssssssSSSSSS. */ -+{ "add", 0x26807000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add<.f> a,limm,limm 0010011000000000F111111110AAAAAA. */ -+{ "add", 0x26007F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add<.f> 0,limm,limm 0010011000000000F111111110111110. */ -+{ "add", 0x26007FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add<.f><.cc> 0,limm,limm 0010011011000000F1111111100QQQQQ. */ -+{ "add", 0x26C07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add1<.f> a,b,c 00100bbb00010100FBBBCCCCCCAAAAAA. */ -+{ "add1", 0x20140000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add1<.f> 0,b,c 00100bbb00010100FBBBCCCCCC111110. */ -+{ "add1", 0x2014003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add1<.f><.cc> b,b,c 00100bbb11010100FBBBCCCCCC0QQQQQ. */ -+{ "add1", 0x20D40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add1<.f> a,b,u6 00100bbb01010100FBBBuuuuuuAAAAAA. */ -+{ "add1", 0x20540000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1<.f> 0,b,u6 00100bbb01010100FBBBuuuuuu111110. */ -+{ "add1", 0x2054003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1<.f><.cc> b,b,u6 00100bbb11010100FBBBuuuuuu1QQQQQ. */ -+{ "add1", 0x20D40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add1<.f> b,b,s12 00100bbb10010100FBBBssssssSSSSSS. */ -+{ "add1", 0x20940000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add1<.f> a,limm,c 0010011000010100F111CCCCCCAAAAAA. */ -+{ "add1", 0x26147000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add1<.f> a,b,limm 00100bbb00010100FBBB111110AAAAAA. */ -+{ "add1", 0x20140F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add1<.f> 0,limm,c 0010011000010100F111CCCCCC111110. */ -+{ "add1", 0x2614703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add1<.f> 0,b,limm 00100bbb00010100FBBB111110111110. */ -+{ "add1", 0x20140FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add1<.f><.cc> b,b,limm 00100bbb11010100FBBB1111100QQQQQ. */ -+{ "add1", 0x20D40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add1<.f><.cc> 0,limm,c 0010011011010100F111CCCCCC0QQQQQ. */ -+{ "add1", 0x26D47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add1<.f> a,limm,u6 0010011001010100F111uuuuuuAAAAAA. */ -+{ "add1", 0x26547000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1<.f> 0,limm,u6 0010011001010100F111uuuuuu111110. */ -+{ "add1", 0x2654703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1<.f><.cc> 0,limm,u6 0010011011010100F111uuuuuu1QQQQQ. */ -+{ "add1", 0x26D47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add1<.f> 0,limm,s12 0010011010010100F111ssssssSSSSSS. */ -+{ "add1", 0x26947000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add1<.f> a,limm,limm 0010011000010100F111111110AAAAAA. */ -+{ "add1", 0x26147F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add1<.f> 0,limm,limm 0010011000010100F111111110111110. */ -+{ "add1", 0x26147FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add1<.f><.cc> 0,limm,limm 0010011011010100F1111111100QQQQQ. */ -+{ "add1", 0x26D47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add1l<.f> OPERAND_RA,RB,RC 01011bbb00010100FBBBccccccaaaaaa. */ -+{ "add1l", 0x58140000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add1l<.f> 0,RB,RC 01011bbb00010100FBBBcccccc111110. */ -+{ "add1l", 0x5814003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add1l<.f><.cc> OPERAND_RB,RB,RC 01011bbb11010100FBBBcccccc0QQQQQ. */ -+{ "add1l", 0x58D40000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add1l<.f> OPERAND_RA,RB,u6 01011bbb01010100FBBBuuuuuuaaaaaa. */ -+{ "add1l", 0x58540000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1l<.f> 0,RB,u6 01011bbb01010100FBBBuuuuuu111110. */ -+{ "add1l", 0x5854003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1l<.f><.cc> OPERAND_RB,RB,u6 01011bbb11010100FBBBuuuuuu1QQQQQ. */ -+{ "add1l", 0x58D40020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add1l<.f> OPERAND_RB,RB,s12 01011bbb10010100FBBBssssssSSSSSS. */ -+{ "add1l", 0x58940000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add1l<.f> OPERAND_RA,ximm,RC 0101110000010100F111ccccccaaaaaa. */ -+{ "add1l", 0x5C147000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* add1l<.f> OPERAND_RA,RB,ximm 01011bbb00010100FBBB111100aaaaaa. */ -+{ "add1l", 0x58140F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* add1l<.f> 0,ximm,RC 0101110000010100F111cccccc111110. */ -+{ "add1l", 0x5C14703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* add1l<.f> 0,RB,ximm 01011bbb00010100FBBB111100111110. */ -+{ "add1l", 0x58140F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* add1l<.f><.cc> 0,ximm,RC 0101110011010100F111cccccc0QQQQQ. */ -+{ "add1l", 0x5CD47000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add1l<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11010100FBBB1111000QQQQQ. */ -+{ "add1l", 0x58D40F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* add1l<.f> OPERAND_RA,ximm,u6 0101110001010100F111uuuuuuaaaaaa. */ -+{ "add1l", 0x5C547000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1l<.f> 0,ximm,u6 0101110001010100F111uuuuuu111110. */ -+{ "add1l", 0x5C54703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1l<.f><.cc> 0,ximm,u6 0101110011010100F111uuuuuu1QQQQQ. */ -+{ "add1l", 0x5CD47020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add1l<.f> OPERAND_RA,limm,RC 0101111000010100F111ccccccaaaaaa. */ -+{ "add1l", 0x5E147000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add1l<.f> OPERAND_RA,RB,limm 01011bbb00010100FBBB111110aaaaaa. */ -+{ "add1l", 0x58140F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add1l<.f> 0,limm,RC 0101111000010100F111cccccc111110. */ -+{ "add1l", 0x5E14703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add1l<.f> 0,RB,limm 01011bbb00010100FBBB111110111110. */ -+{ "add1l", 0x58140FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add1l<.f><.cc> 0,limm,RC 0101111011010100F111cccccc0QQQQQ. */ -+{ "add1l", 0x5ED47000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add1l<.f><.cc> OPERAND_RB,RB,limm 01011bbb11010100FBBB1111100QQQQQ. */ -+{ "add1l", 0x58D40F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add1l<.f> OPERAND_RA,limm,u6 0101111001010100F111uuuuuuaaaaaa. */ -+{ "add1l", 0x5E547000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1l<.f> 0,limm,u6 0101111001010100F111uuuuuu111110. */ -+{ "add1l", 0x5E54703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1l<.f><.cc> 0,limm,u6 0101111011010100F111uuuuuu1QQQQQ. */ -+{ "add1l", 0x5ED47020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add1l<.f> 0,ximm,s12 0101110010010100F111ssssssSSSSSS. */ -+{ "add1l", 0x5C947000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add1l<.f> 0,limm,s12 0101111010010100F111ssssssSSSSSS. */ -+{ "add1l", 0x5E947000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add1l<.f> OPERAND_RA,ximm,ximm 0101110000010100F111111100aaaaaa. */ -+{ "add1l", 0x5C147F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* add1l<.f> 0,ximm,ximm 0101110000010100F111111100111110. */ -+{ "add1l", 0x5C147F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* add1l<.f><.cc> 0,ximm,ximm 0101110011010100F1111111000QQQQQ. */ -+{ "add1l", 0x5CD47F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* add1l<.f> OPERAND_RA,limm,limm 0101111000010100F111111110aaaaaa. */ -+{ "add1l", 0x5E147F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add1l<.f> 0,limm,limm 0101111000010100F111111110111110. */ -+{ "add1l", 0x5E147FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add1l<.f><.cc> 0,limm,limm 0101111011010100F1111111100QQQQQ. */ -+{ "add1l", 0x5ED47F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add1_s b,b,c 01111bbbccc10100. */ -+{ "add1_s", 0x00007814, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* add2<.f> a,b,c 00100bbb00010101FBBBCCCCCCAAAAAA. */ -+{ "add2", 0x20150000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add2<.f> 0,b,c 00100bbb00010101FBBBCCCCCC111110. */ -+{ "add2", 0x2015003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add2<.f><.cc> b,b,c 00100bbb11010101FBBBCCCCCC0QQQQQ. */ -+{ "add2", 0x20D50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add2<.f> a,b,u6 00100bbb01010101FBBBuuuuuuAAAAAA. */ -+{ "add2", 0x20550000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2<.f> 0,b,u6 00100bbb01010101FBBBuuuuuu111110. */ -+{ "add2", 0x2055003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2<.f><.cc> b,b,u6 00100bbb11010101FBBBuuuuuu1QQQQQ. */ -+{ "add2", 0x20D50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add2<.f> b,b,s12 00100bbb10010101FBBBssssssSSSSSS. */ -+{ "add2", 0x20950000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add2<.f> a,limm,c 0010011000010101F111CCCCCCAAAAAA. */ -+{ "add2", 0x26157000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add2<.f> a,b,limm 00100bbb00010101FBBB111110AAAAAA. */ -+{ "add2", 0x20150F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add2<.f> 0,limm,c 0010011000010101F111CCCCCC111110. */ -+{ "add2", 0x2615703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add2<.f> 0,b,limm 00100bbb00010101FBBB111110111110. */ -+{ "add2", 0x20150FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add2<.f><.cc> b,b,limm 00100bbb11010101FBBB1111100QQQQQ. */ -+{ "add2", 0x20D50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add2<.f><.cc> 0,limm,c 0010011011010101F111CCCCCC0QQQQQ. */ -+{ "add2", 0x26D57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add2<.f> a,limm,u6 0010011001010101F111uuuuuuAAAAAA. */ -+{ "add2", 0x26557000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2<.f> 0,limm,u6 0010011001010101F111uuuuuu111110. */ -+{ "add2", 0x2655703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2<.f><.cc> 0,limm,u6 0010011011010101F111uuuuuu1QQQQQ. */ -+{ "add2", 0x26D57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add2<.f> 0,limm,s12 0010011010010101F111ssssssSSSSSS. */ -+{ "add2", 0x26957000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add2<.f> a,limm,limm 0010011000010101F111111110AAAAAA. */ -+{ "add2", 0x26157F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add2<.f> 0,limm,limm 0010011000010101F111111110111110. */ -+{ "add2", 0x26157FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add2<.f><.cc> 0,limm,limm 0010011011010101F1111111100QQQQQ. */ -+{ "add2", 0x26D57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add2l<.f> OPERAND_RA,RB,RC 01011bbb00010101FBBBccccccaaaaaa. */ -+{ "add2l", 0x58150000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add2l<.f> 0,RB,RC 01011bbb00010101FBBBcccccc111110. */ -+{ "add2l", 0x5815003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add2l<.f><.cc> OPERAND_RB,RB,RC 01011bbb11010101FBBBcccccc0QQQQQ. */ -+{ "add2l", 0x58D50000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add2l<.f> OPERAND_RA,RB,u6 01011bbb01010101FBBBuuuuuuaaaaaa. */ -+{ "add2l", 0x58550000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2l<.f> 0,RB,u6 01011bbb01010101FBBBuuuuuu111110. */ -+{ "add2l", 0x5855003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2l<.f><.cc> OPERAND_RB,RB,u6 01011bbb11010101FBBBuuuuuu1QQQQQ. */ -+{ "add2l", 0x58D50020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add2l<.f> OPERAND_RB,RB,s12 01011bbb10010101FBBBssssssSSSSSS. */ -+{ "add2l", 0x58950000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add2l<.f> OPERAND_RA,ximm,RC 0101110000010101F111ccccccaaaaaa. */ -+{ "add2l", 0x5C157000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* add2l<.f> OPERAND_RA,RB,ximm 01011bbb00010101FBBB111100aaaaaa. */ -+{ "add2l", 0x58150F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* add2l<.f> 0,ximm,RC 0101110000010101F111cccccc111110. */ -+{ "add2l", 0x5C15703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* add2l<.f> 0,RB,ximm 01011bbb00010101FBBB111100111110. */ -+{ "add2l", 0x58150F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* add2l<.f><.cc> 0,ximm,RC 0101110011010101F111cccccc0QQQQQ. */ -+{ "add2l", 0x5CD57000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add2l<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11010101FBBB1111000QQQQQ. */ -+{ "add2l", 0x58D50F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* add2l<.f> OPERAND_RA,ximm,u6 0101110001010101F111uuuuuuaaaaaa. */ -+{ "add2l", 0x5C557000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2l<.f> 0,ximm,u6 0101110001010101F111uuuuuu111110. */ -+{ "add2l", 0x5C55703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2l<.f><.cc> 0,ximm,u6 0101110011010101F111uuuuuu1QQQQQ. */ -+{ "add2l", 0x5CD57020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add2l<.f> OPERAND_RA,limm,RC 0101111000010101F111ccccccaaaaaa. */ -+{ "add2l", 0x5E157000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add2l<.f> OPERAND_RA,RB,limm 01011bbb00010101FBBB111110aaaaaa. */ -+{ "add2l", 0x58150F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add2l<.f> 0,limm,RC 0101111000010101F111cccccc111110. */ -+{ "add2l", 0x5E15703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add2l<.f> 0,RB,limm 01011bbb00010101FBBB111110111110. */ -+{ "add2l", 0x58150FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add2l<.f><.cc> 0,limm,RC 0101111011010101F111cccccc0QQQQQ. */ -+{ "add2l", 0x5ED57000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add2l<.f><.cc> OPERAND_RB,RB,limm 01011bbb11010101FBBB1111100QQQQQ. */ -+{ "add2l", 0x58D50F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add2l<.f> OPERAND_RA,limm,u6 0101111001010101F111uuuuuuaaaaaa. */ -+{ "add2l", 0x5E557000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2l<.f> 0,limm,u6 0101111001010101F111uuuuuu111110. */ -+{ "add2l", 0x5E55703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2l<.f><.cc> 0,limm,u6 0101111011010101F111uuuuuu1QQQQQ. */ -+{ "add2l", 0x5ED57020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add2l<.f> 0,ximm,s12 0101110010010101F111ssssssSSSSSS. */ -+{ "add2l", 0x5C957000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add2l<.f> 0,limm,s12 0101111010010101F111ssssssSSSSSS. */ -+{ "add2l", 0x5E957000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add2l<.f> OPERAND_RA,ximm,ximm 0101110000010101F111111100aaaaaa. */ -+{ "add2l", 0x5C157F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* add2l<.f> 0,ximm,ximm 0101110000010101F111111100111110. */ -+{ "add2l", 0x5C157F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* add2l<.f><.cc> 0,ximm,ximm 0101110011010101F1111111000QQQQQ. */ -+{ "add2l", 0x5CD57F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* add2l<.f> OPERAND_RA,limm,limm 0101111000010101F111111110aaaaaa. */ -+{ "add2l", 0x5E157F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add2l<.f> 0,limm,limm 0101111000010101F111111110111110. */ -+{ "add2l", 0x5E157FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add2l<.f><.cc> 0,limm,limm 0101111011010101F1111111100QQQQQ. */ -+{ "add2l", 0x5ED57F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add2_s b,b,c 01111bbbccc10101. */ -+{ "add2_s", 0x00007815, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* add3<.f> a,b,c 00100bbb00010110FBBBCCCCCCAAAAAA. */ -+{ "add3", 0x20160000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add3<.f> 0,b,c 00100bbb00010110FBBBCCCCCC111110. */ -+{ "add3", 0x2016003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add3<.f><.cc> b,b,c 00100bbb11010110FBBBCCCCCC0QQQQQ. */ -+{ "add3", 0x20D60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add3<.f> a,b,u6 00100bbb01010110FBBBuuuuuuAAAAAA. */ -+{ "add3", 0x20560000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3<.f> 0,b,u6 00100bbb01010110FBBBuuuuuu111110. */ -+{ "add3", 0x2056003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3<.f><.cc> b,b,u6 00100bbb11010110FBBBuuuuuu1QQQQQ. */ -+{ "add3", 0x20D60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add3<.f> b,b,s12 00100bbb10010110FBBBssssssSSSSSS. */ -+{ "add3", 0x20960000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add3<.f> a,limm,c 0010011000010110F111CCCCCCAAAAAA. */ -+{ "add3", 0x26167000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add3<.f> a,b,limm 00100bbb00010110FBBB111110AAAAAA. */ -+{ "add3", 0x20160F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add3<.f> 0,limm,c 0010011000010110F111CCCCCC111110. */ -+{ "add3", 0x2616703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add3<.f> 0,b,limm 00100bbb00010110FBBB111110111110. */ -+{ "add3", 0x20160FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add3<.f><.cc> b,b,limm 00100bbb11010110FBBB1111100QQQQQ. */ -+{ "add3", 0x20D60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add3<.f><.cc> 0,limm,c 0010011011010110F111CCCCCC0QQQQQ. */ -+{ "add3", 0x26D67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add3<.f> a,limm,u6 0010011001010110F111uuuuuuAAAAAA. */ -+{ "add3", 0x26567000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3<.f> 0,limm,u6 0010011001010110F111uuuuuu111110. */ -+{ "add3", 0x2656703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3<.f><.cc> 0,limm,u6 0010011011010110F111uuuuuu1QQQQQ. */ -+{ "add3", 0x26D67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add3<.f> 0,limm,s12 0010011010010110F111ssssssSSSSSS. */ -+{ "add3", 0x26967000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add3<.f> a,limm,limm 0010011000010110F111111110AAAAAA. */ -+{ "add3", 0x26167F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add3<.f> 0,limm,limm 0010011000010110F111111110111110. */ -+{ "add3", 0x26167FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add3<.f><.cc> 0,limm,limm 0010011011010110F1111111100QQQQQ. */ -+{ "add3", 0x26D67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add3l<.f> OPERAND_RA,RB,RC 01011bbb00010110FBBBccccccaaaaaa. */ -+{ "add3l", 0x58160000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add3l<.f> 0,RB,RC 01011bbb00010110FBBBcccccc111110. */ -+{ "add3l", 0x5816003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add3l<.f><.cc> OPERAND_RB,RB,RC 01011bbb11010110FBBBcccccc0QQQQQ. */ -+{ "add3l", 0x58D60000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add3l<.f> OPERAND_RA,RB,u6 01011bbb01010110FBBBuuuuuuaaaaaa. */ -+{ "add3l", 0x58560000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3l<.f> 0,RB,u6 01011bbb01010110FBBBuuuuuu111110. */ -+{ "add3l", 0x5856003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3l<.f><.cc> OPERAND_RB,RB,u6 01011bbb11010110FBBBuuuuuu1QQQQQ. */ -+{ "add3l", 0x58D60020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add3l<.f> OPERAND_RB,RB,s12 01011bbb10010110FBBBssssssSSSSSS. */ -+{ "add3l", 0x58960000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add3l<.f> OPERAND_RA,ximm,RC 0101110000010110F111ccccccaaaaaa. */ -+{ "add3l", 0x5C167000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* add3l<.f> OPERAND_RA,RB,ximm 01011bbb00010110FBBB111100aaaaaa. */ -+{ "add3l", 0x58160F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* add3l<.f> 0,ximm,RC 0101110000010110F111cccccc111110. */ -+{ "add3l", 0x5C16703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* add3l<.f> 0,RB,ximm 01011bbb00010110FBBB111100111110. */ -+{ "add3l", 0x58160F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* add3l<.f><.cc> 0,ximm,RC 0101110011010110F111cccccc0QQQQQ. */ -+{ "add3l", 0x5CD67000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add3l<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11010110FBBB1111000QQQQQ. */ -+{ "add3l", 0x58D60F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* add3l<.f> OPERAND_RA,ximm,u6 0101110001010110F111uuuuuuaaaaaa. */ -+{ "add3l", 0x5C567000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3l<.f> 0,ximm,u6 0101110001010110F111uuuuuu111110. */ -+{ "add3l", 0x5C56703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3l<.f><.cc> 0,ximm,u6 0101110011010110F111uuuuuu1QQQQQ. */ -+{ "add3l", 0x5CD67020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add3l<.f> OPERAND_RA,limm,RC 0101111000010110F111ccccccaaaaaa. */ -+{ "add3l", 0x5E167000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add3l<.f> OPERAND_RA,RB,limm 01011bbb00010110FBBB111110aaaaaa. */ -+{ "add3l", 0x58160F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add3l<.f> 0,limm,RC 0101111000010110F111cccccc111110. */ -+{ "add3l", 0x5E16703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add3l<.f> 0,RB,limm 01011bbb00010110FBBB111110111110. */ -+{ "add3l", 0x58160FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add3l<.f><.cc> 0,limm,RC 0101111011010110F111cccccc0QQQQQ. */ -+{ "add3l", 0x5ED67000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add3l<.f><.cc> OPERAND_RB,RB,limm 01011bbb11010110FBBB1111100QQQQQ. */ -+{ "add3l", 0x58D60F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add3l<.f> OPERAND_RA,limm,u6 0101111001010110F111uuuuuuaaaaaa. */ -+{ "add3l", 0x5E567000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3l<.f> 0,limm,u6 0101111001010110F111uuuuuu111110. */ -+{ "add3l", 0x5E56703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3l<.f><.cc> 0,limm,u6 0101111011010110F111uuuuuu1QQQQQ. */ -+{ "add3l", 0x5ED67020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add3l<.f> 0,ximm,s12 0101110010010110F111ssssssSSSSSS. */ -+{ "add3l", 0x5C967000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add3l<.f> 0,limm,s12 0101111010010110F111ssssssSSSSSS. */ -+{ "add3l", 0x5E967000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add3l<.f> OPERAND_RA,ximm,ximm 0101110000010110F111111100aaaaaa. */ -+{ "add3l", 0x5C167F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* add3l<.f> 0,ximm,ximm 0101110000010110F111111100111110. */ -+{ "add3l", 0x5C167F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* add3l<.f><.cc> 0,ximm,ximm 0101110011010110F1111111000QQQQQ. */ -+{ "add3l", 0x5CD67F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* add3l<.f> OPERAND_RA,limm,limm 0101111000010110F111111110aaaaaa. */ -+{ "add3l", 0x5E167F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add3l<.f> 0,limm,limm 0101111000010110F111111110111110. */ -+{ "add3l", 0x5E167FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add3l<.f><.cc> 0,limm,limm 0101111011010110F1111111100QQQQQ. */ -+{ "add3l", 0x5ED67F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add3_s b,b,c 01111bbbccc10110. */ -+{ "add3_s", 0x00007816, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* addhl OPERAND_RA,RB,RC 01011bbb001011100BBBccccccaaaaaa. */ -+{ "addhl", 0x582E0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* addhl 0,RB,RC 01011bbb001011100BBBcccccc111110. */ -+{ "addhl", 0x582E003E, 0xF8FF803F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* addhl<.cc> OPERAND_RB,RB,RC 01011bbb111011100BBBcccccc0QQQQQ. */ -+{ "addhl", 0x58EE0000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* addhl OPERAND_RA,RB,u6 01011bbb011011100BBBuuuuuuaaaaaa. */ -+{ "addhl", 0x586E0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* addhl 0,RB,u6 01011bbb011011100BBBuuuuuu111110. */ -+{ "addhl", 0x586E003E, 0xF8FF803F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* addhl<.cc> OPERAND_RB,RB,u6 01011bbb111011100BBBuuuuuu1QQQQQ. */ -+{ "addhl", 0x58EE0020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* addhl OPERAND_RB,RB,s12 01011bbb101011100BBBssssssSSSSSS. */ -+{ "addhl", 0x58AE0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* addhl OPERAND_RA,ximm,RC 01011100001011100111ccccccaaaaaa. */ -+{ "addhl", 0x5C2E7000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* addhl OPERAND_RA,RB,ximm 01011bbb001011100BBB111100aaaaaa. */ -+{ "addhl", 0x582E0F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* addhl 0,ximm,RC 01011100001011100111cccccc111110. */ -+{ "addhl", 0x5C2E703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* addhl 0,RB,ximm 01011bbb001011100BBB111100111110. */ -+{ "addhl", 0x582E0F3E, 0xF8FF8FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* addhl<.cc> 0,ximm,RC 01011100111011100111cccccc0QQQQQ. */ -+{ "addhl", 0x5CEE7000, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_CC }}, -+ -+/* addhl<.cc> OPERAND_RB,RB,ximm 01011bbb111011100BBB1111000QQQQQ. */ -+{ "addhl", 0x58EE0F00, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_CC }}, -+ -+/* addhl OPERAND_RA,ximm,u6 01011100011011100111uuuuuuaaaaaa. */ -+{ "addhl", 0x5C6E7000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* addhl 0,ximm,u6 01011100011011100111uuuuuu111110. */ -+{ "addhl", 0x5C6E703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* addhl<.cc> 0,ximm,u6 01011100111011100111uuuuuu1QQQQQ. */ -+{ "addhl", 0x5CEE7020, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* addhl OPERAND_RA,limm,RC 01011110001011100111ccccccaaaaaa. */ -+{ "addhl", 0x5E2E7000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* addhl OPERAND_RA,RB,limm 01011bbb001011100BBB111110aaaaaa. */ -+{ "addhl", 0x582E0F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* addhl 0,limm,RC 01011110001011100111cccccc111110. */ -+{ "addhl", 0x5E2E703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* addhl 0,RB,limm 01011bbb001011100BBB111110111110. */ -+{ "addhl", 0x582E0FBE, 0xF8FF8FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* addhl<.cc> 0,limm,RC 01011110111011100111cccccc0QQQQQ. */ -+{ "addhl", 0x5EEE7000, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* addhl<.cc> OPERAND_RB,RB,limm 01011bbb111011100BBB1111100QQQQQ. */ -+{ "addhl", 0x58EE0F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* addhl OPERAND_RA,limm,u6 01011110011011100111uuuuuuaaaaaa. */ -+{ "addhl", 0x5E6E7000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* addhl 0,limm,u6 01011110011011100111uuuuuu111110. */ -+{ "addhl", 0x5E6E703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* addhl<.cc> 0,limm,u6 01011110111011100111uuuuuu1QQQQQ. */ -+{ "addhl", 0x5EEE7020, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* addhl 0,ximm,s12 01011100101011100111ssssssSSSSSS. */ -+{ "addhl", 0x5CAE7000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* addhl 0,limm,s12 01011110101011100111ssssssSSSSSS. */ -+{ "addhl", 0x5EAE7000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* addhl OPERAND_RA,ximm,ximm 01011100001011100111111100aaaaaa. */ -+{ "addhl", 0x5C2E7F00, 0xFFFFFFC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { 0 }}, -+ -+/* addhl 0,ximm,ximm 01011100001011100111111100111110. */ -+{ "addhl", 0x5C2E7F3E, 0xFFFFFFFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { 0 }}, -+ -+/* addhl<.cc> 0,ximm,ximm 010111001110111001111111000QQQQQ. */ -+{ "addhl", 0x5CEE7F00, 0xFFFFFFE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_CC }}, -+ -+/* addhl OPERAND_RA,limm,limm 01011110001011100111111110aaaaaa. */ -+{ "addhl", 0x5E2E7F80, 0xFFFFFFC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* addhl 0,limm,limm 01011110001011100111111110111110. */ -+{ "addhl", 0x5E2E7FBE, 0xFFFFFFFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* addhl<.cc> 0,limm,limm 010111101110111001111111100QQQQQ. */ -+{ "addhl", 0x5EEE7F80, 0xFFFFFFE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* addhl_s h,PCL,ximm 01110011hhh010HH. */ -+{ "addhl_s", 0x00007308, 0x0000FF1C, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RH_S, OPERAND_PCL_S, OPERAND_XIMM_S }, { 0 }}, -+ -+/* addhl_s h,h,limm 01110001hhh010HH. */ -+{ "addhl_s", 0x00007108, 0x0000FF1C, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RH_S, OPERAND_RH_Sdup, OPERAND_HI32 }, { 0 }}, -+ -+/* addl<.f> OPERAND_RA,RB,RC 01011bbb00000000FBBBccccccaaaaaa. */ -+{ "addl", 0x58000000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* addl<.f> 0,RB,RC 01011bbb00000000FBBBcccccc111110. */ -+{ "addl", 0x5800003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* addl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11000000FBBBcccccc0QQQQQ. */ -+{ "addl", 0x58C00000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* addl<.f> OPERAND_RA,RB,u6 01011bbb01000000FBBBuuuuuuaaaaaa. */ -+{ "addl", 0x58400000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addl<.f> 0,RB,u6 01011bbb01000000FBBBuuuuuu111110. */ -+{ "addl", 0x5840003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11000000FBBBuuuuuu1QQQQQ. */ -+{ "addl", 0x58C00020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* addl<.f> OPERAND_RB,RB,s12 01011bbb10000000FBBBssssssSSSSSS. */ -+{ "addl", 0x58800000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* addl<.f> OPERAND_RA,ximm,RC 0101110000000000F111ccccccaaaaaa. */ -+{ "addl", 0x5C007000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* addl<.f> OPERAND_RA,RB,ximm 01011bbb00000000FBBB111100aaaaaa. */ -+{ "addl", 0x58000F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* addl<.f> 0,ximm,RC 0101110000000000F111cccccc111110. */ -+{ "addl", 0x5C00703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* addl<.f> 0,RB,ximm 01011bbb00000000FBBB111100111110. */ -+{ "addl", 0x58000F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* addl<.f><.cc> 0,ximm,RC 0101110011000000F111cccccc0QQQQQ. */ -+{ "addl", 0x5CC07000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* addl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11000000FBBB1111000QQQQQ. */ -+{ "addl", 0x58C00F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* addl<.f> OPERAND_RA,ximm,u6 0101110001000000F111uuuuuuaaaaaa. */ -+{ "addl", 0x5C407000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addl<.f> 0,ximm,u6 0101110001000000F111uuuuuu111110. */ -+{ "addl", 0x5C40703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addl<.f><.cc> 0,ximm,u6 0101110011000000F111uuuuuu1QQQQQ. */ -+{ "addl", 0x5CC07020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* addl<.f> OPERAND_RA,limm,RC 0101111000000000F111ccccccaaaaaa. */ -+{ "addl", 0x5E007000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* addl<.f> OPERAND_RA,RB,limm 01011bbb00000000FBBB111110aaaaaa. */ -+{ "addl", 0x58000F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* addl<.f> 0,limm,RC 0101111000000000F111cccccc111110. */ -+{ "addl", 0x5E00703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* addl<.f> 0,RB,limm 01011bbb00000000FBBB111110111110. */ -+{ "addl", 0x58000FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* addl<.f><.cc> 0,limm,RC 0101111011000000F111cccccc0QQQQQ. */ -+{ "addl", 0x5EC07000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* addl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11000000FBBB1111100QQQQQ. */ -+{ "addl", 0x58C00F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* addl<.f> OPERAND_RA,limm,u6 0101111001000000F111uuuuuuaaaaaa. */ -+{ "addl", 0x5E407000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addl<.f> 0,limm,u6 0101111001000000F111uuuuuu111110. */ -+{ "addl", 0x5E40703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addl<.f><.cc> 0,limm,u6 0101111011000000F111uuuuuu1QQQQQ. */ -+{ "addl", 0x5EC07020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* addl<.f> 0,ximm,s12 0101110010000000F111ssssssSSSSSS. */ -+{ "addl", 0x5C807000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* addl<.f> 0,limm,s12 0101111010000000F111ssssssSSSSSS. */ -+{ "addl", 0x5E807000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* addl<.f> OPERAND_RA,ximm,ximm 0101110000000000F111111100aaaaaa. */ -+{ "addl", 0x5C007F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* addl<.f> 0,ximm,ximm 0101110000000000F111111100111110. */ -+{ "addl", 0x5C007F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* addl<.f><.cc> 0,ximm,ximm 0101110011000000F1111111000QQQQQ. */ -+{ "addl", 0x5CC07F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* addl<.f> OPERAND_RA,limm,limm 0101111000000000F111111110aaaaaa. */ -+{ "addl", 0x5E007F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* addl<.f> 0,limm,limm 0101111000000000F111111110111110. */ -+{ "addl", 0x5E007FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* addl<.f><.cc> 0,limm,limm 0101111011000000F1111111100QQQQQ. */ -+{ "addl", 0x5EC07F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* addl_s SP,SP,u9 11000UU0101uuuuu. */ -+{ "addl_s", 0x0000C0A0, 0x0000F9E0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM9_A32_11_S }, { 0 }}, -+ -+/* addl_s b,b,c 01111bbbccc00001. */ -+{ "addl_s", 0x00007801, 0x0000F81F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* addl_s b,SP,u7 11000bbb100uuuuu. */ -+{ "addl_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S }, { 0 }}, -+ -+/* addl_s R0,GP,s11 1100111sssssssss. */ -+{ "addl_s", 0x0000CE00, 0x0000FE00, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_R0_S, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S }, { 0 }}, -+ -+/* addl_s h,h,LO32 01110001hhh110HH. */ -+{ "addl_s", 0x00007118, 0x0000FF1C, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RH_S, OPERAND_RH_Sdup, OPERAND_LO32 }, { 0 }}, -+ -+/* addl_s h,PCL,LO32 01110011hhh110HH. */ -+{ "addl_s", 0x00007318, 0x0000FF1C, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RH_S, OPERAND_PCL_S, OPERAND_LO32 }, { 0 }}, -+ -+/* adds<.f> a,b,c 00101bbb00000110FBBBCCCCCCAAAAAA. */ -+{ "adds", 0x28060000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adds<.f> 0,b,c 00101bbb00000110FBBBCCCCCC111110. */ -+{ "adds", 0x2806003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adds<.f><.cc> b,b,c 00101bbb11000110FBBBCCCCCC0QQQQQ. */ -+{ "adds", 0x28C60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adds<.f> a,b,u6 00101bbb01000110FBBBuuuuuuAAAAAA. */ -+{ "adds", 0x28460000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adds<.f> 0,b,u6 00101bbb01000110FBBBuuuuuu111110. */ -+{ "adds", 0x2846003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adds<.f><.cc> b,b,u6 00101bbb11000110FBBBuuuuuu1QQQQQ. */ -+{ "adds", 0x28C60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adds<.f> b,b,s12 00101bbb10000110FBBBssssssSSSSSS. */ -+{ "adds", 0x28860000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adds<.f> a,limm,c 0010111000000110F111CCCCCCAAAAAA. */ -+{ "adds", 0x2E067000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adds<.f> a,b,limm 00101bbb00000110FBBB111110AAAAAA. */ -+{ "adds", 0x28060F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adds<.f> 0,limm,c 0010111000000110F111CCCCCC111110. */ -+{ "adds", 0x2E06703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adds<.f> 0,b,limm 00101bbb00000110FBBB111110111110. */ -+{ "adds", 0x28060FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adds<.f><.cc> b,b,limm 00101bbb11000110FBBB1111100QQQQQ. */ -+{ "adds", 0x28C60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* adds<.f><.cc> 0,limm,c 0010111011000110F111CCCCCC0QQQQQ. */ -+{ "adds", 0x2EC67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adds<.f> a,limm,u6 0010111001000110F111uuuuuuAAAAAA. */ -+{ "adds", 0x2E467000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adds<.f> 0,limm,u6 0010111001000110F111uuuuuu111110. */ -+{ "adds", 0x2E46703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adds<.f><.cc> 0,limm,u6 0010111011000110F111uuuuuu1QQQQQ. */ -+{ "adds", 0x2EC67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adds<.f> 0,limm,s12 0010111010000110F111ssssssSSSSSS. */ -+{ "adds", 0x2E867000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adds<.f> a,limm,limm 0010111000000110F111111110AAAAAA. */ -+{ "adds", 0x2E067F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adds<.f> 0,limm,limm 0010111000000110F111111110111110. */ -+{ "adds", 0x2E067FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adds<.f><.cc> 0,limm,limm 0010111011000110F1111111100QQQQQ. */ -+{ "adds", 0x2EC67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add_s a,b,c 01100bbbccc11aaa. */ -+{ "add_s", 0x00006018, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* add_s b,b,h 01110bbbhhh000HH. */ -+{ "add_s", 0x00007000, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RH_S }, { 0 }}, -+ -+/* add_s h,h,s3 01110ssshhh001HH. */ -+{ "add_s", 0x00007004, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RH_S, OPERAND_RH_Sdup, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* add_s c,b,u3 01101bbbccc00uuu. */ -+{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, -+ -+/* add_s R0,b,u6 01001bbb0UUU1uuu. */ -+{ "add_s", 0x00004808, 0x0000F888, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, CD2, { OPERAND_R0_S, OPERAND_RB_S, OPERAND_UIMM6_13_S }, { 0 }}, -+ -+/* add_s R1,b,u6 01001bbb1UUU1uuu. */ -+{ "add_s", 0x00004888, 0x0000F888, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, CD2, { OPERAND_R1_S, OPERAND_RB_S, OPERAND_UIMM6_13_S }, { 0 }}, -+ -+/* add_s b,b,limm 01110bbb11000011. */ -+{ "add_s", 0x000070C3, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_LIMM_S }, { 0 }}, -+ -+/* add_s 0,limm,s3 01110sss11000111. */ -+{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA_S, OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR. */ -+{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> b,c 00100bbb11100111RBBBCCCCCC0QQQQQ. */ -+{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex b,u6 00100bbb01100111RBBBuuuuuuRRRRRR. */ -+{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> b,u6 00100bbb11100111RBBBuuuuuu1QQQQQ. */ -+{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex b,s12 00100bbb10100111RBBBssssssSSSSSS. */ -+{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex limm,c 0010011000100111R111CCCCCCRRRRRR. */ -+{ "aex", 0x26277000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex b,limm 00100bbb00100111RBBB111110RRRRRR. */ -+{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> limm,c 0010011011100111R111CCCCCC0QQQQQ. */ -+{ "aex", 0x26E77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex<.cc> b,limm 00100bbb11100111RBBB1111100QQQQQ. */ -+{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex limm,u6 0010011001100111R111uuuuuuRRRRRR. */ -+{ "aex", 0x26677000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> limm,u6 0010011011100111R111uuuuuu1QQQQQ. */ -+{ "aex", 0x26E77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex limm,s12 0010011010100111R111ssssssSSSSSS. */ -+{ "aex", 0x26A77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex limm,limm 0010011000100111R111111110RRRRRR. */ -+{ "aex", 0x26277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> limm,limm 0010011011100111R1111111100QQQQQ. */ -+{ "aex", 0x26E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aexl OPERAND_RB,RC 01011bbb001001110BBBccccccRRRRRR. */ -+{ "aexl", 0x58270000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aexl<.cc> OPERAND_RB,RC 01011bbb111001110BBBcccccc0QQQQQ. */ -+{ "aexl", 0x58E70000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aexl OPERAND_RB,u6 01011bbb011001110BBBuuuuuuRRRRRR. */ -+{ "aexl", 0x58670000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aexl<.cc> OPERAND_RB,u6 01011bbb111001110BBBuuuuuu1QQQQQ. */ -+{ "aexl", 0x58E70020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aexl OPERAND_RB,s12 01011bbb101001110BBBssssssSSSSSS. */ -+{ "aexl", 0x58A70000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aexl OPERAND_RB,ximm 01011bbb001001110BBB111100RRRRRR. */ -+{ "aexl", 0x58270F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_XIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aexl<.cc> OPERAND_RB,ximm 01011bbb111001110BBB1111000QQQQQ. */ -+{ "aexl", 0x58E70F00, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_XIMM, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aexl OPERAND_RB,limm 01011bbb001001110BBB111110RRRRRR. */ -+{ "aexl", 0x58270F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aexl<.cc> OPERAND_RB,limm 01011bbb111001110BBB1111100QQQQQ. */ -+{ "aexl", 0x58E70F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* and<.f> a,b,c 00100bbb00000100FBBBCCCCCCAAAAAA. */ -+{ "and", 0x20040000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* and<.f> 0,b,c 00100bbb00000100FBBBCCCCCC111110. */ -+{ "and", 0x2004003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* and<.f><.cc> b,b,c 00100bbb11000100FBBBCCCCCC0QQQQQ. */ -+{ "and", 0x20C40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* and<.f> a,b,u6 00100bbb01000100FBBBuuuuuuAAAAAA. */ -+{ "and", 0x20440000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* and<.f> 0,b,u6 00100bbb01000100FBBBuuuuuu111110. */ -+{ "and", 0x2044003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* and<.f><.cc> b,b,u6 00100bbb11000100FBBBuuuuuu1QQQQQ. */ -+{ "and", 0x20C40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* and<.f> b,b,s12 00100bbb10000100FBBBssssssSSSSSS. */ -+{ "and", 0x20840000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* and<.f> a,limm,c 0010011000000100F111CCCCCCAAAAAA. */ -+{ "and", 0x26047000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* and<.f> a,b,limm 00100bbb00000100FBBB111110AAAAAA. */ -+{ "and", 0x20040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* and<.f> 0,limm,c 0010011000000100F111CCCCCC111110. */ -+{ "and", 0x2604703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* and<.f> 0,b,limm 00100bbb00000100FBBB111110111110. */ -+{ "and", 0x20040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* and<.f><.cc> b,b,limm 00100bbb11000100FBBB1111100QQQQQ. */ -+{ "and", 0x20C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* and<.f><.cc> 0,limm,c 0010011011000100F111CCCCCC0QQQQQ. */ -+{ "and", 0x26C47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* and<.f> a,limm,u6 0010011001000100F111uuuuuuAAAAAA. */ -+{ "and", 0x26447000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* and<.f> 0,limm,u6 0010011001000100F111uuuuuu111110. */ -+{ "and", 0x2644703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* and<.f><.cc> 0,limm,u6 0010011011000100F111uuuuuu1QQQQQ. */ -+{ "and", 0x26C47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* and<.f> 0,limm,s12 0010011010000100F111ssssssSSSSSS. */ -+{ "and", 0x26847000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* and<.f> a,limm,limm 0010011000000100F111111110AAAAAA. */ -+{ "and", 0x26047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* and<.f> 0,limm,limm 0010011000000100F111111110111110. */ -+{ "and", 0x26047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* and<.f><.cc> 0,limm,limm 0010011011000100F1111111100QQQQQ. */ -+{ "and", 0x26C47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* andl<.f> OPERAND_RA,RB,RC 01011bbb00000100FBBBccccccaaaaaa. */ -+{ "andl", 0x58040000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* andl<.f> 0,RB,RC 01011bbb00000100FBBBcccccc111110. */ -+{ "andl", 0x5804003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* andl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11000100FBBBcccccc0QQQQQ. */ -+{ "andl", 0x58C40000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* andl<.f> OPERAND_RA,RB,u6 01011bbb01000100FBBBuuuuuuaaaaaa. */ -+{ "andl", 0x58440000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* andl<.f> 0,RB,u6 01011bbb01000100FBBBuuuuuu111110. */ -+{ "andl", 0x5844003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* andl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11000100FBBBuuuuuu1QQQQQ. */ -+{ "andl", 0x58C40020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* andl<.f> OPERAND_RB,RB,s12 01011bbb10000100FBBBssssssSSSSSS. */ -+{ "andl", 0x58840000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* andl<.f> OPERAND_RA,ximm,RC 0101110000000100F111ccccccaaaaaa. */ -+{ "andl", 0x5C047000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* andl<.f> OPERAND_RA,RB,ximm 01011bbb00000100FBBB111100aaaaaa. */ -+{ "andl", 0x58040F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* andl<.f> 0,ximm,RC 0101110000000100F111cccccc111110. */ -+{ "andl", 0x5C04703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* andl<.f> 0,RB,ximm 01011bbb00000100FBBB111100111110. */ -+{ "andl", 0x58040F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* andl<.f><.cc> 0,ximm,RC 0101110011000100F111cccccc0QQQQQ. */ -+{ "andl", 0x5CC47000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* andl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11000100FBBB1111000QQQQQ. */ -+{ "andl", 0x58C40F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* andl<.f> OPERAND_RA,ximm,u6 0101110001000100F111uuuuuuaaaaaa. */ -+{ "andl", 0x5C447000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* andl<.f> 0,ximm,u6 0101110001000100F111uuuuuu111110. */ -+{ "andl", 0x5C44703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* andl<.f><.cc> 0,ximm,u6 0101110011000100F111uuuuuu1QQQQQ. */ -+{ "andl", 0x5CC47020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* andl<.f> OPERAND_RA,limm,RC 0101111000000100F111ccccccaaaaaa. */ -+{ "andl", 0x5E047000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* andl<.f> OPERAND_RA,RB,limm 01011bbb00000100FBBB111110aaaaaa. */ -+{ "andl", 0x58040F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* andl<.f> 0,limm,RC 0101111000000100F111cccccc111110. */ -+{ "andl", 0x5E04703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* andl<.f> 0,RB,limm 01011bbb00000100FBBB111110111110. */ -+{ "andl", 0x58040FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* andl<.f><.cc> 0,limm,RC 0101111011000100F111cccccc0QQQQQ. */ -+{ "andl", 0x5EC47000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* andl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11000100FBBB1111100QQQQQ. */ -+{ "andl", 0x58C40F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* andl<.f> OPERAND_RA,limm,u6 0101111001000100F111uuuuuuaaaaaa. */ -+{ "andl", 0x5E447000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* andl<.f> 0,limm,u6 0101111001000100F111uuuuuu111110. */ -+{ "andl", 0x5E44703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* andl<.f><.cc> 0,limm,u6 0101111011000100F111uuuuuu1QQQQQ. */ -+{ "andl", 0x5EC47020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* andl<.f> 0,ximm,s12 0101110010000100F111ssssssSSSSSS. */ -+{ "andl", 0x5C847000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* andl<.f> 0,limm,s12 0101111010000100F111ssssssSSSSSS. */ -+{ "andl", 0x5E847000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* andl<.f> OPERAND_RA,ximm,ximm 0101110000000100F111111100aaaaaa. */ -+{ "andl", 0x5C047F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* andl<.f> 0,ximm,ximm 0101110000000100F111111100111110. */ -+{ "andl", 0x5C047F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* andl<.f><.cc> 0,ximm,ximm 0101110011000100F1111111000QQQQQ. */ -+{ "andl", 0x5CC47F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* andl<.f> OPERAND_RA,limm,limm 0101111000000100F111111110aaaaaa. */ -+{ "andl", 0x5E047F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* andl<.f> 0,limm,limm 0101111000000100F111111110111110. */ -+{ "andl", 0x5E047FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* andl<.f><.cc> 0,limm,limm 0101111011000100F1111111100QQQQQ. */ -+{ "andl", 0x5EC47F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* andl_s b,b,c 01111bbbccc01000. */ -+{ "andl_s", 0x00007808, 0x0000F81F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* and_s b,b,c 01111bbbccc00100. */ -+{ "and_s", 0x00007804, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* asl<.f> b,c 00100bbb00101111FBBBCCCCCC000000. */ -+{ "asl", 0x202F0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> 0,c 0010011000101111F111CCCCCC000000. */ -+{ "asl", 0x262F7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> a,b,c 00101bbb00000000FBBBCCCCCCAAAAAA. */ -+{ "asl", 0x28000000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> 0,b,c 00101bbb00000000FBBBCCCCCC111110. */ -+{ "asl", 0x2800003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f><.cc> b,b,c 00101bbb11000000FBBBCCCCCC0QQQQQ. */ -+{ "asl", 0x28C00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asl<.f> b,u6 00100bbb01101111FBBBuuuuuu000000. */ -+{ "asl", 0x206F0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f> 0,u6 0010011001101111F111uuuuuu000000. */ -+{ "asl", 0x266F7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f> a,b,u6 00101bbb01000000FBBBuuuuuuAAAAAA. */ -+{ "asl", 0x28400000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f> 0,b,u6 00101bbb01000000FBBBuuuuuu111110. */ -+{ "asl", 0x2840003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f><.cc> b,b,u6 00101bbb11000000FBBBuuuuuu1QQQQQ. */ -+{ "asl", 0x28C00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asl<.f> b,b,s12 00101bbb10000000FBBBssssssSSSSSS. */ -+{ "asl", 0x28800000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asl<.f> b,limm 00100bbb00101111FBBB111110000000. */ -+{ "asl", 0x202F0F80, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asl<.f> 0,limm 0010011000101111F111111110000000. */ -+{ "asl", 0x262F7F80, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asl<.f> a,limm,c 0010111000000000F111CCCCCCAAAAAA. */ -+{ "asl", 0x2E007000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> a,b,limm 00101bbb00000000FBBB111110AAAAAA. */ -+{ "asl", 0x28000F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asl<.f> 0,limm,c 0010111000000000F111CCCCCC111110. */ -+{ "asl", 0x2E00703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> 0,b,limm 00101bbb00000000FBBB111110111110. */ -+{ "asl", 0x28000FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asl<.f><.cc> b,b,limm 00101bbb11000000FBBB1111100QQQQQ. */ -+{ "asl", 0x28C00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asl<.f><.cc> 0,limm,c 0010111011000000F111CCCCCC0QQQQQ. */ -+{ "asl", 0x2EC07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asl<.f> a,limm,u6 0010111001000000F111uuuuuuAAAAAA. */ -+{ "asl", 0x2E407000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f> 0,limm,u6 0010111001000000F111uuuuuu111110. */ -+{ "asl", 0x2E40703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f><.cc> 0,limm,u6 0010111011000000F111uuuuuu1QQQQQ. */ -+{ "asl", 0x2EC07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asl<.f> 0,limm,s12 0010111010000000F111ssssssSSSSSS. */ -+{ "asl", 0x2E807000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asl<.f> a,limm,limm 0010111000000000F111111110AAAAAA. */ -+{ "asl", 0x2E007F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asl<.f> 0,limm,limm 0010111000000000F111111110111110. */ -+{ "asl", 0x2E007FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asl<.f><.cc> 0,limm,limm 0010111011000000F1111111100QQQQQ. */ -+{ "asl", 0x2EC07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* aslacc c 00101000001011110000CCCCCC111111. */ -+{ "aslacc", 0x282F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RC_CHK }, { 0 }}, -+ -+/* aslacc u6 00101000011011110000uuuuuu111111. */ -+{ "aslacc", 0x286F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* asll<.f> OPERAND_RA,RB,RC 01011bbb00100000FBBBccccccaaaaaa. */ -+{ "asll", 0x58200000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asll<.f> 0,RB,RC 01011bbb00100000FBBBcccccc111110. */ -+{ "asll", 0x5820003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asll<.f><.cc> OPERAND_RB,RB,RC 01011bbb11100000FBBBcccccc0QQQQQ. */ -+{ "asll", 0x58E00000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asll<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc000000. */ -+{ "asll", 0x582F0000, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asll<.f> 0,RC 0101111000101111F111cccccc000000. */ -+{ "asll", 0x5E2F7000, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asll<.f> OPERAND_RA,RB,u6 01011bbb01100000FBBBuuuuuuaaaaaa. */ -+{ "asll", 0x58600000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asll<.f> 0,RB,u6 01011bbb01100000FBBBuuuuuu111110. */ -+{ "asll", 0x5860003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asll<.f><.cc> OPERAND_RB,RB,u6 01011bbb11100000FBBBuuuuuu1QQQQQ. */ -+{ "asll", 0x58E00020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asll<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu000000. */ -+{ "asll", 0x586F0000, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asll<.f> 0,u6 0101111001101111F111uuuuuu000000. */ -+{ "asll", 0x5E6F7000, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asll<.f> OPERAND_RB,RB,s12 01011bbb10100000FBBBssssssSSSSSS. */ -+{ "asll", 0x58A00000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asll<.f> OPERAND_RA,ximm,RC 0101110000100000F111ccccccaaaaaa. */ -+{ "asll", 0x5C207000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* asll<.f> OPERAND_RA,RB,ximm 01011bbb00100000FBBB111100aaaaaa. */ -+{ "asll", 0x58200F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* asll<.f> 0,ximm,RC 0101110000100000F111cccccc111110. */ -+{ "asll", 0x5C20703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* asll<.f> 0,RB,ximm 01011bbb00100000FBBB111100111110. */ -+{ "asll", 0x58200F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* asll<.f><.cc> 0,ximm,RC 0101110011100000F111cccccc0QQQQQ. */ -+{ "asll", 0x5CE07000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asll<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11100000FBBB1111000QQQQQ. */ -+{ "asll", 0x58E00F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* asll<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100000000. */ -+{ "asll", 0x582F0F00, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* asll<.f> 0,ximm 0101111000101111F111111100000000. */ -+{ "asll", 0x5E2F7F00, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* asll<.f> OPERAND_RA,ximm,u6 0101110001100000F111uuuuuuaaaaaa. */ -+{ "asll", 0x5C607000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asll<.f> 0,ximm,u6 0101110001100000F111uuuuuu111110. */ -+{ "asll", 0x5C60703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asll<.f><.cc> 0,ximm,u6 0101110011100000F111uuuuuu1QQQQQ. */ -+{ "asll", 0x5CE07020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asll<.f> OPERAND_RA,limm,RC 0101111000100000F111ccccccaaaaaa. */ -+{ "asll", 0x5E207000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asll<.f> OPERAND_RA,RB,limm 01011bbb00100000FBBB111110aaaaaa. */ -+{ "asll", 0x58200F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asll<.f> 0,limm,RC 0101111000100000F111cccccc111110. */ -+{ "asll", 0x5E20703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asll<.f> 0,RB,limm 01011bbb00100000FBBB111110111110. */ -+{ "asll", 0x58200FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asll<.f><.cc> 0,limm,RC 0101111011100000F111cccccc0QQQQQ. */ -+{ "asll", 0x5EE07000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asll<.f><.cc> OPERAND_RB,RB,limm 01011bbb11100000FBBB1111100QQQQQ. */ -+{ "asll", 0x58E00F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asll<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110000000. */ -+{ "asll", 0x582F0F80, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asll<.f> 0,limm 0101111000101111F111111110000000. */ -+{ "asll", 0x5E2F7F80, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asll<.f> OPERAND_RA,limm,u6 0101111001100000F111uuuuuuaaaaaa. */ -+{ "asll", 0x5E607000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asll<.f> 0,limm,u6 0101111001100000F111uuuuuu111110. */ -+{ "asll", 0x5E60703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asll<.f><.cc> 0,limm,u6 0101111011100000F111uuuuuu1QQQQQ. */ -+{ "asll", 0x5EE07020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asll<.f> 0,ximm,s12 0101110010100000F111ssssssSSSSSS. */ -+{ "asll", 0x5CA07000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asll<.f> 0,limm,s12 0101111010100000F111ssssssSSSSSS. */ -+{ "asll", 0x5EA07000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asll<.f> OPERAND_RA,ximm,ximm 0101110000100000F111111100aaaaaa. */ -+{ "asll", 0x5C207F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* asll<.f> 0,ximm,ximm 0101110000100000F111111100111110. */ -+{ "asll", 0x5C207F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* asll<.f><.cc> 0,ximm,ximm 0101110011100000F1111111000QQQQQ. */ -+{ "asll", 0x5CE07F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* asll<.f> OPERAND_RA,limm,limm 0101111000100000F111111110aaaaaa. */ -+{ "asll", 0x5E207F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asll<.f> 0,limm,limm 0101111000100000F111111110111110. */ -+{ "asll", 0x5E207FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asll<.f><.cc> 0,limm,limm 0101111011100000F1111111100QQQQQ. */ -+{ "asll", 0x5EE07F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asls<.f> a,b,c 00101bbb00001010FBBBCCCCCCAAAAAA. */ -+{ "asls", 0x280A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asls<.f> 0,b,c 00101bbb00001010FBBBCCCCCC111110. */ -+{ "asls", 0x280A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asls<.f><.cc> b,b,c 00101bbb11001010FBBBCCCCCC0QQQQQ. */ -+{ "asls", 0x28CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asls<.f> a,b,u6 00101bbb01001010FBBBuuuuuuAAAAAA. */ -+{ "asls", 0x284A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asls<.f> 0,b,u6 00101bbb01001010FBBBuuuuuu111110. */ -+{ "asls", 0x284A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asls<.f><.cc> b,b,u6 00101bbb11001010FBBBuuuuuu1QQQQQ. */ -+{ "asls", 0x28CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asls<.f> b,b,s12 00101bbb10001010FBBBssssssSSSSSS. */ -+{ "asls", 0x288A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asls<.f> a,limm,c 0010111000001010F111CCCCCCAAAAAA. */ -+{ "asls", 0x2E0A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asls<.f> a,b,limm 00101bbb00001010FBBB111110AAAAAA. */ -+{ "asls", 0x280A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asls<.f> 0,limm,c 0010111000001010F111CCCCCC111110. */ -+{ "asls", 0x2E0A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asls<.f> 0,b,limm 00101bbb00001010FBBB111110111110. */ -+{ "asls", 0x280A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asls<.f><.cc> b,b,limm 00101bbb11001010FBBB1111100QQQQQ. */ -+{ "asls", 0x28CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asls<.f><.cc> 0,limm,c 0010111011001010F111CCCCCC0QQQQQ. */ -+{ "asls", 0x2ECA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asls<.f> a,limm,u6 0010111001001010F111uuuuuuAAAAAA. */ -+{ "asls", 0x2E4A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asls<.f> 0,limm,u6 0010111001001010F111uuuuuu111110. */ -+{ "asls", 0x2E4A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asls<.f><.cc> 0,limm,u6 0010111011001010F111uuuuuu1QQQQQ. */ -+{ "asls", 0x2ECA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asls<.f> 0,limm,s12 0010111010001010F111ssssssSSSSSS. */ -+{ "asls", 0x2E8A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asls<.f> a,limm,limm 0010111000001010F111111110AAAAAA. */ -+{ "asls", 0x2E0A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asls<.f> 0,limm,limm 0010111000001010F111111110111110. */ -+{ "asls", 0x2E0A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asls<.f><.cc> 0,limm,limm 0010111011001010F1111111100QQQQQ. */ -+{ "asls", 0x2ECA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* aslsacc c 00101001001011110000CCCCCC111111. */ -+{ "aslsacc", 0x292F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RC_CHK }, { 0 }}, -+ -+/* aslsacc u6 00101001011011110000uuuuuu111111. */ -+{ "aslsacc", 0x296F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* asl_s b,c 01111bbbccc11011. */ -+{ "asl_s", 0x0000781B, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* asl_s b,b,c 01111bbbccc11000. */ -+{ "asl_s", 0x00007818, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* asl_s c,b,u3 01101bbbccc10uuu. */ -+{ "asl_s", 0x00006810, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, -+ -+/* asl_s b,b,u5 10111bbb000uuuuu. */ -+{ "asl_s", 0x0000B800, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* asr<.f> b,c 00100bbb00101111FBBBCCCCCC000001. */ -+{ "asr", 0x202F0001, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> 0,c 0010011000101111F111CCCCCC000001. */ -+{ "asr", 0x262F7001, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> a,b,c 00101bbb00000010FBBBCCCCCCAAAAAA. */ -+{ "asr", 0x28020000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> 0,b,c 00101bbb00000010FBBBCCCCCC111110. */ -+{ "asr", 0x2802003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f><.cc> b,b,c 00101bbb11000010FBBBCCCCCC0QQQQQ. */ -+{ "asr", 0x28C20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asr<.f> b,u6 00100bbb01101111FBBBuuuuuu000001. */ -+{ "asr", 0x206F0001, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f> 0,u6 0010011001101111F111uuuuuu000001. */ -+{ "asr", 0x266F7001, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f> a,b,u6 00101bbb01000010FBBBuuuuuuAAAAAA. */ -+{ "asr", 0x28420000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f> 0,b,u6 00101bbb01000010FBBBuuuuuu111110. */ -+{ "asr", 0x2842003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f><.cc> b,b,u6 00101bbb11000010FBBBuuuuuu1QQQQQ. */ -+{ "asr", 0x28C20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asr<.f> b,b,s12 00101bbb10000010FBBBssssssSSSSSS. */ -+{ "asr", 0x28820000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asr<.f> b,limm 00100bbb00101111FBBB111110000001. */ -+{ "asr", 0x202F0F81, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr<.f> 0,limm 0010011000101111F111111110000001. */ -+{ "asr", 0x262F7F81, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asr<.f> a,limm,c 0010111000000010F111CCCCCCAAAAAA. */ -+{ "asr", 0x2E027000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> a,b,limm 00101bbb00000010FBBB111110AAAAAA. */ -+{ "asr", 0x28020F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr<.f> 0,limm,c 0010111000000010F111CCCCCC111110. */ -+{ "asr", 0x2E02703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> 0,b,limm 00101bbb00000010FBBB111110111110. */ -+{ "asr", 0x28020FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr<.f><.cc> b,b,limm 00101bbb11000010FBBB1111100QQQQQ. */ -+{ "asr", 0x28C20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asr<.f><.cc> 0,limm,c 0010111011000010F111CCCCCC0QQQQQ. */ -+{ "asr", 0x2EC27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asr<.f> a,limm,u6 0010111001000010F111uuuuuuAAAAAA. */ -+{ "asr", 0x2E427000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f> 0,limm,u6 0010111001000010F111uuuuuu111110. */ -+{ "asr", 0x2E42703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f><.cc> 0,limm,u6 0010111011000010F111uuuuuu1QQQQQ. */ -+{ "asr", 0x2EC27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asr<.f> 0,limm,s12 0010111010000010F111ssssssSSSSSS. */ -+{ "asr", 0x2E827000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asr<.f> a,limm,limm 0010111000000010F111111110AAAAAA. */ -+{ "asr", 0x2E027F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asr<.f> 0,limm,limm 0010111000000010F111111110111110. */ -+{ "asr", 0x2E027FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asr<.f><.cc> 0,limm,limm 0010111011000010F1111111100QQQQQ. */ -+{ "asr", 0x2EC27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asr16<.f> b,c 00101bbb00101111FBBBCCCCCC001100. */ -+{ "asr16", 0x282F000C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr16<.f> 0,c 0010111000101111F111CCCCCC001100. */ -+{ "asr16", 0x2E2F700C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001100. */ -+{ "asr16", 0x286F000C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr16<.f> 0,u6 0010111001101111F111uuuuuu001100. */ -+{ "asr16", 0x2E6F700C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr16<.f> b,limm 00101bbb00101111FBBB111110001100. */ -+{ "asr16", 0x282F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr16<.f> 0,limm 0010111000101111F111111110001100. */ -+{ "asr16", 0x2E2F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asr8<.f> b,c 00101bbb00101111FBBBCCCCCC001101. */ -+{ "asr8", 0x282F000D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr8<.f> 0,c 0010111000101111F111CCCCCC001101. */ -+{ "asr8", 0x2E2F700D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001101. */ -+{ "asr8", 0x286F000D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr8<.f> 0,u6 0010111001101111F111uuuuuu001101. */ -+{ "asr8", 0x2E6F700D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr8<.f> b,limm 00101bbb00101111FBBB111110001101. */ -+{ "asr8", 0x282F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr8<.f> 0,limm 0010111000101111F111111110001101. */ -+{ "asr8", 0x2E2F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asrl<.f> OPERAND_RA,RB,RC 01011bbb00100010FBBBccccccaaaaaa. */ -+{ "asrl", 0x58220000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrl<.f> 0,RB,RC 01011bbb00100010FBBBcccccc111110. */ -+{ "asrl", 0x5822003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11100010FBBBcccccc0QQQQQ. */ -+{ "asrl", 0x58E20000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc000001. */ -+{ "asrl", 0x582F0001, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrl<.f> 0,RC 0101111000101111F111cccccc000001. */ -+{ "asrl", 0x5E2F7001, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asrl<.f> OPERAND_RA,RB,u6 01011bbb01100010FBBBuuuuuuaaaaaa. */ -+{ "asrl", 0x58620000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrl<.f> 0,RB,u6 01011bbb01100010FBBBuuuuuu111110. */ -+{ "asrl", 0x5862003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11100010FBBBuuuuuu1QQQQQ. */ -+{ "asrl", 0x58E20020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu000001. */ -+{ "asrl", 0x586F0001, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrl<.f> 0,u6 0101111001101111F111uuuuuu000001. */ -+{ "asrl", 0x5E6F7001, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrl<.f> OPERAND_RB,RB,s12 01011bbb10100010FBBBssssssSSSSSS. */ -+{ "asrl", 0x58A20000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrl<.f> OPERAND_RA,ximm,RC 0101110000100010F111ccccccaaaaaa. */ -+{ "asrl", 0x5C227000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrl<.f> OPERAND_RA,RB,ximm 01011bbb00100010FBBB111100aaaaaa. */ -+{ "asrl", 0x58220F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* asrl<.f> 0,ximm,RC 0101110000100010F111cccccc111110. */ -+{ "asrl", 0x5C22703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrl<.f> 0,RB,ximm 01011bbb00100010FBBB111100111110. */ -+{ "asrl", 0x58220F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* asrl<.f><.cc> 0,ximm,RC 0101110011100010F111cccccc0QQQQQ. */ -+{ "asrl", 0x5CE27000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11100010FBBB1111000QQQQQ. */ -+{ "asrl", 0x58E20F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* asrl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100000001. */ -+{ "asrl", 0x582F0F01, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* asrl<.f> 0,ximm 0101111000101111F111111100000001. */ -+{ "asrl", 0x5E2F7F01, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* asrl<.f> OPERAND_RA,ximm,u6 0101110001100010F111uuuuuuaaaaaa. */ -+{ "asrl", 0x5C627000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrl<.f> 0,ximm,u6 0101110001100010F111uuuuuu111110. */ -+{ "asrl", 0x5C62703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrl<.f><.cc> 0,ximm,u6 0101110011100010F111uuuuuu1QQQQQ. */ -+{ "asrl", 0x5CE27020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrl<.f> OPERAND_RA,limm,RC 0101111000100010F111ccccccaaaaaa. */ -+{ "asrl", 0x5E227000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrl<.f> OPERAND_RA,RB,limm 01011bbb00100010FBBB111110aaaaaa. */ -+{ "asrl", 0x58220F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrl<.f> 0,limm,RC 0101111000100010F111cccccc111110. */ -+{ "asrl", 0x5E22703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrl<.f> 0,RB,limm 01011bbb00100010FBBB111110111110. */ -+{ "asrl", 0x58220FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrl<.f><.cc> 0,limm,RC 0101111011100010F111cccccc0QQQQQ. */ -+{ "asrl", 0x5EE27000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11100010FBBB1111100QQQQQ. */ -+{ "asrl", 0x58E20F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asrl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110000001. */ -+{ "asrl", 0x582F0F81, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrl<.f> 0,limm 0101111000101111F111111110000001. */ -+{ "asrl", 0x5E2F7F81, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asrl<.f> OPERAND_RA,limm,u6 0101111001100010F111uuuuuuaaaaaa. */ -+{ "asrl", 0x5E627000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrl<.f> 0,limm,u6 0101111001100010F111uuuuuu111110. */ -+{ "asrl", 0x5E62703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrl<.f><.cc> 0,limm,u6 0101111011100010F111uuuuuu1QQQQQ. */ -+{ "asrl", 0x5EE27020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrl<.f> 0,ximm,s12 0101110010100010F111ssssssSSSSSS. */ -+{ "asrl", 0x5CA27000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrl<.f> 0,limm,s12 0101111010100010F111ssssssSSSSSS. */ -+{ "asrl", 0x5EA27000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrl<.f> OPERAND_RA,ximm,ximm 0101110000100010F111111100aaaaaa. */ -+{ "asrl", 0x5C227F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* asrl<.f> 0,ximm,ximm 0101110000100010F111111100111110. */ -+{ "asrl", 0x5C227F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* asrl<.f><.cc> 0,ximm,ximm 0101110011100010F1111111000QQQQQ. */ -+{ "asrl", 0x5CE27F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* asrl<.f> OPERAND_RA,limm,limm 0101111000100010F111111110aaaaaa. */ -+{ "asrl", 0x5E227F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrl<.f> 0,limm,limm 0101111000100010F111111110111110. */ -+{ "asrl", 0x5E227FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrl<.f><.cc> 0,limm,limm 0101111011100010F1111111100QQQQQ. */ -+{ "asrl", 0x5EE27F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asrs<.f> a,b,c 00101bbb00001011FBBBCCCCCCAAAAAA. */ -+{ "asrs", 0x280B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrs<.f> 0,b,c 00101bbb00001011FBBBCCCCCC111110. */ -+{ "asrs", 0x280B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrs<.f><.cc> b,b,c 00101bbb11001011FBBBCCCCCC0QQQQQ. */ -+{ "asrs", 0x28CB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrs<.f> a,b,u6 00101bbb01001011FBBBuuuuuuAAAAAA. */ -+{ "asrs", 0x284B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrs<.f> 0,b,u6 00101bbb01001011FBBBuuuuuu111110. */ -+{ "asrs", 0x284B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrs<.f><.cc> b,b,u6 00101bbb11001011FBBBuuuuuu1QQQQQ. */ -+{ "asrs", 0x28CB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrs<.f> b,b,s12 00101bbb10001011FBBBssssssSSSSSS. */ -+{ "asrs", 0x288B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrs<.f> a,limm,c 0010111000001011F111CCCCCCAAAAAA. */ -+{ "asrs", 0x2E0B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrs<.f> a,b,limm 00101bbb00001011FBBB111110AAAAAA. */ -+{ "asrs", 0x280B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrs<.f> 0,limm,c 0010111000001011F111CCCCCC111110. */ -+{ "asrs", 0x2E0B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrs<.f> 0,b,limm 00101bbb00001011FBBB111110111110. */ -+{ "asrs", 0x280B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrs<.f><.cc> b,b,limm 00101bbb11001011FBBB1111100QQQQQ. */ -+{ "asrs", 0x28CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asrs<.f><.cc> 0,limm,c 0010111011001011F111CCCCCC0QQQQQ. */ -+{ "asrs", 0x2ECB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrs<.f> a,limm,u6 0010111001001011F111uuuuuuAAAAAA. */ -+{ "asrs", 0x2E4B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrs<.f> 0,limm,u6 0010111001001011F111uuuuuu111110. */ -+{ "asrs", 0x2E4B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrs<.f><.cc> 0,limm,u6 0010111011001011F111uuuuuu1QQQQQ. */ -+{ "asrs", 0x2ECB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrs<.f> 0,limm,s12 0010111010001011F111ssssssSSSSSS. */ -+{ "asrs", 0x2E8B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrs<.f> a,limm,limm 0010111000001011F111111110AAAAAA. */ -+{ "asrs", 0x2E0B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrs<.f> 0,limm,limm 0010111000001011F111111110111110. */ -+{ "asrs", 0x2E0B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrs<.f><.cc> 0,limm,limm 0010111011001011F1111111100QQQQQ. */ -+{ "asrs", 0x2ECB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asrsr<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA. */ -+{ "asrsr", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrsr<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110. */ -+{ "asrsr", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrsr<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ. */ -+{ "asrsr", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrsr<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA. */ -+{ "asrsr", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsr<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110. */ -+{ "asrsr", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsr<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ. */ -+{ "asrsr", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrsr<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS. */ -+{ "asrsr", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrsr<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA. */ -+{ "asrsr", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrsr<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA. */ -+{ "asrsr", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrsr<.f> 0,limm,c 0010111000001100F111CCCCCC111110. */ -+{ "asrsr", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrsr<.f> 0,b,limm 00101bbb00001100FBBB111110111110. */ -+{ "asrsr", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrsr<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ. */ -+{ "asrsr", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asrsr<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ. */ -+{ "asrsr", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrsr<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA. */ -+{ "asrsr", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsr<.f> 0,limm,u6 0010111001001100F111uuuuuu111110. */ -+{ "asrsr", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsr<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ. */ -+{ "asrsr", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrsr<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS. */ -+{ "asrsr", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrsr<.f> a,limm,limm 0010111000001100F111111110AAAAAA. */ -+{ "asrsr", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrsr<.f> 0,limm,limm 0010111000001100F111111110111110. */ -+{ "asrsr", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrsr<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ. */ -+{ "asrsr", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asr_s b,c 01111bbbccc11100. */ -+{ "asr_s", 0x0000781C, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* asr_s b,b,c 01111bbbccc11010. */ -+{ "asr_s", 0x0000781A, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* asr_s c,b,u3 01101bbbccc11uuu. */ -+{ "asr_s", 0x00006818, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, -+ -+/* asr_s b,b,u5 10111bbb010uuuuu. */ -+{ "asr_s", 0x0000B840, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* atld<.op><.aq> OPERAND_RB,RC 00100bbb00101111FBBBcccccc110OOO. */ -+{ "atld", 0x202F0030, 0xF8FF0038, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_ATOP, C_AQ }}, -+ -+/* atldl_add<.aq> OPERAND_RB,RC 01011bbb00101111FBBBcccccc110000. */ -+{ "atldl", 0x582F0030, 0xF8FF0038, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_ATOP, C_AQ }}, -+ -+/* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ -+{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, NONE, { OPERAND_SIMM25_A16_5 }, { C_D }}, -+ -+/* b<.d> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ. */ -+{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, NONE, { OPERAND_SIMM21_A16_5 }, { C_CC, C_D }}, -+ -+/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00110. */ -+{ "bbit0", 0x08010006, 0xF801001F, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10110. */ -+{ "bbit0", 0x08010016, 0xF801001F, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110000110. */ -+{ "bbit0", 0x08010F86, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC000110. */ -+{ "bbit0", 0x0E017006, 0xFF01703F, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu010110. */ -+{ "bbit0", 0x0E017016, 0xFF01703F, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0 limm,limm,s9 00001110sssssss1S111111110000110. */ -+{ "bbit0", 0x0E017F86, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0l<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */ -+{ "bbit0l", 0x0801000E, 0xF801001F, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit0l<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110. */ -+{ "bbit0l", 0x0801001E, 0xF801001F, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit0l b,limm,s9 00001bbbsssssss1SBBB111110001110. */ -+{ "bbit0l", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0l limm,c,s9 00001110sssssss1S111CCCCCC001110. */ -+{ "bbit0l", 0x0E01700E, 0xFF01703F, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0l limm,u6,s9 00001110sssssss1S111uuuuuu011110. */ -+{ "bbit0l", 0x0E01701E, 0xFF01703F, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0l limm,limm,s9 00001110sssssss1S111111110001110. */ -+{ "bbit0l", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BBIT0, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00111. */ -+{ "bbit1", 0x08010007, 0xF801001F, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10111. */ -+{ "bbit1", 0x08010017, 0xF801001F, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110000111. */ -+{ "bbit1", 0x08010F87, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC000111. */ -+{ "bbit1", 0x0E017007, 0xFF01703F, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu010111. */ -+{ "bbit1", 0x0E017017, 0xFF01703F, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1 limm,limm,s9 00001110sssssss1S111111110000111. */ -+{ "bbit1", 0x0E017F87, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1l<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111. */ -+{ "bbit1l", 0x0801000F, 0xF801001F, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit1l<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111. */ -+{ "bbit1l", 0x0801001F, 0xF801001F, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit1l b,limm,s9 00001bbbsssssss1SBBB111110001111. */ -+{ "bbit1l", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1l limm,c,s9 00001110sssssss1S111CCCCCC001111. */ -+{ "bbit1l", 0x0E01700F, 0xFF01703F, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1l limm,u6,s9 00001110sssssss1S111uuuuuu011111. */ -+{ "bbit1l", 0x0E01701F, 0xFF01703F, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1l limm,limm,s9 00001110sssssss1S111111110001111. */ -+{ "bbit1l", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BBIT1, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA. */ -+{ "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bclr<.f> 0,b,c 00100bbb00010000FBBBCCCCCC111110. */ -+{ "bclr", 0x2010003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bclr<.f><.cc> b,b,c 00100bbb11010000FBBBCCCCCC0QQQQQ. */ -+{ "bclr", 0x20D00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bclr<.f> a,b,u6 00100bbb01010000FBBBuuuuuuAAAAAA. */ -+{ "bclr", 0x20500000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclr<.f> 0,b,u6 00100bbb01010000FBBBuuuuuu111110. */ -+{ "bclr", 0x2050003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclr<.f><.cc> b,b,u6 00100bbb11010000FBBBuuuuuu1QQQQQ. */ -+{ "bclr", 0x20D00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bclr<.f> b,b,s12 00100bbb10010000FBBBssssssSSSSSS. */ -+{ "bclr", 0x20900000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bclr<.f> a,limm,c 0010011000010000F111CCCCCCAAAAAA. */ -+{ "bclr", 0x26107000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bclr<.f> a,b,limm 00100bbb00010000FBBB111110AAAAAA. */ -+{ "bclr", 0x20100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bclr<.f> 0,limm,c 0010011000010000F111CCCCCC111110. */ -+{ "bclr", 0x2610703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bclr<.f> 0,b,limm 00100bbb00010000FBBB111110111110. */ -+{ "bclr", 0x20100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bclr<.f><.cc> b,b,limm 00100bbb11010000FBBB1111100QQQQQ. */ -+{ "bclr", 0x20D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bclr<.f><.cc> 0,limm,c 0010011011010000F111CCCCCC0QQQQQ. */ -+{ "bclr", 0x26D07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bclr<.f> a,limm,u6 0010011001010000F111uuuuuuAAAAAA. */ -+{ "bclr", 0x26507000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclr<.f> 0,limm,u6 0010011001010000F111uuuuuu111110. */ -+{ "bclr", 0x2650703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclr<.f><.cc> 0,limm,u6 0010011011010000F111uuuuuu1QQQQQ. */ -+{ "bclr", 0x26D07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bclr<.f> 0,limm,s12 0010011010010000F111ssssssSSSSSS. */ -+{ "bclr", 0x26907000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bclr<.f> a,limm,limm 0010011000010000F111111110AAAAAA. */ -+{ "bclr", 0x26107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bclr<.f> 0,limm,limm 0010011000010000F111111110111110. */ -+{ "bclr", 0x26107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bclr<.f><.cc> 0,limm,limm 0010011011010000F1111111100QQQQQ. */ -+{ "bclr", 0x26D07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bclrl<.f> OPERAND_RA,RB,RC 01011bbb00010000FBBBccccccaaaaaa. */ -+{ "bclrl", 0x58100000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bclrl<.f> 0,RB,RC 01011bbb00010000FBBBcccccc111110. */ -+{ "bclrl", 0x5810003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bclrl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11010000FBBBcccccc0QQQQQ. */ -+{ "bclrl", 0x58D00000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bclrl<.f> OPERAND_RA,RB,u6 01011bbb01010000FBBBuuuuuuaaaaaa. */ -+{ "bclrl", 0x58500000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclrl<.f> 0,RB,u6 01011bbb01010000FBBBuuuuuu111110. */ -+{ "bclrl", 0x5850003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclrl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11010000FBBBuuuuuu1QQQQQ. */ -+{ "bclrl", 0x58D00020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bclrl<.f> OPERAND_RB,RB,s12 01011bbb10010000FBBBssssssSSSSSS. */ -+{ "bclrl", 0x58900000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bclrl<.f> OPERAND_RA,ximm,RC 0101110000010000F111ccccccaaaaaa. */ -+{ "bclrl", 0x5C107000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bclrl<.f> OPERAND_RA,RB,ximm 01011bbb00010000FBBB111100aaaaaa. */ -+{ "bclrl", 0x58100F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bclrl<.f> 0,ximm,RC 0101110000010000F111cccccc111110. */ -+{ "bclrl", 0x5C10703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bclrl<.f> 0,RB,ximm 01011bbb00010000FBBB111100111110. */ -+{ "bclrl", 0x58100F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bclrl<.f><.cc> 0,ximm,RC 0101110011010000F111cccccc0QQQQQ. */ -+{ "bclrl", 0x5CD07000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bclrl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11010000FBBB1111000QQQQQ. */ -+{ "bclrl", 0x58D00F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* bclrl<.f> OPERAND_RA,ximm,u6 0101110001010000F111uuuuuuaaaaaa. */ -+{ "bclrl", 0x5C507000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclrl<.f> 0,ximm,u6 0101110001010000F111uuuuuu111110. */ -+{ "bclrl", 0x5C50703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclrl<.f><.cc> 0,ximm,u6 0101110011010000F111uuuuuu1QQQQQ. */ -+{ "bclrl", 0x5CD07020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bclrl<.f> OPERAND_RA,limm,RC 0101111000010000F111ccccccaaaaaa. */ -+{ "bclrl", 0x5E107000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bclrl<.f> OPERAND_RA,RB,limm 01011bbb00010000FBBB111110aaaaaa. */ -+{ "bclrl", 0x58100F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bclrl<.f> 0,limm,RC 0101111000010000F111cccccc111110. */ -+{ "bclrl", 0x5E10703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bclrl<.f> 0,RB,limm 01011bbb00010000FBBB111110111110. */ -+{ "bclrl", 0x58100FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bclrl<.f><.cc> 0,limm,RC 0101111011010000F111cccccc0QQQQQ. */ -+{ "bclrl", 0x5ED07000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bclrl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11010000FBBB1111100QQQQQ. */ -+{ "bclrl", 0x58D00F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bclrl<.f> OPERAND_RA,limm,u6 0101111001010000F111uuuuuuaaaaaa. */ -+{ "bclrl", 0x5E507000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclrl<.f> 0,limm,u6 0101111001010000F111uuuuuu111110. */ -+{ "bclrl", 0x5E50703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclrl<.f><.cc> 0,limm,u6 0101111011010000F111uuuuuu1QQQQQ. */ -+{ "bclrl", 0x5ED07020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bclrl<.f> 0,ximm,s12 0101110010010000F111ssssssSSSSSS. */ -+{ "bclrl", 0x5C907000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bclrl<.f> 0,limm,s12 0101111010010000F111ssssssSSSSSS. */ -+{ "bclrl", 0x5E907000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bclrl<.f> OPERAND_RA,ximm,ximm 0101110000010000F111111100aaaaaa. */ -+{ "bclrl", 0x5C107F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bclrl<.f> 0,ximm,ximm 0101110000010000F111111100111110. */ -+{ "bclrl", 0x5C107F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bclrl<.f><.cc> 0,ximm,ximm 0101110011010000F1111111000QQQQQ. */ -+{ "bclrl", 0x5CD07F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* bclrl<.f> OPERAND_RA,limm,limm 0101111000010000F111111110aaaaaa. */ -+{ "bclrl", 0x5E107F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bclrl<.f> 0,limm,limm 0101111000010000F111111110111110. */ -+{ "bclrl", 0x5E107FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bclrl<.f><.cc> 0,limm,limm 0101111011010000F1111111100QQQQQ. */ -+{ "bclrl", 0x5ED07F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bclr_s b,b,u5 10111bbb101uuuuu. */ -+{ "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* beq_sCC_EQ s10 1111001sssssssss. */ -+{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM10_A16_7_S }, { C_CC_EQ }}, -+ -+/* bge_sCC_GE s7 1111011001ssssss. */ -+{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_GE }}, -+ -+/* bgt_sCC_GT s7 1111011000ssssss. */ -+{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_GT }}, -+ -+/* bhi_sCC_HI s7 1111011100ssssss. */ -+{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_HI }}, -+ -+/* bhs_sCC_HS s7 1111011101ssssss. */ -+{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_HS }}, -+ -+/* bi c 00100RRR001001000RRRCCCCCCRRRRRR. */ -+{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BI, CD1, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* bi limm 00100RRR001001000RRR111110RRRRRR. */ -+{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BI, CD1, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA. */ -+{ "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bic<.f> 0,b,c 00100bbb00000110FBBBCCCCCC111110. */ -+{ "bic", 0x2006003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bic<.f><.cc> b,b,c 00100bbb11000110FBBBCCCCCC0QQQQQ. */ -+{ "bic", 0x20C60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bic<.f> a,b,u6 00100bbb01000110FBBBuuuuuuAAAAAA. */ -+{ "bic", 0x20460000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bic<.f> 0,b,u6 00100bbb01000110FBBBuuuuuu111110. */ -+{ "bic", 0x2046003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bic<.f><.cc> b,b,u6 00100bbb11000110FBBBuuuuuu1QQQQQ. */ -+{ "bic", 0x20C60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bic<.f> b,b,s12 00100bbb10000110FBBBssssssSSSSSS. */ -+{ "bic", 0x20860000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bic<.f> a,limm,c 0010011000000110F111CCCCCCAAAAAA. */ -+{ "bic", 0x26067000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bic<.f> a,b,limm 00100bbb00000110FBBB111110AAAAAA. */ -+{ "bic", 0x20060F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bic<.f> 0,limm,c 0010011000000110F111CCCCCC111110. */ -+{ "bic", 0x2606703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bic<.f> 0,b,limm 00100bbb00000110FBBB111110111110. */ -+{ "bic", 0x20060FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bic<.f><.cc> b,b,limm 00100bbb11000110FBBB1111100QQQQQ. */ -+{ "bic", 0x20C60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bic<.f><.cc> 0,limm,c 0010011011000110F111CCCCCC0QQQQQ. */ -+{ "bic", 0x26C67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bic<.f> a,limm,u6 0010011001000110F111uuuuuuAAAAAA. */ -+{ "bic", 0x26467000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bic<.f> 0,limm,u6 0010011001000110F111uuuuuu111110. */ -+{ "bic", 0x2646703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bic<.f><.cc> 0,limm,u6 0010011011000110F111uuuuuu1QQQQQ. */ -+{ "bic", 0x26C67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bic<.f> 0,limm,s12 0010011010000110F111ssssssSSSSSS. */ -+{ "bic", 0x26867000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bic<.f> a,limm,limm 0010011000000110F111111110AAAAAA. */ -+{ "bic", 0x26067F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bic<.f> 0,limm,limm 0010011000000110F111111110111110. */ -+{ "bic", 0x26067FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bic<.f><.cc> 0,limm,limm 0010011011000110F1111111100QQQQQ. */ -+{ "bic", 0x26C67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bicl<.f> OPERAND_RA,RB,RC 01011bbb00000110FBBBccccccaaaaaa. */ -+{ "bicl", 0x58060000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bicl<.f> 0,RB,RC 01011bbb00000110FBBBcccccc111110. */ -+{ "bicl", 0x5806003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bicl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11000110FBBBcccccc0QQQQQ. */ -+{ "bicl", 0x58C60000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bicl<.f> OPERAND_RA,RB,u6 01011bbb01000110FBBBuuuuuuaaaaaa. */ -+{ "bicl", 0x58460000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bicl<.f> 0,RB,u6 01011bbb01000110FBBBuuuuuu111110. */ -+{ "bicl", 0x5846003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bicl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11000110FBBBuuuuuu1QQQQQ. */ -+{ "bicl", 0x58C60020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bicl<.f> OPERAND_RB,RB,s12 01011bbb10000110FBBBssssssSSSSSS. */ -+{ "bicl", 0x58860000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bicl<.f> OPERAND_RA,ximm,RC 0101110000000110F111ccccccaaaaaa. */ -+{ "bicl", 0x5C067000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bicl<.f> OPERAND_RA,RB,ximm 01011bbb00000110FBBB111100aaaaaa. */ -+{ "bicl", 0x58060F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bicl<.f> 0,ximm,RC 0101110000000110F111cccccc111110. */ -+{ "bicl", 0x5C06703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bicl<.f> 0,RB,ximm 01011bbb00000110FBBB111100111110. */ -+{ "bicl", 0x58060F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bicl<.f><.cc> 0,ximm,RC 0101110011000110F111cccccc0QQQQQ. */ -+{ "bicl", 0x5CC67000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bicl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11000110FBBB1111000QQQQQ. */ -+{ "bicl", 0x58C60F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* bicl<.f> OPERAND_RA,ximm,u6 0101110001000110F111uuuuuuaaaaaa. */ -+{ "bicl", 0x5C467000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bicl<.f> 0,ximm,u6 0101110001000110F111uuuuuu111110. */ -+{ "bicl", 0x5C46703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bicl<.f><.cc> 0,ximm,u6 0101110011000110F111uuuuuu1QQQQQ. */ -+{ "bicl", 0x5CC67020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bicl<.f> OPERAND_RA,limm,RC 0101111000000110F111ccccccaaaaaa. */ -+{ "bicl", 0x5E067000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bicl<.f> OPERAND_RA,RB,limm 01011bbb00000110FBBB111110aaaaaa. */ -+{ "bicl", 0x58060F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bicl<.f> 0,limm,RC 0101111000000110F111cccccc111110. */ -+{ "bicl", 0x5E06703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bicl<.f> 0,RB,limm 01011bbb00000110FBBB111110111110. */ -+{ "bicl", 0x58060FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bicl<.f><.cc> 0,limm,RC 0101111011000110F111cccccc0QQQQQ. */ -+{ "bicl", 0x5EC67000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bicl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11000110FBBB1111100QQQQQ. */ -+{ "bicl", 0x58C60F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bicl<.f> OPERAND_RA,limm,u6 0101111001000110F111uuuuuuaaaaaa. */ -+{ "bicl", 0x5E467000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bicl<.f> 0,limm,u6 0101111001000110F111uuuuuu111110. */ -+{ "bicl", 0x5E46703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bicl<.f><.cc> 0,limm,u6 0101111011000110F111uuuuuu1QQQQQ. */ -+{ "bicl", 0x5EC67020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bicl<.f> 0,ximm,s12 0101110010000110F111ssssssSSSSSS. */ -+{ "bicl", 0x5C867000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bicl<.f> 0,limm,s12 0101111010000110F111ssssssSSSSSS. */ -+{ "bicl", 0x5E867000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bicl<.f> OPERAND_RA,ximm,ximm 0101110000000110F111111100aaaaaa. */ -+{ "bicl", 0x5C067F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bicl<.f> 0,ximm,ximm 0101110000000110F111111100111110. */ -+{ "bicl", 0x5C067F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bicl<.f><.cc> 0,ximm,ximm 0101110011000110F1111111000QQQQQ. */ -+{ "bicl", 0x5CC67F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* bicl<.f> OPERAND_RA,limm,limm 0101111000000110F111111110aaaaaa. */ -+{ "bicl", 0x5E067F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bicl<.f> 0,limm,limm 0101111000000110F111111110111110. */ -+{ "bicl", 0x5E067FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bicl<.f><.cc> 0,limm,limm 0101111011000110F1111111100QQQQQ. */ -+{ "bicl", 0x5EC67F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bic_s b,b,c 01111bbbccc00110. */ -+{ "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* bih c 00100RRR001001010RRRCCCCCCRRRRRR. */ -+{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BIH, CD1, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* bih limm 00100RRR001001010RRR111110RRRRRR. */ -+{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BIH, CD1, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ -+{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, NONE, { OPERAND_SIMM25_A32_5 }, { C_D }}, -+ -+/* bl<.d><.cc> s21 00001sssssssss00SSSSSSSSSSNQQQQQ. */ -+{ "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, NONE, { OPERAND_SIMM21_A32_5 }, { C_CC, C_D }}, -+ -+/* ble_sCC_LE s7 1111011011ssssss. */ -+{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LE }}, -+ -+/* blo_sCC_LO s7 1111011110ssssss. */ -+{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LO }}, -+ -+/* bls_sCC_LS s7 1111011111ssssss. */ -+{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LS }}, -+ -+/* blt_sCC_LT s7 1111011010ssssss. */ -+{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LT }}, -+ -+/* bl_s s13 11111sssssssssss. */ -+{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, NONE, { OPERAND_SIMM13_A32_5_S }, { 0 }}, -+ -+/* bmsk<.f> a,b,c 00100bbb00010011FBBBCCCCCCAAAAAA. */ -+{ "bmsk", 0x20130000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmsk<.f> 0,b,c 00100bbb00010011FBBBCCCCCC111110. */ -+{ "bmsk", 0x2013003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmsk<.f><.cc> b,b,c 00100bbb11010011FBBBCCCCCC0QQQQQ. */ -+{ "bmsk", 0x20D30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmsk<.f> a,b,u6 00100bbb01010011FBBBuuuuuuAAAAAA. */ -+{ "bmsk", 0x20530000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsk<.f> 0,b,u6 00100bbb01010011FBBBuuuuuu111110. */ -+{ "bmsk", 0x2053003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsk<.f><.cc> b,b,u6 00100bbb11010011FBBBuuuuuu1QQQQQ. */ -+{ "bmsk", 0x20D30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmsk<.f> b,b,s12 00100bbb10010011FBBBssssssSSSSSS. */ -+{ "bmsk", 0x20930000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmsk<.f> a,limm,c 0010011000010011F111CCCCCCAAAAAA. */ -+{ "bmsk", 0x26137000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmsk<.f> a,b,limm 00100bbb00010011FBBB111110AAAAAA. */ -+{ "bmsk", 0x20130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmsk<.f> 0,limm,c 0010011000010011F111CCCCCC111110. */ -+{ "bmsk", 0x2613703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmsk<.f> 0,b,limm 00100bbb00010011FBBB111110111110. */ -+{ "bmsk", 0x20130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmsk<.f><.cc> b,b,limm 00100bbb11010011FBBB1111100QQQQQ. */ -+{ "bmsk", 0x20D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bmsk<.f><.cc> 0,limm,c 0010011011010011F111CCCCCC0QQQQQ. */ -+{ "bmsk", 0x26D37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmsk<.f> a,limm,u6 0010011001010011F111uuuuuuAAAAAA. */ -+{ "bmsk", 0x26537000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsk<.f> 0,limm,u6 0010011001010011F111uuuuuu111110. */ -+{ "bmsk", 0x2653703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsk<.f><.cc> 0,limm,u6 0010011011010011F111uuuuuu1QQQQQ. */ -+{ "bmsk", 0x26D37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmsk<.f> 0,limm,s12 0010011010010011F111ssssssSSSSSS. */ -+{ "bmsk", 0x26937000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmsk<.f> a,limm,limm 0010011000010011F111111110AAAAAA. */ -+{ "bmsk", 0x26137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmsk<.f> 0,limm,limm 0010011000010011F111111110111110. */ -+{ "bmsk", 0x26137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmsk<.f><.cc> 0,limm,limm 0010011011010011F1111111100QQQQQ. */ -+{ "bmsk", 0x26D37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bmskl<.f> OPERAND_RA,RB,RC 01011bbb00010011FBBBccccccaaaaaa. */ -+{ "bmskl", 0x58130000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmskl<.f> 0,RB,RC 01011bbb00010011FBBBcccccc111110. */ -+{ "bmskl", 0x5813003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmskl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11010011FBBBcccccc0QQQQQ. */ -+{ "bmskl", 0x58D30000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmskl<.f> OPERAND_RA,RB,u6 01011bbb01010011FBBBuuuuuuaaaaaa. */ -+{ "bmskl", 0x58530000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskl<.f> 0,RB,u6 01011bbb01010011FBBBuuuuuu111110. */ -+{ "bmskl", 0x5853003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11010011FBBBuuuuuu1QQQQQ. */ -+{ "bmskl", 0x58D30020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmskl<.f> OPERAND_RB,RB,s12 01011bbb10010011FBBBssssssSSSSSS. */ -+{ "bmskl", 0x58930000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmskl<.f> OPERAND_RA,ximm,RC 0101110000010011F111ccccccaaaaaa. */ -+{ "bmskl", 0x5C137000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmskl<.f> OPERAND_RA,RB,ximm 01011bbb00010011FBBB111100aaaaaa. */ -+{ "bmskl", 0x58130F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bmskl<.f> 0,ximm,RC 0101110000010011F111cccccc111110. */ -+{ "bmskl", 0x5C13703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmskl<.f> 0,RB,ximm 01011bbb00010011FBBB111100111110. */ -+{ "bmskl", 0x58130F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bmskl<.f><.cc> 0,ximm,RC 0101110011010011F111cccccc0QQQQQ. */ -+{ "bmskl", 0x5CD37000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmskl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11010011FBBB1111000QQQQQ. */ -+{ "bmskl", 0x58D30F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* bmskl<.f> OPERAND_RA,ximm,u6 0101110001010011F111uuuuuuaaaaaa. */ -+{ "bmskl", 0x5C537000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskl<.f> 0,ximm,u6 0101110001010011F111uuuuuu111110. */ -+{ "bmskl", 0x5C53703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskl<.f><.cc> 0,ximm,u6 0101110011010011F111uuuuuu1QQQQQ. */ -+{ "bmskl", 0x5CD37020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmskl<.f> OPERAND_RA,limm,RC 0101111000010011F111ccccccaaaaaa. */ -+{ "bmskl", 0x5E137000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmskl<.f> OPERAND_RA,RB,limm 01011bbb00010011FBBB111110aaaaaa. */ -+{ "bmskl", 0x58130F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmskl<.f> 0,limm,RC 0101111000010011F111cccccc111110. */ -+{ "bmskl", 0x5E13703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmskl<.f> 0,RB,limm 01011bbb00010011FBBB111110111110. */ -+{ "bmskl", 0x58130FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmskl<.f><.cc> 0,limm,RC 0101111011010011F111cccccc0QQQQQ. */ -+{ "bmskl", 0x5ED37000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmskl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11010011FBBB1111100QQQQQ. */ -+{ "bmskl", 0x58D30F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bmskl<.f> OPERAND_RA,limm,u6 0101111001010011F111uuuuuuaaaaaa. */ -+{ "bmskl", 0x5E537000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskl<.f> 0,limm,u6 0101111001010011F111uuuuuu111110. */ -+{ "bmskl", 0x5E53703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskl<.f><.cc> 0,limm,u6 0101111011010011F111uuuuuu1QQQQQ. */ -+{ "bmskl", 0x5ED37020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmskl<.f> 0,ximm,s12 0101110010010011F111ssssssSSSSSS. */ -+{ "bmskl", 0x5C937000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmskl<.f> 0,limm,s12 0101111010010011F111ssssssSSSSSS. */ -+{ "bmskl", 0x5E937000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmskl<.f> OPERAND_RA,ximm,ximm 0101110000010011F111111100aaaaaa. */ -+{ "bmskl", 0x5C137F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bmskl<.f> 0,ximm,ximm 0101110000010011F111111100111110. */ -+{ "bmskl", 0x5C137F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bmskl<.f><.cc> 0,ximm,ximm 0101110011010011F1111111000QQQQQ. */ -+{ "bmskl", 0x5CD37F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* bmskl<.f> OPERAND_RA,limm,limm 0101111000010011F111111110aaaaaa. */ -+{ "bmskl", 0x5E137F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmskl<.f> 0,limm,limm 0101111000010011F111111110111110. */ -+{ "bmskl", 0x5E137FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmskl<.f><.cc> 0,limm,limm 0101111011010011F1111111100QQQQQ. */ -+{ "bmskl", 0x5ED37F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bmskn<.f> a,b,c 00100bbb00101100FBBBCCCCCCAAAAAA. */ -+{ "bmskn", 0x202C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmskn<.f> 0,b,c 00100bbb00101100FBBBCCCCCC111110. */ -+{ "bmskn", 0x202C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmskn<.f><.cc> b,b,c 00100bbb11101100FBBBCCCCCC0QQQQQ. */ -+{ "bmskn", 0x20EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmskn<.f> a,b,u6 00100bbb01101100FBBBuuuuuuAAAAAA. */ -+{ "bmskn", 0x206C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskn<.f> 0,b,u6 00100bbb01101100FBBBuuuuuu111110. */ -+{ "bmskn", 0x206C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskn<.f><.cc> b,b,u6 00100bbb11101100FBBBuuuuuu1QQQQQ. */ -+{ "bmskn", 0x20EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmskn<.f> b,b,s12 00100bbb10101100FBBBssssssSSSSSS. */ -+{ "bmskn", 0x20AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmskn<.f> a,limm,c 0010011000101100F111CCCCCCAAAAAA. */ -+{ "bmskn", 0x262C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmskn<.f> a,b,limm 00100bbb00101100FBBB111110AAAAAA. */ -+{ "bmskn", 0x202C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmskn<.f> 0,limm,c 0010011000101100F111CCCCCC111110. */ -+{ "bmskn", 0x262C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmskn<.f> 0,b,limm 00100bbb00101100FBBB111110111110. */ -+{ "bmskn", 0x202C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmskn<.f><.cc> b,b,limm 00100bbb11101100FBBB1111100QQQQQ. */ -+{ "bmskn", 0x20EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bmskn<.f><.cc> 0,limm,c 0010011011101100F111CCCCCC0QQQQQ. */ -+{ "bmskn", 0x26EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmskn<.f> a,limm,u6 0010011001101100F111uuuuuuAAAAAA. */ -+{ "bmskn", 0x266C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskn<.f> 0,limm,u6 0010011001101100F111uuuuuu111110. */ -+{ "bmskn", 0x266C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskn<.f><.cc> 0,limm,u6 0010011011101100F111uuuuuu1QQQQQ. */ -+{ "bmskn", 0x26EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmskn<.f> 0,limm,s12 0010011010101100F111ssssssSSSSSS. */ -+{ "bmskn", 0x26AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmskn<.f> a,limm,limm 0010011000101100F111111110AAAAAA. */ -+{ "bmskn", 0x262C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmskn<.f> 0,limm,limm 0010011000101100F111111110111110. */ -+{ "bmskn", 0x262C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmskn<.f><.cc> 0,limm,limm 0010011011101100F1111111100QQQQQ. */ -+{ "bmskn", 0x26EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bmsknl<.f> OPERAND_RA,RB,RC 01011bbb00101100FBBBccccccaaaaaa. */ -+{ "bmsknl", 0x582C0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmsknl<.f> 0,RB,RC 01011bbb00101100FBBBcccccc111110. */ -+{ "bmsknl", 0x582C003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmsknl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11101100FBBBcccccc0QQQQQ. */ -+{ "bmsknl", 0x58EC0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmsknl<.f> OPERAND_RA,RB,u6 01011bbb01101100FBBBuuuuuuaaaaaa. */ -+{ "bmsknl", 0x586C0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsknl<.f> 0,RB,u6 01011bbb01101100FBBBuuuuuu111110. */ -+{ "bmsknl", 0x586C003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsknl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11101100FBBBuuuuuu1QQQQQ. */ -+{ "bmsknl", 0x58EC0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmsknl<.f> OPERAND_RB,RB,s12 01011bbb10101100FBBBssssssSSSSSS. */ -+{ "bmsknl", 0x58AC0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmsknl<.f> OPERAND_RA,ximm,RC 0101110000101100F111ccccccaaaaaa. */ -+{ "bmsknl", 0x5C2C7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmsknl<.f> OPERAND_RA,RB,ximm 01011bbb00101100FBBB111100aaaaaa. */ -+{ "bmsknl", 0x582C0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bmsknl<.f> 0,ximm,RC 0101110000101100F111cccccc111110. */ -+{ "bmsknl", 0x5C2C703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmsknl<.f> 0,RB,ximm 01011bbb00101100FBBB111100111110. */ -+{ "bmsknl", 0x582C0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bmsknl<.f><.cc> 0,ximm,RC 0101110011101100F111cccccc0QQQQQ. */ -+{ "bmsknl", 0x5CEC7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmsknl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11101100FBBB1111000QQQQQ. */ -+{ "bmsknl", 0x58EC0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* bmsknl<.f> OPERAND_RA,ximm,u6 0101110001101100F111uuuuuuaaaaaa. */ -+{ "bmsknl", 0x5C6C7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsknl<.f> 0,ximm,u6 0101110001101100F111uuuuuu111110. */ -+{ "bmsknl", 0x5C6C703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsknl<.f><.cc> 0,ximm,u6 0101110011101100F111uuuuuu1QQQQQ. */ -+{ "bmsknl", 0x5CEC7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmsknl<.f> OPERAND_RA,limm,RC 0101111000101100F111ccccccaaaaaa. */ -+{ "bmsknl", 0x5E2C7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmsknl<.f> OPERAND_RA,RB,limm 01011bbb00101100FBBB111110aaaaaa. */ -+{ "bmsknl", 0x582C0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmsknl<.f> 0,limm,RC 0101111000101100F111cccccc111110. */ -+{ "bmsknl", 0x5E2C703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmsknl<.f> 0,RB,limm 01011bbb00101100FBBB111110111110. */ -+{ "bmsknl", 0x582C0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmsknl<.f><.cc> 0,limm,RC 0101111011101100F111cccccc0QQQQQ. */ -+{ "bmsknl", 0x5EEC7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmsknl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11101100FBBB1111100QQQQQ. */ -+{ "bmsknl", 0x58EC0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bmsknl<.f> OPERAND_RA,limm,u6 0101111001101100F111uuuuuuaaaaaa. */ -+{ "bmsknl", 0x5E6C7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsknl<.f> 0,limm,u6 0101111001101100F111uuuuuu111110. */ -+{ "bmsknl", 0x5E6C703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsknl<.f><.cc> 0,limm,u6 0101111011101100F111uuuuuu1QQQQQ. */ -+{ "bmsknl", 0x5EEC7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmsknl<.f> 0,ximm,s12 0101110010101100F111ssssssSSSSSS. */ -+{ "bmsknl", 0x5CAC7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmsknl<.f> 0,limm,s12 0101111010101100F111ssssssSSSSSS. */ -+{ "bmsknl", 0x5EAC7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmsknl<.f> OPERAND_RA,ximm,ximm 0101110000101100F111111100aaaaaa. */ -+{ "bmsknl", 0x5C2C7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bmsknl<.f> 0,ximm,ximm 0101110000101100F111111100111110. */ -+{ "bmsknl", 0x5C2C7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bmsknl<.f><.cc> 0,ximm,ximm 0101110011101100F1111111000QQQQQ. */ -+{ "bmsknl", 0x5CEC7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* bmsknl<.f> OPERAND_RA,limm,limm 0101111000101100F111111110aaaaaa. */ -+{ "bmsknl", 0x5E2C7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmsknl<.f> 0,limm,limm 0101111000101100F111111110111110. */ -+{ "bmsknl", 0x5E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmsknl<.f><.cc> 0,limm,limm 0101111011101100F1111111100QQQQQ. */ -+{ "bmsknl", 0x5EEC7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bmsk_s b,b,u5 10111bbb110uuuuu. */ -+{ "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* bne_sCC_NE s10 1111010sssssssss. */ -+{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, COND, { OPERAND_SIMM10_A16_7_S }, { C_CC_NE }}, -+ -+/* breq<.d>CC_EQ b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000. */ -+{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_EQ }}, -+ -+/* breq<.d>CC_EQ b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000. */ -+{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_EQ }}, -+ -+/* breqCC_EQ b,limm,s9 00001bbbsssssss1SBBB111110000000. */ -+{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, -+ -+/* breqCC_EQ limm,c,s9 00001110sssssss1S111CCCCCC000000. */ -+{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, -+ -+/* breqCC_EQ limm,u6,s9 00001110sssssss1S111uuuuuu010000. */ -+{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, -+ -+/* breqCC_EQ limm,limm,s9 00001110sssssss1S111111110000000. */ -+{ "breq", 0x0E017F80, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, -+ -+/* breql<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01000. */ -+{ "breql", 0x08010008, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* breql<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11000. */ -+{ "breql", 0x08010018, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* breql b,limm,s9 00001bbbsssssss1SBBB111110001000. */ -+{ "breql", 0x08010F88, 0xF8010FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* breql limm,c,s9 00001110sssssss1S111CCCCCC001000. */ -+{ "breql", 0x0E017008, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* breql limm,u6,s9 00001110sssssss1S111uuuuuu011000. */ -+{ "breql", 0x0E017018, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* breql_s b,0,s8 11101bbb0sssssss. */ -+{ "breql_s", 0x0000E800, 0x0000F880, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_ZB_S, OPERAND_SIMM8_A16_9_S }, { 0 }}, -+ -+/* brge<.d>CC_GE b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011. */ -+{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_GE }}, -+ -+/* brge<.d>CC_GE b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011. */ -+{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_GE }}, -+ -+/* brgeCC_GE b,limm,s9 00001bbbsssssss1SBBB111110000011. */ -+{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, -+ -+/* brgeCC_GE limm,c,s9 00001110sssssss1S111CCCCCC000011. */ -+{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, -+ -+/* brgeCC_GE limm,u6,s9 00001110sssssss1S111uuuuuu010011. */ -+{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, -+ -+/* brgeCC_GE limm,limm,s9 00001110sssssss1S111111110000011. */ -+{ "brge", 0x0E017F83, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, -+ -+/* brgel<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01011. */ -+{ "brgel", 0x0801000B, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brgel<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11011. */ -+{ "brgel", 0x0801001B, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brgel b,limm,s9 00001bbbsssssss1SBBB111110001011. */ -+{ "brgel", 0x08010F8B, 0xF8010FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brgel limm,c,s9 00001110sssssss1S111CCCCCC001011. */ -+{ "brgel", 0x0E01700B, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brgel limm,u6,s9 00001110sssssss1S111uuuuuu011011. */ -+{ "brgel", 0x0E01701B, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brhs<.d>CC_HS b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101. */ -+{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_HS }}, -+ -+/* brhs<.d>CC_HS b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101. */ -+{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_HS }}, -+ -+/* brhsCC_HS b,limm,s9 00001bbbsssssss1SBBB111110000101. */ -+{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, -+ -+/* brhsCC_HS limm,c,s9 00001110sssssss1S111CCCCCC000101. */ -+{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, -+ -+/* brhsCC_HS limm,u6,s9 00001110sssssss1S111uuuuuu010101. */ -+{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, -+ -+/* brhsCC_HS limm,limm,s9 00001110sssssss1S111111110000101. */ -+{ "brhs", 0x0E017F85, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, -+ -+/* brhsl<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01101. */ -+{ "brhsl", 0x0801000D, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brhsl<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11101. */ -+{ "brhsl", 0x0801001D, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brhsl b,limm,s9 00001bbbsssssss1SBBB111110001101. */ -+{ "brhsl", 0x08010F8D, 0xF8010FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brhsl limm,c,s9 00001110sssssss1S111CCCCCC001101. */ -+{ "brhsl", 0x0E01700D, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brhsl limm,u6,s9 00001110sssssss1S111uuuuuu011101. */ -+{ "brhsl", 0x0E01701D, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brk 00100101011011110000000000111111. */ -+{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* brk_s 0111111111111111. */ -+{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* brlo<.d>CC_LO b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */ -+{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LO }}, -+ -+/* brlo<.d>CC_LO b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100. */ -+{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LO }}, -+ -+/* brloCC_LO b,limm,s9 00001bbbsssssss1SBBB111110000100. */ -+{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, -+ -+/* brloCC_LO limm,c,s9 00001110sssssss1S111CCCCCC000100. */ -+{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, -+ -+/* brloCC_LO limm,u6,s9 00001110sssssss1S111uuuuuu010100. */ -+{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, -+ -+/* brloCC_LO limm,limm,s9 00001110sssssss1S111111110000100. */ -+{ "brlo", 0x0E017F84, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, -+ -+/* brlol<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01100. */ -+{ "brlol", 0x0801000C, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brlol<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11100. */ -+{ "brlol", 0x0801001C, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brlol b,limm,s9 00001bbbsssssss1SBBB111110001100. */ -+{ "brlol", 0x08010F8C, 0xF8010FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brlol limm,c,s9 00001110sssssss1S111CCCCCC001100. */ -+{ "brlol", 0x0E01700C, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brlol limm,u6,s9 00001110sssssss1S111uuuuuu011100. */ -+{ "brlol", 0x0E01701C, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brlt<.d>CC_LT b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010. */ -+{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LT }}, -+ -+/* brlt<.d>CC_LT b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010. */ -+{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LT }}, -+ -+/* brltCC_LT b,limm,s9 00001bbbsssssss1SBBB111110000010. */ -+{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, -+ -+/* brltCC_LT limm,c,s9 00001110sssssss1S111CCCCCC000010. */ -+{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, -+ -+/* brltCC_LT limm,u6,s9 00001110sssssss1S111uuuuuu010010. */ -+{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, -+ -+/* brltCC_LT limm,limm,s9 00001110sssssss1S111111110000010. */ -+{ "brlt", 0x0E017F82, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, -+ -+/* brltl<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01010. */ -+{ "brltl", 0x0801000A, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brltl<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11010. */ -+{ "brltl", 0x0801001A, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brltl b,limm,s9 00001bbbsssssss1SBBB111110001010. */ -+{ "brltl", 0x08010F8A, 0xF8010FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brltl limm,c,s9 00001110sssssss1S111CCCCCC001010. */ -+{ "brltl", 0x0E01700A, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brltl limm,u6,s9 00001110sssssss1S111uuuuuu011010. */ -+{ "brltl", 0x0E01701A, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brne<.d>CC_NE b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001. */ -+{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_NE }}, -+ -+/* brne<.d>CC_NE b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10001. */ -+{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_NE }}, -+ -+/* brneCC_NE b,limm,s9 00001bbbsssssss1SBBB111110000001. */ -+{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, -+ -+/* brneCC_NE limm,c,s9 00001110sssssss1S111CCCCCC000001. */ -+{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, -+ -+/* brneCC_NE limm,u6,s9 00001110sssssss1S111uuuuuu010001. */ -+{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, -+ -+/* brneCC_NE limm,limm,s9 00001110sssssss1S111111110000001. */ -+{ "brne", 0x0E017F81, 0xFF017FFF, ARC_OPCODE_V3_ARC64, BRCC, NONE, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, -+ -+/* brnel<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01001. */ -+{ "brnel", 0x08010009, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brnel<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN11001. */ -+{ "brnel", 0x08010019, 0xF801001F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* brnel b,limm,s9 00001bbbsssssss1SBBB111110001001. */ -+{ "brnel", 0x08010F89, 0xF8010FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brnel limm,c,s9 00001110sssssss1S111CCCCCC001001. */ -+{ "brnel", 0x0E017009, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brnel limm,u6,s9 00001110sssssss1S111uuuuuu011001. */ -+{ "brnel", 0x0E017019, 0xFF01703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* brnel_s b,0,s8 11101bbb1sssssss. */ -+{ "brnel_s", 0x0000E880, 0x0000F880, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_ZB_S, OPERAND_SIMM8_A16_9_S }, { 0 }}, -+ -+/* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA. */ -+{ "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bset<.f> 0,b,c 00100bbb00001111FBBBCCCCCC111110. */ -+{ "bset", 0x200F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bset<.f><.cc> b,b,c 00100bbb11001111FBBBCCCCCC0QQQQQ. */ -+{ "bset", 0x20CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bset<.f> a,b,u6 00100bbb01001111FBBBuuuuuuAAAAAA. */ -+{ "bset", 0x204F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bset<.f> 0,b,u6 00100bbb01001111FBBBuuuuuu111110. */ -+{ "bset", 0x204F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bset<.f><.cc> b,b,u6 00100bbb11001111FBBBuuuuuu1QQQQQ. */ -+{ "bset", 0x20CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bset<.f> b,b,s12 00100bbb10001111FBBBssssssSSSSSS. */ -+{ "bset", 0x208F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bset<.f> a,limm,c 0010011000001111F111CCCCCCAAAAAA. */ -+{ "bset", 0x260F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bset<.f> a,b,limm 00100bbb00001111FBBB111110AAAAAA. */ -+{ "bset", 0x200F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bset<.f> 0,limm,c 0010011000001111F111CCCCCC111110. */ -+{ "bset", 0x260F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bset<.f> 0,b,limm 00100bbb00001111FBBB111110111110. */ -+{ "bset", 0x200F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bset<.f><.cc> b,b,limm 00100bbb11001111FBBB1111100QQQQQ. */ -+{ "bset", 0x20CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bset<.f><.cc> 0,limm,c 0010011011001111F111CCCCCC0QQQQQ. */ -+{ "bset", 0x26CF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bset<.f> a,limm,u6 0010011001001111F111uuuuuuAAAAAA. */ -+{ "bset", 0x264F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bset<.f> 0,limm,u6 0010011001001111F111uuuuuu111110. */ -+{ "bset", 0x264F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bset<.f><.cc> 0,limm,u6 0010011011001111F111uuuuuu1QQQQQ. */ -+{ "bset", 0x26CF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bset<.f> 0,limm,s12 0010011010001111F111ssssssSSSSSS. */ -+{ "bset", 0x268F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bset<.f> a,limm,limm 0010011000001111F111111110AAAAAA. */ -+{ "bset", 0x260F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bset<.f> 0,limm,limm 0010011000001111F111111110111110. */ -+{ "bset", 0x260F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bset<.f><.cc> 0,limm,limm 0010011011001111F1111111100QQQQQ. */ -+{ "bset", 0x26CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bsetl<.f> OPERAND_RA,RB,RC 01011bbb00001111FBBBccccccaaaaaa. */ -+{ "bsetl", 0x580F0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bsetl<.f> 0,RB,RC 01011bbb00001111FBBBcccccc111110. */ -+{ "bsetl", 0x580F003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bsetl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11001111FBBBcccccc0QQQQQ. */ -+{ "bsetl", 0x58CF0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bsetl<.f> OPERAND_RA,RB,u6 01011bbb01001111FBBBuuuuuuaaaaaa. */ -+{ "bsetl", 0x584F0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bsetl<.f> 0,RB,u6 01011bbb01001111FBBBuuuuuu111110. */ -+{ "bsetl", 0x584F003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bsetl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11001111FBBBuuuuuu1QQQQQ. */ -+{ "bsetl", 0x58CF0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bsetl<.f> OPERAND_RB,RB,s12 01011bbb10001111FBBBssssssSSSSSS. */ -+{ "bsetl", 0x588F0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bsetl<.f> OPERAND_RA,ximm,RC 0101110000001111F111ccccccaaaaaa. */ -+{ "bsetl", 0x5C0F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bsetl<.f> OPERAND_RA,RB,ximm 01011bbb00001111FBBB111100aaaaaa. */ -+{ "bsetl", 0x580F0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bsetl<.f> 0,ximm,RC 0101110000001111F111cccccc111110. */ -+{ "bsetl", 0x5C0F703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bsetl<.f> 0,RB,ximm 01011bbb00001111FBBB111100111110. */ -+{ "bsetl", 0x580F0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bsetl<.f><.cc> 0,ximm,RC 0101110011001111F111cccccc0QQQQQ. */ -+{ "bsetl", 0x5CCF7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bsetl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11001111FBBB1111000QQQQQ. */ -+{ "bsetl", 0x58CF0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* bsetl<.f> OPERAND_RA,ximm,u6 0101110001001111F111uuuuuuaaaaaa. */ -+{ "bsetl", 0x5C4F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bsetl<.f> 0,ximm,u6 0101110001001111F111uuuuuu111110. */ -+{ "bsetl", 0x5C4F703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bsetl<.f><.cc> 0,ximm,u6 0101110011001111F111uuuuuu1QQQQQ. */ -+{ "bsetl", 0x5CCF7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bsetl<.f> OPERAND_RA,limm,RC 0101111000001111F111ccccccaaaaaa. */ -+{ "bsetl", 0x5E0F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bsetl<.f> OPERAND_RA,RB,limm 01011bbb00001111FBBB111110aaaaaa. */ -+{ "bsetl", 0x580F0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bsetl<.f> 0,limm,RC 0101111000001111F111cccccc111110. */ -+{ "bsetl", 0x5E0F703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bsetl<.f> 0,RB,limm 01011bbb00001111FBBB111110111110. */ -+{ "bsetl", 0x580F0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bsetl<.f><.cc> 0,limm,RC 0101111011001111F111cccccc0QQQQQ. */ -+{ "bsetl", 0x5ECF7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bsetl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11001111FBBB1111100QQQQQ. */ -+{ "bsetl", 0x58CF0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bsetl<.f> OPERAND_RA,limm,u6 0101111001001111F111uuuuuuaaaaaa. */ -+{ "bsetl", 0x5E4F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bsetl<.f> 0,limm,u6 0101111001001111F111uuuuuu111110. */ -+{ "bsetl", 0x5E4F703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bsetl<.f><.cc> 0,limm,u6 0101111011001111F111uuuuuu1QQQQQ. */ -+{ "bsetl", 0x5ECF7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bsetl<.f> 0,ximm,s12 0101110010001111F111ssssssSSSSSS. */ -+{ "bsetl", 0x5C8F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bsetl<.f> 0,limm,s12 0101111010001111F111ssssssSSSSSS. */ -+{ "bsetl", 0x5E8F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bsetl<.f> OPERAND_RA,ximm,ximm 0101110000001111F111111100aaaaaa. */ -+{ "bsetl", 0x5C0F7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bsetl<.f> 0,ximm,ximm 0101110000001111F111111100111110. */ -+{ "bsetl", 0x5C0F7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bsetl<.f><.cc> 0,ximm,ximm 0101110011001111F1111111000QQQQQ. */ -+{ "bsetl", 0x5CCF7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* bsetl<.f> OPERAND_RA,limm,limm 0101111000001111F111111110aaaaaa. */ -+{ "bsetl", 0x5E0F7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bsetl<.f> 0,limm,limm 0101111000001111F111111110111110. */ -+{ "bsetl", 0x5E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bsetl<.f><.cc> 0,limm,limm 0101111011001111F1111111100QQQQQ. */ -+{ "bsetl", 0x5ECF7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bset_s b,b,u5 10111bbb100uuuuu. */ -+{ "bset_s", 0x0000B880, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* btst b,c 00100bbb000100011BBBCCCCCCRRRRRR. */ -+{ "btst", 0x20118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* btst<.cc> b,c 00100bbb110100011BBBCCCCCC0QQQQQ. */ -+{ "btst", 0x20D18000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* btst b,u6 00100bbb010100011BBBuuuuuuRRRRRR. */ -+{ "btst", 0x20518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* btst<.cc> b,u6 00100bbb110100011BBBuuuuuu1QQQQQ. */ -+{ "btst", 0x20D18020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* btst b,s12 00100bbb100100011BBBssssssSSSSSS. */ -+{ "btst", 0x20918000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* btst limm,c 00100110000100011111CCCCCCRRRRRR. */ -+{ "btst", 0x2611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* btst b,limm 00100bbb000100011BBB111110RRRRRR. */ -+{ "btst", 0x20118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* btst<.cc> b,limm 00100bbb110100011BBB1111100QQQQQ. */ -+{ "btst", 0x20D18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* btst<.cc> limm,c 00100110110100011111CCCCCC0QQQQQ. */ -+{ "btst", 0x26D1F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* btst limm,u6 00100110010100011111uuuuuuRRRRRR. */ -+{ "btst", 0x2651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* btst<.cc> limm,u6 00100110110100011111uuuuuu1QQQQQ. */ -+{ "btst", 0x26D1F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* btst limm,s12 00100110100100011111ssssssSSSSSS. */ -+{ "btst", 0x2691F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* btst limm,limm 00100110000100011111111110RRRRRR. */ -+{ "btst", 0x2611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* btst<.cc> limm,limm 001001101101000111111111100QQQQQ. */ -+{ "btst", 0x26D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* btstl OPERAND_RB,RC 01011bbb000100011BBBccccccRRRRRR. */ -+{ "btstl", 0x58118000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* btstl<.cc> OPERAND_RB,RC 01011bbb110100011BBBcccccc0QQQQQ. */ -+{ "btstl", 0x58D18000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* btstl OPERAND_RB,u6 01011bbb010100011BBBuuuuuuRRRRRR. */ -+{ "btstl", 0x58518000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* btstl<.cc> OPERAND_RB,u6 01011bbb110100011BBBuuuuuu1QQQQQ. */ -+{ "btstl", 0x58D18020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* btstl OPERAND_RB,s12 01011bbb100100011BBBssssssSSSSSS. */ -+{ "btstl", 0x58918000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* btstl ximm,RC 01011100000100011111ccccccRRRRRR. */ -+{ "btstl", 0x5C11F000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* btstl OPERAND_RB,ximm 01011bbb000100011BBB111100RRRRRR. */ -+{ "btstl", 0x58118F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* btstl<.cc> OPERAND_RB,ximm 01011bbb110100011BBB1111000QQQQQ. */ -+{ "btstl", 0x58D18F00, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_CC }}, -+ -+/* btstl limm,RC 01011110000100011111ccccccRRRRRR. */ -+{ "btstl", 0x5E11F000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* btstl OPERAND_RB,limm 01011bbb000100011BBB111110RRRRRR. */ -+{ "btstl", 0x58118F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* btstl<.cc> OPERAND_RB,limm 01011bbb110100011BBB1111100QQQQQ. */ -+{ "btstl", 0x58D18F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* btst_s b,u5 10111bbb111uuuuu. */ -+{ "btst_s", 0x0000B8E0, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* bxor<.f> a,b,c 00100bbb00010010FBBBCCCCCCAAAAAA. */ -+{ "bxor", 0x20120000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bxor<.f> 0,b,c 00100bbb00010010FBBBCCCCCC111110. */ -+{ "bxor", 0x2012003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bxor<.f><.cc> b,b,c 00100bbb11010010FBBBCCCCCC0QQQQQ. */ -+{ "bxor", 0x20D20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bxor<.f> a,b,u6 00100bbb01010010FBBBuuuuuuAAAAAA. */ -+{ "bxor", 0x20520000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxor<.f> 0,b,u6 00100bbb01010010FBBBuuuuuu111110. */ -+{ "bxor", 0x2052003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxor<.f><.cc> b,b,u6 00100bbb11010010FBBBuuuuuu1QQQQQ. */ -+{ "bxor", 0x20D20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bxor<.f> b,b,s12 00100bbb10010010FBBBssssssSSSSSS. */ -+{ "bxor", 0x20920000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bxor<.f> a,limm,c 0010011000010010F111CCCCCCAAAAAA. */ -+{ "bxor", 0x26127000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bxor<.f> a,b,limm 00100bbb00010010FBBB111110AAAAAA. */ -+{ "bxor", 0x20120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bxor<.f> 0,limm,c 0010011000010010F111CCCCCC111110. */ -+{ "bxor", 0x2612703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bxor<.f> 0,b,limm 00100bbb00010010FBBB111110111110. */ -+{ "bxor", 0x20120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bxor<.f><.cc> b,b,limm 00100bbb11010010FBBB1111100QQQQQ. */ -+{ "bxor", 0x20D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bxor<.f><.cc> 0,limm,c 0010011011010010F111CCCCCC0QQQQQ. */ -+{ "bxor", 0x26D27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bxor<.f> a,limm,u6 0010011001010010F111uuuuuuAAAAAA. */ -+{ "bxor", 0x26527000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxor<.f> 0,limm,u6 0010011001010010F111uuuuuu111110. */ -+{ "bxor", 0x2652703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxor<.f><.cc> 0,limm,u6 0010011011010010F111uuuuuu1QQQQQ. */ -+{ "bxor", 0x26D27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bxor<.f> 0,limm,s12 0010011010010010F111ssssssSSSSSS. */ -+{ "bxor", 0x26927000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bxor<.f> a,limm,limm 0010011000010010F111111110AAAAAA. */ -+{ "bxor", 0x26127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bxor<.f> 0,limm,limm 0010011000010010F111111110111110. */ -+{ "bxor", 0x26127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bxor<.f><.cc> 0,limm,limm 0010011011010010F1111111100QQQQQ. */ -+{ "bxor", 0x26D27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bxorl<.f> OPERAND_RA,RB,RC 01011bbb00010010FBBBccccccaaaaaa. */ -+{ "bxorl", 0x58120000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bxorl<.f> 0,RB,RC 01011bbb00010010FBBBcccccc111110. */ -+{ "bxorl", 0x5812003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bxorl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11010010FBBBcccccc0QQQQQ. */ -+{ "bxorl", 0x58D20000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bxorl<.f> OPERAND_RA,RB,u6 01011bbb01010010FBBBuuuuuuaaaaaa. */ -+{ "bxorl", 0x58520000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxorl<.f> 0,RB,u6 01011bbb01010010FBBBuuuuuu111110. */ -+{ "bxorl", 0x5852003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxorl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11010010FBBBuuuuuu1QQQQQ. */ -+{ "bxorl", 0x58D20020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bxorl<.f> OPERAND_RB,RB,s12 01011bbb10010010FBBBssssssSSSSSS. */ -+{ "bxorl", 0x58920000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bxorl<.f> OPERAND_RA,ximm,RC 0101110000010010F111ccccccaaaaaa. */ -+{ "bxorl", 0x5C127000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bxorl<.f> OPERAND_RA,RB,ximm 01011bbb00010010FBBB111100aaaaaa. */ -+{ "bxorl", 0x58120F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bxorl<.f> 0,ximm,RC 0101110000010010F111cccccc111110. */ -+{ "bxorl", 0x5C12703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* bxorl<.f> 0,RB,ximm 01011bbb00010010FBBB111100111110. */ -+{ "bxorl", 0x58120F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* bxorl<.f><.cc> 0,ximm,RC 0101110011010010F111cccccc0QQQQQ. */ -+{ "bxorl", 0x5CD27000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bxorl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11010010FBBB1111000QQQQQ. */ -+{ "bxorl", 0x58D20F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* bxorl<.f> OPERAND_RA,ximm,u6 0101110001010010F111uuuuuuaaaaaa. */ -+{ "bxorl", 0x5C527000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxorl<.f> 0,ximm,u6 0101110001010010F111uuuuuu111110. */ -+{ "bxorl", 0x5C52703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxorl<.f><.cc> 0,ximm,u6 0101110011010010F111uuuuuu1QQQQQ. */ -+{ "bxorl", 0x5CD27020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bxorl<.f> OPERAND_RA,limm,RC 0101111000010010F111ccccccaaaaaa. */ -+{ "bxorl", 0x5E127000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bxorl<.f> OPERAND_RA,RB,limm 01011bbb00010010FBBB111110aaaaaa. */ -+{ "bxorl", 0x58120F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bxorl<.f> 0,limm,RC 0101111000010010F111cccccc111110. */ -+{ "bxorl", 0x5E12703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bxorl<.f> 0,RB,limm 01011bbb00010010FBBB111110111110. */ -+{ "bxorl", 0x58120FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bxorl<.f><.cc> 0,limm,RC 0101111011010010F111cccccc0QQQQQ. */ -+{ "bxorl", 0x5ED27000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bxorl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11010010FBBB1111100QQQQQ. */ -+{ "bxorl", 0x58D20F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bxorl<.f> OPERAND_RA,limm,u6 0101111001010010F111uuuuuuaaaaaa. */ -+{ "bxorl", 0x5E527000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxorl<.f> 0,limm,u6 0101111001010010F111uuuuuu111110. */ -+{ "bxorl", 0x5E52703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxorl<.f><.cc> 0,limm,u6 0101111011010010F111uuuuuu1QQQQQ. */ -+{ "bxorl", 0x5ED27020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bxorl<.f> 0,ximm,s12 0101110010010010F111ssssssSSSSSS. */ -+{ "bxorl", 0x5C927000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bxorl<.f> 0,limm,s12 0101111010010010F111ssssssSSSSSS. */ -+{ "bxorl", 0x5E927000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bxorl<.f> OPERAND_RA,ximm,ximm 0101110000010010F111111100aaaaaa. */ -+{ "bxorl", 0x5C127F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bxorl<.f> 0,ximm,ximm 0101110000010010F111111100111110. */ -+{ "bxorl", 0x5C127F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* bxorl<.f><.cc> 0,ximm,ximm 0101110011010010F1111111000QQQQQ. */ -+{ "bxorl", 0x5CD27F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* bxorl<.f> OPERAND_RA,limm,limm 0101111000010010F111111110aaaaaa. */ -+{ "bxorl", 0x5E127F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bxorl<.f> 0,limm,limm 0101111000010010F111111110111110. */ -+{ "bxorl", 0x5E127FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bxorl<.f><.cc> 0,limm,limm 0101111011010010F1111111100QQQQQ. */ -+{ "bxorl", 0x5ED27F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* b_s s10 1111000sssssssss. */ -+{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, NONE, { OPERAND_SIMM10_A16_7_S }, { 0 }}, -+ -+/* cbflyhf0r a,b,c 00110bbb000110111BBBCCCCCCAAAAAA. */ -+{ "cbflyhf0r", 0x301B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf0r 0,b,c 00110bbb000110111BBBCCCCCC111110. */ -+{ "cbflyhf0r", 0x301B803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf0r<.cc> b,b,c 00110bbb110110111BBBCCCCCC0QQQQQ. */ -+{ "cbflyhf0r", 0x30DB8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cbflyhf0r a,b,u6 00110bbb010110111BBBuuuuuuAAAAAA. */ -+{ "cbflyhf0r", 0x305B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf0r 0,b,u6 00110bbb010110111BBBuuuuuu111110. */ -+{ "cbflyhf0r", 0x305B803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf0r<.cc> b,b,u6 00110bbb110110111BBBuuuuuu1QQQQQ. */ -+{ "cbflyhf0r", 0x30DB8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cbflyhf0r b,b,s12 00110bbb100110111BBBssssssSSSSSS. */ -+{ "cbflyhf0r", 0x309B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cbflyhf0r a,limm,c 00110110000110111111CCCCCCAAAAAA. */ -+{ "cbflyhf0r", 0x361BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf0r a,b,limm 00110bbb000110111BBB111110AAAAAA. */ -+{ "cbflyhf0r", 0x301B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cbflyhf0r 0,limm,c 00110110000110111111CCCCCC111110. */ -+{ "cbflyhf0r", 0x361BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf0r 0,b,limm 00110bbb000110111BBB111110111110. */ -+{ "cbflyhf0r", 0x301B8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cbflyhf0r<.cc> b,b,limm 00110bbb110110111BBB1111100QQQQQ. */ -+{ "cbflyhf0r", 0x30DB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cbflyhf0r<.cc> 0,limm,c 00110110110110111111CCCCCC0QQQQQ. */ -+{ "cbflyhf0r", 0x36DBF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cbflyhf0r a,limm,u6 00110110010110111111uuuuuuAAAAAA. */ -+{ "cbflyhf0r", 0x365BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf0r 0,limm,u6 00110110010110111111uuuuuu111110. */ -+{ "cbflyhf0r", 0x365BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf0r<.cc> 0,limm,u6 00110110110110111111uuuuuu1QQQQQ. */ -+{ "cbflyhf0r", 0x36DBF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cbflyhf0r 0,limm,s12 00110110100110111111ssssssSSSSSS. */ -+{ "cbflyhf0r", 0x369BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cbflyhf0r a,limm,limm 00110110000110111111111110AAAAAA. */ -+{ "cbflyhf0r", 0x361BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cbflyhf0r 0,limm,limm 00110110000110111111111110111110. */ -+{ "cbflyhf0r", 0x361BFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cbflyhf0r<.cc> 0,limm,limm 001101101101101111111111100QQQQQ. */ -+{ "cbflyhf0r", 0x36DBFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cbflyhf1r b,c 00110bbb001011110BBBCCCCCC111001. */ -+{ "cbflyhf1r", 0x302F0039, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf1r 0,c 00110110001011110111CCCCCC011001. */ -+{ "cbflyhf1r", 0x362F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf1r b,u6 00110bbb011011110BBBuuuuuu011001. */ -+{ "cbflyhf1r", 0x306F0019, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf1r 0,u6 00110110011011110111uuuuuu011001. */ -+{ "cbflyhf1r", 0x366F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf1r b,limm 00110bbb001011110BBB111110011001. */ -+{ "cbflyhf1r", 0x302F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* cbflyhf1r 0,limm 00110110001011110111111110011001. */ -+{ "cbflyhf1r", 0x362F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* clri c 00100111001011110000CCCCCC111111. */ -+{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* clri u6 00100111011011110000uuuuuu111111. */ -+{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* clri 00100111001011110000000000111111. */ -+{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA. */ -+{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmacchfr 0,b,c 00110bbb000010011BBBCCCCCC111110. */ -+{ "cmacchfr", 0x3009803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmacchfr<.cc> b,b,c 00110bbb110010011BBBCCCCCC0QQQQQ. */ -+{ "cmacchfr", 0x30C98000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmacchfr a,b,u6 00110bbb010010011BBBuuuuuuAAAAAA. */ -+{ "cmacchfr", 0x30498000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchfr 0,b,u6 00110bbb010010011BBBuuuuuu111110. */ -+{ "cmacchfr", 0x3049803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchfr<.cc> b,b,u6 00110bbb110010011BBBuuuuuu1QQQQQ. */ -+{ "cmacchfr", 0x30C98020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmacchfr b,b,s12 00110bbb100010011BBBssssssSSSSSS. */ -+{ "cmacchfr", 0x30898000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmacchfr a,limm,c 00110110000010011111CCCCCCAAAAAA. */ -+{ "cmacchfr", 0x3609F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmacchfr a,b,limm 00110bbb000010011BBB111110AAAAAA. */ -+{ "cmacchfr", 0x30098F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmacchfr 0,limm,c 00110110000010011111CCCCCC111110. */ -+{ "cmacchfr", 0x3609F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmacchfr 0,b,limm 00110bbb000010011BBB111110111110. */ -+{ "cmacchfr", 0x30098FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmacchfr<.cc> b,b,limm 00110bbb110010011BBB1111100QQQQQ. */ -+{ "cmacchfr", 0x30C98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmacchfr<.cc> 0,limm,c 00110110110010011111CCCCCC0QQQQQ. */ -+{ "cmacchfr", 0x36C9F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmacchfr a,limm,u6 00110110010010011111uuuuuuAAAAAA. */ -+{ "cmacchfr", 0x3649F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchfr 0,limm,u6 00110110010010011111uuuuuu111110. */ -+{ "cmacchfr", 0x3649F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchfr<.cc> 0,limm,u6 00110110110010011111uuuuuu1QQQQQ. */ -+{ "cmacchfr", 0x36C9F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmacchfr 0,limm,s12 00110110100010011111ssssssSSSSSS. */ -+{ "cmacchfr", 0x3689F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmacchfr a,limm,limm 00110110000010011111111110AAAAAA. */ -+{ "cmacchfr", 0x3609FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmacchfr 0,limm,limm 00110110000010011111111110111110. */ -+{ "cmacchfr", 0x3609FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmacchfr<.cc> 0,limm,limm 001101101100100111111111100QQQQQ. */ -+{ "cmacchfr", 0x36C9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmacchnfr a,b,c 00110bbb000010001BBBCCCCCCAAAAAA. */ -+{ "cmacchnfr", 0x30088000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmacchnfr 0,b,c 00110bbb000010001BBBCCCCCC111110. */ -+{ "cmacchnfr", 0x3008803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmacchnfr<.cc> b,b,c 00110bbb110010001BBBCCCCCC0QQQQQ. */ -+{ "cmacchnfr", 0x30C88000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmacchnfr a,b,u6 00110bbb010010001BBBuuuuuuAAAAAA. */ -+{ "cmacchnfr", 0x30488000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchnfr 0,b,u6 00110bbb010010001BBBuuuuuu111110. */ -+{ "cmacchnfr", 0x3048803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchnfr<.cc> b,b,u6 00110bbb110010001BBBuuuuuu1QQQQQ. */ -+{ "cmacchnfr", 0x30C88020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmacchnfr b,b,s12 00110bbb100010001BBBssssssSSSSSS. */ -+{ "cmacchnfr", 0x30888000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmacchnfr a,limm,c 00110110000010001111CCCCCCAAAAAA. */ -+{ "cmacchnfr", 0x3608F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmacchnfr a,b,limm 00110bbb000010001BBB111110AAAAAA. */ -+{ "cmacchnfr", 0x30088F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmacchnfr 0,limm,c 00110110000010001111CCCCCC111110. */ -+{ "cmacchnfr", 0x3608F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmacchnfr 0,b,limm 00110bbb000010001BBB111110111110. */ -+{ "cmacchnfr", 0x30088FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmacchnfr<.cc> b,b,limm 00110bbb110010001BBB1111100QQQQQ. */ -+{ "cmacchnfr", 0x30C88F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmacchnfr<.cc> 0,limm,c 00110110110010001111CCCCCC0QQQQQ. */ -+{ "cmacchnfr", 0x36C8F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmacchnfr a,limm,u6 00110110010010001111uuuuuuAAAAAA. */ -+{ "cmacchnfr", 0x3648F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchnfr 0,limm,u6 00110110010010001111uuuuuu111110. */ -+{ "cmacchnfr", 0x3648F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchnfr<.cc> 0,limm,u6 00110110110010001111uuuuuu1QQQQQ. */ -+{ "cmacchnfr", 0x36C8F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmacchnfr 0,limm,s12 00110110100010001111ssssssSSSSSS. */ -+{ "cmacchnfr", 0x3688F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmacchnfr a,limm,limm 00110110000010001111111110AAAAAA. */ -+{ "cmacchnfr", 0x3608FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmacchnfr 0,limm,limm 00110110000010001111111110111110. */ -+{ "cmacchnfr", 0x3608FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmacchnfr<.cc> 0,limm,limm 001101101100100011111111100QQQQQ. */ -+{ "cmacchnfr", 0x36C8FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmachfr a,b,c 00110bbb000001111BBBCCCCCCAAAAAA. */ -+{ "cmachfr", 0x30078000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmachfr 0,b,c 00110bbb000001111BBBCCCCCC111110. */ -+{ "cmachfr", 0x3007803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmachfr<.cc> b,b,c 00110bbb110001111BBBCCCCCC0QQQQQ. */ -+{ "cmachfr", 0x30C78000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmachfr a,b,u6 00110bbb010001111BBBuuuuuuAAAAAA. */ -+{ "cmachfr", 0x30478000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachfr 0,b,u6 00110bbb010001111BBBuuuuuu111110. */ -+{ "cmachfr", 0x3047803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachfr<.cc> b,b,u6 00110bbb110001111BBBuuuuuu1QQQQQ. */ -+{ "cmachfr", 0x30C78020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmachfr b,b,s12 00110bbb100001111BBBssssssSSSSSS. */ -+{ "cmachfr", 0x30878000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmachfr a,limm,c 00110110000001111111CCCCCCAAAAAA. */ -+{ "cmachfr", 0x3607F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmachfr a,b,limm 00110bbb000001111BBB111110AAAAAA. */ -+{ "cmachfr", 0x30078F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmachfr 0,limm,c 00110110000001111111CCCCCC111110. */ -+{ "cmachfr", 0x3607F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmachfr 0,b,limm 00110bbb000001111BBB111110111110. */ -+{ "cmachfr", 0x30078FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmachfr<.cc> b,b,limm 00110bbb110001111BBB1111100QQQQQ. */ -+{ "cmachfr", 0x30C78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmachfr<.cc> 0,limm,c 00110110110001111111CCCCCC0QQQQQ. */ -+{ "cmachfr", 0x36C7F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmachfr a,limm,u6 00110110010001111111uuuuuuAAAAAA. */ -+{ "cmachfr", 0x3647F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachfr 0,limm,u6 00110110010001111111uuuuuu111110. */ -+{ "cmachfr", 0x3647F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachfr<.cc> 0,limm,u6 00110110110001111111uuuuuu1QQQQQ. */ -+{ "cmachfr", 0x36C7F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmachfr 0,limm,s12 00110110100001111111ssssssSSSSSS. */ -+{ "cmachfr", 0x3687F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmachfr a,limm,limm 00110110000001111111111110AAAAAA. */ -+{ "cmachfr", 0x3607FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmachfr 0,limm,limm 00110110000001111111111110111110. */ -+{ "cmachfr", 0x3607FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmachfr<.cc> 0,limm,limm 001101101100011111111111100QQQQQ. */ -+{ "cmachfr", 0x36C7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmachnfr a,b,c 00110bbb000001101BBBCCCCCCAAAAAA. */ -+{ "cmachnfr", 0x30068000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmachnfr 0,b,c 00110bbb000001101BBBCCCCCC111110. */ -+{ "cmachnfr", 0x3006803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmachnfr<.cc> b,b,c 00110bbb110001101BBBCCCCCC0QQQQQ. */ -+{ "cmachnfr", 0x30C68000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmachnfr a,b,u6 00110bbb010001101BBBuuuuuuAAAAAA. */ -+{ "cmachnfr", 0x30468000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachnfr 0,b,u6 00110bbb010001101BBBuuuuuu111110. */ -+{ "cmachnfr", 0x3046803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachnfr<.cc> b,b,u6 00110bbb110001101BBBuuuuuu1QQQQQ. */ -+{ "cmachnfr", 0x30C68020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmachnfr b,b,s12 00110bbb100001101BBBssssssSSSSSS. */ -+{ "cmachnfr", 0x30868000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmachnfr a,limm,c 00110110000001101111CCCCCCAAAAAA. */ -+{ "cmachnfr", 0x3606F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmachnfr a,b,limm 00110bbb000001101BBB111110AAAAAA. */ -+{ "cmachnfr", 0x30068F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmachnfr 0,limm,c 00110110000001101111CCCCCC111110. */ -+{ "cmachnfr", 0x3606F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmachnfr 0,b,limm 00110bbb000001101BBB111110111110. */ -+{ "cmachnfr", 0x30068FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmachnfr<.cc> b,b,limm 00110bbb110001101BBB1111100QQQQQ. */ -+{ "cmachnfr", 0x30C68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmachnfr<.cc> 0,limm,c 00110110110001101111CCCCCC0QQQQQ. */ -+{ "cmachnfr", 0x36C6F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmachnfr a,limm,u6 00110110010001101111uuuuuuAAAAAA. */ -+{ "cmachnfr", 0x3646F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachnfr 0,limm,u6 00110110010001101111uuuuuu111110. */ -+{ "cmachnfr", 0x3646F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachnfr<.cc> 0,limm,u6 00110110110001101111uuuuuu1QQQQQ. */ -+{ "cmachnfr", 0x36C6F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmachnfr 0,limm,s12 00110110100001101111ssssssSSSSSS. */ -+{ "cmachnfr", 0x3686F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmachnfr a,limm,limm 00110110000001101111111110AAAAAA. */ -+{ "cmachnfr", 0x3606FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmachnfr 0,limm,limm 00110110000001101111111110111110. */ -+{ "cmachnfr", 0x3606FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmachnfr<.cc> 0,limm,limm 001101101100011011111111100QQQQQ. */ -+{ "cmachnfr", 0x36C6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmp b,c 00100bbb000011001BBBCCCCCCRRRRRR. */ -+{ "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmp<.cc> b,c 00100bbb110011001BBBCCCCCC0QQQQQ. */ -+{ "cmp", 0x20CC8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* cmp b,u6 00100bbb010011001BBBuuuuuuRRRRRR. */ -+{ "cmp", 0x204C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmp<.cc> b,u6 00100bbb110011001BBBuuuuuu1QQQQQ. */ -+{ "cmp", 0x20CC8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmp b,s12 00100bbb100011001BBBssssssSSSSSS. */ -+{ "cmp", 0x208C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmp limm,c 00100110000011001111CCCCCCRRRRRR. */ -+{ "cmp", 0x260CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmp b,limm 00100bbb000011001BBB111110RRRRRR. */ -+{ "cmp", 0x200C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmp<.cc> b,limm 00100bbb110011001BBB1111100QQQQQ. */ -+{ "cmp", 0x20CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmp<.cc> limm,c 00100110110011001111CCCCCC0QQQQQ. */ -+{ "cmp", 0x26CCF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmp limm,u6 00100110010011001111uuuuuuRRRRRR. */ -+{ "cmp", 0x264CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmp<.cc> limm,u6 00100110110011001111uuuuuu1QQQQQ. */ -+{ "cmp", 0x26CCF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmp limm,s12 00100110100011001111ssssssSSSSSS. */ -+{ "cmp", 0x268CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmp limm,limm 00100110000011001111111110RRRRRR. */ -+{ "cmp", 0x260CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmp<.cc> limm,limm 001001101100110011111111100QQQQQ. */ -+{ "cmp", 0x26CCFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpl OPERAND_RB,RC 01011bbb000011001BBBccccccRRRRRR. */ -+{ "cmpl", 0x580C8000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpl<.cc> OPERAND_RB,RC 01011bbb110011001BBBcccccc0QQQQQ. */ -+{ "cmpl", 0x58CC8000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* cmpl OPERAND_RB,u6 01011bbb010011001BBBuuuuuuRRRRRR. */ -+{ "cmpl", 0x584C8000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpl<.cc> OPERAND_RB,u6 01011bbb110011001BBBuuuuuu1QQQQQ. */ -+{ "cmpl", 0x58CC8020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpl OPERAND_RB,s12 01011bbb100011001BBBssssssSSSSSS. */ -+{ "cmpl", 0x588C8000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpl ximm,RC 01011100000011001111ccccccRRRRRR. */ -+{ "cmpl", 0x5C0CF000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpl OPERAND_RB,ximm 01011bbb000011001BBB111100RRRRRR. */ -+{ "cmpl", 0x580C8F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* cmpl<.cc> OPERAND_RB,ximm 01011bbb110011001BBB1111000QQQQQ. */ -+{ "cmpl", 0x58CC8F00, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_CC }}, -+ -+/* cmpl limm,RC 01011110000011001111ccccccRRRRRR. */ -+{ "cmpl", 0x5E0CF000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpl OPERAND_RB,limm 01011bbb000011001BBB111110RRRRRR. */ -+{ "cmpl", 0x580C8F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpl<.cc> OPERAND_RB,limm 01011bbb110011001BBB1111100QQQQQ. */ -+{ "cmpl", 0x58CC8F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpychfr a,b,c 00110bbb000001011BBBCCCCCCAAAAAA. */ -+{ "cmpychfr", 0x30058000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpychfr 0,b,c 00110bbb000001011BBBCCCCCC111110. */ -+{ "cmpychfr", 0x3005803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpychfr<.cc> b,b,c 00110bbb110001011BBBCCCCCC0QQQQQ. */ -+{ "cmpychfr", 0x30C58000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpychfr a,b,u6 00110bbb010001011BBBuuuuuuAAAAAA. */ -+{ "cmpychfr", 0x30458000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychfr 0,b,u6 00110bbb010001011BBBuuuuuu111110. */ -+{ "cmpychfr", 0x3045803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychfr<.cc> b,b,u6 00110bbb110001011BBBuuuuuu1QQQQQ. */ -+{ "cmpychfr", 0x30C58020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpychfr b,b,s12 00110bbb100001011BBBssssssSSSSSS. */ -+{ "cmpychfr", 0x30858000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpychfr a,limm,c 00110110000001011111CCCCCCAAAAAA. */ -+{ "cmpychfr", 0x3605F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpychfr a,b,limm 00110bbb000001011BBB111110AAAAAA. */ -+{ "cmpychfr", 0x30058F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpychfr 0,limm,c 00110110000001011111CCCCCC111110. */ -+{ "cmpychfr", 0x3605F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpychfr 0,b,limm 00110bbb000001011BBB111110111110. */ -+{ "cmpychfr", 0x30058FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpychfr<.cc> b,b,limm 00110bbb110001011BBB1111100QQQQQ. */ -+{ "cmpychfr", 0x30C58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpychfr<.cc> 0,limm,c 00110110110001011111CCCCCC0QQQQQ. */ -+{ "cmpychfr", 0x36C5F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpychfr a,limm,u6 00110110010001011111uuuuuuAAAAAA. */ -+{ "cmpychfr", 0x3645F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychfr 0,limm,u6 00110110010001011111uuuuuu111110. */ -+{ "cmpychfr", 0x3645F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychfr<.cc> 0,limm,u6 00110110110001011111uuuuuu1QQQQQ. */ -+{ "cmpychfr", 0x36C5F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpychfr 0,limm,s12 00110110100001011111ssssssSSSSSS. */ -+{ "cmpychfr", 0x3685F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpychfr a,limm,limm 00110110000001011111111110AAAAAA. */ -+{ "cmpychfr", 0x3605FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpychfr 0,limm,limm 00110110000001011111111110111110. */ -+{ "cmpychfr", 0x3605FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpychfr<.cc> 0,limm,limm 001101101100010111111111100QQQQQ. */ -+{ "cmpychfr", 0x36C5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpychnfr a,b,c 00110bbb000000101BBBCCCCCCAAAAAA. */ -+{ "cmpychnfr", 0x30028000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpychnfr 0,b,c 00110bbb000000001BBBCCCCCC111110. */ -+{ "cmpychnfr", 0x3000803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpychnfr<.cc> b,b,c 00110bbb110000001BBBCCCCCC0QQQQQ. */ -+{ "cmpychnfr", 0x30C08000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpychnfr a,b,u6 00110bbb010000001BBBuuuuuuAAAAAA. */ -+{ "cmpychnfr", 0x30408000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychnfr 0,b,u6 00110bbb010000001BBBuuuuuu111110. */ -+{ "cmpychnfr", 0x3040803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychnfr<.cc> b,b,u6 00110bbb110000001BBBuuuuuu1QQQQQ. */ -+{ "cmpychnfr", 0x30C08020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpychnfr b,b,s12 00110bbb100000001BBBssssssSSSSSS. */ -+{ "cmpychnfr", 0x30808000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpychnfr a,limm,c 00110110000000001111CCCCCCAAAAAA. */ -+{ "cmpychnfr", 0x3600F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpychnfr a,b,limm 00110bbb000000001BBB111110AAAAAA. */ -+{ "cmpychnfr", 0x30008F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpychnfr 0,limm,c 00110110000000001111CCCCCC111110. */ -+{ "cmpychnfr", 0x3600F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpychnfr 0,b,limm 00110bbb000000001BBB111110111110. */ -+{ "cmpychnfr", 0x30008FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpychnfr<.cc> b,b,limm 00110bbb110000001BBB1111100QQQQQ. */ -+{ "cmpychnfr", 0x30C08F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpychnfr<.cc> 0,limm,c 00110110110000001111CCCCCC0QQQQQ. */ -+{ "cmpychnfr", 0x36C0F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpychnfr a,limm,u6 00110110010000001111uuuuuuAAAAAA. */ -+{ "cmpychnfr", 0x3640F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychnfr 0,limm,u6 00110110010000001111uuuuuu111110. */ -+{ "cmpychnfr", 0x3640F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychnfr<.cc> 0,limm,u6 00110110110000001111uuuuuu1QQQQQ. */ -+{ "cmpychnfr", 0x36C0F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpychnfr 0,limm,s12 00110110100000001111ssssssSSSSSS. */ -+{ "cmpychnfr", 0x3680F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpychnfr a,limm,limm 00110110000000001111111110AAAAAA. */ -+{ "cmpychnfr", 0x3600FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpychnfr 0,limm,limm 00110110000000001111111110111110. */ -+{ "cmpychnfr", 0x3600FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpychnfr<.cc> 0,limm,limm 001101101100000011111111100QQQQQ. */ -+{ "cmpychnfr", 0x36C0FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpyhfmr a,b,c 00110bbb000110110BBBCCCCCCAAAAAA. */ -+{ "cmpyhfmr", 0x301B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfmr 0,b,c 00110bbb000110110BBBCCCCCC111110. */ -+{ "cmpyhfmr", 0x301B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfmr<.cc> b,b,c 00110bbb110110110BBBCCCCCC0QQQQQ. */ -+{ "cmpyhfmr", 0x30DB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhfmr a,b,u6 00110bbb010110110BBBuuuuuuAAAAAA. */ -+{ "cmpyhfmr", 0x305B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfmr 0,b,u6 00110bbb010110110BBBuuuuuu111110. */ -+{ "cmpyhfmr", 0x305B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfmr<.cc> b,b,u6 00110bbb110110110BBBuuuuuu1QQQQQ. */ -+{ "cmpyhfmr", 0x30DB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhfmr b,b,s12 00110bbb100110110BBBssssssSSSSSS. */ -+{ "cmpyhfmr", 0x309B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhfmr a,limm,c 00110110000110110111CCCCCCAAAAAA. */ -+{ "cmpyhfmr", 0x361B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfmr a,b,limm 00110bbb000110110BBB111110AAAAAA. */ -+{ "cmpyhfmr", 0x301B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhfmr 0,limm,c 00110110000110110111CCCCCC111110. */ -+{ "cmpyhfmr", 0x361B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfmr 0,b,limm 00110bbb000110110BBB111110111110. */ -+{ "cmpyhfmr", 0x301B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhfmr<.cc> b,b,limm 00110bbb110110110BBB1111100QQQQQ. */ -+{ "cmpyhfmr", 0x30DB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpyhfmr<.cc> 0,limm,c 00110110110110110111CCCCCC0QQQQQ. */ -+{ "cmpyhfmr", 0x36DB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhfmr a,limm,u6 00110110010110110111uuuuuuAAAAAA. */ -+{ "cmpyhfmr", 0x365B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfmr 0,limm,u6 00110110010110110111uuuuuu111110. */ -+{ "cmpyhfmr", 0x365B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfmr<.cc> 0,limm,u6 00110110110110110111uuuuuu1QQQQQ. */ -+{ "cmpyhfmr", 0x36DB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhfmr 0,limm,s12 00110110100110110111ssssssSSSSSS. */ -+{ "cmpyhfmr", 0x369B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhfmr a,limm,limm 00110110000110110111111110AAAAAA. */ -+{ "cmpyhfmr", 0x361B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhfmr 0,limm,limm 00110110000110110111111110111110. */ -+{ "cmpyhfmr", 0x361B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhfmr<.cc> 0,limm,limm 001101101101101101111111100QQQQQ. */ -+{ "cmpyhfmr", 0x36DB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpyhfr a,b,c 00110bbb000000011BBBCCCCCCAAAAAA. */ -+{ "cmpyhfr", 0x30018000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfr 0,b,c 00110bbb000000011BBBCCCCCC111110. */ -+{ "cmpyhfr", 0x3001803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfr<.cc> b,b,c 00110bbb110000011BBBCCCCCC0QQQQQ. */ -+{ "cmpyhfr", 0x30C18000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhfr a,b,u6 00110bbb010000011BBBuuuuuuAAAAAA. */ -+{ "cmpyhfr", 0x30418000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfr 0,b,u6 00110bbb010000011BBBuuuuuu111110. */ -+{ "cmpyhfr", 0x3041803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfr<.cc> b,b,u6 00110bbb110000011BBBuuuuuu1QQQQQ. */ -+{ "cmpyhfr", 0x30C18020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhfr b,b,s12 00110bbb100000011BBBssssssSSSSSS. */ -+{ "cmpyhfr", 0x30818000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhfr a,limm,c 00110110000000011111CCCCCCAAAAAA. */ -+{ "cmpyhfr", 0x3601F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfr a,b,limm 00110bbb000000011BBB111110AAAAAA. */ -+{ "cmpyhfr", 0x30018F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhfr 0,limm,c 00110110000000011111CCCCCC111110. */ -+{ "cmpyhfr", 0x3601F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfr 0,b,limm 00110bbb000000011BBB111110111110. */ -+{ "cmpyhfr", 0x30018FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhfr<.cc> b,b,limm 00110bbb110000011BBB1111100QQQQQ. */ -+{ "cmpyhfr", 0x30C18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpyhfr<.cc> 0,limm,c 00110110110000011111CCCCCC0QQQQQ. */ -+{ "cmpyhfr", 0x36C1F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhfr a,limm,u6 00110110010000011111uuuuuuAAAAAA. */ -+{ "cmpyhfr", 0x3641F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfr 0,limm,u6 00110110010000011111uuuuuu111110. */ -+{ "cmpyhfr", 0x3641F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfr<.cc> 0,limm,u6 00110110110000011111uuuuuu1QQQQQ. */ -+{ "cmpyhfr", 0x36C1F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhfr 0,limm,s12 00110110100000011111ssssssSSSSSS. */ -+{ "cmpyhfr", 0x3681F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhfr a,limm,limm 00110110000000011111111110AAAAAA. */ -+{ "cmpyhfr", 0x3601FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhfr 0,limm,limm 00110110000000011111111110111110. */ -+{ "cmpyhfr", 0x3601FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhfr<.cc> 0,limm,limm 001101101100000111111111100QQQQQ. */ -+{ "cmpyhfr", 0x36C1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpyhnfr a,b,c 00110bbb000000001BBBCCCCCCAAAAAA. */ -+{ "cmpyhnfr", 0x30008000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhnfr 0,b,c 00110bbb000000101BBBCCCCCC111110. */ -+{ "cmpyhnfr", 0x3002803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhnfr<.cc> b,b,c 00110bbb110000101BBBCCCCCC0QQQQQ. */ -+{ "cmpyhnfr", 0x30C28000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhnfr a,b,u6 00110bbb010000101BBBuuuuuuAAAAAA. */ -+{ "cmpyhnfr", 0x30428000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhnfr 0,b,u6 00110bbb010000101BBBuuuuuu111110. */ -+{ "cmpyhnfr", 0x3042803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhnfr<.cc> b,b,u6 00110bbb110000101BBBuuuuuu1QQQQQ. */ -+{ "cmpyhnfr", 0x30C28020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhnfr b,b,s12 00110bbb100000101BBBssssssSSSSSS. */ -+{ "cmpyhnfr", 0x30828000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhnfr a,limm,c 00110110000000101111CCCCCCAAAAAA. */ -+{ "cmpyhnfr", 0x3602F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhnfr a,b,limm 00110bbb000000101BBB111110AAAAAA. */ -+{ "cmpyhnfr", 0x30028F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhnfr 0,limm,c 00110110000000101111CCCCCC111110. */ -+{ "cmpyhnfr", 0x3602F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhnfr 0,b,limm 00110bbb000000101BBB111110111110. */ -+{ "cmpyhnfr", 0x30028FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhnfr<.cc> b,b,limm 00110bbb110000101BBB1111100QQQQQ. */ -+{ "cmpyhnfr", 0x30C28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpyhnfr<.cc> 0,limm,c 00110110110000101111CCCCCC0QQQQQ. */ -+{ "cmpyhnfr", 0x36C2F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhnfr a,limm,u6 00110110010000101111uuuuuuAAAAAA. */ -+{ "cmpyhnfr", 0x3642F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhnfr 0,limm,u6 00110110010000101111uuuuuu111110. */ -+{ "cmpyhnfr", 0x3642F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhnfr<.cc> 0,limm,u6 00110110110000101111uuuuuu1QQQQQ. */ -+{ "cmpyhnfr", 0x36C2F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhnfr 0,limm,s12 00110110100000101111ssssssSSSSSS. */ -+{ "cmpyhnfr", 0x3682F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhnfr a,limm,limm 00110110000000101111111110AAAAAA. */ -+{ "cmpyhnfr", 0x3602FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhnfr 0,limm,limm 00110110000000101111111110111110. */ -+{ "cmpyhnfr", 0x3602FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhnfr<.cc> 0,limm,limm 001101101100001011111111100QQQQQ. */ -+{ "cmpyhnfr", 0x36C2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmp_s b,h 01110bbbhhh100HH. */ -+{ "cmp_s", 0x00007010, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { 0 }}, -+ -+/* cmp_s h,s3 01110ssshhh101HH. */ -+{ "cmp_s", 0x00007014, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* cmp_s b,limm 01110bbb11010011. */ -+{ "cmp_s", 0x000070D3, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* cmp_s limm,s3 01110sss11010111. */ -+{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS. */ -+{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, BRANCH, NONE, { OPERAND_RB, OPERAND_SIMM13_A16_20 }, { C_DNZ_D }}, -+ -+/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA. */ -+{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110. */ -+{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ. */ -+{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA. */ -+{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110. */ -+{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ. */ -+{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA. */ -+{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110. */ -+{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ. */ -+{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA. */ -+{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110. */ -+{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ. */ -+{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS. */ -+{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS. */ -+{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA. */ -+{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA. */ -+{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110. */ -+{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110. */ -+{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ. */ -+{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ. */ -+{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA. */ -+{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA. */ -+{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110. */ -+{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110. */ -+{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ. */ -+{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ. */ -+{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA. */ -+{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110. */ -+{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ. */ -+{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA. */ -+{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110. */ -+{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ. */ -+{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS. */ -+{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS. */ -+{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA. */ -+{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* div<.f> 0,limm,limm 0010111000000100F111111110111110. */ -+{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ. */ -+{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA. */ -+{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* div<.f> 0,limm,limm 0010111000000100F111111110111110. */ -+{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ. */ -+{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* divf<.f> a,b,c 00110bbb00010000FBBBCCCCCCAAAAAA. */ -+{ "divf", 0x30100000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divf<.f> 0,b,c 00110bbb00010000FBBBCCCCCC111110. */ -+{ "divf", 0x3010003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divf<.f><.cc> b,b,c 00110bbb11010000FBBBCCCCCC0QQQQQ. */ -+{ "divf", 0x30D00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divf<.f> a,b,u6 00110bbb01010000FBBBuuuuuuAAAAAA. */ -+{ "divf", 0x30500000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divf<.f> 0,b,u6 00110bbb01010000FBBBuuuuuu111110. */ -+{ "divf", 0x3050003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divf<.f><.cc> b,b,u6 00110bbb11010000FBBBuuuuuu1QQQQQ. */ -+{ "divf", 0x30D00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divf<.f> b,b,s12 00110bbb10010000FBBBssssssSSSSSS. */ -+{ "divf", 0x30900000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divf<.f> a,limm,c 0011011000010000F111CCCCCCAAAAAA. */ -+{ "divf", 0x36107000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divf<.f> a,b,limm 00110bbb00010000FBBB111110AAAAAA. */ -+{ "divf", 0x30100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divf<.f> 0,limm,c 0011011000010000F111CCCCCC111110. */ -+{ "divf", 0x3610703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divf<.f> 0,b,limm 00110bbb00010000FBBB111110111110. */ -+{ "divf", 0x30100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divf<.f><.cc> b,b,limm 00110bbb11010000FBBB1111100QQQQQ. */ -+{ "divf", 0x30D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* divf<.f><.cc> 0,limm,c 0011011011010000F111CCCCCC0QQQQQ. */ -+{ "divf", 0x36D07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divf<.f> a,limm,u6 0011011001010000F111uuuuuuAAAAAA. */ -+{ "divf", 0x36507000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divf<.f> 0,limm,u6 0011011001010000F111uuuuuu111110. */ -+{ "divf", 0x3650703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divf<.f><.cc> 0,limm,u6 0011011011010000F111uuuuuu1QQQQQ. */ -+{ "divf", 0x36D07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divf<.f> 0,limm,s12 0011011010010000F111ssssssSSSSSS. */ -+{ "divf", 0x36907000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divf<.f> a,limm,limm 0011011000010000F111111110AAAAAA. */ -+{ "divf", 0x36107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divf<.f> 0,limm,limm 0011011000010000F111111110111110. */ -+{ "divf", 0x36107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divf<.f><.cc> 0,limm,limm 0011011011010000F1111111100QQQQQ. */ -+{ "divf", 0x36D07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* divl<.f> OPERAND_RA,RB,RC 01011bbb00100100FBBBccccccaaaaaa. */ -+{ "divl", 0x58240000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divl<.f> 0,RB,RC 01011bbb00100100FBBBcccccc111110. */ -+{ "divl", 0x5824003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11100100FBBBcccccc0QQQQQ. */ -+{ "divl", 0x58E40000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divl<.f> OPERAND_RA,RB,u6 01011bbb01100100FBBBuuuuuuaaaaaa. */ -+{ "divl", 0x58640000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divl<.f> 0,RB,u6 01011bbb01100100FBBBuuuuuu111110. */ -+{ "divl", 0x5864003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11100100FBBBuuuuuu1QQQQQ. */ -+{ "divl", 0x58E40020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divl<.f> OPERAND_RB,RB,s12 01011bbb10100100FBBBssssssSSSSSS. */ -+{ "divl", 0x58A40000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divl<.f> OPERAND_RA,ximm,RC 0101110000100100F111ccccccaaaaaa. */ -+{ "divl", 0x5C247000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* divl<.f> OPERAND_RA,RB,ximm 01011bbb00100100FBBB111100aaaaaa. */ -+{ "divl", 0x58240F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* divl<.f> 0,ximm,RC 0101110000100100F111cccccc111110. */ -+{ "divl", 0x5C24703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* divl<.f> 0,RB,ximm 01011bbb00100100FBBB111100111110. */ -+{ "divl", 0x58240F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* divl<.f><.cc> 0,ximm,RC 0101110011100100F111cccccc0QQQQQ. */ -+{ "divl", 0x5CE47000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11100100FBBB1111000QQQQQ. */ -+{ "divl", 0x58E40F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* divl<.f> OPERAND_RA,ximm,u6 0101110001100100F111uuuuuuaaaaaa. */ -+{ "divl", 0x5C647000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divl<.f> 0,ximm,u6 0101110001100100F111uuuuuu111110. */ -+{ "divl", 0x5C64703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divl<.f><.cc> 0,ximm,u6 0101110011100100F111uuuuuu1QQQQQ. */ -+{ "divl", 0x5CE47020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divl<.f> OPERAND_RA,limm,RC 0101111000100100F111ccccccaaaaaa. */ -+{ "divl", 0x5E247000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divl<.f> OPERAND_RA,RB,limm 01011bbb00100100FBBB111110aaaaaa. */ -+{ "divl", 0x58240F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divl<.f> 0,limm,RC 0101111000100100F111cccccc111110. */ -+{ "divl", 0x5E24703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divl<.f> 0,RB,limm 01011bbb00100100FBBB111110111110. */ -+{ "divl", 0x58240FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divl<.f><.cc> 0,limm,RC 0101111011100100F111cccccc0QQQQQ. */ -+{ "divl", 0x5EE47000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11100100FBBB1111100QQQQQ. */ -+{ "divl", 0x58E40F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* divl<.f> OPERAND_RA,limm,u6 0101111001100100F111uuuuuuaaaaaa. */ -+{ "divl", 0x5E647000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divl<.f> 0,limm,u6 0101111001100100F111uuuuuu111110. */ -+{ "divl", 0x5E64703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divl<.f><.cc> 0,limm,u6 0101111011100100F111uuuuuu1QQQQQ. */ -+{ "divl", 0x5EE47020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divl<.f> 0,ximm,s12 0101110010100100F111ssssssSSSSSS. */ -+{ "divl", 0x5CA47000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divl<.f> 0,limm,s12 0101111010100100F111ssssssSSSSSS. */ -+{ "divl", 0x5EA47000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divl<.f> OPERAND_RA,ximm,ximm 0101110000100100F111111100aaaaaa. */ -+{ "divl", 0x5C247F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* divl<.f> 0,ximm,ximm 0101110000100100F111111100111110. */ -+{ "divl", 0x5C247F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* divl<.f><.cc> 0,ximm,ximm 0101110011100100F1111111000QQQQQ. */ -+{ "divl", 0x5CE47F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* divl<.f> OPERAND_RA,limm,limm 0101111000100100F111111110aaaaaa. */ -+{ "divl", 0x5E247F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divl<.f> 0,limm,limm 0101111000100100F111111110111110. */ -+{ "divl", 0x5E247FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divl<.f><.cc> 0,limm,limm 0101111011100100F1111111100QQQQQ. */ -+{ "divl", 0x5EE47F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA. */ -+{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110. */ -+{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ. */ -+{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA. */ -+{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110. */ -+{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ. */ -+{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA. */ -+{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110. */ -+{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ. */ -+{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA. */ -+{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110. */ -+{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ. */ -+{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS. */ -+{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS. */ -+{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA. */ -+{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f> a,b,limm 00101bbb00000101FBBB111110AAAAAA. */ -+{ "divu", 0x28050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divu<.f> 0,limm,c 0010111000000101F111CCCCCC111110. */ -+{ "divu", 0x2E05703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f> 0,b,limm 00101bbb00000101FBBB111110111110. */ -+{ "divu", 0x28050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divu<.f><.cc> b,b,limm 00101bbb11000101FBBB1111100QQQQQ. */ -+{ "divu", 0x28C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* divu<.f><.cc> 0,limm,c 0010111011000101F111CCCCCC0QQQQQ. */ -+{ "divu", 0x2EC57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA. */ -+{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f> a,b,limm 00101bbb00000101FBBB111110AAAAAA. */ -+{ "divu", 0x28050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divu<.f> 0,limm,c 0010111000000101F111CCCCCC111110. */ -+{ "divu", 0x2E05703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f> 0,b,limm 00101bbb00000101FBBB111110111110. */ -+{ "divu", 0x28050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divu<.f><.cc> b,b,limm 00101bbb11000101FBBB1111100QQQQQ. */ -+{ "divu", 0x28C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* divu<.f><.cc> 0,limm,c 0010111011000101F111CCCCCC0QQQQQ. */ -+{ "divu", 0x2EC57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divu<.f> a,limm,u6 0010111001000101F111uuuuuuAAAAAA. */ -+{ "divu", 0x2E457000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f> 0,limm,u6 0010111001000101F111uuuuuu111110. */ -+{ "divu", 0x2E45703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f><.cc> 0,limm,u6 0010111011000101F111uuuuuu1QQQQQ. */ -+{ "divu", 0x2EC57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divu<.f> a,limm,u6 0010111001000101F111uuuuuuAAAAAA. */ -+{ "divu", 0x2E457000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f> 0,limm,u6 0010111001000101F111uuuuuu111110. */ -+{ "divu", 0x2E45703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f><.cc> 0,limm,u6 0010111011000101F111uuuuuu1QQQQQ. */ -+{ "divu", 0x2EC57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divu<.f> 0,limm,s12 0010111010000101F111ssssssSSSSSS. */ -+{ "divu", 0x2E857000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divu<.f> 0,limm,s12 0010111010000101F111ssssssSSSSSS. */ -+{ "divu", 0x2E857000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divu<.f> a,limm,limm 0010111000000101F111111110AAAAAA. */ -+{ "divu", 0x2E057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divu<.f> 0,limm,limm 0010111000000101F111111110111110. */ -+{ "divu", 0x2E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divu<.f><.cc> 0,limm,limm 0010111011000101F1111111100QQQQQ. */ -+{ "divu", 0x2EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* divu<.f> a,limm,limm 0010111000000101F111111110AAAAAA. */ -+{ "divu", 0x2E057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divu<.f> 0,limm,limm 0010111000000101F111111110111110. */ -+{ "divu", 0x2E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divu<.f><.cc> 0,limm,limm 0010111011000101F1111111100QQQQQ. */ -+{ "divu", 0x2EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* divul<.f> OPERAND_RA,RB,RC 01011bbb00100101FBBBccccccaaaaaa. */ -+{ "divul", 0x58250000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divul<.f> 0,RB,RC 01011bbb00100101FBBBcccccc111110. */ -+{ "divul", 0x5825003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divul<.f><.cc> OPERAND_RB,RB,RC 01011bbb11100101FBBBcccccc0QQQQQ. */ -+{ "divul", 0x58E50000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divul<.f> OPERAND_RA,RB,u6 01011bbb01100101FBBBuuuuuuaaaaaa. */ -+{ "divul", 0x58650000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divul<.f> 0,RB,u6 01011bbb01100101FBBBuuuuuu111110. */ -+{ "divul", 0x5865003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divul<.f><.cc> OPERAND_RB,RB,u6 01011bbb11100101FBBBuuuuuu1QQQQQ. */ -+{ "divul", 0x58E50020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divul<.f> OPERAND_RB,RB,s12 01011bbb10100101FBBBssssssSSSSSS. */ -+{ "divul", 0x58A50000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divul<.f> OPERAND_RA,ximm,RC 0101110000100101F111ccccccaaaaaa. */ -+{ "divul", 0x5C257000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* divul<.f> OPERAND_RA,RB,ximm 01011bbb00100101FBBB111100aaaaaa. */ -+{ "divul", 0x58250F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* divul<.f> 0,ximm,RC 0101110000100101F111cccccc111110. */ -+{ "divul", 0x5C25703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* divul<.f> 0,RB,ximm 01011bbb00100101FBBB111100111110. */ -+{ "divul", 0x58250F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* divul<.f><.cc> 0,ximm,RC 0101110011100101F111cccccc0QQQQQ. */ -+{ "divul", 0x5CE57000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divul<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11100101FBBB1111000QQQQQ. */ -+{ "divul", 0x58E50F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* divul<.f> OPERAND_RA,ximm,u6 0101110001100101F111uuuuuuaaaaaa. */ -+{ "divul", 0x5C657000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divul<.f> 0,ximm,u6 0101110001100101F111uuuuuu111110. */ -+{ "divul", 0x5C65703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divul<.f><.cc> 0,ximm,u6 0101110011100101F111uuuuuu1QQQQQ. */ -+{ "divul", 0x5CE57020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divul<.f> OPERAND_RA,limm,RC 0101111000100101F111ccccccaaaaaa. */ -+{ "divul", 0x5E257000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divul<.f> OPERAND_RA,RB,limm 01011bbb00100101FBBB111110aaaaaa. */ -+{ "divul", 0x58250F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divul<.f> 0,limm,RC 0101111000100101F111cccccc111110. */ -+{ "divul", 0x5E25703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divul<.f> 0,RB,limm 01011bbb00100101FBBB111110111110. */ -+{ "divul", 0x58250FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divul<.f><.cc> 0,limm,RC 0101111011100101F111cccccc0QQQQQ. */ -+{ "divul", 0x5EE57000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divul<.f><.cc> OPERAND_RB,RB,limm 01011bbb11100101FBBB1111100QQQQQ. */ -+{ "divul", 0x58E50F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* divul<.f> OPERAND_RA,limm,u6 0101111001100101F111uuuuuuaaaaaa. */ -+{ "divul", 0x5E657000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divul<.f> 0,limm,u6 0101111001100101F111uuuuuu111110. */ -+{ "divul", 0x5E65703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divul<.f><.cc> 0,limm,u6 0101111011100101F111uuuuuu1QQQQQ. */ -+{ "divul", 0x5EE57020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divul<.f> 0,ximm,s12 0101110010100101F111ssssssSSSSSS. */ -+{ "divul", 0x5CA57000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divul<.f> 0,limm,s12 0101111010100101F111ssssssSSSSSS. */ -+{ "divul", 0x5EA57000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divul<.f> OPERAND_RA,ximm,ximm 0101110000100101F111111100aaaaaa. */ -+{ "divul", 0x5C257F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* divul<.f> 0,ximm,ximm 0101110000100101F111111100111110. */ -+{ "divul", 0x5C257F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* divul<.f><.cc> 0,ximm,ximm 0101110011100101F1111111000QQQQQ. */ -+{ "divul", 0x5CE57F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* divul<.f> OPERAND_RA,limm,limm 0101111000100101F111111110aaaaaa. */ -+{ "divul", 0x5E257F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divul<.f> 0,limm,limm 0101111000100101F111111110111110. */ -+{ "divul", 0x5E257FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divul<.f><.cc> 0,limm,limm 0101111011100101F1111111100QQQQQ. */ -+{ "divul", 0x5EE57F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmach<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA. */ -+{ "dmach", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmach<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110. */ -+{ "dmach", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmach<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ. */ -+{ "dmach", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmach<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA. */ -+{ "dmach", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmach<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110. */ -+{ "dmach", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmach<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ. */ -+{ "dmach", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmach<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS. */ -+{ "dmach", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmach<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA. */ -+{ "dmach", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmach<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA. */ -+{ "dmach", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmach<.f> 0,limm,c 0010111000010010F111CCCCCC111110. */ -+{ "dmach", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmach<.f> 0,b,limm 00101bbb00010010FBBB111110111110. */ -+{ "dmach", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmach<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ. */ -+{ "dmach", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmach<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ. */ -+{ "dmach", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmach<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA. */ -+{ "dmach", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmach<.f> 0,limm,u6 0010111001010010F111uuuuuu111110. */ -+{ "dmach", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmach<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ. */ -+{ "dmach", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmach<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS. */ -+{ "dmach", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmach<.f> a,limm,limm 0010111000010010F111111110AAAAAA. */ -+{ "dmach", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmach<.f> 0,limm,limm 0010111000010010F111111110111110. */ -+{ "dmach", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmach<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ. */ -+{ "dmach", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA. */ -+{ "dmachbl", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachbl<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110. */ -+{ "dmachbl", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachbl<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ. */ -+{ "dmachbl", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA. */ -+{ "dmachbl", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbl<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110. */ -+{ "dmachbl", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbl<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ. */ -+{ "dmachbl", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS. */ -+{ "dmachbl", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachbl<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA. */ -+{ "dmachbl", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachbl<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA. */ -+{ "dmachbl", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachbl<.f> 0,limm,c 0011011000011000F111CCCCCC111110. */ -+{ "dmachbl", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachbl<.f> 0,b,limm 00110bbb00011000FBBB111110111110. */ -+{ "dmachbl", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachbl<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ. */ -+{ "dmachbl", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachbl<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ. */ -+{ "dmachbl", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA. */ -+{ "dmachbl", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbl<.f> 0,limm,u6 0011011001011000F111uuuuuu111110. */ -+{ "dmachbl", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbl<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ. */ -+{ "dmachbl", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS. */ -+{ "dmachbl", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachbl<.f> a,limm,limm 0011011000011000F111111110AAAAAA. */ -+{ "dmachbl", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachbl<.f> 0,limm,limm 0011011000011000F111111110111110. */ -+{ "dmachbl", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachbl<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ. */ -+{ "dmachbl", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA. */ -+{ "dmachbm", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachbm<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110. */ -+{ "dmachbm", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachbm<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ. */ -+{ "dmachbm", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA. */ -+{ "dmachbm", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbm<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110. */ -+{ "dmachbm", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbm<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ. */ -+{ "dmachbm", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS. */ -+{ "dmachbm", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachbm<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA. */ -+{ "dmachbm", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachbm<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA. */ -+{ "dmachbm", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachbm<.f> 0,limm,c 0011011000011001F111CCCCCC111110. */ -+{ "dmachbm", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachbm<.f> 0,b,limm 00110bbb00011001FBBB111110111110. */ -+{ "dmachbm", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachbm<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ. */ -+{ "dmachbm", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachbm<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ. */ -+{ "dmachbm", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA. */ -+{ "dmachbm", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbm<.f> 0,limm,u6 0011011001011001F111uuuuuu111110. */ -+{ "dmachbm", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbm<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ. */ -+{ "dmachbm", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS. */ -+{ "dmachbm", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachbm<.f> a,limm,limm 0011011000011001F111111110AAAAAA. */ -+{ "dmachbm", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachbm<.f> 0,limm,limm 0011011000011001F111111110111110. */ -+{ "dmachbm", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachbm<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ. */ -+{ "dmachbm", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachf<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA. */ -+{ "dmachf", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachf<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110. */ -+{ "dmachf", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachf<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ. */ -+{ "dmachf", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachf<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA. */ -+{ "dmachf", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachf<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110. */ -+{ "dmachf", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachf<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ. */ -+{ "dmachf", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachf<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS. */ -+{ "dmachf", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachf<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA. */ -+{ "dmachf", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachf<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA. */ -+{ "dmachf", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachf<.f> 0,limm,c 0010111001101100F111CCCCCC111110. */ -+{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachf<.f> 0,b,limm 00101bbb00101100FBBB111110111110. */ -+{ "dmachf", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachf<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ. */ -+{ "dmachf", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachf<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ. */ -+{ "dmachf", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachf<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA. */ -+{ "dmachf", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachf<.f> 0,limm,u6 0010111001101100F111uuuuuu111110. */ -+{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachf<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ. */ -+{ "dmachf", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachf<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS. */ -+{ "dmachf", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachf<.f> a,limm,limm 0010111000101100F111111110AAAAAA. */ -+{ "dmachf", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachf<.f> 0,limm,limm 0010111000101100F111111110111110. */ -+{ "dmachf", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachf<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ. */ -+{ "dmachf", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> a,b,c 00101bbb00101101FBBBCCCCCCAAAAAA. */ -+{ "dmachfr", 0x282D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachfr<.f> 0,b,c 00101bbb00101101FBBBCCCCCC111110. */ -+{ "dmachfr", 0x282D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachfr<.f><.cc> b,b,c 00101bbb11101101FBBBCCCCCC0QQQQQ. */ -+{ "dmachfr", 0x28ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> a,b,u6 00101bbb01101101FBBBuuuuuuAAAAAA. */ -+{ "dmachfr", 0x286D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachfr<.f> 0,b,u6 00101bbb01101101FBBBuuuuuu111110. */ -+{ "dmachfr", 0x286D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachfr<.f><.cc> b,b,u6 00101bbb11101101FBBBuuuuuu1QQQQQ. */ -+{ "dmachfr", 0x28ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> b,b,s12 00101bbb10101101FBBBssssssSSSSSS. */ -+{ "dmachfr", 0x28AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachfr<.f> a,limm,c 0010111000101101F111CCCCCCAAAAAA. */ -+{ "dmachfr", 0x2E2D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachfr<.f> a,b,limm 00101bbb00101101FBBB111110AAAAAA. */ -+{ "dmachfr", 0x282D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachfr<.f> 0,limm,c 0010111001101101F111CCCCCC111110. */ -+{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachfr<.f> 0,b,limm 00101bbb00101101FBBB111110111110. */ -+{ "dmachfr", 0x282D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachfr<.f><.cc> b,b,limm 00101bbb11101101FBBB1111100QQQQQ. */ -+{ "dmachfr", 0x28ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachfr<.f><.cc> 0,limm,c 0010111011101101F111CCCCCC0QQQQQ. */ -+{ "dmachfr", 0x2EED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> a,limm,u6 0010111001101101F111uuuuuuAAAAAA. */ -+{ "dmachfr", 0x2E6D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachfr<.f> 0,limm,u6 0010111001101101F111uuuuuu111110. */ -+{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachfr<.f><.cc> 0,limm,u6 0010111011101101F111uuuuuu1QQQQQ. */ -+{ "dmachfr", 0x2EED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> 0,limm,s12 0010111010101101F111ssssssSSSSSS. */ -+{ "dmachfr", 0x2EAD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachfr<.f> a,limm,limm 0010111000101101F111111110AAAAAA. */ -+{ "dmachfr", 0x2E2D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachfr<.f> 0,limm,limm 0010111000101101F111111110111110. */ -+{ "dmachfr", 0x2E2D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachfr<.f><.cc> 0,limm,limm 0010111011101101F1111111100QQQQQ. */ -+{ "dmachfr", 0x2EED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachu<.f> a,b,c 00101bbb00010011FBBBCCCCCCAAAAAA. */ -+{ "dmachu", 0x28130000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachu<.f> 0,b,c 00101bbb00010011FBBBCCCCCC111110. */ -+{ "dmachu", 0x2813003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachu<.f><.cc> b,b,c 00101bbb11010011FBBBCCCCCC0QQQQQ. */ -+{ "dmachu", 0x28D30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachu<.f> a,b,u6 00101bbb01010011FBBBuuuuuuAAAAAA. */ -+{ "dmachu", 0x28530000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachu<.f> 0,b,u6 00101bbb01010011FBBBuuuuuu111110. */ -+{ "dmachu", 0x2853003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachu<.f><.cc> b,b,u6 00101bbb11010011FBBBuuuuuu1QQQQQ. */ -+{ "dmachu", 0x28D30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachu<.f> b,b,s12 00101bbb10010011FBBBssssssSSSSSS. */ -+{ "dmachu", 0x28930000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachu<.f> a,limm,c 0010111000010011F111CCCCCCAAAAAA. */ -+{ "dmachu", 0x2E137000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachu<.f> a,b,limm 00101bbb00010011FBBB111110AAAAAA. */ -+{ "dmachu", 0x28130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachu<.f> 0,limm,c 0010111000010011F111CCCCCC111110. */ -+{ "dmachu", 0x2E13703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachu<.f> 0,b,limm 00101bbb00010011FBBB111110111110. */ -+{ "dmachu", 0x28130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachu<.f><.cc> b,b,limm 00101bbb11010011FBBB1111100QQQQQ. */ -+{ "dmachu", 0x28D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachu<.f><.cc> 0,limm,c 0010111011010011F111CCCCCC0QQQQQ. */ -+{ "dmachu", 0x2ED37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachu<.f> a,limm,u6 0010111001010011F111uuuuuuAAAAAA. */ -+{ "dmachu", 0x2E537000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachu<.f> 0,limm,u6 0010111001010011F111uuuuuu111110. */ -+{ "dmachu", 0x2E53703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachu<.f><.cc> 0,limm,u6 0010111011010011F111uuuuuu1QQQQQ. */ -+{ "dmachu", 0x2ED37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachu<.f> 0,limm,s12 0010111010010011F111ssssssSSSSSS. */ -+{ "dmachu", 0x2E937000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachu<.f> a,limm,limm 0010111000010011F111111110AAAAAA. */ -+{ "dmachu", 0x2E137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachu<.f> 0,limm,limm 0010111000010011F111111110111110. */ -+{ "dmachu", 0x2E137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachu<.f><.cc> 0,limm,limm 0010111011010011F1111111100QQQQQ. */ -+{ "dmachu", 0x2ED37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA. */ -+{ "dmacwh", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwh<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110. */ -+{ "dmacwh", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwh<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ. */ -+{ "dmacwh", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA. */ -+{ "dmacwh", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwh<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110. */ -+{ "dmacwh", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwh<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ. */ -+{ "dmacwh", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS. */ -+{ "dmacwh", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwh<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA. */ -+{ "dmacwh", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwh<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA. */ -+{ "dmacwh", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwh<.f> 0,limm,c 0010111000110110F111CCCCCC111110. */ -+{ "dmacwh", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwh<.f> 0,b,limm 00101bbb00110110FBBB111110111110. */ -+{ "dmacwh", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwh<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ. */ -+{ "dmacwh", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmacwh<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ. */ -+{ "dmacwh", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA. */ -+{ "dmacwh", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwh<.f> 0,limm,u6 0010111001110110F111uuuuuu111110. */ -+{ "dmacwh", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwh<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ. */ -+{ "dmacwh", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS. */ -+{ "dmacwh", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwh<.f> a,limm,limm 0010111000110110F111111110AAAAAA. */ -+{ "dmacwh", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwh<.f> 0,limm,limm 0010111000110110F111111110111110. */ -+{ "dmacwh", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwh<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ. */ -+{ "dmacwh", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> a,b,c 00110bbb00110111FBBBCCCCCCAAAAAA. */ -+{ "dmacwhf", 0x30370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhf<.f> 0,b,c 00110bbb00110111FBBBCCCCCC111110. */ -+{ "dmacwhf", 0x3037003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> b,b,c 00110bbb11110111FBBBCCCCCC0QQQQQ. */ -+{ "dmacwhf", 0x30F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> a,b,u6 00110bbb01110111FBBBuuuuuuAAAAAA. */ -+{ "dmacwhf", 0x30770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhf<.f> 0,b,u6 00110bbb01110111FBBBuuuuuu111110. */ -+{ "dmacwhf", 0x3077003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> b,b,u6 00110bbb11110111FBBBuuuuuu1QQQQQ. */ -+{ "dmacwhf", 0x30F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> b,b,s12 00110bbb10110111FBBBssssssSSSSSS. */ -+{ "dmacwhf", 0x30B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwhf<.f> a,limm,c 0011011000110111F111CCCCCCAAAAAA. */ -+{ "dmacwhf", 0x36377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhf<.f> a,b,limm 00110bbb00110111FBBB111110AAAAAA. */ -+{ "dmacwhf", 0x30370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwhf<.f> 0,limm,c 0011011000110111F111CCCCCC111110. */ -+{ "dmacwhf", 0x3637703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhf<.f> 0,b,limm 00110bbb00110111FBBB111110111110. */ -+{ "dmacwhf", 0x30370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> b,b,limm 00110bbb11110111FBBB1111100QQQQQ. */ -+{ "dmacwhf", 0x30F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f><.cc> 0,limm,c 0011011011110111F111CCCCCC0QQQQQ. */ -+{ "dmacwhf", 0x36F77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> a,limm,u6 0011011001110111F111uuuuuuAAAAAA. */ -+{ "dmacwhf", 0x36777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhf<.f> 0,limm,u6 0011011001110111F111uuuuuu111110. */ -+{ "dmacwhf", 0x3677703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> 0,limm,u6 0011011011110111F111uuuuuu1QQQQQ. */ -+{ "dmacwhf", 0x36F77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> 0,limm,s12 0011011010110111F111ssssssSSSSSS. */ -+{ "dmacwhf", 0x36B77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwhf<.f> a,limm,limm 0011011000110111F111111110AAAAAA. */ -+{ "dmacwhf", 0x36377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwhf<.f> 0,limm,limm 0011011000110111F111111110111110. */ -+{ "dmacwhf", 0x36377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ. */ -+{ "dmacwhf", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA. */ -+{ "dmacwhu", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhu<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110. */ -+{ "dmacwhu", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ. */ -+{ "dmacwhu", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA. */ -+{ "dmacwhu", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhu<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110. */ -+{ "dmacwhu", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ. */ -+{ "dmacwhu", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS. */ -+{ "dmacwhu", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwhu<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA. */ -+{ "dmacwhu", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhu<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA. */ -+{ "dmacwhu", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwhu<.f> 0,limm,c 0010111000110111F111CCCCCC111110. */ -+{ "dmacwhu", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhu<.f> 0,b,limm 00101bbb00110111FBBB111110111110. */ -+{ "dmacwhu", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ. */ -+{ "dmacwhu", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ. */ -+{ "dmacwhu", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA. */ -+{ "dmacwhu", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhu<.f> 0,limm,u6 0010111001110111F111uuuuuu111110. */ -+{ "dmacwhu", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ. */ -+{ "dmacwhu", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS. */ -+{ "dmacwhu", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwhu<.f> a,limm,limm 0010111000110111F111111110AAAAAA. */ -+{ "dmacwhu", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwhu<.f> 0,limm,limm 0010111000110111F111111110111110. */ -+{ "dmacwhu", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ. */ -+{ "dmacwhu", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmb 00100011011011110001RRR000111111. */ -+{ "dmb", 0x236F103F, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* dmb u3 00100011011011110001RRRuuu111111. */ -+{ "dmb", 0x236F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_UIMM3_23 }, { 0 }}, -+ -+/* dmpyh<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */ -+{ "dmpyh", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyh<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110. */ -+{ "dmpyh", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyh<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ. */ -+{ "dmpyh", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyh<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA. */ -+{ "dmpyh", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyh<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110. */ -+{ "dmpyh", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyh<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ. */ -+{ "dmpyh", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyh<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS. */ -+{ "dmpyh", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyh<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA. */ -+{ "dmpyh", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyh<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA. */ -+{ "dmpyh", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyh<.f> 0,limm,c 0010111000010000F111CCCCCC111110. */ -+{ "dmpyh", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyh<.f> 0,b,limm 00101bbb00010000FBBB111110111110. */ -+{ "dmpyh", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyh<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ. */ -+{ "dmpyh", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyh<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ. */ -+{ "dmpyh", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyh<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA. */ -+{ "dmpyh", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyh<.f> 0,limm,u6 0010111001010000F111uuuuuu111110. */ -+{ "dmpyh", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyh<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ. */ -+{ "dmpyh", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyh<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS. */ -+{ "dmpyh", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyh<.f> a,limm,limm 0010111000010000F111111110AAAAAA. */ -+{ "dmpyh", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyh<.f> 0,limm,limm 0010111000010000F111111110111110. */ -+{ "dmpyh", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyh<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ. */ -+{ "dmpyh", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA. */ -+{ "dmpyhbl", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110. */ -+{ "dmpyhbl", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhbl", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA. */ -+{ "dmpyhbl", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110. */ -+{ "dmpyhbl", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhbl", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS. */ -+{ "dmpyhbl", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhbl<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA. */ -+{ "dmpyhbl", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbl<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA. */ -+{ "dmpyhbl", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,limm,c 0011011000010110F111CCCCCC111110. */ -+{ "dmpyhbl", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,b,limm 00110bbb00010110FBBB111110111110. */ -+{ "dmpyhbl", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ. */ -+{ "dmpyhbl", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ. */ -+{ "dmpyhbl", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA. */ -+{ "dmpyhbl", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,limm,u6 0011011001010110F111uuuuuu111110. */ -+{ "dmpyhbl", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ. */ -+{ "dmpyhbl", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS. */ -+{ "dmpyhbl", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhbl<.f> a,limm,limm 0011011000010110F111111110AAAAAA. */ -+{ "dmpyhbl", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,limm,limm 0011011000010110F111111110111110. */ -+{ "dmpyhbl", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ. */ -+{ "dmpyhbl", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA. */ -+{ "dmpyhbm", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110. */ -+{ "dmpyhbm", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhbm", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA. */ -+{ "dmpyhbm", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110. */ -+{ "dmpyhbm", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhbm", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS. */ -+{ "dmpyhbm", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhbm<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA. */ -+{ "dmpyhbm", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbm<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA. */ -+{ "dmpyhbm", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,limm,c 0011011000010111F111CCCCCC111110. */ -+{ "dmpyhbm", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,b,limm 00110bbb00010111FBBB111110111110. */ -+{ "dmpyhbm", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ. */ -+{ "dmpyhbm", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ. */ -+{ "dmpyhbm", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA. */ -+{ "dmpyhbm", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,limm,u6 0011011001010111F111uuuuuu111110. */ -+{ "dmpyhbm", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ. */ -+{ "dmpyhbm", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS. */ -+{ "dmpyhbm", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhbm<.f> a,limm,limm 0011011000010111F111111110AAAAAA. */ -+{ "dmpyhbm", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,limm,limm 0011011000010111F111111110111110. */ -+{ "dmpyhbm", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ. */ -+{ "dmpyhbm", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> a,b,c 00101bbb00101010FBBBCCCCCCAAAAAA. */ -+{ "dmpyhf", 0x282A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhf<.f> 0,b,c 00101bbb00101010FBBBCCCCCC111110. */ -+{ "dmpyhf", 0x282A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> b,b,c 00101bbb11101010FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhf", 0x28EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> a,b,u6 00101bbb01101010FBBBuuuuuuAAAAAA. */ -+{ "dmpyhf", 0x286A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhf<.f> 0,b,u6 00101bbb01101010FBBBuuuuuu111110. */ -+{ "dmpyhf", 0x286A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> b,b,u6 00101bbb11101010FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhf", 0x28EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> b,b,s12 00101bbb10101010FBBBssssssSSSSSS. */ -+{ "dmpyhf", 0x28AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhf<.f> a,limm,c 0010111000101010F111CCCCCCAAAAAA. */ -+{ "dmpyhf", 0x2E2A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhf<.f> a,b,limm 00101bbb00101010FBBB111110AAAAAA. */ -+{ "dmpyhf", 0x282A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhf<.f> 0,limm,c 0010111001101010F111CCCCCC111110. */ -+{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhf<.f> 0,b,limm 00101bbb00101010FBBB111110111110. */ -+{ "dmpyhf", 0x282A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> b,b,limm 00101bbb11101010FBBB1111100QQQQQ. */ -+{ "dmpyhf", 0x28EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f><.cc> 0,limm,c 0010111011101010F111CCCCCC0QQQQQ. */ -+{ "dmpyhf", 0x2EEA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> a,limm,u6 0010111001101010F111uuuuuuAAAAAA. */ -+{ "dmpyhf", 0x2E6A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhf<.f> 0,limm,u6 0010111001101010F111uuuuuu111110. */ -+{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> 0,limm,u6 0010111011101010F111uuuuuu1QQQQQ. */ -+{ "dmpyhf", 0x2EEA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> 0,limm,s12 0010111010101010F111ssssssSSSSSS. */ -+{ "dmpyhf", 0x2EAA7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhf<.f> a,limm,limm 0010111000101010F111111110AAAAAA. */ -+{ "dmpyhf", 0x2E2A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhf<.f> 0,limm,limm 0010111000101010F111111110111110. */ -+{ "dmpyhf", 0x2E2A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> 0,limm,limm 0010111011101010F1111111100QQQQQ. */ -+{ "dmpyhf", 0x2EEA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA. */ -+{ "dmpyhfr", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110. */ -+{ "dmpyhfr", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhfr", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA. */ -+{ "dmpyhfr", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110. */ -+{ "dmpyhfr", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhfr", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS. */ -+{ "dmpyhfr", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhfr<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA. */ -+{ "dmpyhfr", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhfr<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA. */ -+{ "dmpyhfr", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,limm,c 0010111001101011F111CCCCCC111110. */ -+{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,b,limm 00101bbb00101011FBBB111110111110. */ -+{ "dmpyhfr", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ. */ -+{ "dmpyhfr", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ. */ -+{ "dmpyhfr", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA. */ -+{ "dmpyhfr", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,limm,u6 0010111001101011F111uuuuuu111110. */ -+{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ. */ -+{ "dmpyhfr", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS. */ -+{ "dmpyhfr", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhfr<.f> a,limm,limm 0010111000101011F111111110AAAAAA. */ -+{ "dmpyhfr", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,limm,limm 0010111000101011F111111110111110. */ -+{ "dmpyhfr", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ. */ -+{ "dmpyhfr", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA. */ -+{ "dmpyhu", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhu<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110. */ -+{ "dmpyhu", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhu", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA. */ -+{ "dmpyhu", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhu<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110. */ -+{ "dmpyhu", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhu", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS. */ -+{ "dmpyhu", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhu<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA. */ -+{ "dmpyhu", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhu<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA. */ -+{ "dmpyhu", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhu<.f> 0,limm,c 0010111000010001F111CCCCCC111110. */ -+{ "dmpyhu", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhu<.f> 0,b,limm 00101bbb00010001FBBB111110111110. */ -+{ "dmpyhu", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ. */ -+{ "dmpyhu", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ. */ -+{ "dmpyhu", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA. */ -+{ "dmpyhu", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhu<.f> 0,limm,u6 0010111001010001F111uuuuuu111110. */ -+{ "dmpyhu", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ. */ -+{ "dmpyhu", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS. */ -+{ "dmpyhu", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhu<.f> a,limm,limm 0010111000010001F111111110AAAAAA. */ -+{ "dmpyhu", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhu<.f> 0,limm,limm 0010111000010001F111111110111110. */ -+{ "dmpyhu", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ. */ -+{ "dmpyhu", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA. */ -+{ "dmpyhwf", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110. */ -+{ "dmpyhwf", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhwf", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA. */ -+{ "dmpyhwf", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110. */ -+{ "dmpyhwf", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhwf", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS. */ -+{ "dmpyhwf", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhwf<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA. */ -+{ "dmpyhwf", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhwf<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA. */ -+{ "dmpyhwf", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,limm,c 0010111001101000F111CCCCCC111110. */ -+{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,b,limm 00101bbb00101000FBBB111110111110. */ -+{ "dmpyhwf", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ. */ -+{ "dmpyhwf", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ. */ -+{ "dmpyhwf", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA. */ -+{ "dmpyhwf", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,limm,u6 0010111001101000F111uuuuuu111110. */ -+{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ. */ -+{ "dmpyhwf", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS. */ -+{ "dmpyhwf", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhwf<.f> a,limm,limm 0010111000101000F111111110AAAAAA. */ -+{ "dmpyhwf", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,limm,limm 0010111000101000F111111110111110. */ -+{ "dmpyhwf", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ. */ -+{ "dmpyhwf", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA. */ -+{ "dmpywh", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywh<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110. */ -+{ "dmpywh", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywh<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ. */ -+{ "dmpywh", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA. */ -+{ "dmpywh", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywh<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110. */ -+{ "dmpywh", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywh<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ. */ -+{ "dmpywh", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS. */ -+{ "dmpywh", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywh<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA. */ -+{ "dmpywh", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywh<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA. */ -+{ "dmpywh", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywh<.f> 0,limm,c 0010111000110010F111CCCCCC111110. */ -+{ "dmpywh", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywh<.f> 0,b,limm 00101bbb00110010FBBB111110111110. */ -+{ "dmpywh", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywh<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ. */ -+{ "dmpywh", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpywh<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ. */ -+{ "dmpywh", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA. */ -+{ "dmpywh", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywh<.f> 0,limm,u6 0010111001110010F111uuuuuu111110. */ -+{ "dmpywh", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywh<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ. */ -+{ "dmpywh", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS. */ -+{ "dmpywh", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywh<.f> a,limm,limm 0010111000110010F111111110AAAAAA. */ -+{ "dmpywh", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywh<.f> 0,limm,limm 0010111000110010F111111110111110. */ -+{ "dmpywh", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywh<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ. */ -+{ "dmpywh", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> a,b,c 00110bbb00110011FBBBCCCCCCAAAAAA. */ -+{ "dmpywhf", 0x30330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhf<.f> 0,b,c 00110bbb00110011FBBBCCCCCC111110. */ -+{ "dmpywhf", 0x3033003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> b,b,c 00110bbb11110011FBBBCCCCCC0QQQQQ. */ -+{ "dmpywhf", 0x30F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> a,b,u6 00110bbb01110011FBBBuuuuuuAAAAAA. */ -+{ "dmpywhf", 0x30730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhf<.f> 0,b,u6 00110bbb01110011FBBBuuuuuu111110. */ -+{ "dmpywhf", 0x3073003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> b,b,u6 00110bbb11110011FBBBuuuuuu1QQQQQ. */ -+{ "dmpywhf", 0x30F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> b,b,s12 00110bbb10110011FBBBssssssSSSSSS. */ -+{ "dmpywhf", 0x30B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywhf<.f> a,limm,c 0011011000110011F111CCCCCCAAAAAA. */ -+{ "dmpywhf", 0x36337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhf<.f> a,b,limm 00110bbb00110011FBBB111110AAAAAA. */ -+{ "dmpywhf", 0x30330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywhf<.f> 0,limm,c 0011011000110011F111CCCCCC111110. */ -+{ "dmpywhf", 0x3633703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhf<.f> 0,b,limm 00110bbb00110011FBBB111110111110. */ -+{ "dmpywhf", 0x30330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> b,b,limm 00110bbb11110011FBBB1111100QQQQQ. */ -+{ "dmpywhf", 0x30F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f><.cc> 0,limm,c 0011011011110011F111CCCCCC0QQQQQ. */ -+{ "dmpywhf", 0x36F37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> a,limm,u6 0011011001110011F111uuuuuuAAAAAA. */ -+{ "dmpywhf", 0x36737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhf<.f> 0,limm,u6 0011011001110011F111uuuuuu111110. */ -+{ "dmpywhf", 0x3673703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> 0,limm,u6 0011011011110011F111uuuuuu1QQQQQ. */ -+{ "dmpywhf", 0x36F37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> 0,limm,s12 0011011010110011F111ssssssSSSSSS. */ -+{ "dmpywhf", 0x36B37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywhf<.f> a,limm,limm 0011011000110011F111111110AAAAAA. */ -+{ "dmpywhf", 0x36337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywhf<.f> 0,limm,limm 0011011000110011F111111110111110. */ -+{ "dmpywhf", 0x36337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> 0,limm,limm 0011011011110011F1111111100QQQQQ. */ -+{ "dmpywhf", 0x36F37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA. */ -+{ "dmpywhu", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhu<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110. */ -+{ "dmpywhu", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ. */ -+{ "dmpywhu", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA. */ -+{ "dmpywhu", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhu<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110. */ -+{ "dmpywhu", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ. */ -+{ "dmpywhu", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS. */ -+{ "dmpywhu", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywhu<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA. */ -+{ "dmpywhu", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhu<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA. */ -+{ "dmpywhu", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywhu<.f> 0,limm,c 0010111000110011F111CCCCCC111110. */ -+{ "dmpywhu", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhu<.f> 0,b,limm 00101bbb00110011FBBB111110111110. */ -+{ "dmpywhu", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ. */ -+{ "dmpywhu", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ. */ -+{ "dmpywhu", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA. */ -+{ "dmpywhu", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhu<.f> 0,limm,u6 0010111001110011F111uuuuuu111110. */ -+{ "dmpywhu", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ. */ -+{ "dmpywhu", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS. */ -+{ "dmpywhu", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywhu<.f> a,limm,limm 0010111000110011F111111110AAAAAA. */ -+{ "dmpywhu", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywhu<.f> 0,limm,limm 0010111000110011F111111110111110. */ -+{ "dmpywhu", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ. */ -+{ "dmpywhu", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsync 00100010011011110001RRRRRR111111. */ -+{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* enter_s u6 110000UU111uuuu0. */ -+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { OPERAND_BRAKET, OPERAND_RRANGE_EL, OPERAND_FP_EL, OPERAND_BLINK_EL, OPERAND_BRAKETdup }, { 0 }}, -+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { OPERAND_BRAKET, OPERAND_R13_EL, OPERAND_FP_EL, OPERAND_BLINK_EL, OPERAND_BRAKETdup }, { 0 }}, -+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ENTER, CD1, { OPERAND_UIMM6_11_S }, { 0 }}, -+ -+/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */ -+{ "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> b,u6 00100bbb01101111DBBBuuuuuu001100. */ -+{ "ex", 0x206F000C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> b,limm 00100bbb00101111DBBB111110001100. */ -+{ "ex", 0x202F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> limm,c 0010011000101111D111CCCCCC001100. */ -+{ "ex", 0x262F700C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> limm,u6 0010011001101111D111uuuuuu001100. */ -+{ "ex", 0x266F700C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> limm,limm 0010011000101111D111111110001100. */ -+{ "ex", 0x262F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* exl<.aq> OPERAND_RB,RC 01011bbb00101111FBBBcccccc001100. */ -+{ "exl", 0x582F000C, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_AQ }}, -+ -+/* extb<.f> b,c 00100bbb00101111FBBBCCCCCC000111. */ -+{ "extb", 0x202F0007, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* extb<.f> 0,c 0010011000101111F111CCCCCC000111. */ -+{ "extb", 0x262F7007, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* extb<.f> b,u6 00100bbb01101111FBBBuuuuuu000111. */ -+{ "extb", 0x206F0007, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* extb<.f> 0,u6 0010011001101111F111uuuuuu000111. */ -+{ "extb", 0x266F7007, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* extb<.f> b,limm 00100bbb00101111FBBB111110000111. */ -+{ "extb", 0x202F0F87, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* extb<.f> 0,limm 0010011000101111F111111110000111. */ -+{ "extb", 0x262F7F87, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* extb_s b,c 01111bbbccc01111. */ -+{ "extb_s", 0x0000780F, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* exth<.f> b,c 00100bbb00101111FBBBCCCCCC001000. */ -+{ "exth", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* exth<.f> 0,c 0010011000101111F111CCCCCC001000. */ -+{ "exth", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* exth<.f> b,u6 00100bbb01101111FBBBuuuuuu001000. */ -+{ "exth", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* exth<.f> 0,u6 0010011001101111F111uuuuuu001000. */ -+{ "exth", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* exth<.f> b,limm 00100bbb00101111FBBB111110001000. */ -+{ "exth", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* exth<.f> 0,limm 0010011000101111F111111110001000. */ -+{ "exth", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* exth_s b,c 01111bbbccc10000. */ -+{ "exth_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* ffs<.f> b,c 00101bbb00101111FBBBCCCCCC010010. */ -+{ "ffs", 0x282F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ffs<.f> 0,c 0010111000101111F111CCCCCC010010. */ -+{ "ffs", 0x2E2F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* ffs<.f> b,u6 00101bbb01101111FBBBuuuuuu010010. */ -+{ "ffs", 0x286F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ffs<.f> 0,u6 0010111001101111F111uuuuuu010010. */ -+{ "ffs", 0x2E6F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ffs<.f> b,limm 00101bbb00101111FBBB111110010010. */ -+{ "ffs", 0x282F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ffs<.f> 0,limm 0010111000101111F111111110010010. */ -+{ "ffs", 0x2E2F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* ffsl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc010010. */ -+{ "ffsl", 0x582F0012, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ffsl<.f> 0,RC 0101111000101111F111cccccc010010. */ -+{ "ffsl", 0x5E2F7012, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* ffsl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu010010. */ -+{ "ffsl", 0x586F0012, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ffsl<.f> 0,u6 0101111001101111F111uuuuuu010010. */ -+{ "ffsl", 0x5E6F7012, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ffsl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100010010. */ -+{ "ffsl", 0x582F0F12, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* ffsl<.f> 0,ximm 0101111000101111F111111100010010. */ -+{ "ffsl", 0x5E2F7F12, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* ffsl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110010010. */ -+{ "ffsl", 0x582F0F92, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ffsl<.f> 0,limm 0101111000101111F111111110010010. */ -+{ "ffsl", 0x5E2F7F92, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* flag c 00100RRR001010010RRRCCCCCCRRRRRR. */ -+{ "flag", 0x20290000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* flag<.cc> c 00100RRR111010010RRRCCCCCC0QQQQQ. */ -+{ "flag", 0x20E90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_RC }, { C_CC }}, -+ -+/* flag u6 00100RRR011010010RRRuuuuuuRRRRRR. */ -+{ "flag", 0x20690000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* flag<.cc> u6 00100RRR111010010RRRuuuuuu1QQQQQ. */ -+{ "flag", 0x20E90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* flag s12 00100RRR101010010RRRssssssSSSSSS. */ -+{ "flag", 0x20A90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* flag limm 00100RRR001010010RRR111110RRRRRR. */ -+{ "flag", 0x20290F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* flag<.cc> limm 00100RRR111010010RRR1111100QQQQQ. */ -+{ "flag", 0x20E90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_LIMM }, { C_CC }}, -+ -+/* flagacc c 00101100001011111000CCCCCC111111. */ -+{ "flagacc", 0x2C2F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RC_CHK }, { 0 }}, -+ -+/* flagacc u6 00101100011011111000uuuuuu111111. */ -+{ "flagacc", 0x2C6F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fls<.f> b,c 00101bbb00101111FBBBCCCCCC010011. */ -+{ "fls", 0x282F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fls<.f> 0,c 0010111000101111F111CCCCCC010011. */ -+{ "fls", 0x2E2F7013, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fls<.f> b,u6 00101bbb01101111FBBBuuuuuu010011. */ -+{ "fls", 0x286F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fls<.f> 0,u6 0010111001101111F111uuuuuu010011. */ -+{ "fls", 0x2E6F7013, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fls<.f> b,limm 00101bbb00101111FBBB111110010011. */ -+{ "fls", 0x282F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fls<.f> 0,limm 0010111000101111F111111110010011. */ -+{ "fls", 0x2E2F7F93, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* flsl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc010011. */ -+{ "flsl", 0x582F0013, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* flsl<.f> 0,RC 0101111000101111F111cccccc010011. */ -+{ "flsl", 0x5E2F7013, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* flsl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu010011. */ -+{ "flsl", 0x586F0013, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* flsl<.f> 0,u6 0101111001101111F111uuuuuu010011. */ -+{ "flsl", 0x5E6F7013, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* flsl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100010011. */ -+{ "flsl", 0x582F0F13, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* flsl<.f> 0,ximm 0101111000101111F111111100010011. */ -+{ "flsl", 0x5E2F7F13, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* flsl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110010011. */ -+{ "flsl", 0x582F0F93, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* flsl<.f> 0,limm 0101111000101111F111111110010011. */ -+{ "flsl", 0x5E2F7F93, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_adds<.f> a,b,c 00111bbb00100010FBBBCCCCCCAAAAAA. */ -+{ "fmp_adds", 0x38220000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_adds<.f> 0,b,c 00111bbb00100010FBBBCCCCCC111110. */ -+{ "fmp_adds", 0x3822003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_adds<.f><.cc> b,b,c 00111bbb11100010FBBBCCCCCC0QQQQQ. */ -+{ "fmp_adds", 0x38E20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fmp_adds<.f> a,b,u6 00111bbb01100010FBBBuuuuuuAAAAAA. */ -+{ "fmp_adds", 0x38620000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_adds<.f> 0,b,u6 00111bbb01100010FBBBuuuuuu111110. */ -+{ "fmp_adds", 0x3862003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_adds<.f><.cc> b,b,u6 00111bbb11100010FBBBuuuuuu1QQQQQ. */ -+{ "fmp_adds", 0x38E20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fmp_adds<.f> b,b,s12 00111bbb10100010FBBBssssssSSSSSS. */ -+{ "fmp_adds", 0x38A20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fmp_adds<.f> a,limm,c 0011111000100010F111CCCCCCAAAAAA. */ -+{ "fmp_adds", 0x3E227000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fmp_adds<.f> a,b,limm 00111bbb00100010FBBB111110AAAAAA. */ -+{ "fmp_adds", 0x38220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_adds<.f> 0,limm,c 0011111000100010F111CCCCCC111110. */ -+{ "fmp_adds", 0x3E22703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fmp_adds<.f> 0,b,limm 00111bbb00100010FBBB111110111110. */ -+{ "fmp_adds", 0x38220FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_adds<.f><.cc> b,b,limm 00111bbb11100010FBBB1111100QQQQQ. */ -+{ "fmp_adds", 0x38E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* fmp_adds<.f><.cc> 0,limm,c 0011111011100010F111CCCCCC0QQQQQ. */ -+{ "fmp_adds", 0x3EE27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fmp_adds<.f> a,limm,u6 0011111001100010F111uuuuuuAAAAAA. */ -+{ "fmp_adds", 0x3E627000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_adds<.f> 0,limm,u6 0011111001100010F111uuuuuu111110. */ -+{ "fmp_adds", 0x3E62703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_adds<.f><.cc> 0,limm,u6 0011111011100010F111uuuuuu1QQQQQ. */ -+{ "fmp_adds", 0x3EE27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fmp_adds<.f> 0,limm,s12 0011111010100010F111ssssssSSSSSS. */ -+{ "fmp_adds", 0x3EA27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fmp_adds<.f> a,limm,limm 0011111000100010F111111110AAAAAA. */ -+{ "fmp_adds", 0x3E227F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fmp_adds<.f> 0,limm,limm 0011111000100010F111111110111110. */ -+{ "fmp_adds", 0x3E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fmp_adds<.f><.cc> 0,limm,limm 0011111011100010F1111111100QQQQQ. */ -+{ "fmp_adds", 0x3EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* fmp_atan<.f> b,c 00111bbb00101111FBBBCCCCCC100101. */ -+{ "fmp_atan", 0x382F0025, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_atan<.f> 0,c 0011111000101111F111CCCCCC100101. */ -+{ "fmp_atan", 0x3E2F7025, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_atan<.f> b,u6 00111bbb01101111FBBBuuuuuu100101. */ -+{ "fmp_atan", 0x386F0025, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_atan<.f> 0,u6 0011111001101111F111uuuuuu100101. */ -+{ "fmp_atan", 0x3E6F7025, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_atan<.f> b,limm 00111bbb00101111FBBB111110100101. */ -+{ "fmp_atan", 0x382F0FA5, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_atan<.f> 0,limm 0011111000101111F111111110100101. */ -+{ "fmp_atan", 0x3E2F7FA5, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_atan15<.f> b,c 00111bbb00101111FBBBCCCCCC101110. */ -+{ "fmp_atan15", 0x382F002E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_atan15<.f> 0,c 0011111000101111F111CCCCCC101110. */ -+{ "fmp_atan15", 0x3E2F702E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_atan15<.f> b,u6 00111bbb01101111FBBBuuuuuu101110. */ -+{ "fmp_atan15", 0x386F002E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_atan15<.f> 0,u6 0011111001101111F111uuuuuu101110. */ -+{ "fmp_atan15", 0x3E6F702E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_atan15<.f> b,limm 00111bbb00101111FBBB111110101110. */ -+{ "fmp_atan15", 0x382F0FAE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_atan15<.f> 0,limm 0011111000101111F111111110101110. */ -+{ "fmp_atan15", 0x3E2F7FAE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_cos<.f> b,c 00111bbb00101111FBBBCCCCCC011110. */ -+{ "fmp_cos", 0x382F001E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_cos<.f> 0,c 0011111000101111F111CCCCCC011110. */ -+{ "fmp_cos", 0x3E2F701E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_cos<.f> b,u6 00111bbb01101111FBBBuuuuuu011110. */ -+{ "fmp_cos", 0x386F001E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_cos<.f> 0,u6 0011111001101111F111uuuuuu011110. */ -+{ "fmp_cos", 0x3E6F701E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_cos<.f> b,limm 00111bbb00101111FBBB111110011110. */ -+{ "fmp_cos", 0x382F0F9E, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_cos<.f> 0,limm 0011111000101111F111111110011110. */ -+{ "fmp_cos", 0x3E2F7F9E, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_cos15<.f> b,c 00111bbb00101111FBBBCCCCCC101100. */ -+{ "fmp_cos15", 0x382F002C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_cos15<.f> 0,c 0011111000101111F111CCCCCC101100. */ -+{ "fmp_cos15", 0x3E2F702C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_cos15<.f> b,u6 00111bbb01101111FBBBuuuuuu101100. */ -+{ "fmp_cos15", 0x386F002C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_cos15<.f> 0,u6 0011111001101111F111uuuuuu101100. */ -+{ "fmp_cos15", 0x3E6F702C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_cos15<.f> b,limm 00111bbb00101111FBBB111110101100. */ -+{ "fmp_cos15", 0x382F0FAC, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_cos15<.f> 0,limm 0011111000101111F111111110101100. */ -+{ "fmp_cos15", 0x3E2F7FAC, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_divf<.f> a,b,c 00111bbb00100000FBBBCCCCCCAAAAAA. */ -+{ "fmp_divf", 0x38200000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_divf<.f> 0,b,c 00111bbb00100000FBBBCCCCCC111110. */ -+{ "fmp_divf", 0x3820003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_divf<.f><.cc> b,b,c 00111bbb11100000FBBBCCCCCC0QQQQQ. */ -+{ "fmp_divf", 0x38E00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fmp_divf<.f> a,b,u6 00111bbb01100000FBBBuuuuuuAAAAAA. */ -+{ "fmp_divf", 0x38600000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_divf<.f> 0,b,u6 00111bbb01100000FBBBuuuuuu111110. */ -+{ "fmp_divf", 0x3860003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_divf<.f><.cc> b,b,u6 00111bbb11100000FBBBuuuuuu1QQQQQ. */ -+{ "fmp_divf", 0x38E00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fmp_divf<.f> b,b,s12 00111bbb10100000FBBBssssssSSSSSS. */ -+{ "fmp_divf", 0x38A00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fmp_divf<.f> a,limm,c 0011111000100000F111CCCCCCAAAAAA. */ -+{ "fmp_divf", 0x3E207000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fmp_divf<.f> a,b,limm 00111bbb00100000FBBB111110AAAAAA. */ -+{ "fmp_divf", 0x38200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_divf<.f> 0,limm,c 0011111000100000F111CCCCCC111110. */ -+{ "fmp_divf", 0x3E20703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fmp_divf<.f> 0,b,limm 00111bbb00100000FBBB111110111110. */ -+{ "fmp_divf", 0x38200FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_divf<.f><.cc> b,b,limm 00111bbb11100000FBBB1111100QQQQQ. */ -+{ "fmp_divf", 0x38E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* fmp_divf<.f><.cc> 0,limm,c 0011111011100000F111CCCCCC0QQQQQ. */ -+{ "fmp_divf", 0x3EE07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fmp_divf<.f> a,limm,u6 0011111001100000F111uuuuuuAAAAAA. */ -+{ "fmp_divf", 0x3E607000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_divf<.f> 0,limm,u6 0011111001100000F111uuuuuu111110. */ -+{ "fmp_divf", 0x3E60703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_divf<.f><.cc> 0,limm,u6 0011111011100000F111uuuuuu1QQQQQ. */ -+{ "fmp_divf", 0x3EE07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fmp_divf<.f> 0,limm,s12 0011111010100000F111ssssssSSSSSS. */ -+{ "fmp_divf", 0x3EA07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fmp_divf<.f> a,limm,limm 0011111000100000F111111110AAAAAA. */ -+{ "fmp_divf", 0x3E207F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fmp_divf<.f> 0,limm,limm 0011111000100000F111111110111110. */ -+{ "fmp_divf", 0x3E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fmp_divf<.f><.cc> 0,limm,limm 0011111011100000F1111111100QQQQQ. */ -+{ "fmp_divf", 0x3EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* fmp_divf15<.f> a,b,c 00111bbb00100001FBBBCCCCCCAAAAAA. */ -+{ "fmp_divf15", 0x38210000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_divf15<.f> 0,b,c 00111bbb00100001FBBBCCCCCC111110. */ -+{ "fmp_divf15", 0x3821003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_divf15<.f><.cc> b,b,c 00111bbb11100001FBBBCCCCCC0QQQQQ. */ -+{ "fmp_divf15", 0x38E10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fmp_divf15<.f> a,b,u6 00111bbb01100001FBBBuuuuuuAAAAAA. */ -+{ "fmp_divf15", 0x38610000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_divf15<.f> 0,b,u6 00111bbb01100001FBBBuuuuuu111110. */ -+{ "fmp_divf15", 0x3861003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_divf15<.f><.cc> b,b,u6 00111bbb11100001FBBBuuuuuu1QQQQQ. */ -+{ "fmp_divf15", 0x38E10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fmp_divf15<.f> b,b,s12 00111bbb10100001FBBBssssssSSSSSS. */ -+{ "fmp_divf15", 0x38A10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fmp_divf15<.f> a,limm,c 0011111000100001F111CCCCCCAAAAAA. */ -+{ "fmp_divf15", 0x3E217000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fmp_divf15<.f> a,b,limm 00111bbb00100001FBBB111110AAAAAA. */ -+{ "fmp_divf15", 0x38210F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_divf15<.f> 0,limm,c 0011111000100001F111CCCCCC111110. */ -+{ "fmp_divf15", 0x3E21703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fmp_divf15<.f> 0,b,limm 00111bbb00100001FBBB111110111110. */ -+{ "fmp_divf15", 0x38210FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_divf15<.f><.cc> b,b,limm 00111bbb11100001FBBB1111100QQQQQ. */ -+{ "fmp_divf15", 0x38E10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* fmp_divf15<.f><.cc> 0,limm,c 0011111011100001F111CCCCCC0QQQQQ. */ -+{ "fmp_divf15", 0x3EE17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fmp_divf15<.f> a,limm,u6 0011111001100001F111uuuuuuAAAAAA. */ -+{ "fmp_divf15", 0x3E617000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_divf15<.f> 0,limm,u6 0011111001100001F111uuuuuu111110. */ -+{ "fmp_divf15", 0x3E61703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_divf15<.f><.cc> 0,limm,u6 0011111011100001F111uuuuuu1QQQQQ. */ -+{ "fmp_divf15", 0x3EE17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fmp_divf15<.f> 0,limm,s12 0011111010100001F111ssssssSSSSSS. */ -+{ "fmp_divf15", 0x3EA17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fmp_divf15<.f> a,limm,limm 0011111000100001F111111110AAAAAA. */ -+{ "fmp_divf15", 0x3E217F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fmp_divf15<.f> 0,limm,limm 0011111000100001F111111110111110. */ -+{ "fmp_divf15", 0x3E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fmp_divf15<.f><.cc> 0,limm,limm 0011111011100001F1111111100QQQQQ. */ -+{ "fmp_divf15", 0x3EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* fmp_exp2<.f> b,c 00111bbb00101111FBBBCCCCCC100111. */ -+{ "fmp_exp2", 0x382F0027, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_exp2<.f> 0,c 0011111000101111F111CCCCCC100111. */ -+{ "fmp_exp2", 0x3E2F7027, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_exp2<.f> b,u6 00111bbb01101111FBBBuuuuuu100111. */ -+{ "fmp_exp2", 0x386F0027, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_exp2<.f> 0,u6 0011111001101111F111uuuuuu100111. */ -+{ "fmp_exp2", 0x3E6F7027, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_exp2<.f> b,limm 00111bbb00101111FBBB111110100111. */ -+{ "fmp_exp2", 0x382F0FA7, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_exp2<.f> 0,limm 0011111000101111F111111110100111. */ -+{ "fmp_exp2", 0x3E2F7FA7, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_exp215<.f> b,c 00111bbb00101111FBBBCCCCCC101111. */ -+{ "fmp_exp215", 0x382F002F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_exp215<.f> 0,c 0011111000101111F111CCCCCC101111. */ -+{ "fmp_exp215", 0x3E2F702F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_exp215<.f> b,u6 00111bbb01101111FBBBuuuuuu101111. */ -+{ "fmp_exp215", 0x386F002F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_exp215<.f> 0,u6 0011111001101111F111uuuuuu101111. */ -+{ "fmp_exp215", 0x3E6F702F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_exp215<.f> b,limm 00111bbb00101111FBBB111110101111. */ -+{ "fmp_exp215", 0x382F0FAF, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_exp215<.f> 0,limm 0011111000101111F111111110101111. */ -+{ "fmp_exp215", 0x3E2F7FAF, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_log2<.f> b,c 00111bbb00101111FBBBCCCCCC100110. */ -+{ "fmp_log2", 0x382F0026, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_log2<.f> 0,c 0011111000101111F111CCCCCC100110. */ -+{ "fmp_log2", 0x3E2F7026, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_log2<.f> b,u6 00111bbb01101111FBBBuuuuuu100110. */ -+{ "fmp_log2", 0x386F0026, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_log2<.f> 0,u6 0011111001101111F111uuuuuu100110. */ -+{ "fmp_log2", 0x3E6F7026, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_log2<.f> b,limm 00111bbb00101111FBBB111110100110. */ -+{ "fmp_log2", 0x382F0FA6, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_log2<.f> 0,limm 0011111000101111F111111110100110. */ -+{ "fmp_log2", 0x3E2F7FA6, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_log215<.f> b,c 00111bbb00101111FBBBCCCCCC110000. */ -+{ "fmp_log215", 0x382F0030, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_log215<.f> 0,c 0011111000101111F111CCCCCC110000. */ -+{ "fmp_log215", 0x3E2F7030, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_log215<.f> b,u6 00111bbb01101111FBBBuuuuuu110000. */ -+{ "fmp_log215", 0x386F0030, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_log215<.f> 0,u6 0011111001101111F111uuuuuu110000. */ -+{ "fmp_log215", 0x3E6F7030, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_log215<.f> b,limm 00111bbb00101111FBBB111110110000. */ -+{ "fmp_log215", 0x382F0FB0, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_log215<.f> 0,limm 0011111000101111F111111110110000. */ -+{ "fmp_log215", 0x3E2F7FB0, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_recip<.f> b,c 00111bbb00101111FBBBCCCCCC101010. */ -+{ "fmp_recip", 0x382F002A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_recip<.f> 0,c 0011111000101111F111CCCCCC101010. */ -+{ "fmp_recip", 0x3E2F702A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_recip<.f> b,u6 00111bbb01101111FBBBuuuuuu101010. */ -+{ "fmp_recip", 0x386F002A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_recip<.f> 0,u6 0011111001101111F111uuuuuu101010. */ -+{ "fmp_recip", 0x3E6F702A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_recip<.f> b,limm 00111bbb00101111FBBB111110101010. */ -+{ "fmp_recip", 0x382F0FAA, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_recip<.f> 0,limm 0011111000101111F111111110101010. */ -+{ "fmp_recip", 0x3E2F7FAA, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_recip15<.f> b,c 00111bbb00101111FBBBCCCCCC101011. */ -+{ "fmp_recip15", 0x382F002B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_recip15<.f> 0,c 0011111000101111F111CCCCCC101011. */ -+{ "fmp_recip15", 0x3E2F702B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_recip15<.f> b,u6 00111bbb01101111FBBBuuuuuu101011. */ -+{ "fmp_recip15", 0x386F002B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_recip15<.f> 0,u6 0011111001101111F111uuuuuu101011. */ -+{ "fmp_recip15", 0x3E6F702B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_recip15<.f> b,limm 00111bbb00101111FBBB111110101011. */ -+{ "fmp_recip15", 0x382F0FAB, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_recip15<.f> 0,limm 0011111000101111F111111110101011. */ -+{ "fmp_recip15", 0x3E2F7FAB, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_rndh<.f> b,c 00111bbb00101111FBBBCCCCCC101001. */ -+{ "fmp_rndh", 0x382F0029, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_rndh<.f> 0,c 0011111000101111F111CCCCCC101001. */ -+{ "fmp_rndh", 0x3E2F7029, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_rndh<.f> b,u6 00111bbb01101111FBBBuuuuuu101001. */ -+{ "fmp_rndh", 0x386F0029, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_rndh<.f> 0,u6 0011111001101111F111uuuuuu101001. */ -+{ "fmp_rndh", 0x3E6F7029, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_rndh<.f> b,limm 00111bbb00101111FBBB111110101001. */ -+{ "fmp_rndh", 0x382F0FA9, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_rndh<.f> 0,limm 0011111000101111F111111110101001. */ -+{ "fmp_rndh", 0x3E2F7FA9, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sath<.f> b,c 00111bbb00101111FBBBCCCCCC101000. */ -+{ "fmp_sath", 0x382F0028, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sath<.f> 0,c 0011111000101111F111CCCCCC101000. */ -+{ "fmp_sath", 0x3E2F7028, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sath<.f> b,u6 00111bbb01101111FBBBuuuuuu101000. */ -+{ "fmp_sath", 0x386F0028, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sath<.f> 0,u6 0011111001101111F111uuuuuu101000. */ -+{ "fmp_sath", 0x3E6F7028, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sath<.f> b,limm 00111bbb00101111FBBB111110101000. */ -+{ "fmp_sath", 0x382F0FA8, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sath<.f> 0,limm 0011111000101111F111111110101000. */ -+{ "fmp_sath", 0x3E2F7FA8, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sin<.f> b,c 00111bbb00101111FBBBCCCCCC011111. */ -+{ "fmp_sin", 0x382F001F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sin<.f> 0,c 0011111000101111F111CCCCCC011111. */ -+{ "fmp_sin", 0x3E2F701F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sin<.f> b,u6 00111bbb01101111FBBBuuuuuu011111. */ -+{ "fmp_sin", 0x386F001F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sin<.f> 0,u6 0011111001101111F111uuuuuu011111. */ -+{ "fmp_sin", 0x3E6F701F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sin<.f> b,limm 00111bbb00101111FBBB111110011111. */ -+{ "fmp_sin", 0x382F0F9F, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sin<.f> 0,limm 0011111000101111F111111110011111. */ -+{ "fmp_sin", 0x3E2F7F9F, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sin15<.f> b,c 00111bbb00101111FBBBCCCCCC101101. */ -+{ "fmp_sin15", 0x382F002D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sin15<.f> 0,c 0011111000101111F111CCCCCC101101. */ -+{ "fmp_sin15", 0x3E2F702D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sin15<.f> b,u6 00111bbb01101111FBBBuuuuuu101101. */ -+{ "fmp_sin15", 0x386F002D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sin15<.f> 0,u6 0011111001101111F111uuuuuu101101. */ -+{ "fmp_sin15", 0x3E6F702D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sin15<.f> b,limm 00111bbb00101111FBBB111110101101. */ -+{ "fmp_sin15", 0x382F0FAD, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sin15<.f> 0,limm 0011111000101111F111111110101101. */ -+{ "fmp_sin15", 0x3E2F7FAD, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sqrtf<.f> b,c 00111bbb00101111FBBBCCCCCC100000. */ -+{ "fmp_sqrtf", 0x382F0020, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sqrtf<.f> 0,c 0011111000101111F111CCCCCC100000. */ -+{ "fmp_sqrtf", 0x3E2F7020, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sqrtf<.f> b,u6 00111bbb01101111FBBBuuuuuu100000. */ -+{ "fmp_sqrtf", 0x386F0020, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sqrtf<.f> 0,u6 0011111001101111F111uuuuuu100000. */ -+{ "fmp_sqrtf", 0x3E6F7020, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sqrtf<.f> b,limm 00111bbb00101111FBBB111110100000. */ -+{ "fmp_sqrtf", 0x382F0FA0, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sqrtf<.f> 0,limm 0011111000101111F111111110100000. */ -+{ "fmp_sqrtf", 0x3E2F7FA0, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sqrtf15<.f> b,c 00111bbb00101111FBBBCCCCCC100001. */ -+{ "fmp_sqrtf15", 0x382F0021, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sqrtf15<.f> 0,c 0011111000101111F111CCCCCC100001. */ -+{ "fmp_sqrtf15", 0x3E2F7021, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fmp_sqrtf15<.f> b,u6 00111bbb01101111FBBBuuuuuu100001. */ -+{ "fmp_sqrtf15", 0x386F0021, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sqrtf15<.f> 0,u6 0011111001101111F111uuuuuu100001. */ -+{ "fmp_sqrtf15", 0x3E6F7021, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmp_sqrtf15<.f> b,limm 00111bbb00101111FBBB111110100001. */ -+{ "fmp_sqrtf15", 0x382F0FA1, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmp_sqrtf15<.f> 0,limm 0011111000101111F111111110100001. */ -+{ "fmp_sqrtf15", 0x3E2F7FA1, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, FASTMATH, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* getacc b,c 00101bbb001011110BBBCCCCCC011000. */ -+{ "getacc", 0x282F0018, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* getacc 0,c 00101110001011110111CCCCCC011000. */ -+{ "getacc", 0x2E2F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* getacc b,u6 00101bbb011011110BBBuuuuuu011000. */ -+{ "getacc", 0x286F0018, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* getacc 0,u6 00101110011011110111uuuuuu011000. */ -+{ "getacc", 0x2E6F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* getacc b,limm 00101bbb001011110BBB111110011000. */ -+{ "getacc", 0x282F0F98, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* getacc 0,limm 00101110001011110111111110011000. */ -+{ "getacc", 0x2E2F7F98, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* j c 00100RRR00100000RRRRCCCCCCRRRRRR. */ -+{ "j", 0x20200000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j OPERAND_BLINK 00100RRR00100000RRRR011111RRRRRR. */ -+{ "j", 0x202007C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* jcc c 00100RRR11100000RRRRCCCCCC0QQQQQ. */ -+{ "j", 0x20E00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, COND, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* jcc OPERAND_BLINK 00100RRR11100000RRRR0111110QQQQQ. */ -+{ "j", 0x20E007C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* j.D c 00100RRR00100001RRRRCCCCCCRRRRRR. */ -+{ "j", 0x20210000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* j.D OPERAND_BLINK 00100RRR00100001RRRR011111RRRRRR. */ -+{ "j", 0x202107C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* j.Dcc c 00100RRR11100001RRRRCCCCCC0QQQQQ. */ -+{ "j", 0x20E10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, COND, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, -+ -+/* j.Dcc OPERAND_BLINK 00100RRR11100001RRRR0111110QQQQQ. */ -+{ "j", 0x20E107C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, -+ -+/* j s12 00100RRR10100000RRRRssssssSSSSSS. */ -+{ "j", 0x20A00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* j.D s12 00100RRR10100001RRRRssssssSSSSSS. */ -+{ "j", 0x20A10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, -+ -+/* j u6 00100RRR01100000RRRRuuuuuuRRRRRR. */ -+{ "j", 0x20600000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* jcc u6 00100RRR11100000RRRRuuuuuu1QQQQQ. */ -+{ "j", 0x20E00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, COND, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* j.D u6 00100RRR01100001RRRRuuuuuuRRRRRR. */ -+{ "j", 0x20610000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, -+ -+/* j.Dcc u6 00100RRR11100001RRRRuuuuuu1QQQQQ. */ -+{ "j", 0x20E10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, COND, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, -+ -+/* j limm 00100RRR00100000RRRR111110RRRRRR. */ -+{ "j", 0x20200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* jcc limm 00100RRR11100000RRRR1111100QQQQQ. */ -+{ "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, COND, { OPERAND_LIMM }, { C_CC }}, -+ -+/* jeq_sCC_EQ OPERAND_BLINK 0111110011100000. */ -+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_EQ }}, -+ -+/* jl c 00100RRR00100010RRRRCCCCCCRRRRRR. */ -+{ "jl", 0x20220000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* jlcc c 00100RRR11100010RRRRCCCCCC0QQQQQ. */ -+{ "jl", 0x20E20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* jl.D c 00100RRR00100011RRRRCCCCCCRRRRRR. */ -+{ "jl", 0x20230000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* jl.Dcc c 00100RRR11100011RRRRCCCCCC0QQQQQ. */ -+{ "jl", 0x20E30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, -+ -+/* jl s12 00100RRR10100010RRRRssssssSSSSSS. */ -+{ "jl", 0x20A20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* jl.D s12 00100RRR10100011RRRRssssssSSSSSS. */ -+{ "jl", 0x20A30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, -+ -+/* jl u6 00100RRR01100010RRRRuuuuuuRRRRRR. */ -+{ "jl", 0x20620000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* jlcc u6 00100RRR11100010RRRRuuuuuu1QQQQQ. */ -+{ "jl", 0x20E20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* jl.D u6 00100RRR01100011RRRRuuuuuuRRRRRR. */ -+{ "jl", 0x20630000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, -+ -+/* jl.Dcc u6 00100RRR11100011RRRRuuuuuu1QQQQQ. */ -+{ "jl", 0x20E30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, -+ -+/* jl limm 00100RRR00100010RRRR111110RRRRRR. */ -+{ "jl", 0x20220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* jlcc limm 00100RRR11100010RRRR1111100QQQQQ. */ -+{ "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_LIMM }, { C_CC }}, -+ -+/* jli_s u10 01010UUUUUUU1uuu. */ -+{ "jli_s", 0x00005008, 0x0000F808, ARC_OPCODE_V3_ARC64, JLI, NONE, { OPERAND_UIMM10_13_S }, { 0 }}, -+ -+/* jl_s b 01111bbb01000000. */ -+{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* jl_s.D b 01111bbb01100000. */ -+{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* jne_sCC_NE OPERAND_BLINK 0111110111100000. */ -+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_NE }}, -+ -+/* j_s b 01111bbb00000000. */ -+{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j_s.D b 01111bbb00100000. */ -+{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* j_s OPERAND_BLINK 0111111011100000. */ -+{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j_s.D OPERAND_BLINK 0111111111100000. */ -+{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* kflag c 00100RRR001010011RRRCCCCCCRRRRRR. */ -+{ "kflag", 0x20298000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* kflag<.cc> c 00100RRR111010011RRRCCCCCC0QQQQQ. */ -+{ "kflag", 0x20E98000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_RC }, { C_CC }}, -+ -+/* kflag u6 00100RRR011010011RRRuuuuuuRRRRRR. */ -+{ "kflag", 0x20698000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* kflag<.cc> u6 00100RRR111010011RRRuuuuuu1QQQQQ. */ -+{ "kflag", 0x20E98020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* kflag s12 00100RRR101010011RRRssssssSSSSSS. */ -+{ "kflag", 0x20A98000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* kflag limm 00100RRR001010011RRR111110RRRRRR. */ -+{ "kflag", 0x20298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* kflag<.cc> limm 00100RRR111010011RRR1111100QQQQQ. */ -+{ "kflag", 0x20E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_LIMM }, { C_CC }}, -+ -+/* ldZZ_W<.di><.aa> a,b 00010bbb000000000BBBDaa000AAAAAA. */ -+{ "ld", 0x10000000, 0xF8FF81C0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }}, -+ -+/* ldZZ_W<.di><.aa> a,b,c 00100bbbaa110000DBBBCCCCCCAAAAAA. */ -+{ "ld", 0x20300000, 0xF83F0000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }}, -+ -+/* ldZZ_W<.di><.aa> 0,b,c 00100bbbaa110000DBBBCCCCCC111110. */ -+{ "ld", 0x2030003E, 0xF83F003F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }}, -+ -+/* ldZZ_W<.x><.aa> a,b 00010bbb000000000BBB0aa00XAAAAAA. */ -+{ "ld", 0x10000000, 0xF8FF8980, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }}, -+ -+/* ldZZ_W<.x><.aa> a,b,c 00100bbbaa11000X0BBBCCCCCCAAAAAA. */ -+{ "ld", 0x20300000, 0xF83E8000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }}, -+ -+/* ldZZ_W<.x><.aa> 0,b,c 00100bbbaa11000X0BBBCCCCCC111110. */ -+{ "ld", 0x2030003E, 0xF83E803F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }}, -+ -+/* ldZZ_W<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa000AAAAAA. */ -+{ "ld", 0x10000000, 0xF80001C0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }}, -+ -+/* ldZZ_W<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa000111110. */ -+{ "ld", 0x1000003E, 0xF80001FF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }}, -+ -+/* ldZZ_W<.x><.aa> a,b,s9 00010bbbssssssssSBBB0aa00XAAAAAA. */ -+{ "ld", 0x10000000, 0xF8000980, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }}, -+ -+/* ldZZ_W<.x><.aa> 0,b,s9 00010bbbssssssssSBBB0aa00X111110. */ -+{ "ld", 0x1000003E, 0xF80009BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }}, -+ -+/* ldZZ_W<.di> a,limm 00010110000000000111D00000AAAAAA. */ -+{ "ld", 0x16007000, 0xFFFFF7C0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI20 }}, -+ -+/* ldZZ_W<.di> 0,limm 00010110000000000111D00000111110. */ -+{ "ld", 0x1600703E, 0xFFFFF7FF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI20 }}, -+ -+/* ldZZ_W<.di><.aa> a,b,limm 00100bbbaa110000DBBB111110AAAAAA. */ -+{ "ld", 0x20300F80, 0xF83F0FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }}, -+ -+/* ldZZ_W<.di><.aa> a,limm,c 00100110aa110000D111CCCCCCAAAAAA. */ -+{ "ld", 0x26307000, 0xFF3F7000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }}, -+ -+/* ldZZ_W<.di><.aa> 0,b,limm 00100bbbaa110000DBBB111110111110. */ -+{ "ld", 0x20300FBE, 0xF83F0FFF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }}, -+ -+/* ldZZ_W<.di><.aa> 0,limm,c 00100110aa110000D111CCCCCC111110. */ -+{ "ld", 0x2630703E, 0xFF3F703F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }}, -+ -+/* ldZZ_W<.x> a,limm 0001011000000000011100000XAAAAAA. */ -+{ "ld", 0x16007000, 0xFFFFFF80, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_W, C_X25 }}, -+ -+/* ldZZ_W<.x> 0,limm 0001011000000000011100000X111110. */ -+{ "ld", 0x1600703E, 0xFFFFFFBF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_W, C_X25 }}, -+ -+/* ldZZ_W<.x><.aa> a,b,limm 00100bbbaa11000X0BBB111110AAAAAA. */ -+{ "ld", 0x20300F80, 0xF83E8FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }}, -+ -+/* ldZZ_W<.x><.aa> a,b,ximm 00100bbbaa11000X0BBB111100AAAAAA. */ -+{ "ld", 0x20300F00, 0xF83E8FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_XIMM, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }}, -+ -+/* ldZZ_W<.x><.aa> a,limm,c 00100110aa11000X0111CCCCCCAAAAAA. */ -+{ "ld", 0x26307000, 0xFF3EF000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }}, -+ -+/* ldZZ_W<.x><.aa> 0,b,limm 00100bbbaa11000X0BBB111110111110. */ -+{ "ld", 0x20300FBE, 0xF83E8FFF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }}, -+ -+/* ldZZ_W<.di><.aa> a,limm,s9 00010110ssssssssS111Daa000AAAAAA. */ -+{ "ld", 0x16007000, 0xFF0071C0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }}, -+ -+/* ldZZ_W<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa000111110. */ -+{ "ld", 0x1600703E, 0xFF0071FF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }}, -+ -+/* ldZZ_W<.x><.aa> a,limm,s9 00010110ssssssssS1110aa00XAAAAAA. */ -+{ "ld", 0x16007000, 0xFF007980, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }}, -+ -+/* ldZZ_W<.x><.aa> 0,limm,s9 00010110ssssssssS1110aa00X111110. */ -+{ "ld", 0x1600703E, 0xFF0079BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }}, -+ -+/* ld ZZ_W<.x><.aa> 0,limm,c 00100110aa11000X0111CCCCCC111110. */ -+{ "ld ", 0x2630703E, 0xFF3EF03F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_ZZ_W, C_AA8, C_X15 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> a,b 00010bbb000000000BBBDaa01XAAAAAA. */ -+{ "ldb", 0x10000080, 0xF8FF8180, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> a,b,c 00100bbbaa11001XDBBBCCCCCCAAAAAA. */ -+{ "ldb", 0x20320000, 0xF83E0000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> 0,b,c 00100bbbaa11001XDBBBCCCCCC111110. */ -+{ "ldb", 0x2032003E, 0xF83E003F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa01XAAAAAA. */ -+{ "ldb", 0x10000080, 0xF8000180, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa01X111110. */ -+{ "ldb", 0x100000BE, 0xF80001BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldbZZ_B<.x><.di> a,limm 00010110000000000111D0001XAAAAAA. */ -+{ "ldb", 0x16007080, 0xFFFFF780, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 }}, -+ -+/* ldbZZ_B<.x><.di> 0,limm 00010110000000000111D0001X111110. */ -+{ "ldb", 0x160070BE, 0xFFFFF7BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> a,b,limm 00100bbbaa11001XDBBB111110AAAAAA. */ -+{ "ldb", 0x20320F80, 0xF83E0FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> a,b,ximm 00100bbbaa11001XDBBB111100AAAAAA. */ -+{ "ldb", 0x20320F00, 0xF83E0FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_XIMM, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> a,limm,c 00100110aa11001XD111CCCCCCAAAAAA. */ -+{ "ldb", 0x26327000, 0xFF3E7000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> 0,b,limm 00100bbbaa11001XDBBB111110111110. */ -+{ "ldb", 0x20320FBE, 0xF83E0FFF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> 0,limm,c 00100110aa11001XD111CCCCCC111110. */ -+{ "ldb", 0x2632703E, 0xFF3E703F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> a,limm,s9 00010110ssssssssS111Daa01XAAAAAA. */ -+{ "ldb", 0x16007080, 0xFF007180, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldbZZ_B<.x><.di><.aa> 0,limm,s9 00010110ssssssssS111Daa01X111110. */ -+{ "ldb", 0x160070BE, 0xFF0071BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_B, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,b 00010bbb000000000BBBDaa10XAAAAAA. */ -+{ "ldh", 0x10000100, 0xF8FF8180, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,b,c 00100bbbaa11010XDBBBCCCCCCAAAAAA. */ -+{ "ldh", 0x20340000, 0xF83E0000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,b,c 00100bbbaa11010XDBBBCCCCCC111110. */ -+{ "ldh", 0x2034003E, 0xF83E003F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa10XAAAAAA. */ -+{ "ldh", 0x10000100, 0xF8000180, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa10X111110. */ -+{ "ldh", 0x1000013E, 0xF80001BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di> a,limm 00010110000000000111D0010XAAAAAA. */ -+{ "ldh", 0x16007100, 0xFFFFF780, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di> 0,limm 00010110000000000111D0010X111110. */ -+{ "ldh", 0x1600713E, 0xFFFFF7BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,b,limm 00100bbbaa11010XDBBB111110AAAAAA. */ -+{ "ldh", 0x20340F80, 0xF83E0FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,b,ximm 00100bbbaa11010XDBBB111100AAAAAA. */ -+{ "ldh", 0x20340F00, 0xF83E0FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_XIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,limm,c 00100110aa11010XD111CCCCCCAAAAAA. */ -+{ "ldh", 0x26347000, 0xFF3E7000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,b,limm 00100bbbaa11010XDBBB111110111110. */ -+{ "ldh", 0x20340FBE, 0xF83E0FFF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,limm,c 00100110aa11010XD111CCCCCC111110. */ -+{ "ldh", 0x2634703E, 0xFF3E703F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,limm,s9 00010110ssssssssS111Daa10XAAAAAA. */ -+{ "ldh", 0x16007100, 0xFF007180, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,limm,s9 00010110ssssssssS111Daa10X111110. */ -+{ "ldh", 0x1600713E, 0xFF0071BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+ -+/* ldhZZ_H<.x><.di><.aa> a,b 00010bbb000000000BBBDaa10XAAAAAA. */ -+{ "ldw", 0x10000100, 0xF8FF8180, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,b,c 00100bbbaa11010XDBBBCCCCCCAAAAAA. */ -+{ "ldw", 0x20340000, 0xF83E0000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,b,c 00100bbbaa11010XDBBBCCCCCC111110. */ -+{ "ldw", 0x2034003E, 0xF83E003F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa10XAAAAAA. */ -+{ "ldw", 0x10000100, 0xF8000180, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa10X111110. */ -+{ "ldw", 0x1000013E, 0xF80001BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di> a,limm 00010110000000000111D0010XAAAAAA. */ -+{ "ldw", 0x16007100, 0xFFFFF780, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di> 0,limm 00010110000000000111D0010X111110. */ -+{ "ldw", 0x1600713E, 0xFFFFF7BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,b,limm 00100bbbaa11010XDBBB111110AAAAAA. */ -+{ "ldw", 0x20340F80, 0xF83E0FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,b,ximm 00100bbbaa11010XDBBB111100AAAAAA. */ -+{ "ldw", 0x20340F00, 0xF83E0FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_XIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,limm,c 00100110aa11010XD111CCCCCCAAAAAA. */ -+{ "ldw", 0x26347000, 0xFF3E7000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,b,limm 00100bbbaa11010XDBBB111110111110. */ -+{ "ldw", 0x20340FBE, 0xF83E0FFF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,limm,c 00100110aa11010XD111CCCCCC111110. */ -+{ "ldw", 0x2634703E, 0xFF3E703F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> a,limm,s9 00010110ssssssssS111Daa10XAAAAAA. */ -+{ "ldw", 0x16007100, 0xFF007180, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+/* ldhZZ_H<.x><.di><.aa> 0,limm,s9 00010110ssssssssS111Daa10X111110. */ -+{ "ldw", 0x1600713E, 0xFF0071BF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }}, -+ -+ -+ -+/* ldlZZ_L<.aa> a,b 00010bbb000000000BBB1aa001AAAAAA. */ -+{ "ldl", 0x10000840, 0xF8FF89C0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA21 }}, -+ -+/* ldlZZ_L<.aa> 0,b 00010bbb000000000BBB1aa001111110. */ -+{ "ldl", 0x1000087E, 0xF8FF89FF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA21 }}, -+ -+/* ldlZZ_L<.aa> a,b,c 00100bbbaa1100011BBBCCCCCCAAAAAA. */ -+{ "ldl", 0x20318000, 0xF83F8000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA8 }}, -+ -+/* ldlZZ_L<.aa> 0,b,c 00100bbbaa1100011BBBCCCCCC111110. */ -+{ "ldl", 0x2031803E, 0xF83F803F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA8 }}, -+ -+/* ldlZZ_L<.aa> a,b,s9 00010bbbssssssssSBBB1aa001AAAAAA. */ -+{ "ldl", 0x10000840, 0xF80009C0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA21 }}, -+ -+/* ldlZZ_L<.aa> 0,b,s9 00010bbbssssssssSBBB1aa001111110. */ -+{ "ldl", 0x1000087E, 0xF80009FF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA21 }}, -+ -+/* ldlZZ_L 0,limm 00010110000000000111100001111110. */ -+{ "ldl", 0x1600787E, 0xFFFFFFFF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_L }}, -+ -+/* ldlZZ_L a,limm 00010110000000000111100001AAAAAA. */ -+{ "ldl", 0x16007840, 0xFFFFFFC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_L }}, -+ -+/* ldlZZ_L<.aa> a,b,limm 00100bbbaa1100011BBB111110AAAAAA. */ -+{ "ldl", 0x20318F80, 0xF83F8FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA8 }}, -+ -+/* ldlZZ_L<.aa> a,b,ximm 00100bbbaa1100011BBB111100AAAAAA. */ -+{ "ldl", 0x20318F00, 0xF83F8FC0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_XIMM, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA8 }}, -+ -+/* ldlZZ_L<.aa> 0,b,limm 00100bbbaa1100011BBB111110111110. */ -+{ "ldl", 0x20318FBE, 0xF83F8FFF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA8 }}, -+ -+/* ldlZZ_L 0,limm,c 00100110001100011111CCCCCC111110. */ -+{ "ldl", 0x2631F03E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_L }}, -+ -+/* ldlZZ_L a,limm,c 00100110aa1100011111CCCCCCAAAAAA. */ -+{ "ldl", 0x2631F000, 0xFF3FF000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LO32, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA8 }}, -+ -+/* ldlZZ_L<.aa> a,ximm,c 00100100aa1100011111CCCCCCAAAAAA. */ -+{ "ldl", 0x2431F000, 0xFF3FF000, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_XIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ_L , C_AA8 }}, -+ -+/* ldlZZ_L<.aa> a,limm,s9 00010110ssssssssS1111aa001AAAAAA. */ -+{ "ldl", 0x16007840, 0xFF0079C0, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LO32, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA21 }}, -+ -+/* ldlZZ_L<.aa> 0,limm,s9 00010110ssssssssS1111aa001111110. */ -+{ "ldl", 0x1600787E, 0xFF0079FF, ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA21 }}, -+ -+/* ldb_sZZ_B a,b,c 01100bbbccc01aaa. */ -+{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* ldb_sZZ_B c,b,u5 10001bbbcccuuuuu. */ -+{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* ldb_sZZ_B b,SP,u7 11000bbb001uuuuu. */ -+{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* ldb_sZZ_B R0,GP,s9 1100101sssssssss. */ -+{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM9_7_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* ldh_sZZ_H a,b,c 01100bbbccc10aaa. */ -+{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* ldh_sZZ_H c,b,u6 10010bbbcccuuuuu. */ -+{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* ldh_sZZ_H.X c,b,u6 10011bbbcccuuuuu. */ -+{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H, C_XHARD }}, -+ -+/* ldh_sZZ_H R0,GP,s10 1100110sssssssss. */ -+{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM10_A16_7_Sbis, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* ld_s a,b,c 01100bbbccc00aaa. */ -+{ "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s.AS a,b,c 01001bbbccc00aaa. */ -+{ "ld_s", 0x00004800, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, CD2, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_AS }}, -+ -+/* ld_s b,SP,u7 11000bbb000uuuuu. */ -+{ "ld_s", 0x0000C000, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s c,b,u7 10000bbbcccuuuuu. */ -+{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s b,PCL,u10 11010bbbuuuuuuuu. */ -+{ "ld_s", 0x0000D000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_PCL_S, OPERAND_UIMM10_A32_8_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s R0,GP,s11 1100100sssssssss. */ -+{ "ld_s", 0x0000C800, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s R1,GP,s11 01010SSSSSS00sss. */ -+{ "ld_s", 0x00005000, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOAD, CD2, { OPERAND_R1_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_13_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* leave_s u7 11000UUU110uuuu0. */ -+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { OPERAND_BRAKET, OPERAND_RRANGE_EL, OPERAND_FP_EL, OPERAND_BLINK_EL, OPERAND_PCL_EL, OPERAND_BRAKETdup }, { 0 }}, -+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { OPERAND_BRAKET, OPERAND_R13_EL, OPERAND_FP_EL, OPERAND_BLINK_EL, OPERAND_PCL_EL, OPERAND_BRAKETdup }, { 0 }}, -+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LEAVE, CD1, { OPERAND_UIMM7_11_S }, { 0 }}, -+ -+/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */ -+{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> 0,c 0010011000101111D111CCCCCC010000. */ -+{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000. */ -+{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> 0,u6 0010011001101111D111uuuuuu010000. */ -+{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> b,limm 00100bbb00101111DBBB111110010000. */ -+{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> 0,limm 0010011000101111D111111110010000. */ -+{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llockl<.aq> OPERAND_RB,RC 01011bbb00101111FBBBcccccc010000. */ -+{ "llockl", 0x582F0010, 0xF8FF003F, ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_AQ }}, -+ -+/* lr b,c 00100bbb00101010RBBBCCCCCCRRRRRR. */ -+{ "lr", 0x202A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,c 0010011000101010R111CCCCCCRRRRRR. */ -+{ "lr", 0x262A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,u6 00100bbb01101010RBBBuuuuuu000000. */ -+{ "lr", 0x206A0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,u6 0010011001101010R111uuuuuu000000. */ -+{ "lr", 0x266A7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,s12 00100bbb10101010RBBBssssssSSSSSS. */ -+{ "lr", 0x20AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,s12 0010011010101010R111ssssssSSSSSS. */ -+{ "lr", 0x26AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,limm 00100bbb00101010RBBB111110RRRRRR. */ -+{ "lr", 0x202A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,limm 0010011000101010R111111110RRRRRR. */ -+{ "lr", 0x262A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lrl OPERAND_RB,RC 01011bbb001010100BBBccccccRRRRRR. */ -+{ "lrl", 0x582A0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lrl OPERAND_RB,u6 01011bbb011010100BBBuuuuuuRRRRRR. */ -+{ "lrl", 0x586A0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lrl OPERAND_RB,s12 01011bbb101010100BBBssssssSSSSSS. */ -+{ "lrl", 0x58AA0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lrl OPERAND_RB,ximm 01011bbb001010100BBB111100RRRRRR. */ -+{ "lrl", 0x582A0F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_XIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lrl OPERAND_RB,limm 01011bbb001010100BBB111110RRRRRR. */ -+{ "lrl", 0x582A0F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lsl16<.f> b,c 00101bbb00101111FBBBCCCCCC001010. */ -+{ "lsl16", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsl16<.f> 0,c 0010111000101111F111CCCCCC001010. */ -+{ "lsl16", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsl16<.f> b,u6 00101bbb01101111FBBBuuuuuu001010. */ -+{ "lsl16", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsl16<.f> 0,u6 0010111001101111F111uuuuuu001010. */ -+{ "lsl16", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsl16<.f> b,limm 00101bbb00101111FBBB111110001010. */ -+{ "lsl16", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsl16<.f> 0,limm 0010111000101111F111111110001010. */ -+{ "lsl16", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsl8<.f> b,c 00101bbb00101111FBBBCCCCCC001111. */ -+{ "lsl8", 0x282F000F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsl8<.f> 0,c 0010111000101111F111CCCCCC001111. */ -+{ "lsl8", 0x2E2F700F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsl8<.f> b,u6 00101bbb01101111FBBBuuuuuu001111. */ -+{ "lsl8", 0x286F000F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsl8<.f> 0,u6 0010111001101111F111uuuuuu001111. */ -+{ "lsl8", 0x2E6F700F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsl8<.f> b,limm 00101bbb00101111FBBB111110001111. */ -+{ "lsl8", 0x282F0F8F, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsl8<.f> 0,limm 0010111000101111F111111110001111. */ -+{ "lsl8", 0x2E2F7F8F, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f> b,c 00100bbb00101111FBBBCCCCCC000010. */ -+{ "lsr", 0x202F0002, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> 0,c 0010011000101111F111CCCCCC000010. */ -+{ "lsr", 0x262F7002, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> a,b,c 00101bbb00000001FBBBCCCCCCAAAAAA. */ -+{ "lsr", 0x28010000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> 0,b,c 00101bbb00000001FBBBCCCCCC111110. */ -+{ "lsr", 0x2801003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f><.cc> b,b,c 00101bbb11000001FBBBCCCCCC0QQQQQ. */ -+{ "lsr", 0x28C10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* lsr<.f> b,u6 00100bbb01101111FBBBuuuuuu000010. */ -+{ "lsr", 0x206F0002, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f> 0,u6 0010011001101111F111uuuuuu000010. */ -+{ "lsr", 0x266F7002, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f> a,b,u6 00101bbb01000001FBBBuuuuuuAAAAAA. */ -+{ "lsr", 0x28410000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f> 0,b,u6 00101bbb01000001FBBBuuuuuu111110. */ -+{ "lsr", 0x2841003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f><.cc> b,b,u6 00101bbb11000001FBBBuuuuuu1QQQQQ. */ -+{ "lsr", 0x28C10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* lsr<.f> b,b,s12 00101bbb10000001FBBBssssssSSSSSS. */ -+{ "lsr", 0x28810000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* lsr<.f> b,limm 00100bbb00101111FBBB111110000010. */ -+{ "lsr", 0x202F0F82, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f> 0,limm 0010011000101111F111111110000010. */ -+{ "lsr", 0x262F7F82, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f> a,limm,c 0010111000000001F111CCCCCCAAAAAA. */ -+{ "lsr", 0x2E017000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> a,b,limm 00101bbb00000001FBBB111110AAAAAA. */ -+{ "lsr", 0x28010F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f> 0,limm,c 0010111000000001F111CCCCCC111110. */ -+{ "lsr", 0x2E01703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> 0,b,limm 00101bbb00000001FBBB111110111110. */ -+{ "lsr", 0x28010FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f><.cc> b,b,limm 00101bbb11000001FBBB1111100QQQQQ. */ -+{ "lsr", 0x28C10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* lsr<.f><.cc> 0,limm,c 0010111011000001F111CCCCCC0QQQQQ. */ -+{ "lsr", 0x2EC17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* lsr<.f> a,limm,u6 0010111001000001F111uuuuuuAAAAAA. */ -+{ "lsr", 0x2E417000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f> 0,limm,u6 0010111001000001F111uuuuuu111110. */ -+{ "lsr", 0x2E41703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f><.cc> 0,limm,u6 0010111011000001F111uuuuuu1QQQQQ. */ -+{ "lsr", 0x2EC17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* lsr<.f> 0,limm,s12 0010111010000001F111ssssssSSSSSS. */ -+{ "lsr", 0x2E817000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* lsr<.f> a,limm,limm 0010111000000001F111111110AAAAAA. */ -+{ "lsr", 0x2E017F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* lsr<.f> 0,limm,limm 0010111000000001F111111110111110. */ -+{ "lsr", 0x2E017FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* lsr<.f><.cc> 0,limm,limm 0010111011000001F1111111100QQQQQ. */ -+{ "lsr", 0x2EC17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* lsr16<.f> b,c 00101bbb00101111FBBBCCCCCC001011. */ -+{ "lsr16", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr16<.f> 0,c 0010111000101111F111CCCCCC001011. */ -+{ "lsr16", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001011. */ -+{ "lsr16", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr16<.f> 0,u6 0010111001101111F111uuuuuu001011. */ -+{ "lsr16", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr16<.f> b,limm 00101bbb00101111FBBB111110001011. */ -+{ "lsr16", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr16<.f> 0,limm 0010111000101111F111111110001011. */ -+{ "lsr16", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr8<.f> b,c 00101bbb00101111FBBBCCCCCC001110. */ -+{ "lsr8", 0x282F000E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr8<.f> 0,c 0010111000101111F111CCCCCC001110. */ -+{ "lsr8", 0x2E2F700E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001110. */ -+{ "lsr8", 0x286F000E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr8<.f> 0,u6 0010111001101111F111uuuuuu001110. */ -+{ "lsr8", 0x2E6F700E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr8<.f> b,limm 00101bbb00101111FBBB111110001110. */ -+{ "lsr8", 0x282F0F8E, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr8<.f> 0,limm 0010111000101111F111111110001110. */ -+{ "lsr8", 0x2E2F7F8E, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsrl<.f> OPERAND_RA,RB,RC 01011bbb00100001FBBBccccccaaaaaa. */ -+{ "lsrl", 0x58210000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsrl<.f> 0,RB,RC 01011bbb00100001FBBBcccccc111110. */ -+{ "lsrl", 0x5821003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsrl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11100001FBBBcccccc0QQQQQ. */ -+{ "lsrl", 0x58E10000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* lsrl<.f> OPERAND_RA,RB,u6 01011bbb01100001FBBBuuuuuuaaaaaa. */ -+{ "lsrl", 0x58610000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrl<.f> 0,RB,u6 01011bbb01100001FBBBuuuuuu111110. */ -+{ "lsrl", 0x5861003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11100001FBBBuuuuuu1QQQQQ. */ -+{ "lsrl", 0x58E10020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* lsrl<.f> OPERAND_RB,RB,s12 01011bbb10100001FBBBssssssSSSSSS. */ -+{ "lsrl", 0x58A10000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* lsrl<.f> OPERAND_RA,ximm,RC 0101110000100001F111ccccccaaaaaa. */ -+{ "lsrl", 0x5C217000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsrl<.f> OPERAND_RA,RB,ximm 01011bbb00100001FBBB111100aaaaaa. */ -+{ "lsrl", 0x58210F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* lsrl<.f> 0,ximm,RC 0101110000100001F111cccccc111110. */ -+{ "lsrl", 0x5C21703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsrl<.f> 0,RB,ximm 01011bbb00100001FBBB111100111110. */ -+{ "lsrl", 0x58210F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* lsrl<.f><.cc> 0,ximm,RC 0101110011100001F111cccccc0QQQQQ. */ -+{ "lsrl", 0x5CE17000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* lsrl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11100001FBBB1111000QQQQQ. */ -+{ "lsrl", 0x58E10F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* lsrl<.f> OPERAND_RA,ximm,u6 0101110001100001F111uuuuuuaaaaaa. */ -+{ "lsrl", 0x5C617000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrl<.f> 0,ximm,u6 0101110001100001F111uuuuuu111110. */ -+{ "lsrl", 0x5C61703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrl<.f><.cc> 0,ximm,u6 0101110011100001F111uuuuuu1QQQQQ. */ -+{ "lsrl", 0x5CE17020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* lsrl<.f> OPERAND_RA,limm,RC 0101111000100001F111ccccccaaaaaa. */ -+{ "lsrl", 0x5E217000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsrl<.f> OPERAND_RA,RB,limm 01011bbb00100001FBBB111110aaaaaa. */ -+{ "lsrl", 0x58210F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsrl<.f> 0,limm,RC 0101111000100001F111cccccc111110. */ -+{ "lsrl", 0x5E21703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsrl<.f> 0,RB,limm 01011bbb00100001FBBB111110111110. */ -+{ "lsrl", 0x58210FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsrl<.f><.cc> 0,limm,RC 0101111011100001F111cccccc0QQQQQ. */ -+{ "lsrl", 0x5EE17000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* lsrl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11100001FBBB1111100QQQQQ. */ -+{ "lsrl", 0x58E10F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* lsrl<.f> OPERAND_RA,limm,u6 0101111001100001F111uuuuuuaaaaaa. */ -+{ "lsrl", 0x5E617000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrl<.f> 0,limm,u6 0101111001100001F111uuuuuu111110. */ -+{ "lsrl", 0x5E61703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrl<.f><.cc> 0,limm,u6 0101111011100001F111uuuuuu1QQQQQ. */ -+{ "lsrl", 0x5EE17020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* lsrl<.f> 0,ximm,s12 0101110010100001F111ssssssSSSSSS. */ -+{ "lsrl", 0x5CA17000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* lsrl<.f> 0,limm,s12 0101111010100001F111ssssssSSSSSS. */ -+{ "lsrl", 0x5EA17000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* lsrl<.f> OPERAND_RA,ximm,ximm 0101110000100001F111111100aaaaaa. */ -+{ "lsrl", 0x5C217F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* lsrl<.f> 0,ximm,ximm 0101110000100001F111111100111110. */ -+{ "lsrl", 0x5C217F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* lsrl<.f><.cc> 0,ximm,ximm 0101110011100001F1111111000QQQQQ. */ -+{ "lsrl", 0x5CE17F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* lsrl<.f> OPERAND_RA,limm,limm 0101111000100001F111111110aaaaaa. */ -+{ "lsrl", 0x5E217F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* lsrl<.f> 0,limm,limm 0101111000100001F111111110111110. */ -+{ "lsrl", 0x5E217FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* lsrl<.f><.cc> 0,limm,limm 0101111011100001F1111111100QQQQQ. */ -+{ "lsrl", 0x5EE17F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* lsr_s b,c 01111bbbccc11101. */ -+{ "lsr_s", 0x0000781D, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* lsr_s b,b,c 01111bbbccc11001. */ -+{ "lsr_s", 0x00007819, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* lsr_s b,b,u5 10111bbb001uuuuu. */ -+{ "lsr_s", 0x0000B820, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* lstl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc000010. */ -+{ "lstl", 0x582F0002, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lstl<.f> 0,RC 0101111000101111F111cccccc000010. */ -+{ "lstl", 0x5E2F7002, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lstl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu000010. */ -+{ "lstl", 0x586F0002, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lstl<.f> 0,u6 0101111001101111F111uuuuuu000010. */ -+{ "lstl", 0x5E6F7002, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lstl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100000010. */ -+{ "lstl", 0x582F0F02, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* lstl<.f> 0,ximm 0101111000101111F111111100000010. */ -+{ "lstl", 0x5E2F7F02, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* lstl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110000010. */ -+{ "lstl", 0x582F0F82, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lstl<.f> 0,limm 0101111000101111F111111110000010. */ -+{ "lstl", 0x5E2F7F82, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* mac<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA. */ -+{ "mac", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mac<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110. */ -+{ "mac", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mac<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ. */ -+{ "mac", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mac<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA. */ -+{ "mac", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mac<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110. */ -+{ "mac", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mac<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ. */ -+{ "mac", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mac<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS. */ -+{ "mac", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mac<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA. */ -+{ "mac", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mac<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA. */ -+{ "mac", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mac<.f> 0,limm,c 0010111000001110F111CCCCCC111110. */ -+{ "mac", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mac<.f> 0,b,limm 00101bbb00001110FBBB111110111110. */ -+{ "mac", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mac<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ. */ -+{ "mac", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mac<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ. */ -+{ "mac", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mac<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA. */ -+{ "mac", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mac<.f> 0,limm,u6 0010111001001110F111uuuuuu111110. */ -+{ "mac", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mac<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ. */ -+{ "mac", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mac<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS. */ -+{ "mac", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mac<.f> a,limm,limm 0010111000001110F111111110AAAAAA. */ -+{ "mac", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mac<.f> 0,limm,limm 0010111000001110F111111110111110. */ -+{ "mac", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mac<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ. */ -+{ "mac", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macd<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA. */ -+{ "macd", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macd<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110. */ -+{ "macd", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macd<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ. */ -+{ "macd", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macd<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA. */ -+{ "macd", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macd<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110. */ -+{ "macd", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macd<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ. */ -+{ "macd", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macd<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS. */ -+{ "macd", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macd<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA. */ -+{ "macd", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macd<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA. */ -+{ "macd", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macd<.f> 0,limm,c 0010111000011010F111CCCCCC111110. */ -+{ "macd", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macd<.f> 0,b,limm 00101bbb00011010FBBB111110111110. */ -+{ "macd", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macd<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ. */ -+{ "macd", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macd<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ. */ -+{ "macd", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macd<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA. */ -+{ "macd", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macd<.f> 0,limm,u6 0010111001011010F111uuuuuu111110. */ -+{ "macd", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macd<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ. */ -+{ "macd", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macd<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS. */ -+{ "macd", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macd<.f> a,limm,limm 0010111000011010F111111110AAAAAA. */ -+{ "macd", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macd<.f> 0,limm,limm 0010111000011010F111111110111110. */ -+{ "macd", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macd<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ. */ -+{ "macd", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macdf<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA. */ -+{ "macdf", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdf<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110. */ -+{ "macdf", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdf<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ. */ -+{ "macdf", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdf<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA. */ -+{ "macdf", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdf<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110. */ -+{ "macdf", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdf<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ. */ -+{ "macdf", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdf<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS. */ -+{ "macdf", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdf<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA. */ -+{ "macdf", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdf<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA. */ -+{ "macdf", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdf<.f> 0,limm,c 0011011000010011F111CCCCCC111110. */ -+{ "macdf", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdf<.f> 0,b,limm 00110bbb00010011FBBB111110111110. */ -+{ "macdf", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdf<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ. */ -+{ "macdf", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macdf<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ. */ -+{ "macdf", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdf<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA. */ -+{ "macdf", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdf<.f> 0,limm,u6 0011011001010011F111uuuuuu111110. */ -+{ "macdf", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdf<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ. */ -+{ "macdf", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdf<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS. */ -+{ "macdf", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdf<.f> a,limm,limm 0011011000010011F111111110AAAAAA. */ -+{ "macdf", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdf<.f> 0,limm,limm 0011011000010011F111111110111110. */ -+{ "macdf", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdf<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ. */ -+{ "macdf", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macdu<.f> a,b,c 00101bbb00011011FBBBCCCCCCAAAAAA. */ -+{ "macdu", 0x281B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdu<.f> 0,b,c 00101bbb00011011FBBBCCCCCC111110. */ -+{ "macdu", 0x281B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdu<.f><.cc> b,b,c 00101bbb11011011FBBBCCCCCC0QQQQQ. */ -+{ "macdu", 0x28DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdu<.f> a,b,u6 00101bbb01011011FBBBuuuuuuAAAAAA. */ -+{ "macdu", 0x285B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdu<.f> 0,b,u6 00101bbb01011011FBBBuuuuuu111110. */ -+{ "macdu", 0x285B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdu<.f><.cc> b,b,u6 00101bbb11011011FBBBuuuuuu1QQQQQ. */ -+{ "macdu", 0x28DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdu<.f> b,b,s12 00101bbb10011011FBBBssssssSSSSSS. */ -+{ "macdu", 0x289B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdu<.f> a,limm,c 0010111000011011F111CCCCCCAAAAAA. */ -+{ "macdu", 0x2E1B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdu<.f> a,b,limm 00101bbb00011011FBBB111110AAAAAA. */ -+{ "macdu", 0x281B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdu<.f> 0,limm,c 0010111000011011F111CCCCCC111110. */ -+{ "macdu", 0x2E1B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdu<.f> 0,b,limm 00101bbb00011011FBBB111110111110. */ -+{ "macdu", 0x281B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdu<.f><.cc> b,b,limm 00101bbb11011011FBBB1111100QQQQQ. */ -+{ "macdu", 0x28DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macdu<.f><.cc> 0,limm,c 0010111011011011F111CCCCCC0QQQQQ. */ -+{ "macdu", 0x2EDB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdu<.f> a,limm,u6 0010111001011011F111uuuuuuAAAAAA. */ -+{ "macdu", 0x2E5B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdu<.f> 0,limm,u6 0010111001011011F111uuuuuu111110. */ -+{ "macdu", 0x2E5B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdu<.f><.cc> 0,limm,u6 0010111011011011F111uuuuuu1QQQQQ. */ -+{ "macdu", 0x2EDB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdu<.f> 0,limm,s12 0010111010011011F111ssssssSSSSSS. */ -+{ "macdu", 0x2E9B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdu<.f> a,limm,limm 0010111000011011F111111110AAAAAA. */ -+{ "macdu", 0x2E1B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdu<.f> 0,limm,limm 0010111000011011F111111110111110. */ -+{ "macdu", 0x2E1B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdu<.f><.cc> 0,limm,limm 0010111011011011F1111111100QQQQQ. */ -+{ "macdu", 0x2EDB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macf<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA. */ -+{ "macf", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macf<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110. */ -+{ "macf", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macf<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ. */ -+{ "macf", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macf<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA. */ -+{ "macf", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macf<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110. */ -+{ "macf", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macf<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ. */ -+{ "macf", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macf<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS. */ -+{ "macf", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macf<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA. */ -+{ "macf", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macf<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA. */ -+{ "macf", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macf<.f> 0,limm,c 0011011000001100F111CCCCCC111110. */ -+{ "macf", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macf<.f> 0,b,limm 00110bbb00001100FBBB111110111110. */ -+{ "macf", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macf<.f><.cc> b,b,limm 00110bbb11001100FBBB1111100QQQQQ. */ -+{ "macf", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macf<.f><.cc> 0,limm,c 0011011011001100F111CCCCCC0QQQQQ. */ -+{ "macf", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macf<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA. */ -+{ "macf", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macf<.f> 0,limm,u6 0011011001001100F111uuuuuu111110. */ -+{ "macf", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macf<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ. */ -+{ "macf", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macf<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS. */ -+{ "macf", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macf<.f> a,limm,limm 0011011000001100F111111110AAAAAA. */ -+{ "macf", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macf<.f> 0,limm,limm 0011011000001100F111111110111110. */ -+{ "macf", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macf<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ. */ -+{ "macf", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macfr<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA. */ -+{ "macfr", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macfr<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110. */ -+{ "macfr", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macfr<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ. */ -+{ "macfr", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macfr<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA. */ -+{ "macfr", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macfr<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110. */ -+{ "macfr", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macfr<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ. */ -+{ "macfr", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macfr<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS. */ -+{ "macfr", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macfr<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA. */ -+{ "macfr", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macfr<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA. */ -+{ "macfr", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macfr<.f> 0,limm,c 0011011000001101F111CCCCCC111110. */ -+{ "macfr", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macfr<.f> 0,b,limm 00110bbb00001101FBBB111110111110. */ -+{ "macfr", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macfr<.f><.cc> b,b,limm 00110bbb11001101FBBB1111100QQQQQ. */ -+{ "macfr", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macfr<.f><.cc> 0,limm,c 0011011011001101F111CCCCCC0QQQQQ. */ -+{ "macfr", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macfr<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA. */ -+{ "macfr", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macfr<.f> 0,limm,u6 0011011001001101F111uuuuuu111110. */ -+{ "macfr", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macfr<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ. */ -+{ "macfr", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macfr<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS. */ -+{ "macfr", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macfr<.f> a,limm,limm 0011011000001101F111111110AAAAAA. */ -+{ "macfr", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macfr<.f> 0,limm,limm 0011011000001101F111111110111110. */ -+{ "macfr", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macfr<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ. */ -+{ "macfr", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macu<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA. */ -+{ "macu", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macu<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110. */ -+{ "macu", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macu<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ. */ -+{ "macu", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macu<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA. */ -+{ "macu", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macu<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110. */ -+{ "macu", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macu<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ. */ -+{ "macu", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macu<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS. */ -+{ "macu", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macu<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA. */ -+{ "macu", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macu<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA. */ -+{ "macu", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macu<.f> 0,limm,c 0010111000001111F111CCCCCC111110. */ -+{ "macu", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macu<.f> 0,b,limm 00101bbb00001111FBBB111110111110. */ -+{ "macu", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macu<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ. */ -+{ "macu", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macu<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ. */ -+{ "macu", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macu<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA. */ -+{ "macu", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macu<.f> 0,limm,u6 0010111001001111F111uuuuuu111110. */ -+{ "macu", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macu<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ. */ -+{ "macu", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macu<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS. */ -+{ "macu", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macu<.f> a,limm,limm 0010111000001111F111111110AAAAAA. */ -+{ "macu", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macu<.f> 0,limm,limm 0010111000001111F111111110111110. */ -+{ "macu", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macu<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ. */ -+{ "macu", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> a,b,c 00110bbb00100110FBBBCCCCCCAAAAAA. */ -+{ "macwhfl", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfl<.f> 0,b,c 00110bbb00100110FBBBCCCCCC111110. */ -+{ "macwhfl", 0x3026003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfl<.f><.cc> b,b,c 00110bbb11100110FBBBCCCCCC0QQQQQ. */ -+{ "macwhfl", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> a,b,u6 00110bbb01100110FBBBuuuuuuAAAAAA. */ -+{ "macwhfl", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfl<.f> 0,b,u6 00110bbb01100110FBBBuuuuuu111110. */ -+{ "macwhfl", 0x3066003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfl<.f><.cc> b,b,u6 00110bbb11100110FBBBuuuuuu1QQQQQ. */ -+{ "macwhfl", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> b,b,s12 00110bbb10100110FBBBssssssSSSSSS. */ -+{ "macwhfl", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfl<.f> a,limm,c 0011011000100110F111CCCCCCAAAAAA. */ -+{ "macwhfl", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfl<.f> a,b,limm 00110bbb00100110FBBB111110AAAAAA. */ -+{ "macwhfl", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfl<.f> 0,limm,c 0011011001100110F111CCCCCC111110. */ -+{ "macwhfl", 0x3666703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfl<.f> 0,b,limm 00110bbb00100110FBBB111110111110. */ -+{ "macwhfl", 0x30260FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfl<.f><.cc> b,b,limm 00110bbb11100110FBBB1111100QQQQQ. */ -+{ "macwhfl", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhfl<.f><.cc> 0,limm,c 0011011011100110F111CCCCCC0QQQQQ. */ -+{ "macwhfl", 0x36E67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> a,limm,u6 0011011001100110F111uuuuuuAAAAAA. */ -+{ "macwhfl", 0x36667000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfl<.f> 0,limm,u6 0011011001100110F111uuuuuu111110. */ -+{ "macwhfl", 0x3666703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfl<.f><.cc> 0,limm,u6 0011011011100110F111uuuuuu1QQQQQ. */ -+{ "macwhfl", 0x36E67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> 0,limm,s12 0011011010100110F111ssssssSSSSSS. */ -+{ "macwhfl", 0x36A67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfl<.f> a,limm,limm 0011011000100110F111111110AAAAAA. */ -+{ "macwhfl", 0x36267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfl<.f> 0,limm,limm 0011011000100110F111111110111110. */ -+{ "macwhfl", 0x36267FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfl<.f><.cc> 0,limm,limm 0011011011100110F1111111100QQQQQ. */ -+{ "macwhfl", 0x36E67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> a,b,c 00110bbb00100111FBBBCCCCCCAAAAAA. */ -+{ "macwhflr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhflr<.f> 0,b,c 00110bbb00100111FBBBCCCCCC111110. */ -+{ "macwhflr", 0x3027003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhflr<.f><.cc> b,b,c 00110bbb11100111FBBBCCCCCC0QQQQQ. */ -+{ "macwhflr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> a,b,u6 00110bbb01100111FBBBuuuuuuAAAAAA. */ -+{ "macwhflr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhflr<.f> 0,b,u6 00110bbb01100111FBBBuuuuuu111110. */ -+{ "macwhflr", 0x3067003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhflr<.f><.cc> b,b,u6 00110bbb11100111FBBBuuuuuu1QQQQQ. */ -+{ "macwhflr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> b,b,s12 00110bbb10100111FBBBssssssSSSSSS. */ -+{ "macwhflr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhflr<.f> a,limm,c 0011011000100111F111CCCCCCAAAAAA. */ -+{ "macwhflr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhflr<.f> a,b,limm 00110bbb00100111FBBB111110AAAAAA. */ -+{ "macwhflr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhflr<.f> 0,limm,c 0011011001100111F111CCCCCC111110. */ -+{ "macwhflr", 0x3667703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhflr<.f> 0,b,limm 00110bbb00100111FBBB111110111110. */ -+{ "macwhflr", 0x30270FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhflr<.f><.cc> b,b,limm 00110bbb11100111FBBB1111100QQQQQ. */ -+{ "macwhflr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhflr<.f><.cc> 0,limm,c 0011011011100111F111CCCCCC0QQQQQ. */ -+{ "macwhflr", 0x36E77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> a,limm,u6 0011011001100111F111uuuuuuAAAAAA. */ -+{ "macwhflr", 0x36677000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhflr<.f> 0,limm,u6 0011011001100111F111uuuuuu111110. */ -+{ "macwhflr", 0x3667703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhflr<.f><.cc> 0,limm,u6 0011011011100111F111uuuuuu1QQQQQ. */ -+{ "macwhflr", 0x36E77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> 0,limm,s12 0011011010100111F111ssssssSSSSSS. */ -+{ "macwhflr", 0x36A77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhflr<.f> a,limm,limm 0011011000100111F111111110AAAAAA. */ -+{ "macwhflr", 0x36277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhflr<.f> 0,limm,limm 0011011000100111F111111110111110. */ -+{ "macwhflr", 0x36277FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhflr<.f><.cc> 0,limm,limm 0011011011100111F1111111100QQQQQ. */ -+{ "macwhflr", 0x36E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA. */ -+{ "macwhfm", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfm<.f> 0,b,c 00110bbb00100010FBBBCCCCCC111110. */ -+{ "macwhfm", 0x3022003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfm<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ. */ -+{ "macwhfm", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA. */ -+{ "macwhfm", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfm<.f> 0,b,u6 00110bbb01100010FBBBuuuuuu111110. */ -+{ "macwhfm", 0x3062003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfm<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ. */ -+{ "macwhfm", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS. */ -+{ "macwhfm", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfm<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA. */ -+{ "macwhfm", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfm<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA. */ -+{ "macwhfm", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfm<.f> 0,limm,c 0011011001100010F111CCCCCC111110. */ -+{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfm<.f> 0,b,limm 00110bbb00100010FBBB111110111110. */ -+{ "macwhfm", 0x30220FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfm<.f><.cc> b,b,limm 00110bbb11100010FBBB1111100QQQQQ. */ -+{ "macwhfm", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhfm<.f><.cc> 0,limm,c 0011011011100010F111CCCCCC0QQQQQ. */ -+{ "macwhfm", 0x36E27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> a,limm,u6 0011011001100010F111uuuuuuAAAAAA. */ -+{ "macwhfm", 0x36627000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfm<.f> 0,limm,u6 0011011001100010F111uuuuuu111110. */ -+{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfm<.f><.cc> 0,limm,u6 0011011011100010F111uuuuuu1QQQQQ. */ -+{ "macwhfm", 0x36E27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> 0,limm,s12 0011011010100010F111ssssssSSSSSS. */ -+{ "macwhfm", 0x36A27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfm<.f> a,limm,limm 0011011000100010F111111110AAAAAA. */ -+{ "macwhfm", 0x36227F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfm<.f> 0,limm,limm 0011011000100010F111111110111110. */ -+{ "macwhfm", 0x36227FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfm<.f><.cc> 0,limm,limm 0011011011100010F1111111100QQQQQ. */ -+{ "macwhfm", 0x36E27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA. */ -+{ "macwhfmr", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfmr<.f> 0,b,c 00110bbb00100011FBBBCCCCCC111110. */ -+{ "macwhfmr", 0x3023003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ. */ -+{ "macwhfmr", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA. */ -+{ "macwhfmr", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfmr<.f> 0,b,u6 00110bbb01100011FBBBuuuuuu111110. */ -+{ "macwhfmr", 0x3063003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ. */ -+{ "macwhfmr", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS. */ -+{ "macwhfmr", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfmr<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA. */ -+{ "macwhfmr", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfmr<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA. */ -+{ "macwhfmr", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfmr<.f> 0,limm,c 0011011001100011F111CCCCCC111110. */ -+{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfmr<.f> 0,b,limm 00110bbb00100011FBBB111110111110. */ -+{ "macwhfmr", 0x30230FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> b,b,limm 00110bbb11100011FBBB1111100QQQQQ. */ -+{ "macwhfmr", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f><.cc> 0,limm,c 0011011011100011F111CCCCCC0QQQQQ. */ -+{ "macwhfmr", 0x36E37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> a,limm,u6 0011011001100011F111uuuuuuAAAAAA. */ -+{ "macwhfmr", 0x36637000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfmr<.f> 0,limm,u6 0011011001100011F111uuuuuu111110. */ -+{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> 0,limm,u6 0011011011100011F111uuuuuu1QQQQQ. */ -+{ "macwhfmr", 0x36E37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> 0,limm,s12 0011011010100011F111ssssssSSSSSS. */ -+{ "macwhfmr", 0x36A37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfmr<.f> a,limm,limm 0011011000100011F111111110AAAAAA. */ -+{ "macwhfmr", 0x36237F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfmr<.f> 0,limm,limm 0011011000100011F111111110111110. */ -+{ "macwhfmr", 0x36237FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> 0,limm,limm 0011011011100011F1111111100QQQQQ. */ -+{ "macwhfmr", 0x36E37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> a,b,c 00110bbb00101000FBBBCCCCCCAAAAAA. */ -+{ "macwhkl", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhkl<.f> 0,b,c 00110bbb00101000FBBBCCCCCC111110. */ -+{ "macwhkl", 0x3028003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhkl<.f><.cc> b,b,c 00110bbb11101000FBBBCCCCCC0QQQQQ. */ -+{ "macwhkl", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> a,b,u6 00110bbb01101000FBBBuuuuuuAAAAAA. */ -+{ "macwhkl", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkl<.f> 0,b,u6 00110bbb01101000FBBBuuuuuu111110. */ -+{ "macwhkl", 0x3068003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkl<.f><.cc> b,b,u6 00110bbb11101000FBBBuuuuuu1QQQQQ. */ -+{ "macwhkl", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> b,b,s12 00110bbb10101000FBBBssssssSSSSSS. */ -+{ "macwhkl", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhkl<.f> a,limm,c 0011011000101000F111CCCCCCAAAAAA. */ -+{ "macwhkl", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhkl<.f> a,b,limm 00110bbb00101000FBBB111110AAAAAA. */ -+{ "macwhkl", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhkl<.f> 0,limm,c 0011011001101000F111CCCCCC111110. */ -+{ "macwhkl", 0x3668703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhkl<.f> 0,b,limm 00110bbb00101000FBBB111110111110. */ -+{ "macwhkl", 0x30280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhkl<.f><.cc> b,b,limm 00110bbb11101000FBBB1111100QQQQQ. */ -+{ "macwhkl", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhkl<.f><.cc> 0,limm,c 0011011011101000F111CCCCCC0QQQQQ. */ -+{ "macwhkl", 0x36E87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> a,limm,u6 0011011001101000F111uuuuuuAAAAAA. */ -+{ "macwhkl", 0x36687000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkl<.f> 0,limm,u6 0011011001101000F111uuuuuu111110. */ -+{ "macwhkl", 0x3668703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkl<.f><.cc> 0,limm,u6 0011011011101000F111uuuuuu1QQQQQ. */ -+{ "macwhkl", 0x36E87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> 0,limm,s12 0011011010101000F111ssssssSSSSSS. */ -+{ "macwhkl", 0x36A87000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhkl<.f> a,limm,limm 0011011000101000F111111110AAAAAA. */ -+{ "macwhkl", 0x36287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhkl<.f> 0,limm,limm 0011011000101000F111111110111110. */ -+{ "macwhkl", 0x36287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhkl<.f><.cc> 0,limm,limm 0011011011101000F1111111100QQQQQ. */ -+{ "macwhkl", 0x36E87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhkul<.f> a,b,c 00110bbb00101001FBBBCCCCCCAAAAAA. */ -+{ "macwhkul", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhkul<.f> 0,b,c 00110bbb00101001FBBBCCCCCC111110. */ -+{ "macwhkul", 0x3029003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhkul<.f><.cc> b,b,c 00110bbb11101001FBBBCCCCCC0QQQQQ. */ -+{ "macwhkul", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhkul<.f> a,b,u6 00110bbb01101001FBBBuuuuuuAAAAAA. */ -+{ "macwhkul", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkul<.f> 0,b,u6 00110bbb01101001FBBBuuuuuu111110. */ -+{ "macwhkul", 0x3069003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkul<.f><.cc> b,b,u6 00110bbb11101001FBBBuuuuuu1QQQQQ. */ -+{ "macwhkul", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhkul<.f> b,b,s12 00110bbb10101001FBBBssssssSSSSSS. */ -+{ "macwhkul", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhkul<.f> a,limm,c 0011011000101001F111CCCCCCAAAAAA. */ -+{ "macwhkul", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhkul<.f> a,b,limm 00110bbb00101001FBBB111110AAAAAA. */ -+{ "macwhkul", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhkul<.f> 0,limm,c 0011011001101001F111CCCCCC111110. */ -+{ "macwhkul", 0x3669703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhkul<.f> 0,b,limm 00110bbb00101001FBBB111110111110. */ -+{ "macwhkul", 0x30290FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhkul<.f><.cc> b,b,limm 00110bbb11101001FBBB1111100QQQQQ. */ -+{ "macwhkul", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhkul<.f><.cc> 0,limm,c 0011011011101001F111CCCCCC0QQQQQ. */ -+{ "macwhkul", 0x36E97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhkul<.f> a,limm,u6 0011011001101001F111uuuuuuAAAAAA. */ -+{ "macwhkul", 0x36697000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkul<.f> 0,limm,u6 0011011001101001F111uuuuuu111110. */ -+{ "macwhkul", 0x3669703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkul<.f><.cc> 0,limm,u6 0011011011101001F111uuuuuu1QQQQQ. */ -+{ "macwhkul", 0x36E97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhkul<.f> 0,limm,s12 0011011010101001F111ssssssSSSSSS. */ -+{ "macwhkul", 0x36A97000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhkul<.f> a,limm,limm 0011011000101001F111111110AAAAAA. */ -+{ "macwhkul", 0x36297F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhkul<.f> 0,limm,limm 0011011000101001F111111110111110. */ -+{ "macwhkul", 0x36297FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhkul<.f><.cc> 0,limm,limm 0011011011101001F1111111100QQQQQ. */ -+{ "macwhkul", 0x36E97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhl<.f> a,b,c 00110bbb00011101FBBBCCCCCCAAAAAA. */ -+{ "macwhl", 0x301D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhl<.f> 0,b,c 00110bbb00011101FBBBCCCCCC111110. */ -+{ "macwhl", 0x301D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhl<.f><.cc> b,b,c 00110bbb11011101FBBBCCCCCC0QQQQQ. */ -+{ "macwhl", 0x30DD0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhl<.f> a,b,u6 00110bbb01011101FBBBuuuuuuAAAAAA. */ -+{ "macwhl", 0x305D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhl<.f> 0,b,u6 00110bbb01011101FBBBuuuuuu111110. */ -+{ "macwhl", 0x305D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhl<.f><.cc> b,b,u6 00110bbb11011101FBBBuuuuuu1QQQQQ. */ -+{ "macwhl", 0x30DD0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhl<.f> b,b,s12 00110bbb10011101FBBBssssssSSSSSS. */ -+{ "macwhl", 0x309D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhl<.f> a,limm,c 0011011000011101F111CCCCCCAAAAAA. */ -+{ "macwhl", 0x361D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhl<.f> a,b,limm 00110bbb00011101FBBB111110AAAAAA. */ -+{ "macwhl", 0x301D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhl<.f> 0,limm,c 0011011000011101F111CCCCCC111110. */ -+{ "macwhl", 0x361D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhl<.f> 0,b,limm 00110bbb00011101FBBB111110111110. */ -+{ "macwhl", 0x301D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhl<.f><.cc> b,b,limm 00110bbb11011101FBBB1111100QQQQQ. */ -+{ "macwhl", 0x30DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhl<.f><.cc> 0,limm,c 0011011011011101F111CCCCCC0QQQQQ. */ -+{ "macwhl", 0x36DD7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhl<.f> a,limm,u6 0011011001011101F111uuuuuuAAAAAA. */ -+{ "macwhl", 0x365D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhl<.f> 0,limm,u6 0011011001011101F111uuuuuu111110. */ -+{ "macwhl", 0x365D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhl<.f><.cc> 0,limm,u6 0011011011011101F111uuuuuu1QQQQQ. */ -+{ "macwhl", 0x36DD7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhl<.f> 0,limm,s12 0011011010011101F111ssssssSSSSSS. */ -+{ "macwhl", 0x369D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhl<.f> a,limm,limm 0011011000011101F111111110AAAAAA. */ -+{ "macwhl", 0x361D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhl<.f> 0,limm,limm 0011011000011101F111111110111110. */ -+{ "macwhl", 0x361D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhl<.f><.cc> 0,limm,limm 0011011011011101F1111111100QQQQQ. */ -+{ "macwhl", 0x36DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhul<.f> a,b,c 00110bbb00011111FBBBCCCCCCAAAAAA. */ -+{ "macwhul", 0x301F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhul<.f> 0,b,c 00110bbb00011111FBBBCCCCCC111110. */ -+{ "macwhul", 0x301F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhul<.f><.cc> b,b,c 00110bbb11011111FBBBCCCCCC0QQQQQ. */ -+{ "macwhul", 0x30DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhul<.f> a,b,u6 00110bbb01011111FBBBuuuuuuAAAAAA. */ -+{ "macwhul", 0x305F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhul<.f> 0,b,u6 00110bbb01011111FBBBuuuuuu111110. */ -+{ "macwhul", 0x305F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhul<.f><.cc> b,b,u6 00110bbb11011111FBBBuuuuuu1QQQQQ. */ -+{ "macwhul", 0x30DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhul<.f> b,b,s12 00110bbb10011111FBBBssssssSSSSSS. */ -+{ "macwhul", 0x309F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhul<.f> a,limm,c 0011011000011111F111CCCCCCAAAAAA. */ -+{ "macwhul", 0x361F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhul<.f> a,b,limm 00110bbb00011111FBBB111110AAAAAA. */ -+{ "macwhul", 0x301F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhul<.f> 0,limm,c 0011011000011111F111CCCCCC111110. */ -+{ "macwhul", 0x361F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhul<.f> 0,b,limm 00110bbb00011111FBBB111110111110. */ -+{ "macwhul", 0x301F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhul<.f><.cc> b,b,limm 00110bbb11011111FBBB1111100QQQQQ. */ -+{ "macwhul", 0x30DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhul<.f><.cc> 0,limm,c 0011011011011111F111CCCCCC0QQQQQ. */ -+{ "macwhul", 0x36DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhul<.f> a,limm,u6 0011011001011111F111uuuuuuAAAAAA. */ -+{ "macwhul", 0x365F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhul<.f> 0,limm,u6 0011011001011111F111uuuuuu111110. */ -+{ "macwhul", 0x365F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhul<.f><.cc> 0,limm,u6 0011011011011111F111uuuuuu1QQQQQ. */ -+{ "macwhul", 0x36DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhul<.f> 0,limm,s12 0011011010011111F111ssssssSSSSSS. */ -+{ "macwhul", 0x369F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhul<.f> a,limm,limm 0011011000011111F111111110AAAAAA. */ -+{ "macwhul", 0x361F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhul<.f> 0,limm,limm 0011011000011111F111111110111110. */ -+{ "macwhul", 0x361F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhul<.f><.cc> 0,limm,limm 0011011011011111F1111111100QQQQQ. */ -+{ "macwhul", 0x36DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* max<.f> a,b,c 00100bbb00001000FBBBCCCCCCAAAAAA. */ -+{ "max", 0x20080000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* max<.f> 0,b,c 00100bbb00001000FBBBCCCCCC111110. */ -+{ "max", 0x2008003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* max<.f><.cc> b,b,c 00100bbb11001000FBBBCCCCCC0QQQQQ. */ -+{ "max", 0x20C80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* max<.f> a,b,u6 00100bbb01001000FBBBuuuuuuAAAAAA. */ -+{ "max", 0x20480000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* max<.f> 0,b,u6 00100bbb01001000FBBBuuuuuu111110. */ -+{ "max", 0x2048003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* max<.f><.cc> b,b,u6 00100bbb11001000FBBBuuuuuu1QQQQQ. */ -+{ "max", 0x20C80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* max<.f> b,b,s12 00100bbb10001000FBBBssssssSSSSSS. */ -+{ "max", 0x20880000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* max<.f> a,limm,c 0010011000001000F111CCCCCCAAAAAA. */ -+{ "max", 0x26087000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* max<.f> a,b,limm 00100bbb00001000FBBB111110AAAAAA. */ -+{ "max", 0x20080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* max<.f> 0,limm,c 0010011000001000F111CCCCCC111110. */ -+{ "max", 0x2608703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* max<.f> 0,b,limm 00100bbb00001000FBBB111110111110. */ -+{ "max", 0x20080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* max<.f><.cc> b,b,limm 00100bbb11001000FBBB1111100QQQQQ. */ -+{ "max", 0x20C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* max<.f><.cc> 0,limm,c 0010011011001000F111CCCCCC0QQQQQ. */ -+{ "max", 0x26C87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* max<.f> a,limm,u6 0010011001001000F111uuuuuuAAAAAA. */ -+{ "max", 0x26487000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* max<.f> 0,limm,u6 0010011001001000F111uuuuuu111110. */ -+{ "max", 0x2648703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* max<.f><.cc> 0,limm,u6 0010011011001000F111uuuuuu1QQQQQ. */ -+{ "max", 0x26C87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* max<.f> 0,limm,s12 0010011010001000F111ssssssSSSSSS. */ -+{ "max", 0x26887000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* max<.f> a,limm,limm 0010011000001000F111111110AAAAAA. */ -+{ "max", 0x26087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* max<.f> 0,limm,limm 0010011000001000F111111110111110. */ -+{ "max", 0x26087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* max<.f><.cc> 0,limm,limm 0010011011001000F1111111100QQQQQ. */ -+{ "max", 0x26C87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* maxl<.f> OPERAND_RA,RB,RC 01011bbb00001000FBBBccccccaaaaaa. */ -+{ "maxl", 0x58080000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* maxl<.f> 0,RB,RC 01011bbb00001000FBBBcccccc111110. */ -+{ "maxl", 0x5808003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* maxl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11001000FBBBcccccc0QQQQQ. */ -+{ "maxl", 0x58C80000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* maxl<.f> OPERAND_RA,RB,u6 01011bbb01001000FBBBuuuuuuaaaaaa. */ -+{ "maxl", 0x58480000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxl<.f> 0,RB,u6 01011bbb01001000FBBBuuuuuu111110. */ -+{ "maxl", 0x5848003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11001000FBBBuuuuuu1QQQQQ. */ -+{ "maxl", 0x58C80020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* maxl<.f> OPERAND_RB,RB,s12 01011bbb10001000FBBBssssssSSSSSS. */ -+{ "maxl", 0x58880000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* maxl<.f> OPERAND_RA,ximm,RC 0101110000001000F111ccccccaaaaaa. */ -+{ "maxl", 0x5C087000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* maxl<.f> OPERAND_RA,RB,ximm 01011bbb00001000FBBB111100aaaaaa. */ -+{ "maxl", 0x58080F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* maxl<.f> 0,ximm,RC 0101110000001000F111cccccc111110. */ -+{ "maxl", 0x5C08703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* maxl<.f> 0,RB,ximm 01011bbb00001000FBBB111100111110. */ -+{ "maxl", 0x58080F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* maxl<.f><.cc> 0,ximm,RC 0101110011001000F111cccccc0QQQQQ. */ -+{ "maxl", 0x5CC87000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* maxl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11001000FBBB1111000QQQQQ. */ -+{ "maxl", 0x58C80F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* maxl<.f> OPERAND_RA,ximm,u6 0101110001001000F111uuuuuuaaaaaa. */ -+{ "maxl", 0x5C487000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxl<.f> 0,ximm,u6 0101110001001000F111uuuuuu111110. */ -+{ "maxl", 0x5C48703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxl<.f><.cc> 0,ximm,u6 0101110011001000F111uuuuuu1QQQQQ. */ -+{ "maxl", 0x5CC87020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* maxl<.f> OPERAND_RA,limm,RC 0101111000001000F111ccccccaaaaaa. */ -+{ "maxl", 0x5E087000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* maxl<.f> OPERAND_RA,RB,limm 01011bbb00001000FBBB111110aaaaaa. */ -+{ "maxl", 0x58080F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* maxl<.f> 0,limm,RC 0101111000001000F111cccccc111110. */ -+{ "maxl", 0x5E08703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* maxl<.f> 0,RB,limm 01011bbb00001000FBBB111110111110. */ -+{ "maxl", 0x58080FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* maxl<.f><.cc> 0,limm,RC 0101111011001000F111cccccc0QQQQQ. */ -+{ "maxl", 0x5EC87000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* maxl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11001000FBBB1111100QQQQQ. */ -+{ "maxl", 0x58C80F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* maxl<.f> OPERAND_RA,limm,u6 0101111001001000F111uuuuuuaaaaaa. */ -+{ "maxl", 0x5E487000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxl<.f> 0,limm,u6 0101111001001000F111uuuuuu111110. */ -+{ "maxl", 0x5E48703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxl<.f><.cc> 0,limm,u6 0101111011001000F111uuuuuu1QQQQQ. */ -+{ "maxl", 0x5EC87020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* maxl<.f> 0,ximm,s12 0101110010001000F111ssssssSSSSSS. */ -+{ "maxl", 0x5C887000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* maxl<.f> 0,limm,s12 0101111010001000F111ssssssSSSSSS. */ -+{ "maxl", 0x5E887000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* maxl<.f> OPERAND_RA,ximm,ximm 0101110000001000F111111100aaaaaa. */ -+{ "maxl", 0x5C087F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* maxl<.f> 0,ximm,ximm 0101110000001000F111111100111110. */ -+{ "maxl", 0x5C087F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* maxl<.f><.cc> 0,ximm,ximm 0101110011001000F1111111000QQQQQ. */ -+{ "maxl", 0x5CC87F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* maxl<.f> OPERAND_RA,limm,limm 0101111000001000F111111110aaaaaa. */ -+{ "maxl", 0x5E087F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* maxl<.f> 0,limm,limm 0101111000001000F111111110111110. */ -+{ "maxl", 0x5E087FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* maxl<.f><.cc> 0,limm,limm 0101111011001000F1111111100QQQQQ. */ -+{ "maxl", 0x5EC87F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* min<.f> a,b,c 00100bbb00001001FBBBCCCCCCAAAAAA. */ -+{ "min", 0x20090000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* min<.f> 0,b,c 00100bbb00001001FBBBCCCCCC111110. */ -+{ "min", 0x2009003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* min<.f><.cc> b,b,c 00100bbb11001001FBBBCCCCCC0QQQQQ. */ -+{ "min", 0x20C90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* min<.f> a,b,u6 00100bbb01001001FBBBuuuuuuAAAAAA. */ -+{ "min", 0x20490000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* min<.f> 0,b,u6 00100bbb01001001FBBBuuuuuu111110. */ -+{ "min", 0x2049003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* min<.f><.cc> b,b,u6 00100bbb11001001FBBBuuuuuu1QQQQQ. */ -+{ "min", 0x20C90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* min<.f> b,b,s12 00100bbb10001001FBBBssssssSSSSSS. */ -+{ "min", 0x20890000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* min<.f> a,limm,c 0010011000001001F111CCCCCCAAAAAA. */ -+{ "min", 0x26097000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* min<.f> a,b,limm 00100bbb00001001FBBB111110AAAAAA. */ -+{ "min", 0x20090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* min<.f> 0,limm,c 0010011000001001F111CCCCCC111110. */ -+{ "min", 0x2609703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* min<.f> 0,b,limm 00100bbb00001001FBBB111110111110. */ -+{ "min", 0x20090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* min<.f><.cc> b,b,limm 00100bbb11001001FBBB1111100QQQQQ. */ -+{ "min", 0x20C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* min<.f><.cc> 0,limm,c 0010011011001001F111CCCCCC0QQQQQ. */ -+{ "min", 0x26C97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* min<.f> a,limm,u6 0010011001001001F111uuuuuuAAAAAA. */ -+{ "min", 0x26497000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* min<.f> 0,limm,u6 0010011001001001F111uuuuuu111110. */ -+{ "min", 0x2649703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* min<.f><.cc> 0,limm,u6 0010011011001001F111uuuuuu1QQQQQ. */ -+{ "min", 0x26C97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* min<.f> 0,limm,s12 0010011010001001F111ssssssSSSSSS. */ -+{ "min", 0x26897000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* min<.f> a,limm,limm 0010011000001001F111111110AAAAAA. */ -+{ "min", 0x26097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* min<.f> 0,limm,limm 0010011000001001F111111110111110. */ -+{ "min", 0x26097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* min<.f><.cc> 0,limm,limm 0010011011001001F1111111100QQQQQ. */ -+{ "min", 0x26C97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* minl<.f> OPERAND_RA,RB,RC 01011bbb00001001FBBBccccccaaaaaa. */ -+{ "minl", 0x58090000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* minl<.f> 0,RB,RC 01011bbb00001001FBBBcccccc111110. */ -+{ "minl", 0x5809003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* minl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11001001FBBBcccccc0QQQQQ. */ -+{ "minl", 0x58C90000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* minl<.f> OPERAND_RA,RB,u6 01011bbb01001001FBBBuuuuuuaaaaaa. */ -+{ "minl", 0x58490000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minl<.f> 0,RB,u6 01011bbb01001001FBBBuuuuuu111110. */ -+{ "minl", 0x5849003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11001001FBBBuuuuuu1QQQQQ. */ -+{ "minl", 0x58C90020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* minl<.f> OPERAND_RB,RB,s12 01011bbb10001001FBBBssssssSSSSSS. */ -+{ "minl", 0x58890000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* minl<.f> OPERAND_RA,ximm,RC 0101110000001001F111ccccccaaaaaa. */ -+{ "minl", 0x5C097000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* minl<.f> OPERAND_RA,RB,ximm 01011bbb00001001FBBB111100aaaaaa. */ -+{ "minl", 0x58090F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* minl<.f> 0,ximm,RC 0101110000001001F111cccccc111110. */ -+{ "minl", 0x5C09703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* minl<.f> 0,RB,ximm 01011bbb00001001FBBB111100111110. */ -+{ "minl", 0x58090F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* minl<.f><.cc> 0,ximm,RC 0101110011001001F111cccccc0QQQQQ. */ -+{ "minl", 0x5CC97000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* minl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11001001FBBB1111000QQQQQ. */ -+{ "minl", 0x58C90F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* minl<.f> OPERAND_RA,ximm,u6 0101110001001001F111uuuuuuaaaaaa. */ -+{ "minl", 0x5C497000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minl<.f> 0,ximm,u6 0101110001001001F111uuuuuu111110. */ -+{ "minl", 0x5C49703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minl<.f><.cc> 0,ximm,u6 0101110011001001F111uuuuuu1QQQQQ. */ -+{ "minl", 0x5CC97020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* minl<.f> OPERAND_RA,limm,RC 0101111000001001F111ccccccaaaaaa. */ -+{ "minl", 0x5E097000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* minl<.f> OPERAND_RA,RB,limm 01011bbb00001001FBBB111110aaaaaa. */ -+{ "minl", 0x58090F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* minl<.f> 0,limm,RC 0101111000001001F111cccccc111110. */ -+{ "minl", 0x5E09703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* minl<.f> 0,RB,limm 01011bbb00001001FBBB111110111110. */ -+{ "minl", 0x58090FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* minl<.f><.cc> 0,limm,RC 0101111011001001F111cccccc0QQQQQ. */ -+{ "minl", 0x5EC97000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* minl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11001001FBBB1111100QQQQQ. */ -+{ "minl", 0x58C90F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* minl<.f> OPERAND_RA,limm,u6 0101111001001001F111uuuuuuaaaaaa. */ -+{ "minl", 0x5E497000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minl<.f> 0,limm,u6 0101111001001001F111uuuuuu111110. */ -+{ "minl", 0x5E49703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minl<.f><.cc> 0,limm,u6 0101111011001001F111uuuuuu1QQQQQ. */ -+{ "minl", 0x5EC97020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* minl<.f> 0,ximm,s12 0101110010001001F111ssssssSSSSSS. */ -+{ "minl", 0x5C897000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* minl<.f> 0,limm,s12 0101111010001001F111ssssssSSSSSS. */ -+{ "minl", 0x5E897000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* minl<.f> OPERAND_RA,ximm,ximm 0101110000001001F111111100aaaaaa. */ -+{ "minl", 0x5C097F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* minl<.f> 0,ximm,ximm 0101110000001001F111111100111110. */ -+{ "minl", 0x5C097F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* minl<.f><.cc> 0,ximm,ximm 0101110011001001F1111111000QQQQQ. */ -+{ "minl", 0x5CC97F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* minl<.f> OPERAND_RA,limm,limm 0101111000001001F111111110aaaaaa. */ -+{ "minl", 0x5E097F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* minl<.f> 0,limm,limm 0101111000001001F111111110111110. */ -+{ "minl", 0x5E097FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* minl<.f><.cc> 0,limm,limm 0101111011001001F1111111100QQQQQ. */ -+{ "minl", 0x5EC97F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* nop 00100110010010100111000000000000. */ -+{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */ -+{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mov<.f> 0,c 0010011000001010F111CCCCCCRRRRRR. */ -+{ "mov", 0x260A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* mov<.f><.cc> b,c 00100bbb11001010FBBBCCCCCC0QQQQQ. */ -+{ "mov", 0x20CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mov<.f><.cc> 0,c 0010011011001010F111CCCCCC0QQQQQ. */ -+{ "mov", 0x26CA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mov<.f> b,u6 00100bbb01001010FBBBuuuuuuRRRRRR. */ -+{ "mov", 0x204A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mov<.f> 0,u6 0010011001001010F111uuuuuuRRRRRR. */ -+{ "mov", 0x264A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */ -+{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mov<.f><.cc> 0,u6 0010011011001010F111uuuuuu1QQQQQ. */ -+{ "mov", 0x26CA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */ -+{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mov<.f> 0,s12 0010011010001010F111ssssssSSSSSS. */ -+{ "mov", 0x268A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ -+{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mov<.f> 0,limm 0010011000001010F111111110RRRRRR. */ -+{ "mov", 0x260A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ -+{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mov<.f><.cc> 0,limm 0010011011001010F1111111100QQQQQ. */ -+{ "mov", 0x26CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* movhl OPERAND_RB,RC 01011bbb000010110BBBccccccRRRRRR. */ -+{ "movhl", 0x580B0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* movhl<.cc> OPERAND_RB,RC 01011bbb110010110BBBcccccc0QQQQQ. */ -+{ "movhl", 0x58CB0000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* movhl OPERAND_RB,u6 01011bbb010010110BBBuuuuuuRRRRRR. */ -+{ "movhl", 0x584B0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* movhl<.cc> OPERAND_RB,u6 01011bbb110010110BBBuuuuuu1QQQQQ. */ -+{ "movhl", 0x58CB0020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* movhl OPERAND_RB,s12 01011bbb100010110BBBssssssSSSSSS. */ -+{ "movhl", 0x588B0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* movhl OPERAND_RB,limm 01011bbb000010110BBB111110RRRRRR. */ -+{ "movhl", 0x580B0F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_HI32 }, { 0 }}, -+ -+/* movhl<.cc> OPERAND_RB,limm 01011bbb110010110BBB1111100QQQQQ. */ -+{ "movhl", 0x58CB0F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_HI32 }, { C_CC }}, -+ -+/* movhl_s h,limm 01110000hhh010HH. */ -+{ "movhl_s", 0x00007008, 0x0000FF1C, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RH_S, OPERAND_HI32 }, { 0 }}, -+ -+/* movl<.f> OPERAND_RB,RC 01011bbb00001010FBBBccccccRRRRRR. */ -+{ "movl", 0x580A0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* movl<.f><.cc> OPERAND_RB,RC 01011bbb11001010FBBBcccccc0QQQQQ. */ -+{ "movl", 0x58CA0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* movl<.f> OPERAND_RB,u6 01011bbb01001010FBBBuuuuuuRRRRRR. */ -+{ "movl", 0x584A0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* movl<.f><.cc> OPERAND_RB,u6 01011bbb11001010FBBBuuuuuu1QQQQQ. */ -+{ "movl", 0x58CA0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* movl<.f> OPERAND_RB,s12 01011bbb10001010FBBBssssssSSSSSS. */ -+{ "movl", 0x588A0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* movl<.f> OPERAND_RB,ximm 01011bbb00001010FBBB111100RRRRRR. */ -+{ "movl", 0x580A0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* movl<.f><.cc> OPERAND_RB,ximm 01011bbb11001010FBBB1111000QQQQQ. */ -+{ "movl", 0x58CA0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* movl<.f> OPERAND_RB,limm 01011bbb00001010FBBB111110RRRRRR. */ -+{ "movl", 0x580A0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* movl<.f><.cc> OPERAND_RB,limm 01011bbb11001010FBBB1111100QQQQQ. */ -+{ "movl", 0x58CA0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* movl_s g,h 01000ggghhhGG1HH. */ -+{ "movl_s", 0x00004004, 0x0000F804, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_G_S, OPERAND_RH_S }, { 0 }}, -+ -+/* movl_s b,u8 11011bbbuuuuuuuu. */ -+{ "movl_s", 0x0000D800, 0x0000F800, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_UIMM8_8_S }, { 0 }}, -+ -+/* movl_s g,limm 01000ggg110GG111. */ -+{ "movl_s", 0x000040C7, 0x0000F8E7, ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_G_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* mov_s.NE b,h 01110bbbhhh111HH. */ -+{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { C_NE, C_CC_NE}}, -+ -+/* mov_s g,h 01000ggghhhGG0HH. */ -+{ "mov_s", 0x00004000, 0x0000F804, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_G_S, OPERAND_RH_S }, { 0 }}, -+ -+/* mov_s 0,h 01000110hhh110HH. */ -+{ "mov_s", 0x00004618, 0x0000FF1C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA_S, OPERAND_RH_S }, { 0 }}, -+ -+/* mov_s h,s3 01110ssshhh011HH. */ -+{ "mov_s", 0x0000700C, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* mov_s 0,s3 01110sss11001111. */ -+{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* mov_s b,u8 11011bbbuuuuuuuu. */ -+{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB_S, OPERAND_UIMM8_8_S }, { 0 }}, -+ -+/* mov_s.NE b,limm 01110bbb11011111. */ -+{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { C_NE, C_CC_NE}}, -+ -+/* mov_s g,limm 01000ggg110GG011. */ -+{ "mov_s", 0x000040C3, 0x0000F8E7, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_G_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* mov_s 0,limm 0100011011011011. */ -+{ "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MOVE, NONE, { OPERAND_ZA_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA. */ -+{ "mpy", 0x201A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpy<.f> 0,b,c 00100bbb00011010FBBBCCCCCC111110. */ -+{ "mpy", 0x201A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpy<.f><.cc> b,b,c 00100bbb11011010FBBBCCCCCC0QQQQQ. */ -+{ "mpy", 0x20DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */ -+{ "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpy<.f> 0,b,u6 00100bbb01011010FBBBuuuuuu111110. */ -+{ "mpy", 0x205A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpy<.f><.cc> b,b,u6 00100bbb11011010FBBBuuuuuu1QQQQQ. */ -+{ "mpy", 0x20DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpy<.f> b,b,s12 00100bbb10011010FBBBssssssSSSSSS. */ -+{ "mpy", 0x209A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpy<.f> a,limm,c 0010011000011010F111CCCCCCAAAAAA. */ -+{ "mpy", 0x261A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ -+{ "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpy<.f> 0,limm,c 0010011000011010F111CCCCCC111110. */ -+{ "mpy", 0x261A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpy<.f> 0,b,limm 00100bbb00011010FBBB111110111110. */ -+{ "mpy", 0x201A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpy<.f><.cc> b,b,limm 00100bbb11011010FBBB1111100QQQQQ. */ -+{ "mpy", 0x20DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpy<.f><.cc> 0,limm,c 0010011011011010F111CCCCCC0QQQQQ. */ -+{ "mpy", 0x26DA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpy<.f> a,limm,u6 0010011001011010F111uuuuuuAAAAAA. */ -+{ "mpy", 0x265A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpy<.f> 0,limm,u6 0010011001011010F111uuuuuu111110. */ -+{ "mpy", 0x265A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpy<.f><.cc> 0,limm,u6 0010011011011010F111uuuuuu1QQQQQ. */ -+{ "mpy", 0x26DA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpy<.f> 0,limm,s12 0010011010011010F111ssssssSSSSSS. */ -+{ "mpy", 0x269A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpy<.f> a,limm,limm 0010011000011010F111111110AAAAAA. */ -+{ "mpy", 0x261A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpy<.f> 0,limm,limm 0010011000011010F111111110111110. */ -+{ "mpy", 0x261A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpy<.f><.cc> 0,limm,limm 0010011011011010F1111111100QQQQQ. */ -+{ "mpy", 0x26DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyd<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA. */ -+{ "mpyd", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyd<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110. */ -+{ "mpyd", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyd<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ. */ -+{ "mpyd", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyd<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA. */ -+{ "mpyd", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyd<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110. */ -+{ "mpyd", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyd<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ. */ -+{ "mpyd", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyd<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS. */ -+{ "mpyd", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyd<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA. */ -+{ "mpyd", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyd<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA. */ -+{ "mpyd", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyd<.f> 0,limm,c 0010111000011000F111CCCCCC111110. */ -+{ "mpyd", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyd<.f> 0,b,limm 00101bbb00011000FBBB111110111110. */ -+{ "mpyd", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyd<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ. */ -+{ "mpyd", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyd<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ. */ -+{ "mpyd", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyd<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA. */ -+{ "mpyd", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyd<.f> 0,limm,u6 0010111001011000F111uuuuuu111110. */ -+{ "mpyd", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyd<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ. */ -+{ "mpyd", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyd<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS. */ -+{ "mpyd", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyd<.f> a,limm,limm 0010111000011000F111111110AAAAAA. */ -+{ "mpyd", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyd<.f> 0,limm,limm 0010111000011000F111111110111110. */ -+{ "mpyd", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyd<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ. */ -+{ "mpyd", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpydf<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA. */ -+{ "mpydf", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpydf<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110. */ -+{ "mpydf", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpydf<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ. */ -+{ "mpydf", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpydf<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA. */ -+{ "mpydf", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydf<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110. */ -+{ "mpydf", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydf<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ. */ -+{ "mpydf", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpydf<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS. */ -+{ "mpydf", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpydf<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA. */ -+{ "mpydf", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpydf<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA. */ -+{ "mpydf", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpydf<.f> 0,limm,c 0011011000010010F111CCCCCC111110. */ -+{ "mpydf", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpydf<.f> 0,b,limm 00110bbb00010010FBBB111110111110. */ -+{ "mpydf", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpydf<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ. */ -+{ "mpydf", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpydf<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ. */ -+{ "mpydf", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpydf<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA. */ -+{ "mpydf", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydf<.f> 0,limm,u6 0011011001010010F111uuuuuu111110. */ -+{ "mpydf", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydf<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ. */ -+{ "mpydf", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpydf<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS. */ -+{ "mpydf", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpydf<.f> a,limm,limm 0011011000010010F111111110AAAAAA. */ -+{ "mpydf", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpydf<.f> 0,limm,limm 0011011000010010F111111110111110. */ -+{ "mpydf", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpydf<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ. */ -+{ "mpydf", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpydu<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA. */ -+{ "mpydu", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpydu<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110. */ -+{ "mpydu", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpydu<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ. */ -+{ "mpydu", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpydu<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA. */ -+{ "mpydu", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydu<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110. */ -+{ "mpydu", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydu<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ. */ -+{ "mpydu", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpydu<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS. */ -+{ "mpydu", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpydu<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA. */ -+{ "mpydu", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpydu<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA. */ -+{ "mpydu", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpydu<.f> 0,limm,c 0010111000011001F111CCCCCC111110. */ -+{ "mpydu", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpydu<.f> 0,b,limm 00101bbb00011001FBBB111110111110. */ -+{ "mpydu", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpydu<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ. */ -+{ "mpydu", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpydu<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ. */ -+{ "mpydu", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpydu<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA. */ -+{ "mpydu", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydu<.f> 0,limm,u6 0010111001011001F111uuuuuu111110. */ -+{ "mpydu", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydu<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ. */ -+{ "mpydu", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpydu<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS. */ -+{ "mpydu", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpydu<.f> a,limm,limm 0010111000011001F111111110AAAAAA. */ -+{ "mpydu", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpydu<.f> 0,limm,limm 0010111000011001F111111110111110. */ -+{ "mpydu", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpydu<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ. */ -+{ "mpydu", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyf<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA. */ -+{ "mpyf", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyf<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110. */ -+{ "mpyf", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyf<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ. */ -+{ "mpyf", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyf<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA. */ -+{ "mpyf", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyf<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110. */ -+{ "mpyf", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyf<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ. */ -+{ "mpyf", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyf<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS. */ -+{ "mpyf", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyf<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA. */ -+{ "mpyf", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyf<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA. */ -+{ "mpyf", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyf<.f> 0,limm,c 0011011000001010F111CCCCCC111110. */ -+{ "mpyf", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyf<.f> 0,b,limm 00110bbb00001010FBBB111110111110. */ -+{ "mpyf", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyf<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ. */ -+{ "mpyf", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyf<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ. */ -+{ "mpyf", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyf<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA. */ -+{ "mpyf", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyf<.f> 0,limm,u6 0011011001001010F111uuuuuu111110. */ -+{ "mpyf", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyf<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ. */ -+{ "mpyf", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyf<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS. */ -+{ "mpyf", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyf<.f> a,limm,limm 0011011000001010F111111110AAAAAA. */ -+{ "mpyf", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyf<.f> 0,limm,limm 0011011000001010F111111110111110. */ -+{ "mpyf", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyf<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ. */ -+{ "mpyf", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA. */ -+{ "mpyfr", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyfr<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110. */ -+{ "mpyfr", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyfr<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ. */ -+{ "mpyfr", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA. */ -+{ "mpyfr", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyfr<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110. */ -+{ "mpyfr", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyfr<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ. */ -+{ "mpyfr", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS. */ -+{ "mpyfr", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyfr<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA. */ -+{ "mpyfr", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyfr<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA. */ -+{ "mpyfr", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyfr<.f> 0,limm,c 0011011000001011F111CCCCCC111110. */ -+{ "mpyfr", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyfr<.f> 0,b,limm 00110bbb00001011FBBB111110111110. */ -+{ "mpyfr", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyfr<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ. */ -+{ "mpyfr", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyfr<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ. */ -+{ "mpyfr", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA. */ -+{ "mpyfr", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyfr<.f> 0,limm,u6 0011011001001011F111uuuuuu111110. */ -+{ "mpyfr", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyfr<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ. */ -+{ "mpyfr", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS. */ -+{ "mpyfr", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyfr<.f> a,limm,limm 0011011000001011F111111110AAAAAA. */ -+{ "mpyfr", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyfr<.f> 0,limm,limm 0011011000001011F111111110111110. */ -+{ "mpyfr", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyfr<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ. */ -+{ "mpyfr", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyl<.f> OPERAND_RA,RB,RC 01011bbb00110000FBBBccccccaaaaaa. */ -+{ "mpyl", 0x58300000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyl<.f> 0,RB,RC 01011bbb00110000FBBBcccccc111110. */ -+{ "mpyl", 0x5830003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11110000FBBBcccccc0QQQQQ. */ -+{ "mpyl", 0x58F00000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyl<.f> OPERAND_RA,RB,u6 01011bbb01110000FBBBuuuuuuaaaaaa. */ -+{ "mpyl", 0x58700000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyl<.f> 0,RB,u6 01011bbb01110000FBBBuuuuuu111110. */ -+{ "mpyl", 0x5870003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11110000FBBBuuuuuu1QQQQQ. */ -+{ "mpyl", 0x58F00020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyl<.f> OPERAND_RB,RB,s12 01011bbb10110000FBBBssssssSSSSSS. */ -+{ "mpyl", 0x58B00000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyl<.f> OPERAND_RA,ximm,RC 0101110000110000F111ccccccaaaaaa. */ -+{ "mpyl", 0x5C307000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyl<.f> OPERAND_RA,RB,ximm 01011bbb00110000FBBB111100aaaaaa. */ -+{ "mpyl", 0x58300F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* mpyl<.f> 0,ximm,RC 0101110000110000F111cccccc111110. */ -+{ "mpyl", 0x5C30703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyl<.f> 0,RB,ximm 01011bbb00110000FBBB111100111110. */ -+{ "mpyl", 0x58300F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* mpyl<.f><.cc> 0,ximm,RC 0101110011110000F111cccccc0QQQQQ. */ -+{ "mpyl", 0x5CF07000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11110000FBBB1111000QQQQQ. */ -+{ "mpyl", 0x58F00F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* mpyl<.f> OPERAND_RA,ximm,u6 0101110001110000F111uuuuuuaaaaaa. */ -+{ "mpyl", 0x5C707000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyl<.f> 0,ximm,u6 0101110001110000F111uuuuuu111110. */ -+{ "mpyl", 0x5C70703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyl<.f><.cc> 0,ximm,u6 0101110011110000F111uuuuuu1QQQQQ. */ -+{ "mpyl", 0x5CF07020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyl<.f> OPERAND_RA,limm,RC 0101111000110000F111ccccccaaaaaa. */ -+{ "mpyl", 0x5E307000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyl<.f> OPERAND_RA,RB,limm 01011bbb00110000FBBB111110aaaaaa. */ -+{ "mpyl", 0x58300F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyl<.f> 0,limm,RC 0101111000110000F111cccccc111110. */ -+{ "mpyl", 0x5E30703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyl<.f> 0,RB,limm 01011bbb00110000FBBB111110111110. */ -+{ "mpyl", 0x58300FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyl<.f><.cc> 0,limm,RC 0101111011110000F111cccccc0QQQQQ. */ -+{ "mpyl", 0x5EF07000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11110000FBBB1111100QQQQQ. */ -+{ "mpyl", 0x58F00F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyl<.f> OPERAND_RA,limm,u6 0101111001110000F111uuuuuuaaaaaa. */ -+{ "mpyl", 0x5E707000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyl<.f> 0,limm,u6 0101111001110000F111uuuuuu111110. */ -+{ "mpyl", 0x5E70703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyl<.f><.cc> 0,limm,u6 0101111011110000F111uuuuuu1QQQQQ. */ -+{ "mpyl", 0x5EF07020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyl<.f> 0,ximm,s12 0101110010110000F111ssssssSSSSSS. */ -+{ "mpyl", 0x5CB07000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyl<.f> 0,limm,s12 0101111010110000F111ssssssSSSSSS. */ -+{ "mpyl", 0x5EB07000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyl<.f> OPERAND_RA,ximm,ximm 0101110000110000F111111100aaaaaa. */ -+{ "mpyl", 0x5C307F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* mpyl<.f> 0,ximm,ximm 0101110000110000F111111100111110. */ -+{ "mpyl", 0x5C307F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* mpyl<.f><.cc> 0,ximm,ximm 0101110011110000F1111111000QQQQQ. */ -+{ "mpyl", 0x5CF07F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* mpyl<.f> OPERAND_RA,limm,limm 0101111000110000F111111110aaaaaa. */ -+{ "mpyl", 0x5E307F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyl<.f> 0,limm,limm 0101111000110000F111111110111110. */ -+{ "mpyl", 0x5E307FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyl<.f><.cc> 0,limm,limm 0101111011110000F1111111100QQQQQ. */ -+{ "mpyl", 0x5EF07F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpym<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA. */ -+{ "mpym", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpym<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110. */ -+{ "mpym", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpym<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ. */ -+{ "mpym", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpym<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA. */ -+{ "mpym", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpym<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110. */ -+{ "mpym", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpym<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ. */ -+{ "mpym", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpym<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS. */ -+{ "mpym", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpym<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA. */ -+{ "mpym", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpym<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA. */ -+{ "mpym", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpym<.f> 0,limm,c 0010011000011011F111CCCCCC111110. */ -+{ "mpym", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpym<.f> 0,b,limm 00100bbb00011011FBBB111110111110. */ -+{ "mpym", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpym<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ. */ -+{ "mpym", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpym<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ. */ -+{ "mpym", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpym<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA. */ -+{ "mpym", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpym<.f> 0,limm,u6 0010011001011011F111uuuuuu111110. */ -+{ "mpym", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpym<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ. */ -+{ "mpym", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpym<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS. */ -+{ "mpym", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpym<.f> a,limm,limm 0010011000011011F111111110AAAAAA. */ -+{ "mpym", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpym<.f> 0,limm,limm 0010011000011011F111111110111110. */ -+{ "mpym", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpym<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ. */ -+{ "mpym", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyml OPERAND_RA,RB,RC 01011bbb001100010BBBccccccaaaaaa. */ -+{ "mpyml", 0x58310000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mpyml 0,RB,RC 01011bbb001100010BBBcccccc111110. */ -+{ "mpyml", 0x5831003E, 0xF8FF803F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mpyml<.cc> OPERAND_RB,RB,RC 01011bbb111100010BBBcccccc0QQQQQ. */ -+{ "mpyml", 0x58F10000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* mpyml OPERAND_RA,RB,u6 01011bbb011100010BBBuuuuuuaaaaaa. */ -+{ "mpyml", 0x58710000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpyml 0,RB,u6 01011bbb011100010BBBuuuuuu111110. */ -+{ "mpyml", 0x5871003E, 0xF8FF803F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpyml<.cc> OPERAND_RB,RB,u6 01011bbb111100010BBBuuuuuu1QQQQQ. */ -+{ "mpyml", 0x58F10020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mpyml OPERAND_RB,RB,s12 01011bbb101100010BBBssssssSSSSSS. */ -+{ "mpyml", 0x58B10000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mpyml OPERAND_RA,ximm,RC 01011100001100010111ccccccaaaaaa. */ -+{ "mpyml", 0x5C317000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpyml OPERAND_RA,RB,ximm 01011bbb001100010BBB111100aaaaaa. */ -+{ "mpyml", 0x58310F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* mpyml 0,ximm,RC 01011100001100010111cccccc111110. */ -+{ "mpyml", 0x5C31703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpyml 0,RB,ximm 01011bbb001100010BBB111100111110. */ -+{ "mpyml", 0x58310F3E, 0xF8FF8FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* mpyml<.cc> 0,ximm,RC 01011100111100010111cccccc0QQQQQ. */ -+{ "mpyml", 0x5CF17000, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mpyml<.cc> OPERAND_RB,RB,ximm 01011bbb111100010BBB1111000QQQQQ. */ -+{ "mpyml", 0x58F10F00, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_CC }}, -+ -+/* mpyml OPERAND_RA,ximm,u6 01011100011100010111uuuuuuaaaaaa. */ -+{ "mpyml", 0x5C717000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpyml 0,ximm,u6 01011100011100010111uuuuuu111110. */ -+{ "mpyml", 0x5C71703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpyml<.cc> 0,ximm,u6 01011100111100010111uuuuuu1QQQQQ. */ -+{ "mpyml", 0x5CF17020, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mpyml OPERAND_RA,limm,RC 01011110001100010111ccccccaaaaaa. */ -+{ "mpyml", 0x5E317000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpyml OPERAND_RA,RB,limm 01011bbb001100010BBB111110aaaaaa. */ -+{ "mpyml", 0x58310F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mpyml 0,limm,RC 01011110001100010111cccccc111110. */ -+{ "mpyml", 0x5E31703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpyml 0,RB,limm 01011bbb001100010BBB111110111110. */ -+{ "mpyml", 0x58310FBE, 0xF8FF8FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mpyml<.cc> 0,limm,RC 01011110111100010111cccccc0QQQQQ. */ -+{ "mpyml", 0x5EF17000, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mpyml<.cc> OPERAND_RB,RB,limm 01011bbb111100010BBB1111100QQQQQ. */ -+{ "mpyml", 0x58F10F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* mpyml OPERAND_RA,limm,u6 01011110011100010111uuuuuuaaaaaa. */ -+{ "mpyml", 0x5E717000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpyml 0,limm,u6 01011110011100010111uuuuuu111110. */ -+{ "mpyml", 0x5E71703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpyml<.cc> 0,limm,u6 01011110111100010111uuuuuu1QQQQQ. */ -+{ "mpyml", 0x5EF17020, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mpyml 0,ximm,s12 01011100101100010111ssssssSSSSSS. */ -+{ "mpyml", 0x5CB17000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mpyml 0,limm,s12 01011110101100010111ssssssSSSSSS. */ -+{ "mpyml", 0x5EB17000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mpyml OPERAND_RA,ximm,ximm 01011100001100010111111100aaaaaa. */ -+{ "mpyml", 0x5C317F00, 0xFFFFFFC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { 0 }}, -+ -+/* mpyml 0,ximm,ximm 01011100001100010111111100111110. */ -+{ "mpyml", 0x5C317F3E, 0xFFFFFFFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { 0 }}, -+ -+/* mpyml<.cc> 0,ximm,ximm 010111001111000101111111000QQQQQ. */ -+{ "mpyml", 0x5CF17F00, 0xFFFFFFE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_CC }}, -+ -+/* mpyml OPERAND_RA,limm,limm 01011110001100010111111110aaaaaa. */ -+{ "mpyml", 0x5E317F80, 0xFFFFFFC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mpyml 0,limm,limm 01011110001100010111111110111110. */ -+{ "mpyml", 0x5E317FBE, 0xFFFFFFFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mpyml<.cc> 0,limm,limm 010111101111000101111111100QQQQQ. */ -+{ "mpyml", 0x5EF17F80, 0xFFFFFFE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* mpymsul OPERAND_RA,RB,RC 01011bbb001100110BBBccccccaaaaaa. */ -+{ "mpymsul", 0x58330000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mpymsul 0,RB,RC 01011bbb001100110BBBcccccc111110. */ -+{ "mpymsul", 0x5833003E, 0xF8FF803F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mpymsul<.cc> OPERAND_RB,RB,RC 01011bbb111100110BBBcccccc0QQQQQ. */ -+{ "mpymsul", 0x58F30000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* mpymsul OPERAND_RA,RB,u6 01011bbb011100110BBBuuuuuuaaaaaa. */ -+{ "mpymsul", 0x58730000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymsul 0,RB,u6 01011bbb011100110BBBuuuuuu111110. */ -+{ "mpymsul", 0x5873003E, 0xF8FF803F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymsul<.cc> OPERAND_RB,RB,u6 01011bbb111100110BBBuuuuuu1QQQQQ. */ -+{ "mpymsul", 0x58F30020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mpymsul OPERAND_RB,RB,s12 01011bbb101100110BBBssssssSSSSSS. */ -+{ "mpymsul", 0x58B30000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mpymsul OPERAND_RA,ximm,RC 01011100001100110111ccccccaaaaaa. */ -+{ "mpymsul", 0x5C337000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpymsul OPERAND_RA,RB,ximm 01011bbb001100110BBB111100aaaaaa. */ -+{ "mpymsul", 0x58330F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* mpymsul 0,ximm,RC 01011100001100110111cccccc111110. */ -+{ "mpymsul", 0x5C33703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpymsul 0,RB,ximm 01011bbb001100110BBB111100111110. */ -+{ "mpymsul", 0x58330F3E, 0xF8FF8FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* mpymsul<.cc> 0,ximm,RC 01011100111100110111cccccc0QQQQQ. */ -+{ "mpymsul", 0x5CF37000, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mpymsul<.cc> OPERAND_RB,RB,ximm 01011bbb111100110BBB1111000QQQQQ. */ -+{ "mpymsul", 0x58F30F00, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_CC }}, -+ -+/* mpymsul OPERAND_RA,ximm,u6 01011100011100110111uuuuuuaaaaaa. */ -+{ "mpymsul", 0x5C737000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymsul 0,ximm,u6 01011100011100110111uuuuuu111110. */ -+{ "mpymsul", 0x5C73703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymsul<.cc> 0,ximm,u6 01011100111100110111uuuuuu1QQQQQ. */ -+{ "mpymsul", 0x5CF37020, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mpymsul OPERAND_RA,limm,RC 01011110001100110111ccccccaaaaaa. */ -+{ "mpymsul", 0x5E337000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpymsul OPERAND_RA,RB,limm 01011bbb001100110BBB111110aaaaaa. */ -+{ "mpymsul", 0x58330F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mpymsul 0,limm,RC 01011110001100110111cccccc111110. */ -+{ "mpymsul", 0x5E33703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpymsul 0,RB,limm 01011bbb001100110BBB111110111110. */ -+{ "mpymsul", 0x58330FBE, 0xF8FF8FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mpymsul<.cc> 0,limm,RC 01011110111100110111cccccc0QQQQQ. */ -+{ "mpymsul", 0x5EF37000, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mpymsul<.cc> OPERAND_RB,RB,limm 01011bbb111100110BBB1111100QQQQQ. */ -+{ "mpymsul", 0x58F30F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* mpymsul OPERAND_RA,limm,u6 01011110011100110111uuuuuuaaaaaa. */ -+{ "mpymsul", 0x5E737000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymsul 0,limm,u6 01011110011100110111uuuuuu111110. */ -+{ "mpymsul", 0x5E73703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymsul<.cc> 0,limm,u6 01011110111100110111uuuuuu1QQQQQ. */ -+{ "mpymsul", 0x5EF37020, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mpymsul 0,ximm,s12 01011100101100110111ssssssSSSSSS. */ -+{ "mpymsul", 0x5CB37000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mpymsul 0,limm,s12 01011110101100110111ssssssSSSSSS. */ -+{ "mpymsul", 0x5EB37000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mpymsul OPERAND_RA,ximm,ximm 01011100001100110111111100aaaaaa. */ -+{ "mpymsul", 0x5C337F00, 0xFFFFFFC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { 0 }}, -+ -+/* mpymsul 0,ximm,ximm 01011100001100110111111100111110. */ -+{ "mpymsul", 0x5C337F3E, 0xFFFFFFFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { 0 }}, -+ -+/* mpymsul<.cc> 0,ximm,ximm 010111001111001101111111000QQQQQ. */ -+{ "mpymsul", 0x5CF37F00, 0xFFFFFFE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_CC }}, -+ -+/* mpymsul OPERAND_RA,limm,limm 01011110001100110111111110aaaaaa. */ -+{ "mpymsul", 0x5E337F80, 0xFFFFFFC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mpymsul 0,limm,limm 01011110001100110111111110111110. */ -+{ "mpymsul", 0x5E337FBE, 0xFFFFFFFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mpymsul<.cc> 0,limm,limm 010111101111001101111111100QQQQQ. */ -+{ "mpymsul", 0x5EF37F80, 0xFFFFFFE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* mpymu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA. */ -+{ "mpymu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpymu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110. */ -+{ "mpymu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpymu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ. */ -+{ "mpymu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpymu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA. */ -+{ "mpymu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpymu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110. */ -+{ "mpymu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpymu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ. */ -+{ "mpymu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpymu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS. */ -+{ "mpymu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpymu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA. */ -+{ "mpymu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpymu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA. */ -+{ "mpymu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpymu<.f> 0,limm,c 0010011000011100F111CCCCCC111110. */ -+{ "mpymu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpymu<.f> 0,b,limm 00100bbb00011100FBBB111110111110. */ -+{ "mpymu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpymu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ. */ -+{ "mpymu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpymu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ. */ -+{ "mpymu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpymu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA. */ -+{ "mpymu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpymu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110. */ -+{ "mpymu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpymu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ. */ -+{ "mpymu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpymu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS. */ -+{ "mpymu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpymu<.f> a,limm,limm 0010011000011100F111111110AAAAAA. */ -+{ "mpymu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpymu<.f> 0,limm,limm 0010011000011100F111111110111110. */ -+{ "mpymu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpymu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ. */ -+{ "mpymu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpymul OPERAND_RA,RB,RC 01011bbb001100100BBBccccccaaaaaa. */ -+{ "mpymul", 0x58320000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mpymul 0,RB,RC 01011bbb001100100BBBcccccc111110. */ -+{ "mpymul", 0x5832003E, 0xF8FF803F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mpymul<.cc> OPERAND_RB,RB,RC 01011bbb111100100BBBcccccc0QQQQQ. */ -+{ "mpymul", 0x58F20000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* mpymul OPERAND_RA,RB,u6 01011bbb011100100BBBuuuuuuaaaaaa. */ -+{ "mpymul", 0x58720000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymul 0,RB,u6 01011bbb011100100BBBuuuuuu111110. */ -+{ "mpymul", 0x5872003E, 0xF8FF803F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymul<.cc> OPERAND_RB,RB,u6 01011bbb111100100BBBuuuuuu1QQQQQ. */ -+{ "mpymul", 0x58F20020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mpymul OPERAND_RB,RB,s12 01011bbb101100100BBBssssssSSSSSS. */ -+{ "mpymul", 0x58B20000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mpymul OPERAND_RA,ximm,RC 01011100001100100111ccccccaaaaaa. */ -+{ "mpymul", 0x5C327000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpymul OPERAND_RA,RB,ximm 01011bbb001100100BBB111100aaaaaa. */ -+{ "mpymul", 0x58320F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* mpymul 0,ximm,RC 01011100001100100111cccccc111110. */ -+{ "mpymul", 0x5C32703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpymul 0,RB,ximm 01011bbb001100100BBB111100111110. */ -+{ "mpymul", 0x58320F3E, 0xF8FF8FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* mpymul<.cc> 0,ximm,RC 01011100111100100111cccccc0QQQQQ. */ -+{ "mpymul", 0x5CF27000, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mpymul<.cc> OPERAND_RB,RB,ximm 01011bbb111100100BBB1111000QQQQQ. */ -+{ "mpymul", 0x58F20F00, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_CC }}, -+ -+/* mpymul OPERAND_RA,ximm,u6 01011100011100100111uuuuuuaaaaaa. */ -+{ "mpymul", 0x5C727000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymul 0,ximm,u6 01011100011100100111uuuuuu111110. */ -+{ "mpymul", 0x5C72703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymul<.cc> 0,ximm,u6 01011100111100100111uuuuuu1QQQQQ. */ -+{ "mpymul", 0x5CF27020, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mpymul OPERAND_RA,limm,RC 01011110001100100111ccccccaaaaaa. */ -+{ "mpymul", 0x5E327000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpymul OPERAND_RA,RB,limm 01011bbb001100100BBB111110aaaaaa. */ -+{ "mpymul", 0x58320F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mpymul 0,limm,RC 01011110001100100111cccccc111110. */ -+{ "mpymul", 0x5E32703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mpymul 0,RB,limm 01011bbb001100100BBB111110111110. */ -+{ "mpymul", 0x58320FBE, 0xF8FF8FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mpymul<.cc> 0,limm,RC 01011110111100100111cccccc0QQQQQ. */ -+{ "mpymul", 0x5EF27000, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mpymul<.cc> OPERAND_RB,RB,limm 01011bbb111100100BBB1111100QQQQQ. */ -+{ "mpymul", 0x58F20F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* mpymul OPERAND_RA,limm,u6 01011110011100100111uuuuuuaaaaaa. */ -+{ "mpymul", 0x5E727000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymul 0,limm,u6 01011110011100100111uuuuuu111110. */ -+{ "mpymul", 0x5E72703E, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mpymul<.cc> 0,limm,u6 01011110111100100111uuuuuu1QQQQQ. */ -+{ "mpymul", 0x5EF27020, 0xFFFFF020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mpymul 0,ximm,s12 01011100101100100111ssssssSSSSSS. */ -+{ "mpymul", 0x5CB27000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mpymul 0,limm,s12 01011110101100100111ssssssSSSSSS. */ -+{ "mpymul", 0x5EB27000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mpymul OPERAND_RA,ximm,ximm 01011100001100100111111100aaaaaa. */ -+{ "mpymul", 0x5C327F00, 0xFFFFFFC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { 0 }}, -+ -+/* mpymul 0,ximm,ximm 01011100001100100111111100111110. */ -+{ "mpymul", 0x5C327F3E, 0xFFFFFFFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { 0 }}, -+ -+/* mpymul<.cc> 0,ximm,ximm 010111001111001001111111000QQQQQ. */ -+{ "mpymul", 0x5CF27F00, 0xFFFFFFE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_CC }}, -+ -+/* mpymul OPERAND_RA,limm,limm 01011110001100100111111110aaaaaa. */ -+{ "mpymul", 0x5E327F80, 0xFFFFFFC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mpymul 0,limm,limm 01011110001100100111111110111110. */ -+{ "mpymul", 0x5E327FBE, 0xFFFFFFFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mpymul<.cc> 0,limm,limm 010111101111001001111111100QQQQQ. */ -+{ "mpymul", 0x5EF27F80, 0xFFFFFFE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* mpyu<.f> a,b,c 00100bbb00011101FBBBCCCCCCAAAAAA. */ -+{ "mpyu", 0x201D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyu<.f> 0,b,c 00100bbb00011101FBBBCCCCCC111110. */ -+{ "mpyu", 0x201D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyu<.f><.cc> b,b,c 00100bbb11011101FBBBCCCCCC0QQQQQ. */ -+{ "mpyu", 0x20DD0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyu<.f> a,b,u6 00100bbb01011101FBBBuuuuuuAAAAAA. */ -+{ "mpyu", 0x205D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyu<.f> 0,b,u6 00100bbb01011101FBBBuuuuuu111110. */ -+{ "mpyu", 0x205D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyu<.f><.cc> b,b,u6 00100bbb11011101FBBBuuuuuu1QQQQQ. */ -+{ "mpyu", 0x20DD0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyu<.f> b,b,s12 00100bbb10011101FBBBssssssSSSSSS. */ -+{ "mpyu", 0x209D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyu<.f> a,limm,c 0010011000011101F111CCCCCCAAAAAA. */ -+{ "mpyu", 0x261D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyu<.f> a,b,limm 00100bbb00011101FBBB111110AAAAAA. */ -+{ "mpyu", 0x201D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyu<.f> 0,limm,c 0010011000011101F111CCCCCC111110. */ -+{ "mpyu", 0x261D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyu<.f> 0,b,limm 00100bbb00011101FBBB111110111110. */ -+{ "mpyu", 0x201D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyu<.f><.cc> b,b,limm 00100bbb11011101FBBB1111100QQQQQ. */ -+{ "mpyu", 0x20DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyu<.f><.cc> 0,limm,c 0010011011011101F111CCCCCC0QQQQQ. */ -+{ "mpyu", 0x26DD7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyu<.f> a,limm,u6 0010011001011101F111uuuuuuAAAAAA. */ -+{ "mpyu", 0x265D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyu<.f> 0,limm,u6 0010011001011101F111uuuuuu111110. */ -+{ "mpyu", 0x265D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyu<.f><.cc> 0,limm,u6 0010011011011101F111uuuuuu1QQQQQ. */ -+{ "mpyu", 0x26DD7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyu<.f> 0,limm,s12 0010011010011101F111ssssssSSSSSS. */ -+{ "mpyu", 0x269D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyu<.f> a,limm,limm 0010011000011101F111111110AAAAAA. */ -+{ "mpyu", 0x261D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyu<.f> 0,limm,limm 0010011000011101F111111110111110. */ -+{ "mpyu", 0x261D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyu<.f><.cc> 0,limm,limm 0010011011011101F1111111100QQQQQ. */ -+{ "mpyu", 0x26DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,b,c 00100bbb00011111FBBBCCCCCCAAAAAA. */ -+{ "mpyuw", 0x201F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f> 0,b,c 00100bbb00011111FBBBCCCCCC111110. */ -+{ "mpyuw", 0x201F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f><.cc> b,b,c 00100bbb11011111FBBBCCCCCC0QQQQQ. */ -+{ "mpyuw", 0x20DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,b,u6 00100bbb01011111FBBBuuuuuuAAAAAA. */ -+{ "mpyuw", 0x205F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f> 0,b,u6 00100bbb01011111FBBBuuuuuu111110. */ -+{ "mpyuw", 0x205F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f><.cc> b,b,u6 00100bbb11011111FBBBuuuuuu1QQQQQ. */ -+{ "mpyuw", 0x20DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> b,b,s12 00100bbb10011111FBBBssssssSSSSSS. */ -+{ "mpyuw", 0x209F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyuw<.f> a,limm,c 0010011000011111F111CCCCCCAAAAAA. */ -+{ "mpyuw", 0x261F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f> a,b,limm 00100bbb00011111FBBB111110AAAAAA. */ -+{ "mpyuw", 0x201F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,c 0010011000011111F111CCCCCC111110. */ -+{ "mpyuw", 0x261F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f> 0,b,limm 00100bbb00011111FBBB111110111110. */ -+{ "mpyuw", 0x201F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyuw<.f><.cc> b,b,limm 00100bbb11011111FBBB1111100QQQQQ. */ -+{ "mpyuw", 0x20DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyuw<.f><.cc> 0,limm,c 0010011011011111F111CCCCCC0QQQQQ. */ -+{ "mpyuw", 0x26DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,limm,u6 0010011001011111F111uuuuuuAAAAAA. */ -+{ "mpyuw", 0x265F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,u6 0010011001011111F111uuuuuu111110. */ -+{ "mpyuw", 0x265F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f><.cc> 0,limm,u6 0010011011011111F111uuuuuu1QQQQQ. */ -+{ "mpyuw", 0x26DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> 0,limm,s12 0010011010011111F111ssssssSSSSSS. */ -+{ "mpyuw", 0x269F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyuw<.f> a,limm,limm 0010011000011111F111111110AAAAAA. */ -+{ "mpyuw", 0x261F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,limm 0010011000011111F111111110111110. */ -+{ "mpyuw", 0x261F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyuw<.f><.cc> 0,limm,limm 0010011011011111F1111111100QQQQQ. */ -+{ "mpyuw", 0x26DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyuw_s b,b,c 01111bbbccc01010. */ -+{ "mpyuw_s", 0x0000780A, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* mpyw<.f> a,b,c 00100bbb00011110FBBBCCCCCCAAAAAA. */ -+{ "mpyw", 0x201E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f> 0,b,c 00100bbb00011110FBBBCCCCCC111110. */ -+{ "mpyw", 0x201E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f><.cc> b,b,c 00100bbb11011110FBBBCCCCCC0QQQQQ. */ -+{ "mpyw", 0x20DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyw<.f> a,b,u6 00100bbb01011110FBBBuuuuuuAAAAAA. */ -+{ "mpyw", 0x205E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f> 0,b,u6 00100bbb01011110FBBBuuuuuu111110. */ -+{ "mpyw", 0x205E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f><.cc> b,b,u6 00100bbb11011110FBBBuuuuuu1QQQQQ. */ -+{ "mpyw", 0x20DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyw<.f> b,b,s12 00100bbb10011110FBBBssssssSSSSSS. */ -+{ "mpyw", 0x209E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyw<.f> a,limm,c 0010011000011110F111CCCCCCAAAAAA. */ -+{ "mpyw", 0x261E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f> a,b,limm 00100bbb00011110FBBB111110AAAAAA. */ -+{ "mpyw", 0x201E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,c 0010011000011110F111CCCCCC111110. */ -+{ "mpyw", 0x261E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f> 0,b,limm 00100bbb00011110FBBB111110111110. */ -+{ "mpyw", 0x201E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyw<.f><.cc> b,b,limm 00100bbb11011110FBBB1111100QQQQQ. */ -+{ "mpyw", 0x20DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyw<.f><.cc> 0,limm,c 0010011011011110F111CCCCCC0QQQQQ. */ -+{ "mpyw", 0x26DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyw<.f> a,limm,u6 0010011001011110F111uuuuuuAAAAAA. */ -+{ "mpyw", 0x265E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,u6 0010011001011110F111uuuuuu111110. */ -+{ "mpyw", 0x265E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f><.cc> 0,limm,u6 0010011011011110F111uuuuuu1QQQQQ. */ -+{ "mpyw", 0x26DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyw<.f> 0,limm,s12 0010011010011110F111ssssssSSSSSS. */ -+{ "mpyw", 0x269E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyw<.f> a,limm,limm 0010011000011110F111111110AAAAAA. */ -+{ "mpyw", 0x261E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,limm 0010011000011110F111111110111110. */ -+{ "mpyw", 0x261E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyw<.f><.cc> 0,limm,limm 0010011011011110F1111111100QQQQQ. */ -+{ "mpyw", 0x26DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA. */ -+{ "mpywhfl", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfl<.f> 0,b,c 00110bbb00100100FBBBCCCCCC111110. */ -+{ "mpywhfl", 0x3024003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ. */ -+{ "mpywhfl", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA. */ -+{ "mpywhfl", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfl<.f> 0,b,u6 00110bbb01100100FBBBuuuuuu111110. */ -+{ "mpywhfl", 0x3064003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ. */ -+{ "mpywhfl", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS. */ -+{ "mpywhfl", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfl<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA. */ -+{ "mpywhfl", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfl<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA. */ -+{ "mpywhfl", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfl<.f> 0,limm,c 0011011001100100F111CCCCCC111110. */ -+{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfl<.f> 0,b,limm 00110bbb00100100FBBB111110111110. */ -+{ "mpywhfl", 0x30240FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> b,b,limm 00110bbb11100100FBBB1111100QQQQQ. */ -+{ "mpywhfl", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f><.cc> 0,limm,c 0011011011100100F111CCCCCC0QQQQQ. */ -+{ "mpywhfl", 0x36E47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> a,limm,u6 0011011001100100F111uuuuuuAAAAAA. */ -+{ "mpywhfl", 0x36647000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfl<.f> 0,limm,u6 0011011001100100F111uuuuuu111110. */ -+{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> 0,limm,u6 0011011011100100F111uuuuuu1QQQQQ. */ -+{ "mpywhfl", 0x36E47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> 0,limm,s12 0011011010100100F111ssssssSSSSSS. */ -+{ "mpywhfl", 0x36A47000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfl<.f> a,limm,limm 0011011000100100F111111110AAAAAA. */ -+{ "mpywhfl", 0x36247F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfl<.f> 0,limm,limm 0011011000100100F111111110111110. */ -+{ "mpywhfl", 0x36247FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> 0,limm,limm 0011011011100100F1111111100QQQQQ. */ -+{ "mpywhfl", 0x36E47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> a,b,c 00110bbb00100101FBBBCCCCCCAAAAAA. */ -+{ "mpywhflr", 0x30250000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhflr<.f> 0,b,c 00110bbb00100101FBBBCCCCCC111110. */ -+{ "mpywhflr", 0x3025003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ. */ -+{ "mpywhflr", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA. */ -+{ "mpywhflr", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhflr<.f> 0,b,u6 00110bbb01100101FBBBuuuuuu111110. */ -+{ "mpywhflr", 0x3065003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ. */ -+{ "mpywhflr", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS. */ -+{ "mpywhflr", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhflr<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA. */ -+{ "mpywhflr", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhflr<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA. */ -+{ "mpywhflr", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhflr<.f> 0,limm,c 0011011001100101F111CCCCCC111110. */ -+{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhflr<.f> 0,b,limm 00110bbb00100101FBBB111110111110. */ -+{ "mpywhflr", 0x30250FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> b,b,limm 00110bbb11100101FBBB1111100QQQQQ. */ -+{ "mpywhflr", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f><.cc> 0,limm,c 0011011011100101F111CCCCCC0QQQQQ. */ -+{ "mpywhflr", 0x36E57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> a,limm,u6 0011011001100101F111uuuuuuAAAAAA. */ -+{ "mpywhflr", 0x36657000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhflr<.f> 0,limm,u6 0011011001100101F111uuuuuu111110. */ -+{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> 0,limm,u6 0011011011100101F111uuuuuu1QQQQQ. */ -+{ "mpywhflr", 0x36E57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> 0,limm,s12 0011011010100101F111ssssssSSSSSS. */ -+{ "mpywhflr", 0x36A57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhflr<.f> a,limm,limm 0011011000100101F111111110AAAAAA. */ -+{ "mpywhflr", 0x36257F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhflr<.f> 0,limm,limm 0011011000100101F111111110111110. */ -+{ "mpywhflr", 0x36257FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> 0,limm,limm 0011011011100101F1111111100QQQQQ. */ -+{ "mpywhflr", 0x36E57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA. */ -+{ "mpywhfm", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfm<.f> 0,b,c 00110bbb00100000FBBBCCCCCC111110. */ -+{ "mpywhfm", 0x3020003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ. */ -+{ "mpywhfm", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA. */ -+{ "mpywhfm", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfm<.f> 0,b,u6 00110bbb01100000FBBBuuuuuu111110. */ -+{ "mpywhfm", 0x3060003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ. */ -+{ "mpywhfm", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS. */ -+{ "mpywhfm", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfm<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA. */ -+{ "mpywhfm", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfm<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA. */ -+{ "mpywhfm", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfm<.f> 0,limm,c 0011011001100000F111CCCCCC111110. */ -+{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfm<.f> 0,b,limm 00110bbb00100000FBBB111110111110. */ -+{ "mpywhfm", 0x30200FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> b,b,limm 00110bbb11100000FBBB1111100QQQQQ. */ -+{ "mpywhfm", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f><.cc> 0,limm,c 0011011011100000F111CCCCCC0QQQQQ. */ -+{ "mpywhfm", 0x36E07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> a,limm,u6 0011011001100000F111uuuuuuAAAAAA. */ -+{ "mpywhfm", 0x36607000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfm<.f> 0,limm,u6 0011011001100000F111uuuuuu111110. */ -+{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> 0,limm,u6 0011011011100000F111uuuuuu1QQQQQ. */ -+{ "mpywhfm", 0x36E07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> 0,limm,s12 0011011010100000F111ssssssSSSSSS. */ -+{ "mpywhfm", 0x36A07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfm<.f> a,limm,limm 0011011000100000F111111110AAAAAA. */ -+{ "mpywhfm", 0x36207F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfm<.f> 0,limm,limm 0011011000100000F111111110111110. */ -+{ "mpywhfm", 0x36207FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> 0,limm,limm 0011011011100000F1111111100QQQQQ. */ -+{ "mpywhfm", 0x36E07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */ -+{ "mpywhfmr", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,b,c 00110bbb00100001FBBBCCCCCC111110. */ -+{ "mpywhfmr", 0x3021003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ. */ -+{ "mpywhfmr", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA. */ -+{ "mpywhfmr", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,b,u6 00110bbb01100001FBBBuuuuuu111110. */ -+{ "mpywhfmr", 0x3061003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> b,b,u6 00110bbb11100001FBBBuuuuuu1QQQQQ. */ -+{ "mpywhfmr", 0x30E10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS. */ -+{ "mpywhfmr", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfmr<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA. */ -+{ "mpywhfmr", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfmr<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA. */ -+{ "mpywhfmr", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,limm,c 0011011001100001F111CCCCCC111110. */ -+{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,b,limm 00110bbb00100001FBBB111110111110. */ -+{ "mpywhfmr", 0x30210FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> b,b,limm 00110bbb11100001FBBB1111100QQQQQ. */ -+{ "mpywhfmr", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f><.cc> 0,limm,c 0011011011100001F111CCCCCC0QQQQQ. */ -+{ "mpywhfmr", 0x36E17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> a,limm,u6 0011011001100001F111uuuuuuAAAAAA. */ -+{ "mpywhfmr", 0x36617000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,limm,u6 0011011001100001F111uuuuuu111110. */ -+{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> 0,limm,u6 0011011011100001F111uuuuuu1QQQQQ. */ -+{ "mpywhfmr", 0x36E17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> 0,limm,s12 0011011010100001F111ssssssSSSSSS. */ -+{ "mpywhfmr", 0x36A17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfmr<.f> a,limm,limm 0011011000100001F111111110AAAAAA. */ -+{ "mpywhfmr", 0x36217F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,limm,limm 0011011000100001F111111110111110. */ -+{ "mpywhfmr", 0x36217FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> 0,limm,limm 0011011011100001F1111111100QQQQQ. */ -+{ "mpywhfmr", 0x36E17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> a,b,c 00110bbb00101010FBBBCCCCCCAAAAAA. */ -+{ "mpywhkl", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkl<.f> 0,b,c 00110bbb00101010FBBBCCCCCC111110. */ -+{ "mpywhkl", 0x302A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkl<.f><.cc> b,b,c 00110bbb11101010FBBBCCCCCC0QQQQQ. */ -+{ "mpywhkl", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> a,b,u6 00110bbb01101010FBBBuuuuuuAAAAAA. */ -+{ "mpywhkl", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkl<.f> 0,b,u6 00110bbb01101010FBBBuuuuuu111110. */ -+{ "mpywhkl", 0x306A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkl<.f><.cc> b,b,u6 00110bbb11101010FBBBuuuuuu1QQQQQ. */ -+{ "mpywhkl", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> b,b,s12 00110bbb10101010FBBBssssssSSSSSS. */ -+{ "mpywhkl", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhkl<.f> a,limm,c 0011011000101010F111CCCCCCAAAAAA. */ -+{ "mpywhkl", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkl<.f> a,b,limm 00110bbb00101010FBBB111110AAAAAA. */ -+{ "mpywhkl", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhkl<.f> 0,limm,c 0011011001101010F111CCCCCC111110. */ -+{ "mpywhkl", 0x366A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkl<.f> 0,b,limm 00110bbb00101010FBBB111110111110. */ -+{ "mpywhkl", 0x302A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhkl<.f><.cc> b,b,limm 00110bbb11101010FBBB1111100QQQQQ. */ -+{ "mpywhkl", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f><.cc> 0,limm,c 0011011011101010F111CCCCCC0QQQQQ. */ -+{ "mpywhkl", 0x36EA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> a,limm,u6 0011011001101010F111uuuuuuAAAAAA. */ -+{ "mpywhkl", 0x366A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkl<.f> 0,limm,u6 0011011001101010F111uuuuuu111110. */ -+{ "mpywhkl", 0x366A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkl<.f><.cc> 0,limm,u6 0011011011101010F111uuuuuu1QQQQQ. */ -+{ "mpywhkl", 0x36EA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> 0,limm,s12 0011011010101010F111ssssssSSSSSS. */ -+{ "mpywhkl", 0x36AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhkl<.f> a,limm,limm 0011011000101010F111111110AAAAAA. */ -+{ "mpywhkl", 0x362A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhkl<.f> 0,limm,limm 0011011000101010F111111110111110. */ -+{ "mpywhkl", 0x362A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhkl<.f><.cc> 0,limm,limm 0011011011101010F1111111100QQQQQ. */ -+{ "mpywhkl", 0x36EA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> a,b,c 00110bbb00101011FBBBCCCCCCAAAAAA. */ -+{ "mpywhkul", 0x302B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkul<.f> 0,b,c 00110bbb00101011FBBBCCCCCC111110. */ -+{ "mpywhkul", 0x302B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> b,b,c 00110bbb11101011FBBBCCCCCC0QQQQQ. */ -+{ "mpywhkul", 0x30EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> a,b,u6 00110bbb01101011FBBBuuuuuuAAAAAA. */ -+{ "mpywhkul", 0x306B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkul<.f> 0,b,u6 00110bbb01101011FBBBuuuuuu111110. */ -+{ "mpywhkul", 0x306B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> b,b,u6 00110bbb11101011FBBBuuuuuu1QQQQQ. */ -+{ "mpywhkul", 0x30EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> b,b,s12 00110bbb10101011FBBBssssssSSSSSS. */ -+{ "mpywhkul", 0x30AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhkul<.f> a,limm,c 0011011000101011F111CCCCCCAAAAAA. */ -+{ "mpywhkul", 0x362B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkul<.f> a,b,limm 00110bbb00101011FBBB111110AAAAAA. */ -+{ "mpywhkul", 0x302B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhkul<.f> 0,limm,c 0011011001101011F111CCCCCC111110. */ -+{ "mpywhkul", 0x366B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkul<.f> 0,b,limm 00110bbb00101011FBBB111110111110. */ -+{ "mpywhkul", 0x302B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> b,b,limm 00110bbb11101011FBBB1111100QQQQQ. */ -+{ "mpywhkul", 0x30EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f><.cc> 0,limm,c 0011011011101011F111CCCCCC0QQQQQ. */ -+{ "mpywhkul", 0x36EB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> a,limm,u6 0011011001101011F111uuuuuuAAAAAA. */ -+{ "mpywhkul", 0x366B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkul<.f> 0,limm,u6 0011011001101011F111uuuuuu111110. */ -+{ "mpywhkul", 0x366B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> 0,limm,u6 0011011011101011F111uuuuuu1QQQQQ. */ -+{ "mpywhkul", 0x36EB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> 0,limm,s12 0011011010101011F111ssssssSSSSSS. */ -+{ "mpywhkul", 0x36AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhkul<.f> a,limm,limm 0011011000101011F111111110AAAAAA. */ -+{ "mpywhkul", 0x362B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhkul<.f> 0,limm,limm 0011011000101011F111111110111110. */ -+{ "mpywhkul", 0x362B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> 0,limm,limm 0011011011101011F1111111100QQQQQ. */ -+{ "mpywhkul", 0x36EB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhl<.f> a,b,c 00110bbb00011100FBBBCCCCCCAAAAAA. */ -+{ "mpywhl", 0x301C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhl<.f> 0,b,c 00110bbb00011100FBBBCCCCCC111110. */ -+{ "mpywhl", 0x301C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhl<.f><.cc> b,b,c 00110bbb11011100FBBBCCCCCC0QQQQQ. */ -+{ "mpywhl", 0x30DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhl<.f> a,b,u6 00110bbb01011100FBBBuuuuuuAAAAAA. */ -+{ "mpywhl", 0x305C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhl<.f> 0,b,u6 00110bbb01011100FBBBuuuuuu111110. */ -+{ "mpywhl", 0x305C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhl<.f><.cc> b,b,u6 00110bbb11011100FBBBuuuuuu1QQQQQ. */ -+{ "mpywhl", 0x30DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhl<.f> b,b,s12 00110bbb10011100FBBBssssssSSSSSS. */ -+{ "mpywhl", 0x309C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhl<.f> a,limm,c 0011011000011100F111CCCCCCAAAAAA. */ -+{ "mpywhl", 0x361C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhl<.f> a,b,limm 00110bbb00011100FBBB111110AAAAAA. */ -+{ "mpywhl", 0x301C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhl<.f> 0,limm,c 0011011000011100F111CCCCCC111110. */ -+{ "mpywhl", 0x361C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhl<.f> 0,b,limm 00110bbb00011100FBBB111110111110. */ -+{ "mpywhl", 0x301C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhl<.f><.cc> b,b,limm 00110bbb11011100FBBB1111100QQQQQ. */ -+{ "mpywhl", 0x30DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhl<.f><.cc> 0,limm,c 0011011011011100F111CCCCCC0QQQQQ. */ -+{ "mpywhl", 0x36DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhl<.f> a,limm,u6 0011011001011100F111uuuuuuAAAAAA. */ -+{ "mpywhl", 0x365C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhl<.f> 0,limm,u6 0011011001011100F111uuuuuu111110. */ -+{ "mpywhl", 0x365C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhl<.f><.cc> 0,limm,u6 0011011011011100F111uuuuuu1QQQQQ. */ -+{ "mpywhl", 0x36DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhl<.f> 0,limm,s12 0011011010011100F111ssssssSSSSSS. */ -+{ "mpywhl", 0x369C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhl<.f> a,limm,limm 0011011000011100F111111110AAAAAA. */ -+{ "mpywhl", 0x361C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhl<.f> 0,limm,limm 0011011000011100F111111110111110. */ -+{ "mpywhl", 0x361C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhl<.f><.cc> 0,limm,limm 0011011011011100F1111111100QQQQQ. */ -+{ "mpywhl", 0x36DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> a,b,c 00110bbb00011110FBBBCCCCCCAAAAAA. */ -+{ "mpywhul", 0x301E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhul<.f> 0,b,c 00110bbb00011110FBBBCCCCCC111110. */ -+{ "mpywhul", 0x301E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhul<.f><.cc> b,b,c 00110bbb11011110FBBBCCCCCC0QQQQQ. */ -+{ "mpywhul", 0x30DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> a,b,u6 00110bbb01011110FBBBuuuuuuAAAAAA. */ -+{ "mpywhul", 0x305E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhul<.f> 0,b,u6 00110bbb01011110FBBBuuuuuu111110. */ -+{ "mpywhul", 0x305E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhul<.f><.cc> b,b,u6 00110bbb11011110FBBBuuuuuu1QQQQQ. */ -+{ "mpywhul", 0x30DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> b,b,s12 00110bbb10011110FBBBssssssSSSSSS. */ -+{ "mpywhul", 0x309E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhul<.f> a,limm,c 0011011000011110F111CCCCCCAAAAAA. */ -+{ "mpywhul", 0x361E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhul<.f> a,b,limm 00110bbb00011110FBBB111110AAAAAA. */ -+{ "mpywhul", 0x301E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhul<.f> 0,limm,c 0011011000011110F111CCCCCC111110. */ -+{ "mpywhul", 0x361E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhul<.f> 0,b,limm 00110bbb00011110FBBB111110111110. */ -+{ "mpywhul", 0x301E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhul<.f><.cc> b,b,limm 00110bbb11011110FBBB1111100QQQQQ. */ -+{ "mpywhul", 0x30DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhul<.f><.cc> 0,limm,c 0011011011011110F111CCCCCC0QQQQQ. */ -+{ "mpywhul", 0x36DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> a,limm,u6 0011011001011110F111uuuuuuAAAAAA. */ -+{ "mpywhul", 0x365E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhul<.f> 0,limm,u6 0011011001011110F111uuuuuu111110. */ -+{ "mpywhul", 0x365E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhul<.f><.cc> 0,limm,u6 0011011011011110F111uuuuuu1QQQQQ. */ -+{ "mpywhul", 0x36DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> 0,limm,s12 0011011010011110F111ssssssSSSSSS. */ -+{ "mpywhul", 0x369E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhul<.f> a,limm,limm 0011011000011110F111111110AAAAAA. */ -+{ "mpywhul", 0x361E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhul<.f> 0,limm,limm 0011011000011110F111111110111110. */ -+{ "mpywhul", 0x361E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhul<.f><.cc> 0,limm,limm 0011011011011110F1111111100QQQQQ. */ -+{ "mpywhul", 0x36DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyw_s b,b,c 01111bbbccc01001. */ -+{ "mpyw_s", 0x00007809, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY1E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* mpy_s b,b,c 01111bbbccc01100. */ -+{ "mpy_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY6E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* msubdf<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA. */ -+{ "msubdf", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubdf<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110. */ -+{ "msubdf", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubdf<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ. */ -+{ "msubdf", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubdf<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA. */ -+{ "msubdf", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdf<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110. */ -+{ "msubdf", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdf<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ. */ -+{ "msubdf", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubdf<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS. */ -+{ "msubdf", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubdf<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA. */ -+{ "msubdf", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubdf<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA. */ -+{ "msubdf", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubdf<.f> 0,limm,c 0011011000010101F111CCCCCC111110. */ -+{ "msubdf", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubdf<.f> 0,b,limm 00110bbb00010101FBBB111110111110. */ -+{ "msubdf", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubdf<.f><.cc> b,b,limm 00110bbb11010101FBBB1111100QQQQQ. */ -+{ "msubdf", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubdf<.f><.cc> 0,limm,c 0011011011010101F111CCCCCC0QQQQQ. */ -+{ "msubdf", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubdf<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA. */ -+{ "msubdf", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdf<.f> 0,limm,u6 0011011001010101F111uuuuuu111110. */ -+{ "msubdf", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdf<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ. */ -+{ "msubdf", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubdf<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS. */ -+{ "msubdf", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubdf<.f> a,limm,limm 0011011000010101F111111110AAAAAA. */ -+{ "msubdf", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubdf<.f> 0,limm,limm 0011011000010101F111111110111110. */ -+{ "msubdf", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubdf<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ. */ -+{ "msubdf", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubf<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA. */ -+{ "msubf", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubf<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110. */ -+{ "msubf", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubf<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ. */ -+{ "msubf", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubf<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA. */ -+{ "msubf", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubf<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110. */ -+{ "msubf", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubf<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ. */ -+{ "msubf", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubf<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS. */ -+{ "msubf", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubf<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA. */ -+{ "msubf", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubf<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA. */ -+{ "msubf", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubf<.f> 0,limm,c 0011011000001110F111CCCCCC111110. */ -+{ "msubf", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubf<.f> 0,b,limm 00110bbb00001110FBBB111110111110. */ -+{ "msubf", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubf<.f><.cc> b,b,limm 00110bbb11001110FBBB1111100QQQQQ. */ -+{ "msubf", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubf<.f><.cc> 0,limm,c 0011011011001110F111CCCCCC0QQQQQ. */ -+{ "msubf", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubf<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA. */ -+{ "msubf", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubf<.f> 0,limm,u6 0011011001001110F111uuuuuu111110. */ -+{ "msubf", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubf<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ. */ -+{ "msubf", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubf<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS. */ -+{ "msubf", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubf<.f> a,limm,limm 0011011000001110F111111110AAAAAA. */ -+{ "msubf", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubf<.f> 0,limm,limm 0011011000001110F111111110111110. */ -+{ "msubf", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubf<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ. */ -+{ "msubf", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubfr<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA. */ -+{ "msubfr", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubfr<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110. */ -+{ "msubfr", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubfr<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ. */ -+{ "msubfr", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubfr<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA. */ -+{ "msubfr", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubfr<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110. */ -+{ "msubfr", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubfr<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ. */ -+{ "msubfr", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubfr<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS. */ -+{ "msubfr", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubfr<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA. */ -+{ "msubfr", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubfr<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA. */ -+{ "msubfr", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubfr<.f> 0,limm,c 0011011000001111F111CCCCCC111110. */ -+{ "msubfr", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubfr<.f> 0,b,limm 00110bbb00001111FBBB111110111110. */ -+{ "msubfr", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubfr<.f><.cc> b,b,limm 00110bbb11001111FBBB1111100QQQQQ. */ -+{ "msubfr", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubfr<.f><.cc> 0,limm,c 0011011011001111F111CCCCCC0QQQQQ. */ -+{ "msubfr", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubfr<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA. */ -+{ "msubfr", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubfr<.f> 0,limm,u6 0011011001001111F111uuuuuu111110. */ -+{ "msubfr", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubfr<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ. */ -+{ "msubfr", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubfr<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS. */ -+{ "msubfr", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubfr<.f> a,limm,limm 0011011000001111F111111110AAAAAA. */ -+{ "msubfr", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubfr<.f> 0,limm,limm 0011011000001111F111111110111110. */ -+{ "msubfr", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubfr<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ. */ -+{ "msubfr", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> a,b,c 00110bbb00010100FBBBCCCCCCAAAAAA. */ -+{ "msubwhfl", 0x30140000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfl<.f> 0,b,c 00110bbb00010100FBBBCCCCCC111110. */ -+{ "msubwhfl", 0x3014003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> b,b,c 00110bbb11010100FBBBCCCCCC0QQQQQ. */ -+{ "msubwhfl", 0x30D40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> a,b,u6 00110bbb01010100FBBBuuuuuuAAAAAA. */ -+{ "msubwhfl", 0x30540000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfl<.f> 0,b,u6 00110bbb01010100FBBBuuuuuu111110. */ -+{ "msubwhfl", 0x3054003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> b,b,u6 00110bbb11010100FBBBuuuuuu1QQQQQ. */ -+{ "msubwhfl", 0x30D40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> b,b,s12 00110bbb10010100FBBBssssssSSSSSS. */ -+{ "msubwhfl", 0x30940000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfl<.f> a,limm,c 0011011000010100F111CCCCCCAAAAAA. */ -+{ "msubwhfl", 0x36147000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfl<.f> a,b,limm 00110bbb00010100FBBB111110AAAAAA. */ -+{ "msubwhfl", 0x30140F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfl<.f> 0,limm,c 0011011000010100F111CCCCCC111110. */ -+{ "msubwhfl", 0x3614703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfl<.f> 0,b,limm 00110bbb00010100FBBB111110111110. */ -+{ "msubwhfl", 0x30140FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> b,b,limm 00110bbb11010100FBBB1111100QQQQQ. */ -+{ "msubwhfl", 0x30D40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f><.cc> 0,limm,c 0011011011010100F111CCCCCC0QQQQQ. */ -+{ "msubwhfl", 0x36D47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> a,limm,u6 0011011001010100F111uuuuuuAAAAAA. */ -+{ "msubwhfl", 0x36547000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfl<.f> 0,limm,u6 0011011001010100F111uuuuuu111110. */ -+{ "msubwhfl", 0x3654703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> 0,limm,u6 0011011011010100F111uuuuuu1QQQQQ. */ -+{ "msubwhfl", 0x36D47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> 0,limm,s12 0011011010010100F111ssssssSSSSSS. */ -+{ "msubwhfl", 0x36947000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfl<.f> a,limm,limm 0011011000010100F111111110AAAAAA. */ -+{ "msubwhfl", 0x36147F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfl<.f> 0,limm,limm 0011011000010100F111111110111110. */ -+{ "msubwhfl", 0x36147FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> 0,limm,limm 0011011011010100F1111111100QQQQQ. */ -+{ "msubwhfl", 0x36D47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> a,b,c 00110bbb00011010FBBBCCCCCCAAAAAA. */ -+{ "msubwhflr", 0x301A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhflr<.f> 0,b,c 00110bbb00011010FBBBCCCCCC111110. */ -+{ "msubwhflr", 0x301A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> b,b,c 00110bbb11011010FBBBCCCCCC0QQQQQ. */ -+{ "msubwhflr", 0x30DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> a,b,u6 00110bbb01011010FBBBuuuuuuAAAAAA. */ -+{ "msubwhflr", 0x305A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhflr<.f> 0,b,u6 00110bbb01011010FBBBuuuuuu111110. */ -+{ "msubwhflr", 0x305A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> b,b,u6 00110bbb11011010FBBBuuuuuu1QQQQQ. */ -+{ "msubwhflr", 0x30DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> b,b,s12 00110bbb10011010FBBBssssssSSSSSS. */ -+{ "msubwhflr", 0x309A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhflr<.f> a,limm,c 0011011000011010F111CCCCCCAAAAAA. */ -+{ "msubwhflr", 0x361A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhflr<.f> a,b,limm 00110bbb00011010FBBB111110AAAAAA. */ -+{ "msubwhflr", 0x301A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhflr<.f> 0,limm,c 0011011000011010F111CCCCCC111110. */ -+{ "msubwhflr", 0x361A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhflr<.f> 0,b,limm 00110bbb00011010FBBB111110111110. */ -+{ "msubwhflr", 0x301A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> b,b,limm 00110bbb11011010FBBB1111100QQQQQ. */ -+{ "msubwhflr", 0x30DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f><.cc> 0,limm,c 0011011011011010F111CCCCCC0QQQQQ. */ -+{ "msubwhflr", 0x36DA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> a,limm,u6 0011011001011010F111uuuuuuAAAAAA. */ -+{ "msubwhflr", 0x365A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhflr<.f> 0,limm,u6 0011011001011010F111uuuuuu111110. */ -+{ "msubwhflr", 0x365A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> 0,limm,u6 0011011011011010F111uuuuuu1QQQQQ. */ -+{ "msubwhflr", 0x36DA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> 0,limm,s12 0011011010011010F111ssssssSSSSSS. */ -+{ "msubwhflr", 0x369A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhflr<.f> a,limm,limm 0011011000011010F111111110AAAAAA. */ -+{ "msubwhflr", 0x361A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhflr<.f> 0,limm,limm 0011011000011010F111111110111110. */ -+{ "msubwhflr", 0x361A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> 0,limm,limm 0011011011011010F1111111100QQQQQ. */ -+{ "msubwhflr", 0x36DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> a,b,c 00110bbb00101100FBBBCCCCCCAAAAAA. */ -+{ "msubwhfm", 0x302C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfm<.f> 0,b,c 00110bbb00101100FBBBCCCCCC111110. */ -+{ "msubwhfm", 0x302C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> b,b,c 00110bbb11101100FBBBCCCCCC0QQQQQ. */ -+{ "msubwhfm", 0x30EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> a,b,u6 00110bbb01101100FBBBuuuuuuAAAAAA. */ -+{ "msubwhfm", 0x306C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfm<.f> 0,b,u6 00110bbb01101100FBBBuuuuuu111110. */ -+{ "msubwhfm", 0x306C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> b,b,u6 00110bbb11101100FBBBuuuuuu1QQQQQ. */ -+{ "msubwhfm", 0x30EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> b,b,s12 00110bbb10101100FBBBssssssSSSSSS. */ -+{ "msubwhfm", 0x30AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfm<.f> a,limm,c 0011011000101100F111CCCCCCAAAAAA. */ -+{ "msubwhfm", 0x362C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfm<.f> a,b,limm 00110bbb00101100FBBB111110AAAAAA. */ -+{ "msubwhfm", 0x302C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfm<.f> 0,limm,c 0011011001101100F111CCCCCC111110. */ -+{ "msubwhfm", 0x366C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfm<.f> 0,b,limm 00110bbb00101100FBBB111110111110. */ -+{ "msubwhfm", 0x302C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> b,b,limm 00110bbb11101100FBBB1111100QQQQQ. */ -+{ "msubwhfm", 0x30EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f><.cc> 0,limm,c 0011011011101100F111CCCCCC0QQQQQ. */ -+{ "msubwhfm", 0x36EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> a,limm,u6 0011011001101100F111uuuuuuAAAAAA. */ -+{ "msubwhfm", 0x366C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfm<.f> 0,limm,u6 0011011001101100F111uuuuuu111110. */ -+{ "msubwhfm", 0x366C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> 0,limm,u6 0011011011101100F111uuuuuu1QQQQQ. */ -+{ "msubwhfm", 0x36EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> 0,limm,s12 0011011010101100F111ssssssSSSSSS. */ -+{ "msubwhfm", 0x36AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfm<.f> a,limm,limm 0011011000101100F111111110AAAAAA. */ -+{ "msubwhfm", 0x362C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfm<.f> 0,limm,limm 0011011000101100F111111110111110. */ -+{ "msubwhfm", 0x362C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> 0,limm,limm 0011011011101100F1111111100QQQQQ. */ -+{ "msubwhfm", 0x36EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> a,b,c 00110bbb00101101FBBBCCCCCCAAAAAA. */ -+{ "msubwhfmr", 0x302D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,b,c 00110bbb00101101FBBBCCCCCC111110. */ -+{ "msubwhfmr", 0x302D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> b,b,c 00110bbb11101101FBBBCCCCCC0QQQQQ. */ -+{ "msubwhfmr", 0x30ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> a,b,u6 00110bbb01101101FBBBuuuuuuAAAAAA. */ -+{ "msubwhfmr", 0x306D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,b,u6 00110bbb01101101FBBBuuuuuu111110. */ -+{ "msubwhfmr", 0x306D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> b,b,u6 00110bbb11101101FBBBuuuuuu1QQQQQ. */ -+{ "msubwhfmr", 0x30ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> b,b,s12 00110bbb10101101FBBBssssssSSSSSS. */ -+{ "msubwhfmr", 0x30AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfmr<.f> a,limm,c 0011011000101101F111CCCCCCAAAAAA. */ -+{ "msubwhfmr", 0x362D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfmr<.f> a,b,limm 00110bbb00101101FBBB111110AAAAAA. */ -+{ "msubwhfmr", 0x302D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,limm,c 0011011001101101F111CCCCCC111110. */ -+{ "msubwhfmr", 0x366D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,b,limm 00110bbb00101101FBBB111110111110. */ -+{ "msubwhfmr", 0x302D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> b,b,limm 00110bbb11101101FBBB1111100QQQQQ. */ -+{ "msubwhfmr", 0x30ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f><.cc> 0,limm,c 0011011011101101F111CCCCCC0QQQQQ. */ -+{ "msubwhfmr", 0x36ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> a,limm,u6 0011011001101101F111uuuuuuAAAAAA. */ -+{ "msubwhfmr", 0x366D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,limm,u6 0011011001101101F111uuuuuu111110. */ -+{ "msubwhfmr", 0x366D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> 0,limm,u6 0011011011101101F111uuuuuu1QQQQQ. */ -+{ "msubwhfmr", 0x36ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> 0,limm,s12 0011011010101101F111ssssssSSSSSS. */ -+{ "msubwhfmr", 0x36AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfmr<.f> a,limm,limm 0011011000101101F111111110AAAAAA. */ -+{ "msubwhfmr", 0x362D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,limm,limm 0011011000101101F111111110111110. */ -+{ "msubwhfmr", 0x362D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> 0,limm,limm 0011011011101101F1111111100QQQQQ. */ -+{ "msubwhfmr", 0x36ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* neg<.f> a,b 00100bbb01001110FBBB000000AAAAAA. */ -+{ "neg", 0x204E0000, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB }, { C_F }}, -+ -+/* neg<.f><.cc> b,b 00100bbb11001110FBBB0000001QQQQQ. */ -+{ "neg", 0x20CE0020, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup }, { C_F, C_CC }}, -+ -+/* neg<.f> a,limm 0010011001001110F111000000AAAAAA. */ -+{ "neg", 0x264E7000, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM }, { C_F }}, -+ -+/* neg<.f><.cc> 0,limm 0010011011001110F1110000001QQQQQ. */ -+{ "neg", 0x26CE7020, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* negs<.f> b,c 00101bbb00101111FBBBCCCCCC000111. */ -+{ "negs", 0x282F0007, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* negs<.f> 0,c 0010111000101111F111CCCCCC000111. */ -+{ "negs", 0x2E2F7007, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* negs<.f> b,u6 00101bbb01101111FBBBuuuuuu000111. */ -+{ "negs", 0x286F0007, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negs<.f> 0,u6 0010111001101111F111uuuuuu000111. */ -+{ "negs", 0x2E6F7007, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negs<.f> b,limm 00101bbb00101111FBBB111110000111. */ -+{ "negs", 0x282F0F87, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* negs<.f> 0,limm 0010111000101111F111111110000111. */ -+{ "negs", 0x2E2F7F87, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* negsh<.f> b,c 00101bbb00101111FBBBCCCCCC000110. */ -+{ "negsh", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* negsh<.f> 0,c 0010111000101111F111CCCCCC000110. */ -+{ "negsh", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* negsh<.f> b,u6 00101bbb01101111FBBBuuuuuu000110. */ -+{ "negsh", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negsh<.f> 0,u6 0010111001101111F111uuuuuu000110. */ -+{ "negsh", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negsh<.f> b,limm 00101bbb00101111FBBB111110000110. */ -+{ "negsh", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* negsh<.f> 0,limm 0010111000101111F111111110000110. */ -+{ "negsh", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* neg_s b,c 01111bbbccc10011. */ -+{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* nop_s 0111100011100000. */ -+{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001. */ -+{ "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* norm<.f> 0,c 0010111000101111F111CCCCCC000001. */ -+{ "norm", 0x2E2F7001, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* norm<.f> b,u6 00101bbb01101111FBBBuuuuuu000001. */ -+{ "norm", 0x286F0001, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* norm<.f> 0,u6 0010111001101111F111uuuuuu000001. */ -+{ "norm", 0x2E6F7001, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* norm<.f> b,limm 00101bbb00101111FBBB111110000001. */ -+{ "norm", 0x282F0F81, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* norm<.f> 0,limm 0010111000101111F111111110000001. */ -+{ "norm", 0x2E2F7F81, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* normacc b,c 00101bbb001011110BBBCCCCCC011001. */ -+{ "normacc", 0x282F0019, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* normacc 0,c 00101110001011110111CCCCCC011001. */ -+{ "normacc", 0x2E2F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* normacc b,u6 00101bbb011011110BBBuuuuuu011001. */ -+{ "normacc", 0x286F0019, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* normacc 0,u6 00101110011011110111uuuuuu011001. */ -+{ "normacc", 0x2E6F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* normacc b,limm 00101bbb001011110BBB111110011001. */ -+{ "normacc", 0x282F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* normacc 0,limm 00101110001011110111111110011001. */ -+{ "normacc", 0x2E2F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* normh<.f> b,c 00101bbb00101111FBBBCCCCCC001000. */ -+{ "normh", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* normh<.f> 0,c 0010111000101111F111CCCCCC001000. */ -+{ "normh", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* normh<.f> b,u6 00101bbb01101111FBBBuuuuuu001000. */ -+{ "normh", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* normh<.f> 0,u6 0010111001101111F111uuuuuu001000. */ -+{ "normh", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* normh<.f> b,limm 00101bbb00101111FBBB111110001000. */ -+{ "normh", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* normh<.f> 0,limm 0010111000101111F111111110001000. */ -+{ "normh", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* norml<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc100001. */ -+{ "norml", 0x582F0021, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* norml<.f> 0,RC 0101111000101111F111cccccc100001. */ -+{ "norml", 0x5E2F7021, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* norml<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu100001. */ -+{ "norml", 0x586F0021, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* norml<.f> 0,u6 0101111001101111F111uuuuuu100001. */ -+{ "norml", 0x5E6F7021, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* norml<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100100001. */ -+{ "norml", 0x582F0F21, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* norml<.f> 0,ximm 0101111000101111F111111100100001. */ -+{ "norml", 0x5E2F7F21, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* norml<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110100001. */ -+{ "norml", 0x582F0FA1, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* norml<.f> 0,limm 0101111000101111F111111110100001. */ -+{ "norml", 0x5E2F7FA1, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* not<.f> b,c 00100bbb00101111FBBBCCCCCC001010. */ -+{ "not", 0x202F000A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* not<.f> 0,c 0010011000101111F111CCCCCC001010. */ -+{ "not", 0x262F700A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* not<.f> b,u6 00100bbb01101111FBBBuuuuuu001010. */ -+{ "not", 0x206F000A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* not<.f> 0,u6 0010011001101111F111uuuuuu001010. */ -+{ "not", 0x266F700A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* not<.f> b,limm 00100bbb00101111FBBB111110001010. */ -+{ "not", 0x202F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* not<.f> 0,limm 0010011000101111F111111110001010. */ -+{ "not", 0x262F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* notl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc001010. */ -+{ "notl", 0x582F000A, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* notl<.f> 0,RC 0101111000101111F111cccccc001010. */ -+{ "notl", 0x5E2F700A, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* notl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu001010. */ -+{ "notl", 0x586F000A, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* notl<.f> 0,u6 0101111001101111F111uuuuuu001010. */ -+{ "notl", 0x5E6F700A, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* notl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100001010. */ -+{ "notl", 0x582F0F0A, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* notl<.f> 0,ximm 0101111000101111F111111100001010. */ -+{ "notl", 0x5E2F7F0A, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* notl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110001010. */ -+{ "notl", 0x582F0F8A, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* notl<.f> 0,limm 0101111000101111F111111110001010. */ -+{ "notl", 0x5E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* not_s b,c 01111bbbccc10010. */ -+{ "not_s", 0x00007812, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* or<.f> a,b,c 00100bbb00000101FBBBCCCCCCAAAAAA. */ -+{ "or", 0x20050000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* or<.f> 0,b,c 00100bbb00000101FBBBCCCCCC111110. */ -+{ "or", 0x2005003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* or<.f><.cc> b,b,c 00100bbb11000101FBBBCCCCCC0QQQQQ. */ -+{ "or", 0x20C50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* or<.f> a,b,u6 00100bbb01000101FBBBuuuuuuAAAAAA. */ -+{ "or", 0x20450000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* or<.f> 0,b,u6 00100bbb01000101FBBBuuuuuu111110. */ -+{ "or", 0x2045003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* or<.f><.cc> b,b,u6 00100bbb11000101FBBBuuuuuu1QQQQQ. */ -+{ "or", 0x20C50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* or<.f> b,b,s12 00100bbb10000101FBBBssssssSSSSSS. */ -+{ "or", 0x20850000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* or<.f> a,limm,c 0010011000000101F111CCCCCCAAAAAA. */ -+{ "or", 0x26057000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* or<.f> a,b,limm 00100bbb00000101FBBB111110AAAAAA. */ -+{ "or", 0x20050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* or<.f> 0,limm,c 0010011000000101F111CCCCCC111110. */ -+{ "or", 0x2605703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* or<.f> 0,b,limm 00100bbb00000101FBBB111110111110. */ -+{ "or", 0x20050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* or<.f><.cc> b,b,limm 00100bbb11000101FBBB1111100QQQQQ. */ -+{ "or", 0x20C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* or<.f><.cc> 0,limm,c 0010011011000101F111CCCCCC0QQQQQ. */ -+{ "or", 0x26C57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* or<.f> a,limm,u6 0010011001000101F111uuuuuuAAAAAA. */ -+{ "or", 0x26457000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* or<.f> 0,limm,u6 0010011001000101F111uuuuuu111110. */ -+{ "or", 0x2645703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* or<.f><.cc> 0,limm,u6 0010011011000101F111uuuuuu1QQQQQ. */ -+{ "or", 0x26C57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* or<.f> 0,limm,s12 0010011010000101F111ssssssSSSSSS. */ -+{ "or", 0x26857000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* or<.f> a,limm,limm 0010011000000101F111111110AAAAAA. */ -+{ "or", 0x26057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* or<.f> 0,limm,limm 0010011000000101F111111110111110. */ -+{ "or", 0x26057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* or<.f><.cc> 0,limm,limm 0010011011000101F1111111100QQQQQ. */ -+{ "or", 0x26C57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* orl<.f> OPERAND_RA,RB,RC 01011bbb00000101FBBBccccccaaaaaa. */ -+{ "orl", 0x58050000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* orl<.f> 0,RB,RC 01011bbb00000101FBBBcccccc111110. */ -+{ "orl", 0x5805003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* orl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11000101FBBBcccccc0QQQQQ. */ -+{ "orl", 0x58C50000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* orl<.f> OPERAND_RA,RB,u6 01011bbb01000101FBBBuuuuuuaaaaaa. */ -+{ "orl", 0x58450000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* orl<.f> 0,RB,u6 01011bbb01000101FBBBuuuuuu111110. */ -+{ "orl", 0x5845003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* orl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11000101FBBBuuuuuu1QQQQQ. */ -+{ "orl", 0x58C50020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* orl<.f> OPERAND_RB,RB,s12 01011bbb10000101FBBBssssssSSSSSS. */ -+{ "orl", 0x58850000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* orl<.f> OPERAND_RA,ximm,RC 0101110000000101F111ccccccaaaaaa. */ -+{ "orl", 0x5C057000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* orl<.f> OPERAND_RA,RB,ximm 01011bbb00000101FBBB111100aaaaaa. */ -+{ "orl", 0x58050F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* orl<.f> 0,ximm,RC 0101110000000101F111cccccc111110. */ -+{ "orl", 0x5C05703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* orl<.f> 0,RB,ximm 01011bbb00000101FBBB111100111110. */ -+{ "orl", 0x58050F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* orl<.f><.cc> 0,ximm,RC 0101110011000101F111cccccc0QQQQQ. */ -+{ "orl", 0x5CC57000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* orl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11000101FBBB1111000QQQQQ. */ -+{ "orl", 0x58C50F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* orl<.f> OPERAND_RA,ximm,u6 0101110001000101F111uuuuuuaaaaaa. */ -+{ "orl", 0x5C457000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* orl<.f> 0,ximm,u6 0101110001000101F111uuuuuu111110. */ -+{ "orl", 0x5C45703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* orl<.f><.cc> 0,ximm,u6 0101110011000101F111uuuuuu1QQQQQ. */ -+{ "orl", 0x5CC57020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* orl<.f> OPERAND_RA,limm,RC 0101111000000101F111ccccccaaaaaa. */ -+{ "orl", 0x5E057000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* orl<.f> OPERAND_RA,RB,limm 01011bbb00000101FBBB111110aaaaaa. */ -+{ "orl", 0x58050F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* orl<.f> 0,limm,RC 0101111000000101F111cccccc111110. */ -+{ "orl", 0x5E05703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* orl<.f> 0,RB,limm 01011bbb00000101FBBB111110111110. */ -+{ "orl", 0x58050FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* orl<.f><.cc> 0,limm,RC 0101111011000101F111cccccc0QQQQQ. */ -+{ "orl", 0x5EC57000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* orl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11000101FBBB1111100QQQQQ. */ -+{ "orl", 0x58C50F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* orl<.f> OPERAND_RA,limm,u6 0101111001000101F111uuuuuuaaaaaa. */ -+{ "orl", 0x5E457000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* orl<.f> 0,limm,u6 0101111001000101F111uuuuuu111110. */ -+{ "orl", 0x5E45703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* orl<.f><.cc> 0,limm,u6 0101111011000101F111uuuuuu1QQQQQ. */ -+{ "orl", 0x5EC57020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* orl<.f> 0,ximm,s12 0101110010000101F111ssssssSSSSSS. */ -+{ "orl", 0x5C857000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* orl<.f> 0,limm,s12 0101111010000101F111ssssssSSSSSS. */ -+{ "orl", 0x5E857000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* orl<.f> OPERAND_RA,ximm,ximm 0101110000000101F111111100aaaaaa. */ -+{ "orl", 0x5C057F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* orl<.f> 0,ximm,ximm 0101110000000101F111111100111110. */ -+{ "orl", 0x5C057F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* orl<.f><.cc> 0,ximm,ximm 0101110011000101F1111111000QQQQQ. */ -+{ "orl", 0x5CC57F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* orl<.f> OPERAND_RA,limm,limm 0101111000000101F111111110aaaaaa. */ -+{ "orl", 0x5E057F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* orl<.f> 0,limm,limm 0101111000000101F111111110111110. */ -+{ "orl", 0x5E057FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* orl<.f><.cc> 0,limm,limm 0101111011000101F1111111100QQQQQ. */ -+{ "orl", 0x5EC57F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* orl_s b,b,c 01111bbbccc10111. */ -+{ "orl_s", 0x00007817, 0x0000F81F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* orl_s h,h,ximm 01110000hhh110HH. */ -+{ "orl_s", 0x00007018, 0x0000FF1C, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RH_S, OPERAND_RH_Sdup, OPERAND_LO32 }, { 0 }}, -+ -+/* orl_s h,PCL,ximm 01110010hhh110HH. */ -+{ "orl_s", 0x00007218, 0x0000FF1C, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RH_S, OPERAND_PCL_S, OPERAND_LO32 }, { 0 }}, -+ -+/* or_s b,b,c 01111bbbccc00101. */ -+{ "or_s", 0x00007805, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* popdl_s b 11000bbb1101BBB1. */ -+{ "popdl_s", 0x0000C0D1, 0x0000F8F1, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RBB_S }, { 0 }}, -+ -+/* popl_s b 11000bbb1100BBB1. */ -+{ "popl_s", 0x0000C0C1, 0x0000F8F1, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RBB_S }, { 0 }}, -+ -+/* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110. */ -+{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110. */ -+{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, -+ -+/* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110. */ -+{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prealloc limm,c 00100110RR1100010111CCCCCC111110. */ -+{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prealloc limm 000101100000000001110RR001111110. */ -+{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prealloc limm,s9 00010110ssssssssS1110RR001111110. */ -+{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110. */ -+{ "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prefetch<.aa> b,s9 00010bbbssssssssSBBB0aa000111110. */ -+{ "prefetch", 0x1000003E, 0xF80009FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, -+ -+/* prefetch<.aa> b,limm 00100bbbaa1100000BBB111110111110. */ -+{ "prefetch", 0x20300FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prefetch limm,c 00100110RR1100000111CCCCCC111110. */ -+{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetch limm 000101100000000001110RR000111110. */ -+{ "prefetch", 0x1600703E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetch limm,s9 00010110ssssssssS1110RR000111110. */ -+{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetchw<.aa> b,c 00100bbbaa1100001BBBCCCCCC111110. */ -+{ "prefetchw", 0x2030803E, 0xF83F803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prefetchw<.aa> b,s9 00010bbbssssssssSBBB1aa000111110. */ -+{ "prefetchw", 0x1000083E, 0xF80009FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, -+ -+/* prefetchw<.aa> b,limm 00100bbbaa1100001BBB111110111110. */ -+{ "prefetchw", 0x20308FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prefetchw limm,c 00100110RR1100001111CCCCCC111110. */ -+{ "prefetchw", 0x2630F03E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetchw limm 000101100000000001111RR000111110. */ -+{ "prefetchw", 0x1600783E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetchw limm,s9 00010110ssssssssS1111RR000111110. */ -+{ "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* pushdl_s b 11000bbb1111BBB1. */ -+{ "pushdl_s", 0x0000C0F1, 0x0000F8F1, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RBB_S }, { 0 }}, -+ -+/* pushl_s b 11000bbb1110BBB1. */ -+{ "pushl_s", 0x0000C0E1, 0x0000F8F1, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RBB_S }, { 0 }}, -+ -+/* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */ -+{ "qmach", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmach<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110. */ -+{ "qmach", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmach<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ. */ -+{ "qmach", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmach<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA. */ -+{ "qmach", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmach<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110. */ -+{ "qmach", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmach<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ. */ -+{ "qmach", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmach<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS. */ -+{ "qmach", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmach<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA. */ -+{ "qmach", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmach<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA. */ -+{ "qmach", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmach<.f> 0,limm,c 0010111000110100F111CCCCCC111110. */ -+{ "qmach", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmach<.f> 0,b,limm 00101bbb00110100FBBB111110111110. */ -+{ "qmach", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmach<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ. */ -+{ "qmach", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmach<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ. */ -+{ "qmach", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmach<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA. */ -+{ "qmach", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmach<.f> 0,limm,u6 0010111001110100F111uuuuuu111110. */ -+{ "qmach", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmach<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ. */ -+{ "qmach", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmach<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS. */ -+{ "qmach", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmach<.f> a,limm,limm 0010111000110100F111111110AAAAAA. */ -+{ "qmach", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmach<.f> 0,limm,limm 0010111000110100F111111110111110. */ -+{ "qmach", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmach<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ. */ -+{ "qmach", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmachf<.f> a,b,c 00110bbb00110101FBBBCCCCCCAAAAAA. */ -+{ "qmachf", 0x30350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmachf<.f> 0,b,c 00110bbb00110101FBBBCCCCCC111110. */ -+{ "qmachf", 0x3035003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmachf<.f><.cc> b,b,c 00110bbb11110101FBBBCCCCCC0QQQQQ. */ -+{ "qmachf", 0x30F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmachf<.f> a,b,u6 00110bbb01110101FBBBuuuuuuAAAAAA. */ -+{ "qmachf", 0x30750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachf<.f> 0,b,u6 00110bbb01110101FBBBuuuuuu111110. */ -+{ "qmachf", 0x3075003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachf<.f><.cc> b,b,u6 00110bbb11110101FBBBuuuuuu1QQQQQ. */ -+{ "qmachf", 0x30F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmachf<.f> b,b,s12 00110bbb10110101FBBBssssssSSSSSS. */ -+{ "qmachf", 0x30B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmachf<.f> a,limm,c 0011011000110101F111CCCCCCAAAAAA. */ -+{ "qmachf", 0x36357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmachf<.f> a,b,limm 00110bbb00110101FBBB111110AAAAAA. */ -+{ "qmachf", 0x30350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmachf<.f> 0,limm,c 0011011000110101F111CCCCCC111110. */ -+{ "qmachf", 0x3635703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmachf<.f> 0,b,limm 00110bbb00110101FBBB111110111110. */ -+{ "qmachf", 0x30350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmachf<.f><.cc> b,b,limm 00110bbb11110101FBBB1111100QQQQQ. */ -+{ "qmachf", 0x30F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmachf<.f><.cc> 0,limm,c 0011011011110101F111CCCCCC0QQQQQ. */ -+{ "qmachf", 0x36F57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmachf<.f> a,limm,u6 0011011001110101F111uuuuuuAAAAAA. */ -+{ "qmachf", 0x36757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachf<.f> 0,limm,u6 0011011001110101F111uuuuuu111110. */ -+{ "qmachf", 0x3675703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachf<.f><.cc> 0,limm,u6 0011011011110101F111uuuuuu1QQQQQ. */ -+{ "qmachf", 0x36F57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmachf<.f> 0,limm,s12 0011011010110101F111ssssssSSSSSS. */ -+{ "qmachf", 0x36B57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmachf<.f> a,limm,limm 0011011000110101F111111110AAAAAA. */ -+{ "qmachf", 0x36357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmachf<.f> 0,limm,limm 0011011000110101F111111110111110. */ -+{ "qmachf", 0x36357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmachf<.f><.cc> 0,limm,limm 0011011011110101F1111111100QQQQQ. */ -+{ "qmachf", 0x36F57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmachu<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA. */ -+{ "qmachu", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmachu<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110. */ -+{ "qmachu", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmachu<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ. */ -+{ "qmachu", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmachu<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA. */ -+{ "qmachu", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachu<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110. */ -+{ "qmachu", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachu<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ. */ -+{ "qmachu", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmachu<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS. */ -+{ "qmachu", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmachu<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA. */ -+{ "qmachu", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmachu<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA. */ -+{ "qmachu", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmachu<.f> 0,limm,c 0010111000110101F111CCCCCC111110. */ -+{ "qmachu", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmachu<.f> 0,b,limm 00101bbb00110101FBBB111110111110. */ -+{ "qmachu", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmachu<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ. */ -+{ "qmachu", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmachu<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ. */ -+{ "qmachu", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmachu<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA. */ -+{ "qmachu", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachu<.f> 0,limm,u6 0010111001110101F111uuuuuu111110. */ -+{ "qmachu", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachu<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ. */ -+{ "qmachu", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmachu<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS. */ -+{ "qmachu", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmachu<.f> a,limm,limm 0010111000110101F111111110AAAAAA. */ -+{ "qmachu", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmachu<.f> 0,limm,limm 0010111000110101F111111110111110. */ -+{ "qmachu", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmachu<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ. */ -+{ "qmachu", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA. */ -+{ "qmpyh", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyh<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110. */ -+{ "qmpyh", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyh<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ. */ -+{ "qmpyh", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA. */ -+{ "qmpyh", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyh<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110. */ -+{ "qmpyh", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyh<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ. */ -+{ "qmpyh", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS. */ -+{ "qmpyh", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyh<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA. */ -+{ "qmpyh", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyh<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA. */ -+{ "qmpyh", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyh<.f> 0,limm,c 0010111000110000F111CCCCCC111110. */ -+{ "qmpyh", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyh<.f> 0,b,limm 00101bbb00110000FBBB111110111110. */ -+{ "qmpyh", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyh<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ. */ -+{ "qmpyh", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmpyh<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ. */ -+{ "qmpyh", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA. */ -+{ "qmpyh", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyh<.f> 0,limm,u6 0010111001110000F111uuuuuu111110. */ -+{ "qmpyh", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyh<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ. */ -+{ "qmpyh", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS. */ -+{ "qmpyh", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyh<.f> a,limm,limm 0010111000110000F111111110AAAAAA. */ -+{ "qmpyh", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyh<.f> 0,limm,limm 0010111000110000F111111110111110. */ -+{ "qmpyh", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyh<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ. */ -+{ "qmpyh", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> a,b,c 00110bbb00110001FBBBCCCCCCAAAAAA. */ -+{ "qmpyhf", 0x30310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhf<.f> 0,b,c 00110bbb00110001FBBBCCCCCC111110. */ -+{ "qmpyhf", 0x3031003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> b,b,c 00110bbb11110001FBBBCCCCCC0QQQQQ. */ -+{ "qmpyhf", 0x30F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> a,b,u6 00110bbb01110001FBBBuuuuuuAAAAAA. */ -+{ "qmpyhf", 0x30710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhf<.f> 0,b,u6 00110bbb01110001FBBBuuuuuu111110. */ -+{ "qmpyhf", 0x3071003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> b,b,u6 00110bbb11110001FBBBuuuuuu1QQQQQ. */ -+{ "qmpyhf", 0x30F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> b,b,s12 00110bbb10110001FBBBssssssSSSSSS. */ -+{ "qmpyhf", 0x30B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyhf<.f> a,limm,c 0011011000110001F111CCCCCCAAAAAA. */ -+{ "qmpyhf", 0x36317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhf<.f> a,b,limm 00110bbb00110001FBBB111110AAAAAA. */ -+{ "qmpyhf", 0x30310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyhf<.f> 0,limm,c 0011011000110001F111CCCCCC111110. */ -+{ "qmpyhf", 0x3631703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhf<.f> 0,b,limm 00110bbb00110001FBBB111110111110. */ -+{ "qmpyhf", 0x30310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> b,b,limm 00110bbb11110001FBBB1111100QQQQQ. */ -+{ "qmpyhf", 0x30F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f><.cc> 0,limm,c 0011011011110001F111CCCCCC0QQQQQ. */ -+{ "qmpyhf", 0x36F17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> a,limm,u6 0011011001110001F111uuuuuuAAAAAA. */ -+{ "qmpyhf", 0x36717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhf<.f> 0,limm,u6 0011011001110001F111uuuuuu111110. */ -+{ "qmpyhf", 0x3671703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> 0,limm,u6 0011011011110001F111uuuuuu1QQQQQ. */ -+{ "qmpyhf", 0x36F17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> 0,limm,s12 0011011010110001F111ssssssSSSSSS. */ -+{ "qmpyhf", 0x36B17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyhf<.f> a,limm,limm 0011011000110001F111111110AAAAAA. */ -+{ "qmpyhf", 0x36317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyhf<.f> 0,limm,limm 0011011000110001F111111110111110. */ -+{ "qmpyhf", 0x36317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> 0,limm,limm 0011011011110001F1111111100QQQQQ. */ -+{ "qmpyhf", 0x36F17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA. */ -+{ "qmpyhu", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhu<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110. */ -+{ "qmpyhu", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ. */ -+{ "qmpyhu", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA. */ -+{ "qmpyhu", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhu<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110. */ -+{ "qmpyhu", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ. */ -+{ "qmpyhu", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS. */ -+{ "qmpyhu", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyhu<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA. */ -+{ "qmpyhu", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhu<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA. */ -+{ "qmpyhu", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyhu<.f> 0,limm,c 0010111000110001F111CCCCCC111110. */ -+{ "qmpyhu", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhu<.f> 0,b,limm 00101bbb00110001FBBB111110111110. */ -+{ "qmpyhu", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ. */ -+{ "qmpyhu", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ. */ -+{ "qmpyhu", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA. */ -+{ "qmpyhu", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhu<.f> 0,limm,u6 0010111001110001F111uuuuuu111110. */ -+{ "qmpyhu", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ. */ -+{ "qmpyhu", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS. */ -+{ "qmpyhu", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyhu<.f> a,limm,limm 0010111000110001F111111110AAAAAA. */ -+{ "qmpyhu", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyhu<.f> 0,limm,limm 0010111000110001F111111110111110. */ -+{ "qmpyhu", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ. */ -+{ "qmpyhu", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* rcmp b,c 00100bbb000011011BBBCCCCCCRRRRRR. */ -+{ "rcmp", 0x200D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* rcmp<.cc> b,c 00100bbb110011011BBBCCCCCC0QQQQQ. */ -+{ "rcmp", 0x20CD8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* rcmp b,u6 00100bbb010011011BBBuuuuuuRRRRRR. */ -+{ "rcmp", 0x204D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rcmp<.cc> b,u6 00100bbb110011011BBBuuuuuu1QQQQQ. */ -+{ "rcmp", 0x20CD8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* rcmp b,s12 00100bbb100011011BBBssssssSSSSSS. */ -+{ "rcmp", 0x208D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* rcmp limm,c 00100110000011011111CCCCCCRRRRRR. */ -+{ "rcmp", 0x260DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* rcmp b,limm 00100bbb000011011BBB111110RRRRRR. */ -+{ "rcmp", 0x200D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* rcmp<.cc> limm,c 00100110110011011111CCCCCC0QQQQQ. */ -+{ "rcmp", 0x26CDF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* rcmp<.cc> b,limm 00100bbb110011011BBB1111100QQQQQ. */ -+{ "rcmp", 0x20CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* rcmp limm,u6 00100110010011011111uuuuuuRRRRRR. */ -+{ "rcmp", 0x264DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rcmp<.cc> limm,u6 00100110110011011111uuuuuu1QQQQQ. */ -+{ "rcmp", 0x26CDF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* rcmp limm,s12 00100110100011011111ssssssSSSSSS. */ -+{ "rcmp", 0x268DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* rcmp limm,limm 00100110000011011111111110RRRRRR. */ -+{ "rcmp", 0x260DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* rcmp<.cc> limm,limm 001001101100110111111111100QQQQQ. */ -+{ "rcmp", 0x26CDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* rcmpl OPERAND_RB,RC 01011bbb000011011BBBccccccRRRRRR. */ -+{ "rcmpl", 0x580D8000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* rcmpl<.cc> OPERAND_RB,RC 01011bbb110011011BBBcccccc0QQQQQ. */ -+{ "rcmpl", 0x58CD8000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* rcmpl OPERAND_RB,u6 01011bbb010011011BBBuuuuuuRRRRRR. */ -+{ "rcmpl", 0x584D8000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rcmpl<.cc> OPERAND_RB,u6 01011bbb110011011BBBuuuuuu1QQQQQ. */ -+{ "rcmpl", 0x58CD8020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* rcmpl OPERAND_RB,s12 01011bbb100011011BBBssssssSSSSSS. */ -+{ "rcmpl", 0x588D8000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* rcmpl ximm,RC 01011100000011011111ccccccRRRRRR. */ -+{ "rcmpl", 0x5C0DF000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_XIMM, OPERAND_RC }, { 0 }}, -+ -+/* rcmpl OPERAND_RB,ximm 01011bbb000011011BBB111100RRRRRR. */ -+{ "rcmpl", 0x580D8F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* rcmpl<.cc> OPERAND_RB,ximm 01011bbb110011011BBB1111000QQQQQ. */ -+{ "rcmpl", 0x58CD8F00, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_CC }}, -+ -+/* rcmpl limm,RC 01011110000011011111ccccccRRRRRR. */ -+{ "rcmpl", 0x5E0DF000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* rcmpl OPERAND_RB,limm 01011bbb000011011BBB111110RRRRRR. */ -+{ "rcmpl", 0x580D8F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* rcmpl<.cc> OPERAND_RB,limm 01011bbb110011011BBB1111100QQQQQ. */ -+{ "rcmpl", 0x58CD8F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* rcmpl limm,u6 01011110010011011111uuuuuuRRRRRR. */ -+{ "rcmpl", 0x5E4DF000, 0xFFFFF000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */ -+{ "rem", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */ -+{ "rem", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */ -+{ "rem", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */ -+{ "rem", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */ -+{ "rem", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */ -+{ "rem", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rem<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */ -+{ "rem", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */ -+{ "rem", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */ -+{ "rem", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rem<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */ -+{ "rem", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */ -+{ "rem", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */ -+{ "rem", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rem<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */ -+{ "rem", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rem<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */ -+{ "rem", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rem<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */ -+{ "rem", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */ -+{ "rem", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rem<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */ -+{ "rem", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */ -+{ "rem", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rem<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */ -+{ "rem", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* rem<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */ -+{ "rem", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rem<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */ -+{ "rem", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */ -+{ "rem", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rem<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */ -+{ "rem", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */ -+{ "rem", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rem<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */ -+{ "rem", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* rem<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */ -+{ "rem", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rem<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */ -+{ "rem", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */ -+{ "rem", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */ -+{ "rem", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rem<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */ -+{ "rem", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */ -+{ "rem", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */ -+{ "rem", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rem<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */ -+{ "rem", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rem<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */ -+{ "rem", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rem<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */ -+{ "rem", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rem<.f> 0,limm,limm 0010111000001000F111111110111110. */ -+{ "rem", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rem<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */ -+{ "rem", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* rem<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */ -+{ "rem", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rem<.f> 0,limm,limm 0010111000001000F111111110111110. */ -+{ "rem", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rem<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */ -+{ "rem", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* reml<.f> OPERAND_RA,RB,RC 01011bbb00101000FBBBccccccaaaaaa. */ -+{ "reml", 0x58280000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* reml<.f> 0,RB,RC 01011bbb00101000FBBBcccccc111110. */ -+{ "reml", 0x5828003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* reml<.f><.cc> OPERAND_RB,RB,RC 01011bbb11101000FBBBcccccc0QQQQQ. */ -+{ "reml", 0x58E80000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* reml<.f> OPERAND_RA,RB,u6 01011bbb01101000FBBBuuuuuuaaaaaa. */ -+{ "reml", 0x58680000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* reml<.f> 0,RB,u6 01011bbb01101000FBBBuuuuuu111110. */ -+{ "reml", 0x5868003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* reml<.f><.cc> OPERAND_RB,RB,u6 01011bbb11101000FBBBuuuuuu1QQQQQ. */ -+{ "reml", 0x58E80020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* reml<.f> OPERAND_RB,RB,s12 01011bbb10101000FBBBssssssSSSSSS. */ -+{ "reml", 0x58A80000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* reml<.f> OPERAND_RA,ximm,RC 0101110000101000F111ccccccaaaaaa. */ -+{ "reml", 0x5C287000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* reml<.f> OPERAND_RA,RB,ximm 01011bbb00101000FBBB111100aaaaaa. */ -+{ "reml", 0x58280F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* reml<.f> 0,ximm,RC 0101110000101000F111cccccc111110. */ -+{ "reml", 0x5C28703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* reml<.f> 0,RB,ximm 01011bbb00101000FBBB111100111110. */ -+{ "reml", 0x58280F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* reml<.f><.cc> 0,ximm,RC 0101110011101000F111cccccc0QQQQQ. */ -+{ "reml", 0x5CE87000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* reml<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11101000FBBB1111000QQQQQ. */ -+{ "reml", 0x58E80F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* reml<.f> OPERAND_RA,ximm,u6 0101110001101000F111uuuuuuaaaaaa. */ -+{ "reml", 0x5C687000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* reml<.f> 0,ximm,u6 0101110001101000F111uuuuuu111110. */ -+{ "reml", 0x5C68703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* reml<.f><.cc> 0,ximm,u6 0101110011101000F111uuuuuu1QQQQQ. */ -+{ "reml", 0x5CE87020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* reml<.f> OPERAND_RA,limm,RC 0101111000101000F111ccccccaaaaaa. */ -+{ "reml", 0x5E287000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* reml<.f> OPERAND_RA,RB,limm 01011bbb00101000FBBB111110aaaaaa. */ -+{ "reml", 0x58280F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* reml<.f> 0,limm,RC 0101111000101000F111cccccc111110. */ -+{ "reml", 0x5E28703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* reml<.f> 0,RB,limm 01011bbb00101000FBBB111110111110. */ -+{ "reml", 0x58280FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* reml<.f><.cc> 0,limm,RC 0101111011101000F111cccccc0QQQQQ. */ -+{ "reml", 0x5EE87000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* reml<.f><.cc> OPERAND_RB,RB,limm 01011bbb11101000FBBB1111100QQQQQ. */ -+{ "reml", 0x58E80F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* reml<.f> OPERAND_RA,limm,u6 0101111001101000F111uuuuuuaaaaaa. */ -+{ "reml", 0x5E687000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* reml<.f> 0,limm,u6 0101111001101000F111uuuuuu111110. */ -+{ "reml", 0x5E68703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* reml<.f><.cc> 0,limm,u6 0101111011101000F111uuuuuu1QQQQQ. */ -+{ "reml", 0x5EE87020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* reml<.f> 0,ximm,s12 0101110010101000F111ssssssSSSSSS. */ -+{ "reml", 0x5CA87000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* reml<.f> 0,limm,s12 0101111010101000F111ssssssSSSSSS. */ -+{ "reml", 0x5EA87000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* reml<.f> OPERAND_RA,ximm,ximm 0101110000101000F111111100aaaaaa. */ -+{ "reml", 0x5C287F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* reml<.f> 0,ximm,ximm 0101110000101000F111111100111110. */ -+{ "reml", 0x5C287F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* reml<.f><.cc> 0,ximm,ximm 0101110011101000F1111111000QQQQQ. */ -+{ "reml", 0x5CE87F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* reml<.f> OPERAND_RA,limm,limm 0101111000101000F111111110aaaaaa. */ -+{ "reml", 0x5E287F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* reml<.f> 0,limm,limm 0101111000101000F111111110111110. */ -+{ "reml", 0x5E287FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* reml<.f><.cc> 0,limm,limm 0101111011101000F1111111100QQQQQ. */ -+{ "reml", 0x5EE87F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* remu<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */ -+{ "remu", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */ -+{ "remu", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */ -+{ "remu", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* remu<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */ -+{ "remu", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */ -+{ "remu", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */ -+{ "remu", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* remu<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */ -+{ "remu", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */ -+{ "remu", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */ -+{ "remu", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* remu<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */ -+{ "remu", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */ -+{ "remu", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */ -+{ "remu", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* remu<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */ -+{ "remu", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* remu<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */ -+{ "remu", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* remu<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */ -+{ "remu", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */ -+{ "remu", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* remu<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */ -+{ "remu", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */ -+{ "remu", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* remu<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */ -+{ "remu", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* remu<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */ -+{ "remu", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* remu<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */ -+{ "remu", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */ -+{ "remu", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* remu<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */ -+{ "remu", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */ -+{ "remu", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* remu<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */ -+{ "remu", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* remu<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */ -+{ "remu", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* remu<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */ -+{ "remu", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */ -+{ "remu", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */ -+{ "remu", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* remu<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */ -+{ "remu", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */ -+{ "remu", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */ -+{ "remu", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* remu<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */ -+{ "remu", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* remu<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */ -+{ "remu", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* remu<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */ -+{ "remu", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* remu<.f> 0,limm,limm 0010111000001001F111111110111110. */ -+{ "remu", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* remu<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */ -+{ "remu", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* remu<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */ -+{ "remu", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* remu<.f> 0,limm,limm 0010111000001001F111111110111110. */ -+{ "remu", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* remu<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */ -+{ "remu", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* remul<.f> OPERAND_RA,RB,RC 01011bbb00101001FBBBccccccaaaaaa. */ -+{ "remul", 0x58290000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* remul<.f> 0,RB,RC 01011bbb00101001FBBBcccccc111110. */ -+{ "remul", 0x5829003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* remul<.f><.cc> OPERAND_RB,RB,RC 01011bbb11101001FBBBcccccc0QQQQQ. */ -+{ "remul", 0x58E90000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* remul<.f> OPERAND_RA,RB,u6 01011bbb01101001FBBBuuuuuuaaaaaa. */ -+{ "remul", 0x58690000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remul<.f> 0,RB,u6 01011bbb01101001FBBBuuuuuu111110. */ -+{ "remul", 0x5869003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remul<.f><.cc> OPERAND_RB,RB,u6 01011bbb11101001FBBBuuuuuu1QQQQQ. */ -+{ "remul", 0x58E90020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* remul<.f> OPERAND_RB,RB,s12 01011bbb10101001FBBBssssssSSSSSS. */ -+{ "remul", 0x58A90000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* remul<.f> OPERAND_RA,ximm,RC 0101110000101001F111ccccccaaaaaa. */ -+{ "remul", 0x5C297000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* remul<.f> OPERAND_RA,RB,ximm 01011bbb00101001FBBB111100aaaaaa. */ -+{ "remul", 0x58290F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* remul<.f> 0,ximm,RC 0101110000101001F111cccccc111110. */ -+{ "remul", 0x5C29703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* remul<.f> 0,RB,ximm 01011bbb00101001FBBB111100111110. */ -+{ "remul", 0x58290F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* remul<.f><.cc> 0,ximm,RC 0101110011101001F111cccccc0QQQQQ. */ -+{ "remul", 0x5CE97000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* remul<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11101001FBBB1111000QQQQQ. */ -+{ "remul", 0x58E90F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* remul<.f> OPERAND_RA,ximm,u6 0101110001101001F111uuuuuuaaaaaa. */ -+{ "remul", 0x5C697000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remul<.f> 0,ximm,u6 0101110001101001F111uuuuuu111110. */ -+{ "remul", 0x5C69703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remul<.f><.cc> 0,ximm,u6 0101110011101001F111uuuuuu1QQQQQ. */ -+{ "remul", 0x5CE97020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* remul<.f> OPERAND_RA,limm,RC 0101111000101001F111ccccccaaaaaa. */ -+{ "remul", 0x5E297000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* remul<.f> OPERAND_RA,RB,limm 01011bbb00101001FBBB111110aaaaaa. */ -+{ "remul", 0x58290F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* remul<.f> 0,limm,RC 0101111000101001F111cccccc111110. */ -+{ "remul", 0x5E29703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* remul<.f> 0,RB,limm 01011bbb00101001FBBB111110111110. */ -+{ "remul", 0x58290FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* remul<.f><.cc> 0,limm,RC 0101111011101001F111cccccc0QQQQQ. */ -+{ "remul", 0x5EE97000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* remul<.f><.cc> OPERAND_RB,RB,limm 01011bbb11101001FBBB1111100QQQQQ. */ -+{ "remul", 0x58E90F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* remul<.f> OPERAND_RA,limm,u6 0101111001101001F111uuuuuuaaaaaa. */ -+{ "remul", 0x5E697000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remul<.f> 0,limm,u6 0101111001101001F111uuuuuu111110. */ -+{ "remul", 0x5E69703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remul<.f><.cc> 0,limm,u6 0101111011101001F111uuuuuu1QQQQQ. */ -+{ "remul", 0x5EE97020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* remul<.f> 0,ximm,s12 0101110010101001F111ssssssSSSSSS. */ -+{ "remul", 0x5CA97000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* remul<.f> 0,limm,s12 0101111010101001F111ssssssSSSSSS. */ -+{ "remul", 0x5EA97000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* remul<.f> OPERAND_RA,ximm,ximm 0101110000101001F111111100aaaaaa. */ -+{ "remul", 0x5C297F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* remul<.f> 0,ximm,ximm 0101110000101001F111111100111110. */ -+{ "remul", 0x5C297F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* remul<.f><.cc> 0,ximm,ximm 0101110011101001F1111111000QQQQQ. */ -+{ "remul", 0x5CE97F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* remul<.f> OPERAND_RA,limm,limm 0101111000101001F111111110aaaaaa. */ -+{ "remul", 0x5E297F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* remul<.f> 0,limm,limm 0101111000101001F111111110111110. */ -+{ "remul", 0x5E297FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* remul<.f><.cc> 0,limm,limm 0101111011101001F1111111100QQQQQ. */ -+{ "remul", 0x5EE97F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* rlc<.f> b,c 00100bbb00101111FBBBCCCCCC001011. */ -+{ "rlc", 0x202F000B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rlc<.f> 0,c 0010011000101111F111CCCCCC001011. */ -+{ "rlc", 0x262F700B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rlc<.f> b,u6 00100bbb01101111FBBBuuuuuu001011. */ -+{ "rlc", 0x206F000B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rlc<.f> 0,u6 0010011001101111F111uuuuuu001011. */ -+{ "rlc", 0x266F700B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rlc<.f> b,limm 00100bbb00101111FBBB111110001011. */ -+{ "rlc", 0x202F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rlc<.f> 0,limm 0010011000101111F111111110001011. */ -+{ "rlc", 0x262F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rndh<.f> b,c 00101bbb00101111FBBBCCCCCC000011. */ -+{ "rndh", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* rndh<.f> 0,c 0010111000101111F111CCCCCC000011. */ -+{ "rndh", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rndh<.f> b,u6 00101bbb01101111FBBBuuuuuu000011. */ -+{ "rndh", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rndh<.f> 0,u6 0010111001101111F111uuuuuu000011. */ -+{ "rndh", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rndh<.f> b,limm 00101bbb00101111FBBB111110000011. */ -+{ "rndh", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* rndh<.f> 0,limm 0010111000101111F111111110000011. */ -+{ "rndh", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rol<.f> b,c 00100bbb00101111FBBBCCCCCC001101. */ -+{ "rol", 0x202F000D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rol<.f> 0,c 0010011000101111F111CCCCCC001101. */ -+{ "rol", 0x262F700D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rol<.f> b,u6 00100bbb01101111FBBBuuuuuu001101. */ -+{ "rol", 0x206F000D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rol<.f> 0,u6 0010011001101111F111uuuuuu001101. */ -+{ "rol", 0x266F700D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rol<.f> b,limm 00100bbb00101111FBBB111110001101. */ -+{ "rol", 0x202F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rol<.f> 0,limm 0010011000101111F111111110001101. */ -+{ "rol", 0x262F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rol8<.f> b,c 00101bbb00101111FBBBCCCCCC010000. */ -+{ "rol8", 0x282F0010, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rol8<.f> 0,c 0010111000101111F111CCCCCC010000. */ -+{ "rol8", 0x2E2F7010, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rol8<.f> b,u6 00101bbb01101111FBBBuuuuuu010000. */ -+{ "rol8", 0x286F0010, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rol8<.f> 0,u6 0010111001101111F111uuuuuu010000. */ -+{ "rol8", 0x2E6F7010, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rol8<.f> b,limm 00101bbb00101111FBBB111110010000. */ -+{ "rol8", 0x282F0F90, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rol8<.f> 0,limm 0010111000101111F111111110010000. */ -+{ "rol8", 0x2E2F7F90, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f> b,c 00100bbb00101111FBBBCCCCCC000011. */ -+{ "ror", 0x202F0003, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> 0,c 0010011000101111F111CCCCCC000011. */ -+{ "ror", 0x262F7003, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> a,b,c 00101bbb00000011FBBBCCCCCCAAAAAA. */ -+{ "ror", 0x28030000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> 0,b,c 00101bbb00000011FBBBCCCCCC111110. */ -+{ "ror", 0x2803003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f><.cc> b,b,c 00101bbb11000011FBBBCCCCCC0QQQQQ. */ -+{ "ror", 0x28C30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* ror<.f> b,u6 00100bbb01101111FBBBuuuuuu000011. */ -+{ "ror", 0x206F0003, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f> 0,u6 0010011001101111F111uuuuuu000011. */ -+{ "ror", 0x266F7003, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f> a,b,u6 00101bbb01000011FBBBuuuuuuAAAAAA. */ -+{ "ror", 0x28430000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f> 0,b,u6 00101bbb01000011FBBBuuuuuu111110. */ -+{ "ror", 0x2843003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f><.cc> b,b,u6 00101bbb11000011FBBBuuuuuu1QQQQQ. */ -+{ "ror", 0x28C30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* ror<.f> b,b,s12 00101bbb10000011FBBBssssssSSSSSS. */ -+{ "ror", 0x28830000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* ror<.f> b,limm 00100bbb00101111FBBB111110000011. */ -+{ "ror", 0x202F0F83, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f> 0,limm 0010011000101111F111111110000011. */ -+{ "ror", 0x262F7F83, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f> a,limm,c 0010111000000011F111CCCCCCAAAAAA. */ -+{ "ror", 0x2E037000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> a,b,limm 00101bbb00000011FBBB111110AAAAAA. */ -+{ "ror", 0x28030F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f> 0,limm,c 0010111000000011F111CCCCCC111110. */ -+{ "ror", 0x2E03703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> 0,b,limm 00101bbb00000011FBBB111110111110. */ -+{ "ror", 0x28030FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f><.cc> b,b,limm 00101bbb11000011FBBB1111100QQQQQ. */ -+{ "ror", 0x28C30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* ror<.f><.cc> 0,limm,c 0010111011000011F111CCCCCC0QQQQQ. */ -+{ "ror", 0x2EC37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* ror<.f> a,limm,u6 0010111001000011F111uuuuuuAAAAAA. */ -+{ "ror", 0x2E437000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f> 0,limm,u6 0010111001000011F111uuuuuu111110. */ -+{ "ror", 0x2E43703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f><.cc> 0,limm,u6 0010111011000011F111uuuuuu1QQQQQ. */ -+{ "ror", 0x2EC37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* ror<.f> 0,limm,s12 0010111010000011F111ssssssSSSSSS. */ -+{ "ror", 0x2E837000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* ror<.f> a,limm,limm 0010111000000011F111111110AAAAAA. */ -+{ "ror", 0x2E037F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* ror<.f> 0,limm,limm 0010111000000011F111111110111110. */ -+{ "ror", 0x2E037FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* ror<.f><.cc> 0,limm,limm 0010111011000011F1111111100QQQQQ. */ -+{ "ror", 0x2EC37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* ror8<.f> b,c 00101bbb00101111FBBBCCCCCC010001. */ -+{ "ror8", 0x282F0011, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ror8<.f> 0,c 0010111000101111F111CCCCCC010001. */ -+{ "ror8", 0x2E2F7011, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* ror8<.f> b,u6 00101bbb01101111FBBBuuuuuu010001. */ -+{ "ror8", 0x286F0011, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror8<.f> 0,u6 0010111001101111F111uuuuuu010001. */ -+{ "ror8", 0x2E6F7011, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror8<.f> b,limm 00101bbb00101111FBBB111110010001. */ -+{ "ror8", 0x282F0F91, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ror8<.f> 0,limm 0010111000101111F111111110010001. */ -+{ "ror8", 0x2E2F7F91, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rrc<.f> b,c 00100bbb00101111FBBBCCCCCC000100. */ -+{ "rrc", 0x202F0004, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rrc<.f> 0,c 0010011000101111F111CCCCCC000100. */ -+{ "rrc", 0x262F7004, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rrc<.f> b,u6 00100bbb01101111FBBBuuuuuu000100. */ -+{ "rrc", 0x206F0004, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rrc<.f> 0,u6 0010011001101111F111uuuuuu000100. */ -+{ "rrc", 0x266F7004, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rrc<.f> b,limm 00100bbb00101111FBBB111110000100. */ -+{ "rrc", 0x202F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rrc<.f> 0,limm 0010011000101111F111111110000100. */ -+{ "rrc", 0x262F7F84, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rsub<.f> a,b,c 00100bbb00001110FBBBCCCCCCAAAAAA. */ -+{ "rsub", 0x200E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rsub<.f> 0,b,c 00100bbb00001110FBBBCCCCCC111110. */ -+{ "rsub", 0x200E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rsub<.f><.cc> b,b,c 00100bbb11001110FBBBCCCCCC0QQQQQ. */ -+{ "rsub", 0x20CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rsub<.f> a,b,u6 00100bbb01001110FBBBuuuuuuAAAAAA. */ -+{ "rsub", 0x204E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsub<.f> 0,b,u6 00100bbb01001110FBBBuuuuuu111110. */ -+{ "rsub", 0x204E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsub<.f><.cc> b,b,u6 00100bbb11001110FBBBuuuuuu1QQQQQ. */ -+{ "rsub", 0x20CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rsub<.f> b,b,s12 00100bbb10001110FBBBssssssSSSSSS. */ -+{ "rsub", 0x208E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rsub<.f> a,limm,c 0010011000001110F111CCCCCCAAAAAA. */ -+{ "rsub", 0x260E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rsub<.f> a,b,limm 00100bbb00001110FBBB111110AAAAAA. */ -+{ "rsub", 0x200E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rsub<.f> 0,limm,c 0010011000001110F111CCCCCC111110. */ -+{ "rsub", 0x260E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rsub<.f> 0,b,limm 00100bbb00001110FBBB111110111110. */ -+{ "rsub", 0x200E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rsub<.f><.cc> b,b,limm 00100bbb11001110FBBB1111100QQQQQ. */ -+{ "rsub", 0x20CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* rsub<.f><.cc> 0,limm,c 0010011011001110F111CCCCCC0QQQQQ. */ -+{ "rsub", 0x26CE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rsub<.f> a,limm,u6 0010011001001110F111uuuuuuAAAAAA. */ -+{ "rsub", 0x264E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsub<.f> 0,limm,u6 0010011001001110F111uuuuuu111110. */ -+{ "rsub", 0x264E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsub<.f><.cc> 0,limm,u6 0010011011001110F111uuuuuu1QQQQQ. */ -+{ "rsub", 0x26CE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rsub<.f> 0,limm,s12 0010011010001110F111ssssssSSSSSS. */ -+{ "rsub", 0x268E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rsub<.f> a,limm,limm 0010011000001110F111111110AAAAAA. */ -+{ "rsub", 0x260E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rsub<.f> 0,limm,limm 0010011000001110F111111110111110. */ -+{ "rsub", 0x260E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rsub<.f><.cc> 0,limm,limm 0010011011001110F1111111100QQQQQ. */ -+{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* rsubl<.f> OPERAND_RA,RB,RC 01011bbb00001110FBBBccccccaaaaaa. */ -+{ "rsubl", 0x580E0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rsubl<.f> 0,RB,RC 01011bbb00001110FBBBcccccc111110. */ -+{ "rsubl", 0x580E003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rsubl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11001110FBBBcccccc0QQQQQ. */ -+{ "rsubl", 0x58CE0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rsubl<.f> OPERAND_RA,RB,u6 01011bbb01001110FBBBuuuuuuaaaaaa. */ -+{ "rsubl", 0x584E0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsubl<.f> 0,RB,u6 01011bbb01001110FBBBuuuuuu111110. */ -+{ "rsubl", 0x584E003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsubl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11001110FBBBuuuuuu1QQQQQ. */ -+{ "rsubl", 0x58CE0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rsubl<.f> OPERAND_RB,RB,s12 01011bbb10001110FBBBssssssSSSSSS. */ -+{ "rsubl", 0x588E0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rsubl<.f> OPERAND_RA,ximm,RC 0101110000001110F111ccccccaaaaaa. */ -+{ "rsubl", 0x5C0E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* rsubl<.f> OPERAND_RA,RB,ximm 01011bbb00001110FBBB111100aaaaaa. */ -+{ "rsubl", 0x580E0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* rsubl<.f> 0,ximm,RC 0101110000001110F111cccccc111110. */ -+{ "rsubl", 0x5C0E703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* rsubl<.f> 0,RB,ximm 01011bbb00001110FBBB111100111110. */ -+{ "rsubl", 0x580E0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* rsubl<.f><.cc> 0,ximm,RC 0101110011001110F111cccccc0QQQQQ. */ -+{ "rsubl", 0x5CCE7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rsubl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11001110FBBB1111000QQQQQ. */ -+{ "rsubl", 0x58CE0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* rsubl<.f> OPERAND_RA,ximm,u6 0101110001001110F111uuuuuuaaaaaa. */ -+{ "rsubl", 0x5C4E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsubl<.f> 0,ximm,u6 0101110001001110F111uuuuuu111110. */ -+{ "rsubl", 0x5C4E703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsubl<.f><.cc> 0,ximm,u6 0101110011001110F111uuuuuu1QQQQQ. */ -+{ "rsubl", 0x5CCE7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rsubl<.f> OPERAND_RA,limm,RC 0101111000001110F111ccccccaaaaaa. */ -+{ "rsubl", 0x5E0E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rsubl<.f> OPERAND_RA,RB,limm 01011bbb00001110FBBB111110aaaaaa. */ -+{ "rsubl", 0x580E0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rsubl<.f> 0,limm,RC 0101111000001110F111cccccc111110. */ -+{ "rsubl", 0x5E0E703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rsubl<.f> 0,RB,limm 01011bbb00001110FBBB111110111110. */ -+{ "rsubl", 0x580E0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rsubl<.f><.cc> 0,limm,RC 0101111011001110F111cccccc0QQQQQ. */ -+{ "rsubl", 0x5ECE7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rsubl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11001110FBBB1111100QQQQQ. */ -+{ "rsubl", 0x58CE0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* rsubl<.f> OPERAND_RA,limm,u6 0101111001001110F111uuuuuuaaaaaa. */ -+{ "rsubl", 0x5E4E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsubl<.f> 0,limm,u6 0101111001001110F111uuuuuu111110. */ -+{ "rsubl", 0x5E4E703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsubl<.f><.cc> 0,limm,u6 0101111011001110F111uuuuuu1QQQQQ. */ -+{ "rsubl", 0x5ECE7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rsubl<.f> 0,ximm,s12 0101110010001110F111ssssssSSSSSS. */ -+{ "rsubl", 0x5C8E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rsubl<.f> 0,limm,s12 0101111010001110F111ssssssSSSSSS. */ -+{ "rsubl", 0x5E8E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rsubl<.f> OPERAND_RA,ximm,ximm 0101110000001110F111111100aaaaaa. */ -+{ "rsubl", 0x5C0E7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* rsubl<.f> 0,ximm,ximm 0101110000001110F111111100111110. */ -+{ "rsubl", 0x5C0E7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* rsubl<.f><.cc> 0,ximm,ximm 0101110011001110F1111111000QQQQQ. */ -+{ "rsubl", 0x5CCE7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* rsubl<.f> OPERAND_RA,limm,limm 0101111000001110F111111110aaaaaa. */ -+{ "rsubl", 0x5E0E7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rsubl<.f> 0,limm,limm 0101111000001110F111111110111110. */ -+{ "rsubl", 0x5E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rsubl<.f><.cc> 0,limm,limm 0101111011001110F1111111100QQQQQ. */ -+{ "rsubl", 0x5ECE7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* rtie 00100100011011110000000000111111. */ -+{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* satf<.f> b,c 00101bbb00101111FBBBCCCCCC011010. */ -+{ "satf", 0x282F001A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* satf<.f> 0,c 0010111000101111F111CCCCCC011010. */ -+{ "satf", 0x2E2F701A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* satf<.f> b,u6 00101bbb01101111FBBBuuuuuu011010. */ -+{ "satf", 0x286F001A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* satf<.f> 0,u6 0010111001101111F111uuuuuu011010. */ -+{ "satf", 0x2E6F701A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* satf<.f> b,limm 00101bbb00101111FBBB111110011010. */ -+{ "satf", 0x282F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* satf<.f> 0,limm 0010111000101111F111111110011010. */ -+{ "satf", 0x2E2F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sath<.f> b,c 00101bbb00101111FBBBCCCCCC000010. */ -+{ "sath", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* sath<.f> 0,c 0010111000101111F111CCCCCC000010. */ -+{ "sath", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sath<.f> b,u6 00101bbb01101111FBBBuuuuuu000010. */ -+{ "sath", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sath<.f> 0,u6 0010111001101111F111uuuuuu000010. */ -+{ "sath", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sath<.f> b,limm 00101bbb00101111FBBB111110000010. */ -+{ "sath", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* sath<.f> 0,limm 0010111000101111F111111110000010. */ -+{ "sath", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sbc<.f> a,b,c 00100bbb00000011FBBBCCCCCCAAAAAA. */ -+{ "sbc", 0x20030000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbc<.f> 0,b,c 00100bbb00000011FBBBCCCCCC111110. */ -+{ "sbc", 0x2003003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbc<.f><.cc> b,b,c 00100bbb11000011FBBBCCCCCC0QQQQQ. */ -+{ "sbc", 0x20C30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbc<.f> a,b,u6 00100bbb01000011FBBBuuuuuuAAAAAA. */ -+{ "sbc", 0x20430000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbc<.f> 0,b,u6 00100bbb01000011FBBBuuuuuu111110. */ -+{ "sbc", 0x2043003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbc<.f><.cc> b,b,u6 00100bbb11000011FBBBuuuuuu1QQQQQ. */ -+{ "sbc", 0x20C30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbc<.f> b,b,s12 00100bbb10000011FBBBssssssSSSSSS. */ -+{ "sbc", 0x20830000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbc<.f> a,limm,c 0010011000000011F111CCCCCCAAAAAA. */ -+{ "sbc", 0x26037000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbc<.f> a,b,limm 00100bbb00000011FBBB111110AAAAAA. */ -+{ "sbc", 0x20030F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbc<.f> 0,limm,c 0010011000000011F111CCCCCC111110. */ -+{ "sbc", 0x2603703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbc<.f> 0,b,limm 00100bbb00000011FBBB111110111110. */ -+{ "sbc", 0x20030FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbc<.f><.cc> b,b,limm 00100bbb11000011FBBB1111100QQQQQ. */ -+{ "sbc", 0x20C30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sbc<.f><.cc> 0,limm,c 0010011011000011F111CCCCCC0QQQQQ. */ -+{ "sbc", 0x26C37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbc<.f> a,limm,u6 0010011001000011F111uuuuuuAAAAAA. */ -+{ "sbc", 0x26437000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbc<.f> 0,limm,u6 0010011001000011F111uuuuuu111110. */ -+{ "sbc", 0x2643703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbc<.f><.cc> 0,limm,u6 0010011011000011F111uuuuuu1QQQQQ. */ -+{ "sbc", 0x26C37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbc<.f> 0,limm,s12 0010011010000011F111ssssssSSSSSS. */ -+{ "sbc", 0x26837000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbc<.f> a,limm,limm 0010011000000011F111111110AAAAAA. */ -+{ "sbc", 0x26037F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sbc<.f> 0,limm,limm 0010011000000011F111111110111110. */ -+{ "sbc", 0x26037FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sbc<.f><.cc> 0,limm,limm 0010011011000011F1111111100QQQQQ. */ -+{ "sbc", 0x26C37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sbcl<.f> OPERAND_RA,RB,RC 01011bbb00000011FBBBccccccaaaaaa. */ -+{ "sbcl", 0x58030000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbcl<.f> 0,RB,RC 01011bbb00000011FBBBcccccc111110. */ -+{ "sbcl", 0x5803003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbcl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11000011FBBBcccccc0QQQQQ. */ -+{ "sbcl", 0x58C30000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbcl<.f> OPERAND_RA,RB,u6 01011bbb01000011FBBBuuuuuuaaaaaa. */ -+{ "sbcl", 0x58430000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcl<.f> 0,RB,u6 01011bbb01000011FBBBuuuuuu111110. */ -+{ "sbcl", 0x5843003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11000011FBBBuuuuuu1QQQQQ. */ -+{ "sbcl", 0x58C30020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbcl<.f> OPERAND_RB,RB,s12 01011bbb10000011FBBBssssssSSSSSS. */ -+{ "sbcl", 0x58830000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbcl<.f> OPERAND_RA,ximm,RC 0101110000000011F111ccccccaaaaaa. */ -+{ "sbcl", 0x5C037000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbcl<.f> OPERAND_RA,RB,ximm 01011bbb00000011FBBB111100aaaaaa. */ -+{ "sbcl", 0x58030F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sbcl<.f> 0,ximm,RC 0101110000000011F111cccccc111110. */ -+{ "sbcl", 0x5C03703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbcl<.f> 0,RB,ximm 01011bbb00000011FBBB111100111110. */ -+{ "sbcl", 0x58030F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sbcl<.f><.cc> 0,ximm,RC 0101110011000011F111cccccc0QQQQQ. */ -+{ "sbcl", 0x5CC37000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbcl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11000011FBBB1111000QQQQQ. */ -+{ "sbcl", 0x58C30F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* sbcl<.f> OPERAND_RA,ximm,u6 0101110001000011F111uuuuuuaaaaaa. */ -+{ "sbcl", 0x5C437000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcl<.f> 0,ximm,u6 0101110001000011F111uuuuuu111110. */ -+{ "sbcl", 0x5C43703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcl<.f><.cc> 0,ximm,u6 0101110011000011F111uuuuuu1QQQQQ. */ -+{ "sbcl", 0x5CC37020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbcl<.f> OPERAND_RA,limm,RC 0101111000000011F111ccccccaaaaaa. */ -+{ "sbcl", 0x5E037000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbcl<.f> OPERAND_RA,RB,limm 01011bbb00000011FBBB111110aaaaaa. */ -+{ "sbcl", 0x58030F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbcl<.f> 0,limm,RC 0101111000000011F111cccccc111110. */ -+{ "sbcl", 0x5E03703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbcl<.f> 0,RB,limm 01011bbb00000011FBBB111110111110. */ -+{ "sbcl", 0x58030FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbcl<.f><.cc> 0,limm,RC 0101111011000011F111cccccc0QQQQQ. */ -+{ "sbcl", 0x5EC37000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbcl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11000011FBBB1111100QQQQQ. */ -+{ "sbcl", 0x58C30F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sbcl<.f> OPERAND_RA,limm,u6 0101111001000011F111uuuuuuaaaaaa. */ -+{ "sbcl", 0x5E437000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcl<.f> 0,limm,u6 0101111001000011F111uuuuuu111110. */ -+{ "sbcl", 0x5E43703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcl<.f><.cc> 0,limm,u6 0101111011000011F111uuuuuu1QQQQQ. */ -+{ "sbcl", 0x5EC37020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbcl<.f> 0,ximm,s12 0101110010000011F111ssssssSSSSSS. */ -+{ "sbcl", 0x5C837000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbcl<.f> 0,limm,s12 0101111010000011F111ssssssSSSSSS. */ -+{ "sbcl", 0x5E837000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbcl<.f> OPERAND_RA,ximm,ximm 0101110000000011F111111100aaaaaa. */ -+{ "sbcl", 0x5C037F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sbcl<.f> 0,ximm,ximm 0101110000000011F111111100111110. */ -+{ "sbcl", 0x5C037F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sbcl<.f><.cc> 0,ximm,ximm 0101110011000011F1111111000QQQQQ. */ -+{ "sbcl", 0x5CC37F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* sbcl<.f> OPERAND_RA,limm,limm 0101111000000011F111111110aaaaaa. */ -+{ "sbcl", 0x5E037F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sbcl<.f> 0,limm,limm 0101111000000011F111111110111110. */ -+{ "sbcl", 0x5E037FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sbcl<.f><.cc> 0,limm,limm 0101111011000011F1111111100QQQQQ. */ -+{ "sbcl", 0x5EC37F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sbcs<.f> a,b,c 00101bbb00100111FBBBCCCCCCAAAAAA. */ -+{ "sbcs", 0x28270000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbcs<.f> 0,b,c 00101bbb00100111FBBBCCCCCC111110. */ -+{ "sbcs", 0x2827003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbcs<.f><.cc> b,b,c 00101bbb11100111FBBBCCCCCC0QQQQQ. */ -+{ "sbcs", 0x28E70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbcs<.f> a,b,u6 00101bbb01100111FBBBuuuuuuAAAAAA. */ -+{ "sbcs", 0x28670000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcs<.f> 0,b,u6 00101bbb01100111FBBBuuuuuu111110. */ -+{ "sbcs", 0x2867003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcs<.f><.cc> b,b,u6 00101bbb11100111FBBBuuuuuu1QQQQQ. */ -+{ "sbcs", 0x28E70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbcs<.f> b,b,s12 00101bbb10100111FBBBssssssSSSSSS. */ -+{ "sbcs", 0x28A70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbcs<.f> a,limm,c 0010111000100111F111CCCCCCAAAAAA. */ -+{ "sbcs", 0x2E277000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbcs<.f> a,b,limm 00101bbb00100111FBBB111110AAAAAA. */ -+{ "sbcs", 0x28270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbcs<.f> 0,limm,c 0010111001100111F111CCCCCC111110. */ -+{ "sbcs", 0x2E67703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbcs<.f> 0,b,limm 00101bbb00100111FBBB111110111110. */ -+{ "sbcs", 0x28270FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbcs<.f><.cc> b,b,limm 00101bbb11100111FBBB1111100QQQQQ. */ -+{ "sbcs", 0x28E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sbcs<.f><.cc> 0,limm,c 0010111011100111F111CCCCCC0QQQQQ. */ -+{ "sbcs", 0x2EE77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbcs<.f> a,limm,u6 0010111001100111F111uuuuuuAAAAAA. */ -+{ "sbcs", 0x2E677000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcs<.f> 0,limm,u6 0010111001100111F111uuuuuu111110. */ -+{ "sbcs", 0x2E67703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcs<.f><.cc> 0,limm,u6 0010111011100111F111uuuuuu1QQQQQ. */ -+{ "sbcs", 0x2EE77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbcs<.f> 0,limm,s12 0010111010100111F111ssssssSSSSSS. */ -+{ "sbcs", 0x2EA77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbcs<.f> a,limm,limm 0010111000100111F111111110AAAAAA. */ -+{ "sbcs", 0x2E277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sbcs<.f> 0,limm,limm 0010111000100111F111111110111110. */ -+{ "sbcs", 0x2E277FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sbcs<.f><.cc> 0,limm,limm 0010111011100111F1111111100QQQQQ. */ -+{ "sbcs", 0x2EE77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001. */ -+{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001. */ -+{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scond<.di> b,limm 00100bbb00101111DBBB111110010001. */ -+{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scondl<.aq> OPERAND_RB,RC 01011bbb00101111FBBBcccccc010001. */ -+{ "scondl", 0x582F0011, 0xF8FF003F, ARC_OPCODE_V3_ARC64, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_AQ }}, -+ -+/* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA. */ -+{ "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* setacc 0,b,c 00101bbb000011011BBBCCCCCC111110. */ -+{ "setacc", 0x280D803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* setacc<.cc> b,b,c 00101bbb110011011BBBCCCCCC0QQQQQ. */ -+{ "setacc", 0x28CD8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* setacc a,b,u6 00101bbb010011011BBBuuuuuuAAAAAA. */ -+{ "setacc", 0x284D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* setacc 0,b,u6 00101bbb010011011BBBuuuuuu111110. */ -+{ "setacc", 0x284D803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* setacc<.cc> b,b,u6 00101bbb110011011BBBuuuuuu1QQQQQ. */ -+{ "setacc", 0x28CD8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* setacc b,b,s12 00101bbb100011011BBBssssssSSSSSS. */ -+{ "setacc", 0x288D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* setacc a,limm,c 00101110000011011111CCCCCCAAAAAA. */ -+{ "setacc", 0x2E0DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* setacc a,b,limm 00101bbb000011011BBB111110AAAAAA. */ -+{ "setacc", 0x280D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* setacc 0,limm,c 00101110000011011111CCCCCC111110. */ -+{ "setacc", 0x2E0DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* setacc 0,b,limm 00101bbb000011011BBB111110111110. */ -+{ "setacc", 0x280D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* setacc<.cc> b,b,limm 00101bbb110011011BBB1111100QQQQQ. */ -+{ "setacc", 0x28CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* setacc<.cc> 0,limm,c 00101110110011011111CCCCCC0QQQQQ. */ -+{ "setacc", 0x2ECDF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* setacc a,limm,u6 00101110010011011111uuuuuuAAAAAA. */ -+{ "setacc", 0x2E4DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* setacc 0,limm,u6 00101110010011011111uuuuuu111110. */ -+{ "setacc", 0x2E4DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* setacc<.cc> 0,limm,u6 00101110110011011111uuuuuu1QQQQQ. */ -+{ "setacc", 0x2ECDF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* setacc 0,limm,s12 00101110100011011111ssssssSSSSSS. */ -+{ "setacc", 0x2E8DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* setacc a,limm,limm 00101110000011011111111110AAAAAA. */ -+{ "setacc", 0x2E0DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* setacc 0,limm,limm 00101110000011011111111110111110. */ -+{ "setacc", 0x2E0DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* setacc<.cc> 0,limm,limm 001011101100110111111111100QQQQQ. */ -+{ "setacc", 0x2ECDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* seteq<.f> a,b,c 00100bbb00111000FBBBCCCCCCAAAAAA. */ -+{ "seteq", 0x20380000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seteq<.f> 0,b,c 00100bbb00111000FBBBCCCCCC111110. */ -+{ "seteq", 0x2038003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seteq<.f><.cc> b,b,c 00100bbb11111000FBBBCCCCCC0QQQQQ. */ -+{ "seteq", 0x20F80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seteq<.f> a,b,u6 00100bbb01111000FBBBuuuuuuAAAAAA. */ -+{ "seteq", 0x20780000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteq<.f> 0,b,u6 00100bbb01111000FBBBuuuuuu111110. */ -+{ "seteq", 0x2078003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteq<.f><.cc> b,b,u6 00100bbb11111000FBBBuuuuuu1QQQQQ. */ -+{ "seteq", 0x20F80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seteq<.f> b,b,s12 00100bbb10111000FBBBssssssSSSSSS. */ -+{ "seteq", 0x20B80000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seteq<.f> a,limm,c 0010011000111000F111CCCCCCAAAAAA. */ -+{ "seteq", 0x26387000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seteq<.f> a,b,limm 00100bbb00111000FBBB111110AAAAAA. */ -+{ "seteq", 0x20380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seteq<.f> 0,limm,c 0010011000111000F111CCCCCC111110. */ -+{ "seteq", 0x2638703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seteq<.f> 0,b,limm 00100bbb00111000FBBB111110111110. */ -+{ "seteq", 0x20380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seteq<.f><.cc> b,b,limm 00100bbb11111000FBBB1111100QQQQQ. */ -+{ "seteq", 0x20F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* seteq<.f><.cc> 0,limm,c 0010011011111000F111CCCCCC0QQQQQ. */ -+{ "seteq", 0x26F87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seteq<.f> a,limm,u6 0010011001111000F111uuuuuuAAAAAA. */ -+{ "seteq", 0x26787000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteq<.f> 0,limm,u6 0010011001111000F111uuuuuu111110. */ -+{ "seteq", 0x2678703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteq<.f><.cc> 0,limm,u6 0010011011111000F111uuuuuu1QQQQQ. */ -+{ "seteq", 0x26F87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seteq<.f> 0,limm,s12 0010011010111000F111ssssssSSSSSS. */ -+{ "seteq", 0x26B87000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seteq<.f> a,limm,limm 0010011000111000F111111110AAAAAA. */ -+{ "seteq", 0x26387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seteq<.f> 0,limm,limm 0010011000111000F111111110111110. */ -+{ "seteq", 0x26387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seteq<.f><.cc> 0,limm,limm 0010011011111000F1111111100QQQQQ. */ -+{ "seteq", 0x26F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* seteql<.f> OPERAND_RA,RB,RC 01011bbb00111000FBBBccccccaaaaaa. */ -+{ "seteql", 0x58380000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seteql<.f> 0,RB,RC 01011bbb00111000FBBBcccccc111110. */ -+{ "seteql", 0x5838003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seteql<.f><.cc> OPERAND_RB,RB,RC 01011bbb11111000FBBBcccccc0QQQQQ. */ -+{ "seteql", 0x58F80000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seteql<.f> OPERAND_RA,RB,u6 01011bbb01111000FBBBuuuuuuaaaaaa. */ -+{ "seteql", 0x58780000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteql<.f> 0,RB,u6 01011bbb01111000FBBBuuuuuu111110. */ -+{ "seteql", 0x5878003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteql<.f><.cc> OPERAND_RB,RB,u6 01011bbb11111000FBBBuuuuuu1QQQQQ. */ -+{ "seteql", 0x58F80020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seteql<.f> OPERAND_RB,RB,s12 01011bbb10111000FBBBssssssSSSSSS. */ -+{ "seteql", 0x58B80000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seteql<.f> OPERAND_RA,ximm,RC 0101110000111000F111ccccccaaaaaa. */ -+{ "seteql", 0x5C387000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* seteql<.f> OPERAND_RA,RB,ximm 01011bbb00111000FBBB111100aaaaaa. */ -+{ "seteql", 0x58380F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* seteql<.f> 0,ximm,RC 0101110000111000F111cccccc111110. */ -+{ "seteql", 0x5C38703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* seteql<.f> 0,RB,ximm 01011bbb00111000FBBB111100111110. */ -+{ "seteql", 0x58380F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* seteql<.f><.cc> 0,ximm,RC 0101110011111000F111cccccc0QQQQQ. */ -+{ "seteql", 0x5CF87000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seteql<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11111000FBBB1111000QQQQQ. */ -+{ "seteql", 0x58F80F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* seteql<.f> OPERAND_RA,ximm,u6 0101110001111000F111uuuuuuaaaaaa. */ -+{ "seteql", 0x5C787000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteql<.f> 0,ximm,u6 0101110001111000F111uuuuuu111110. */ -+{ "seteql", 0x5C78703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteql<.f><.cc> 0,ximm,u6 0101110011111000F111uuuuuu1QQQQQ. */ -+{ "seteql", 0x5CF87020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seteql<.f> OPERAND_RA,limm,RC 0101111000111000F111ccccccaaaaaa. */ -+{ "seteql", 0x5E387000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seteql<.f> OPERAND_RA,RB,limm 01011bbb00111000FBBB111110aaaaaa. */ -+{ "seteql", 0x58380F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seteql<.f> 0,limm,RC 0101111000111000F111cccccc111110. */ -+{ "seteql", 0x5E38703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seteql<.f> 0,RB,limm 01011bbb00111000FBBB111110111110. */ -+{ "seteql", 0x58380FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seteql<.f><.cc> 0,limm,RC 0101111011111000F111cccccc0QQQQQ. */ -+{ "seteql", 0x5EF87000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seteql<.f><.cc> OPERAND_RB,RB,limm 01011bbb11111000FBBB1111100QQQQQ. */ -+{ "seteql", 0x58F80F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* seteql<.f> OPERAND_RA,limm,u6 0101111001111000F111uuuuuuaaaaaa. */ -+{ "seteql", 0x5E787000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteql<.f> 0,limm,u6 0101111001111000F111uuuuuu111110. */ -+{ "seteql", 0x5E78703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteql<.f><.cc> 0,limm,u6 0101111011111000F111uuuuuu1QQQQQ. */ -+{ "seteql", 0x5EF87020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seteql<.f> 0,ximm,s12 0101110010111000F111ssssssSSSSSS. */ -+{ "seteql", 0x5CB87000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seteql<.f> 0,limm,s12 0101111010111000F111ssssssSSSSSS. */ -+{ "seteql", 0x5EB87000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seteql<.f> OPERAND_RA,ximm,ximm 0101110000111000F111111100aaaaaa. */ -+{ "seteql", 0x5C387F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* seteql<.f> 0,ximm,ximm 0101110000111000F111111100111110. */ -+{ "seteql", 0x5C387F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* seteql<.f><.cc> 0,ximm,ximm 0101110011111000F1111111000QQQQQ. */ -+{ "seteql", 0x5CF87F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* seteql<.f> OPERAND_RA,limm,limm 0101111000111000F111111110aaaaaa. */ -+{ "seteql", 0x5E387F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seteql<.f> 0,limm,limm 0101111000111000F111111110111110. */ -+{ "seteql", 0x5E387FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seteql<.f><.cc> 0,limm,limm 0101111011111000F1111111100QQQQQ. */ -+{ "seteql", 0x5EF87F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setge<.f> a,b,c 00100bbb00111011FBBBCCCCCCAAAAAA. */ -+{ "setge", 0x203B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setge<.f> 0,b,c 00100bbb00111011FBBBCCCCCC111110. */ -+{ "setge", 0x203B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setge<.f><.cc> b,b,c 00100bbb11111011FBBBCCCCCC0QQQQQ. */ -+{ "setge", 0x20FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setge<.f> a,b,u6 00100bbb01111011FBBBuuuuuuAAAAAA. */ -+{ "setge", 0x207B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setge<.f> 0,b,u6 00100bbb01111011FBBBuuuuuu111110. */ -+{ "setge", 0x207B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setge<.f><.cc> b,b,u6 00100bbb11111011FBBBuuuuuu1QQQQQ. */ -+{ "setge", 0x20FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setge<.f> b,b,s12 00100bbb10111011FBBBssssssSSSSSS. */ -+{ "setge", 0x20BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setge<.f> a,limm,c 0010011000111011F111CCCCCCAAAAAA. */ -+{ "setge", 0x263B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setge<.f> a,b,limm 00100bbb00111011FBBB111110AAAAAA. */ -+{ "setge", 0x203B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setge<.f> 0,limm,c 0010011000111011F111CCCCCC111110. */ -+{ "setge", 0x263B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setge<.f> 0,b,limm 00100bbb00111011FBBB111110111110. */ -+{ "setge", 0x203B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setge<.f><.cc> b,b,limm 00100bbb11111011FBBB1111100QQQQQ. */ -+{ "setge", 0x20FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setge<.f><.cc> 0,limm,c 0010011011111011F111CCCCCC0QQQQQ. */ -+{ "setge", 0x26FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setge<.f> a,limm,u6 0010011001111011F111uuuuuuAAAAAA. */ -+{ "setge", 0x267B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setge<.f> 0,limm,u6 0010011001111011F111uuuuuu111110. */ -+{ "setge", 0x267B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setge<.f><.cc> 0,limm,u6 0010011011111011F111uuuuuu1QQQQQ. */ -+{ "setge", 0x26FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setge<.f> 0,limm,s12 0010011010111011F111ssssssSSSSSS. */ -+{ "setge", 0x26BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setge<.f> a,limm,limm 0010011000111011F111111110AAAAAA. */ -+{ "setge", 0x263B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setge<.f> 0,limm,limm 0010011000111011F111111110111110. */ -+{ "setge", 0x263B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setge<.f><.cc> 0,limm,limm 0010011011111011F1111111100QQQQQ. */ -+{ "setge", 0x26FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setgel<.f> OPERAND_RA,RB,RC 01011bbb00111011FBBBccccccaaaaaa. */ -+{ "setgel", 0x583B0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setgel<.f> 0,RB,RC 01011bbb00111011FBBBcccccc111110. */ -+{ "setgel", 0x583B003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setgel<.f><.cc> OPERAND_RB,RB,RC 01011bbb11111011FBBBcccccc0QQQQQ. */ -+{ "setgel", 0x58FB0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgel<.f> OPERAND_RA,RB,u6 01011bbb01111011FBBBuuuuuuaaaaaa. */ -+{ "setgel", 0x587B0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgel<.f> 0,RB,u6 01011bbb01111011FBBBuuuuuu111110. */ -+{ "setgel", 0x587B003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgel<.f><.cc> OPERAND_RB,RB,u6 01011bbb11111011FBBBuuuuuu1QQQQQ. */ -+{ "setgel", 0x58FB0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgel<.f> OPERAND_RB,RB,s12 01011bbb10111011FBBBssssssSSSSSS. */ -+{ "setgel", 0x58BB0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgel<.f> OPERAND_RA,ximm,RC 0101110000111011F111ccccccaaaaaa. */ -+{ "setgel", 0x5C3B7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgel<.f> OPERAND_RA,RB,ximm 01011bbb00111011FBBB111100aaaaaa. */ -+{ "setgel", 0x583B0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setgel<.f> 0,ximm,RC 0101110000111011F111cccccc111110. */ -+{ "setgel", 0x5C3B703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgel<.f> 0,RB,ximm 01011bbb00111011FBBB111100111110. */ -+{ "setgel", 0x583B0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setgel<.f><.cc> 0,ximm,RC 0101110011111011F111cccccc0QQQQQ. */ -+{ "setgel", 0x5CFB7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgel<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11111011FBBB1111000QQQQQ. */ -+{ "setgel", 0x58FB0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* setgel<.f> OPERAND_RA,ximm,u6 0101110001111011F111uuuuuuaaaaaa. */ -+{ "setgel", 0x5C7B7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgel<.f> 0,ximm,u6 0101110001111011F111uuuuuu111110. */ -+{ "setgel", 0x5C7B703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgel<.f><.cc> 0,ximm,u6 0101110011111011F111uuuuuu1QQQQQ. */ -+{ "setgel", 0x5CFB7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgel<.f> OPERAND_RA,limm,RC 0101111000111011F111ccccccaaaaaa. */ -+{ "setgel", 0x5E3B7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgel<.f> OPERAND_RA,RB,limm 01011bbb00111011FBBB111110aaaaaa. */ -+{ "setgel", 0x583B0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setgel<.f> 0,limm,RC 0101111000111011F111cccccc111110. */ -+{ "setgel", 0x5E3B703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgel<.f> 0,RB,limm 01011bbb00111011FBBB111110111110. */ -+{ "setgel", 0x583B0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setgel<.f><.cc> 0,limm,RC 0101111011111011F111cccccc0QQQQQ. */ -+{ "setgel", 0x5EFB7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgel<.f><.cc> OPERAND_RB,RB,limm 01011bbb11111011FBBB1111100QQQQQ. */ -+{ "setgel", 0x58FB0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setgel<.f> OPERAND_RA,limm,u6 0101111001111011F111uuuuuuaaaaaa. */ -+{ "setgel", 0x5E7B7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgel<.f> 0,limm,u6 0101111001111011F111uuuuuu111110. */ -+{ "setgel", 0x5E7B703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgel<.f><.cc> 0,limm,u6 0101111011111011F111uuuuuu1QQQQQ. */ -+{ "setgel", 0x5EFB7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgel<.f> 0,ximm,s12 0101110010111011F111ssssssSSSSSS. */ -+{ "setgel", 0x5CBB7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgel<.f> 0,limm,s12 0101111010111011F111ssssssSSSSSS. */ -+{ "setgel", 0x5EBB7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgel<.f> OPERAND_RA,ximm,ximm 0101110000111011F111111100aaaaaa. */ -+{ "setgel", 0x5C3B7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setgel<.f> 0,ximm,ximm 0101110000111011F111111100111110. */ -+{ "setgel", 0x5C3B7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setgel<.f><.cc> 0,ximm,ximm 0101110011111011F1111111000QQQQQ. */ -+{ "setgel", 0x5CFB7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* setgel<.f> OPERAND_RA,limm,limm 0101111000111011F111111110aaaaaa. */ -+{ "setgel", 0x5E3B7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setgel<.f> 0,limm,limm 0101111000111011F111111110111110. */ -+{ "setgel", 0x5E3B7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setgel<.f><.cc> 0,limm,limm 0101111011111011F1111111100QQQQQ. */ -+{ "setgel", 0x5EFB7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setgt<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA. */ -+{ "setgt", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setgt<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110. */ -+{ "setgt", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setgt<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ. */ -+{ "setgt", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgt<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA. */ -+{ "setgt", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgt<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110. */ -+{ "setgt", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgt<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ. */ -+{ "setgt", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgt<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS. */ -+{ "setgt", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgt<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA. */ -+{ "setgt", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgt<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA. */ -+{ "setgt", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setgt<.f> 0,limm,c 0010011000111111F111CCCCCC111110. */ -+{ "setgt", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgt<.f> 0,b,limm 00100bbb00111111FBBB111110111110. */ -+{ "setgt", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setgt<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ. */ -+{ "setgt", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setgt<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ. */ -+{ "setgt", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgt<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA. */ -+{ "setgt", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgt<.f> 0,limm,u6 0010011001111111F111uuuuuu111110. */ -+{ "setgt", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgt<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ. */ -+{ "setgt", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgt<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS. */ -+{ "setgt", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgt<.f> a,limm,limm 0010011000111111F111111110AAAAAA. */ -+{ "setgt", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setgt<.f> 0,limm,limm 0010011000111111F111111110111110. */ -+{ "setgt", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setgt<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ. */ -+{ "setgt", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setgtl<.f> OPERAND_RA,RB,RC 01011bbb00111111FBBBccccccaaaaaa. */ -+{ "setgtl", 0x583F0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setgtl<.f> 0,RB,RC 01011bbb00111111FBBBcccccc111110. */ -+{ "setgtl", 0x583F003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setgtl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11111111FBBBcccccc0QQQQQ. */ -+{ "setgtl", 0x58FF0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgtl<.f> OPERAND_RA,RB,u6 01011bbb01111111FBBBuuuuuuaaaaaa. */ -+{ "setgtl", 0x587F0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgtl<.f> 0,RB,u6 01011bbb01111111FBBBuuuuuu111110. */ -+{ "setgtl", 0x587F003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgtl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11111111FBBBuuuuuu1QQQQQ. */ -+{ "setgtl", 0x58FF0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgtl<.f> OPERAND_RB,RB,s12 01011bbb10111111FBBBssssssSSSSSS. */ -+{ "setgtl", 0x58BF0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgtl<.f> OPERAND_RA,ximm,RC 0101110000111111F111ccccccaaaaaa. */ -+{ "setgtl", 0x5C3F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgtl<.f> OPERAND_RA,RB,ximm 01011bbb00111111FBBB111100aaaaaa. */ -+{ "setgtl", 0x583F0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setgtl<.f> 0,ximm,RC 0101110000111111F111cccccc111110. */ -+{ "setgtl", 0x5C3F703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgtl<.f> 0,RB,ximm 01011bbb00111111FBBB111100111110. */ -+{ "setgtl", 0x583F0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setgtl<.f><.cc> 0,ximm,RC 0101110011111111F111cccccc0QQQQQ. */ -+{ "setgtl", 0x5CFF7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgtl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11111111FBBB1111000QQQQQ. */ -+{ "setgtl", 0x58FF0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* setgtl<.f> OPERAND_RA,ximm,u6 0101110001111111F111uuuuuuaaaaaa. */ -+{ "setgtl", 0x5C7F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgtl<.f> 0,ximm,u6 0101110001111111F111uuuuuu111110. */ -+{ "setgtl", 0x5C7F703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgtl<.f><.cc> 0,ximm,u6 0101110011111111F111uuuuuu1QQQQQ. */ -+{ "setgtl", 0x5CFF7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgtl<.f> OPERAND_RA,limm,RC 0101111000111111F111ccccccaaaaaa. */ -+{ "setgtl", 0x5E3F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgtl<.f> OPERAND_RA,RB,limm 01011bbb00111111FBBB111110aaaaaa. */ -+{ "setgtl", 0x583F0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setgtl<.f> 0,limm,RC 0101111000111111F111cccccc111110. */ -+{ "setgtl", 0x5E3F703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgtl<.f> 0,RB,limm 01011bbb00111111FBBB111110111110. */ -+{ "setgtl", 0x583F0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setgtl<.f><.cc> 0,limm,RC 0101111011111111F111cccccc0QQQQQ. */ -+{ "setgtl", 0x5EFF7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgtl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11111111FBBB1111100QQQQQ. */ -+{ "setgtl", 0x58FF0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setgtl<.f> OPERAND_RA,limm,u6 0101111001111111F111uuuuuuaaaaaa. */ -+{ "setgtl", 0x5E7F7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgtl<.f> 0,limm,u6 0101111001111111F111uuuuuu111110. */ -+{ "setgtl", 0x5E7F703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgtl<.f><.cc> 0,limm,u6 0101111011111111F111uuuuuu1QQQQQ. */ -+{ "setgtl", 0x5EFF7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgtl<.f> 0,ximm,s12 0101110010111111F111ssssssSSSSSS. */ -+{ "setgtl", 0x5CBF7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgtl<.f> 0,limm,s12 0101111010111111F111ssssssSSSSSS. */ -+{ "setgtl", 0x5EBF7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgtl<.f> OPERAND_RA,ximm,ximm 0101110000111111F111111100aaaaaa. */ -+{ "setgtl", 0x5C3F7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setgtl<.f> 0,ximm,ximm 0101110000111111F111111100111110. */ -+{ "setgtl", 0x5C3F7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setgtl<.f><.cc> 0,ximm,ximm 0101110011111111F1111111000QQQQQ. */ -+{ "setgtl", 0x5CFF7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* setgtl<.f> OPERAND_RA,limm,limm 0101111000111111F111111110aaaaaa. */ -+{ "setgtl", 0x5E3F7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setgtl<.f> 0,limm,limm 0101111000111111F111111110111110. */ -+{ "setgtl", 0x5E3F7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setgtl<.f><.cc> 0,limm,limm 0101111011111111F1111111100QQQQQ. */ -+{ "setgtl", 0x5EFF7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* seths<.f> a,b,c 00100bbb00111101FBBBCCCCCCAAAAAA. */ -+{ "seths", 0x203D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seths<.f> 0,b,c 00100bbb00111101FBBBCCCCCC111110. */ -+{ "seths", 0x203D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seths<.f><.cc> b,b,c 00100bbb11111101FBBBCCCCCC0QQQQQ. */ -+{ "seths", 0x20FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seths<.f> a,b,u6 00100bbb01111101FBBBuuuuuuAAAAAA. */ -+{ "seths", 0x207D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seths<.f> 0,b,u6 00100bbb01111101FBBBuuuuuu111110. */ -+{ "seths", 0x207D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seths<.f><.cc> b,b,u6 00100bbb11111101FBBBuuuuuu1QQQQQ. */ -+{ "seths", 0x20FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seths<.f> b,b,s12 00100bbb10111101FBBBssssssSSSSSS. */ -+{ "seths", 0x20BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seths<.f> a,limm,c 0010011000111101F111CCCCCCAAAAAA. */ -+{ "seths", 0x263D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seths<.f> a,b,limm 00100bbb00111101FBBB111110AAAAAA. */ -+{ "seths", 0x203D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seths<.f> 0,limm,c 0010011000111101F111CCCCCC111110. */ -+{ "seths", 0x263D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seths<.f> 0,b,limm 00100bbb00111101FBBB111110111110. */ -+{ "seths", 0x203D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seths<.f><.cc> b,b,limm 00100bbb11111101FBBB1111100QQQQQ. */ -+{ "seths", 0x20FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* seths<.f><.cc> 0,limm,c 0010011011111101F111CCCCCC0QQQQQ. */ -+{ "seths", 0x26FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seths<.f> a,limm,u6 0010011001111101F111uuuuuuAAAAAA. */ -+{ "seths", 0x267D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seths<.f> 0,limm,u6 0010011001111101F111uuuuuu111110. */ -+{ "seths", 0x267D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seths<.f><.cc> 0,limm,u6 0010011011111101F111uuuuuu1QQQQQ. */ -+{ "seths", 0x26FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seths<.f> 0,limm,s12 0010011010111101F111ssssssSSSSSS. */ -+{ "seths", 0x26BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seths<.f> a,limm,limm 0010011000111101F111111110AAAAAA. */ -+{ "seths", 0x263D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seths<.f> 0,limm,limm 0010011000111101F111111110111110. */ -+{ "seths", 0x263D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seths<.f><.cc> 0,limm,limm 0010011011111101F1111111100QQQQQ. */ -+{ "seths", 0x26FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sethsl<.f> OPERAND_RA,RB,RC 01011bbb00111101FBBBccccccaaaaaa. */ -+{ "sethsl", 0x583D0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sethsl<.f> 0,RB,RC 01011bbb00111101FBBBcccccc111110. */ -+{ "sethsl", 0x583D003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sethsl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11111101FBBBcccccc0QQQQQ. */ -+{ "sethsl", 0x58FD0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sethsl<.f> OPERAND_RA,RB,u6 01011bbb01111101FBBBuuuuuuaaaaaa. */ -+{ "sethsl", 0x587D0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sethsl<.f> 0,RB,u6 01011bbb01111101FBBBuuuuuu111110. */ -+{ "sethsl", 0x587D003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sethsl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11111101FBBBuuuuuu1QQQQQ. */ -+{ "sethsl", 0x58FD0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sethsl<.f> OPERAND_RB,RB,s12 01011bbb10111101FBBBssssssSSSSSS. */ -+{ "sethsl", 0x58BD0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sethsl<.f> OPERAND_RA,ximm,RC 0101110000111101F111ccccccaaaaaa. */ -+{ "sethsl", 0x5C3D7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sethsl<.f> OPERAND_RA,RB,ximm 01011bbb00111101FBBB111100aaaaaa. */ -+{ "sethsl", 0x583D0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sethsl<.f> 0,ximm,RC 0101110000111101F111cccccc111110. */ -+{ "sethsl", 0x5C3D703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sethsl<.f> 0,RB,ximm 01011bbb00111101FBBB111100111110. */ -+{ "sethsl", 0x583D0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sethsl<.f><.cc> 0,ximm,RC 0101110011111101F111cccccc0QQQQQ. */ -+{ "sethsl", 0x5CFD7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sethsl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11111101FBBB1111000QQQQQ. */ -+{ "sethsl", 0x58FD0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* sethsl<.f> OPERAND_RA,ximm,u6 0101110001111101F111uuuuuuaaaaaa. */ -+{ "sethsl", 0x5C7D7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sethsl<.f> 0,ximm,u6 0101110001111101F111uuuuuu111110. */ -+{ "sethsl", 0x5C7D703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sethsl<.f><.cc> 0,ximm,u6 0101110011111101F111uuuuuu1QQQQQ. */ -+{ "sethsl", 0x5CFD7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sethsl<.f> OPERAND_RA,limm,RC 0101111000111101F111ccccccaaaaaa. */ -+{ "sethsl", 0x5E3D7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sethsl<.f> OPERAND_RA,RB,limm 01011bbb00111101FBBB111110aaaaaa. */ -+{ "sethsl", 0x583D0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sethsl<.f> 0,limm,RC 0101111000111101F111cccccc111110. */ -+{ "sethsl", 0x5E3D703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sethsl<.f> 0,RB,limm 01011bbb00111101FBBB111110111110. */ -+{ "sethsl", 0x583D0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sethsl<.f><.cc> 0,limm,RC 0101111011111101F111cccccc0QQQQQ. */ -+{ "sethsl", 0x5EFD7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sethsl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11111101FBBB1111100QQQQQ. */ -+{ "sethsl", 0x58FD0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sethsl<.f> OPERAND_RA,limm,u6 0101111001111101F111uuuuuuaaaaaa. */ -+{ "sethsl", 0x5E7D7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sethsl<.f> 0,limm,u6 0101111001111101F111uuuuuu111110. */ -+{ "sethsl", 0x5E7D703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sethsl<.f><.cc> 0,limm,u6 0101111011111101F111uuuuuu1QQQQQ. */ -+{ "sethsl", 0x5EFD7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sethsl<.f> 0,ximm,s12 0101110010111101F111ssssssSSSSSS. */ -+{ "sethsl", 0x5CBD7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sethsl<.f> 0,limm,s12 0101111010111101F111ssssssSSSSSS. */ -+{ "sethsl", 0x5EBD7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sethsl<.f> OPERAND_RA,ximm,ximm 0101110000111101F111111100aaaaaa. */ -+{ "sethsl", 0x5C3D7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sethsl<.f> 0,ximm,ximm 0101110000111101F111111100111110. */ -+{ "sethsl", 0x5C3D7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sethsl<.f><.cc> 0,ximm,ximm 0101110011111101F1111111000QQQQQ. */ -+{ "sethsl", 0x5CFD7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* sethsl<.f> OPERAND_RA,limm,limm 0101111000111101F111111110aaaaaa. */ -+{ "sethsl", 0x5E3D7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sethsl<.f> 0,limm,limm 0101111000111101F111111110111110. */ -+{ "sethsl", 0x5E3D7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sethsl<.f><.cc> 0,limm,limm 0101111011111101F1111111100QQQQQ. */ -+{ "sethsl", 0x5EFD7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* seti c 00100110001011110000CCCCCC111111. */ -+{ "seti", 0x262F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* seti u6 00100110011011110000uuuuuu111111. */ -+{ "seti", 0x266F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* seti limm 00100110001011110000111110111111. */ -+{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* seti 00100110011011110000000000111111. */ -+{ "seti", 0x266F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */ -+{ "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setle<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110. */ -+{ "setle", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setle<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ. */ -+{ "setle", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setle<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA. */ -+{ "setle", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setle<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110. */ -+{ "setle", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setle<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ. */ -+{ "setle", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setle<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS. */ -+{ "setle", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setle<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA. */ -+{ "setle", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setle<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA. */ -+{ "setle", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setle<.f> 0,limm,c 0010011000111110F111CCCCCC111110. */ -+{ "setle", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setle<.f> 0,b,limm 00100bbb00111110FBBB111110111110. */ -+{ "setle", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setle<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ. */ -+{ "setle", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setle<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ. */ -+{ "setle", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setle<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA. */ -+{ "setle", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setle<.f> 0,limm,u6 0010011001111110F111uuuuuu111110. */ -+{ "setle", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setle<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ. */ -+{ "setle", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setle<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS. */ -+{ "setle", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setle<.f> a,limm,limm 0010011000111110F111111110AAAAAA. */ -+{ "setle", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setle<.f> 0,limm,limm 0010011000111110F111111110111110. */ -+{ "setle", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setle<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ. */ -+{ "setle", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setlel<.f> OPERAND_RA,RB,RC 01011bbb00111110FBBBccccccaaaaaa. */ -+{ "setlel", 0x583E0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlel<.f> 0,RB,RC 01011bbb00111110FBBBcccccc111110. */ -+{ "setlel", 0x583E003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlel<.f><.cc> OPERAND_RB,RB,RC 01011bbb11111110FBBBcccccc0QQQQQ. */ -+{ "setlel", 0x58FE0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlel<.f> OPERAND_RA,RB,u6 01011bbb01111110FBBBuuuuuuaaaaaa. */ -+{ "setlel", 0x587E0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlel<.f> 0,RB,u6 01011bbb01111110FBBBuuuuuu111110. */ -+{ "setlel", 0x587E003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlel<.f><.cc> OPERAND_RB,RB,u6 01011bbb11111110FBBBuuuuuu1QQQQQ. */ -+{ "setlel", 0x58FE0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlel<.f> OPERAND_RB,RB,s12 01011bbb10111110FBBBssssssSSSSSS. */ -+{ "setlel", 0x58BE0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlel<.f> OPERAND_RA,ximm,RC 0101110000111110F111ccccccaaaaaa. */ -+{ "setlel", 0x5C3E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlel<.f> OPERAND_RA,RB,ximm 01011bbb00111110FBBB111100aaaaaa. */ -+{ "setlel", 0x583E0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setlel<.f> 0,ximm,RC 0101110000111110F111cccccc111110. */ -+{ "setlel", 0x5C3E703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlel<.f> 0,RB,ximm 01011bbb00111110FBBB111100111110. */ -+{ "setlel", 0x583E0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setlel<.f><.cc> 0,ximm,RC 0101110011111110F111cccccc0QQQQQ. */ -+{ "setlel", 0x5CFE7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlel<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11111110FBBB1111000QQQQQ. */ -+{ "setlel", 0x58FE0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* setlel<.f> OPERAND_RA,ximm,u6 0101110001111110F111uuuuuuaaaaaa. */ -+{ "setlel", 0x5C7E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlel<.f> 0,ximm,u6 0101110001111110F111uuuuuu111110. */ -+{ "setlel", 0x5C7E703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlel<.f><.cc> 0,ximm,u6 0101110011111110F111uuuuuu1QQQQQ. */ -+{ "setlel", 0x5CFE7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlel<.f> OPERAND_RA,limm,RC 0101111000111110F111ccccccaaaaaa. */ -+{ "setlel", 0x5E3E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlel<.f> OPERAND_RA,RB,limm 01011bbb00111110FBBB111110aaaaaa. */ -+{ "setlel", 0x583E0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlel<.f> 0,limm,RC 0101111000111110F111cccccc111110. */ -+{ "setlel", 0x5E3E703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlel<.f> 0,RB,limm 01011bbb00111110FBBB111110111110. */ -+{ "setlel", 0x583E0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlel<.f><.cc> 0,limm,RC 0101111011111110F111cccccc0QQQQQ. */ -+{ "setlel", 0x5EFE7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlel<.f><.cc> OPERAND_RB,RB,limm 01011bbb11111110FBBB1111100QQQQQ. */ -+{ "setlel", 0x58FE0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setlel<.f> OPERAND_RA,limm,u6 0101111001111110F111uuuuuuaaaaaa. */ -+{ "setlel", 0x5E7E7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlel<.f> 0,limm,u6 0101111001111110F111uuuuuu111110. */ -+{ "setlel", 0x5E7E703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlel<.f><.cc> 0,limm,u6 0101111011111110F111uuuuuu1QQQQQ. */ -+{ "setlel", 0x5EFE7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlel<.f> 0,ximm,s12 0101110010111110F111ssssssSSSSSS. */ -+{ "setlel", 0x5CBE7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlel<.f> 0,limm,s12 0101111010111110F111ssssssSSSSSS. */ -+{ "setlel", 0x5EBE7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlel<.f> OPERAND_RA,ximm,ximm 0101110000111110F111111100aaaaaa. */ -+{ "setlel", 0x5C3E7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setlel<.f> 0,ximm,ximm 0101110000111110F111111100111110. */ -+{ "setlel", 0x5C3E7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setlel<.f><.cc> 0,ximm,ximm 0101110011111110F1111111000QQQQQ. */ -+{ "setlel", 0x5CFE7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* setlel<.f> OPERAND_RA,limm,limm 0101111000111110F111111110aaaaaa. */ -+{ "setlel", 0x5E3E7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlel<.f> 0,limm,limm 0101111000111110F111111110111110. */ -+{ "setlel", 0x5E3E7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlel<.f><.cc> 0,limm,limm 0101111011111110F1111111100QQQQQ. */ -+{ "setlel", 0x5EFE7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setlo<.f> a,b,c 00100bbb00111100FBBBCCCCCCAAAAAA. */ -+{ "setlo", 0x203C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlo<.f> 0,b,c 00100bbb00111100FBBBCCCCCC111110. */ -+{ "setlo", 0x203C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlo<.f><.cc> b,b,c 00100bbb11111100FBBBCCCCCC0QQQQQ. */ -+{ "setlo", 0x20FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlo<.f> a,b,u6 00100bbb01111100FBBBuuuuuuAAAAAA. */ -+{ "setlo", 0x207C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlo<.f> 0,b,u6 00100bbb01111100FBBBuuuuuu111110. */ -+{ "setlo", 0x207C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlo<.f><.cc> b,b,u6 00100bbb11111100FBBBuuuuuu1QQQQQ. */ -+{ "setlo", 0x20FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlo<.f> b,b,s12 00100bbb10111100FBBBssssssSSSSSS. */ -+{ "setlo", 0x20BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlo<.f> a,limm,c 0010011000111100F111CCCCCCAAAAAA. */ -+{ "setlo", 0x263C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlo<.f> a,b,limm 00100bbb00111100FBBB111110AAAAAA. */ -+{ "setlo", 0x203C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlo<.f> 0,limm,c 0010011000111100F111CCCCCC111110. */ -+{ "setlo", 0x263C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlo<.f> 0,b,limm 00100bbb00111100FBBB111110111110. */ -+{ "setlo", 0x203C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlo<.f><.cc> b,b,limm 00100bbb11111100FBBB1111100QQQQQ. */ -+{ "setlo", 0x20FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setlo<.f><.cc> 0,limm,c 0010011011111100F111CCCCCC0QQQQQ. */ -+{ "setlo", 0x26FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlo<.f> a,limm,u6 0010011001111100F111uuuuuuAAAAAA. */ -+{ "setlo", 0x267C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlo<.f> 0,limm,u6 0010011001111100F111uuuuuu111110. */ -+{ "setlo", 0x267C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlo<.f><.cc> 0,limm,u6 0010011011111100F111uuuuuu1QQQQQ. */ -+{ "setlo", 0x26FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlo<.f> 0,limm,s12 0010011010111100F111ssssssSSSSSS. */ -+{ "setlo", 0x26BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlo<.f> a,limm,limm 0010011000111100F111111110AAAAAA. */ -+{ "setlo", 0x263C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlo<.f> 0,limm,limm 0010011000111100F111111110111110. */ -+{ "setlo", 0x263C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlo<.f><.cc> 0,limm,limm 0010011011111100F1111111100QQQQQ. */ -+{ "setlo", 0x26FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setlol<.f> OPERAND_RA,RB,RC 01011bbb00111100FBBBccccccaaaaaa. */ -+{ "setlol", 0x583C0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlol<.f> 0,RB,RC 01011bbb00111100FBBBcccccc111110. */ -+{ "setlol", 0x583C003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlol<.f><.cc> OPERAND_RB,RB,RC 01011bbb11111100FBBBcccccc0QQQQQ. */ -+{ "setlol", 0x58FC0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlol<.f> OPERAND_RA,RB,u6 01011bbb01111100FBBBuuuuuuaaaaaa. */ -+{ "setlol", 0x587C0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlol<.f> 0,RB,u6 01011bbb01111100FBBBuuuuuu111110. */ -+{ "setlol", 0x587C003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlol<.f><.cc> OPERAND_RB,RB,u6 01011bbb11111100FBBBuuuuuu1QQQQQ. */ -+{ "setlol", 0x58FC0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlol<.f> OPERAND_RB,RB,s12 01011bbb10111100FBBBssssssSSSSSS. */ -+{ "setlol", 0x58BC0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlol<.f> OPERAND_RA,ximm,RC 0101110000111100F111ccccccaaaaaa. */ -+{ "setlol", 0x5C3C7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlol<.f> OPERAND_RA,RB,ximm 01011bbb00111100FBBB111100aaaaaa. */ -+{ "setlol", 0x583C0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setlol<.f> 0,ximm,RC 0101110000111100F111cccccc111110. */ -+{ "setlol", 0x5C3C703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlol<.f> 0,RB,ximm 01011bbb00111100FBBB111100111110. */ -+{ "setlol", 0x583C0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setlol<.f><.cc> 0,ximm,RC 0101110011111100F111cccccc0QQQQQ. */ -+{ "setlol", 0x5CFC7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlol<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11111100FBBB1111000QQQQQ. */ -+{ "setlol", 0x58FC0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* setlol<.f> OPERAND_RA,ximm,u6 0101110001111100F111uuuuuuaaaaaa. */ -+{ "setlol", 0x5C7C7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlol<.f> 0,ximm,u6 0101110001111100F111uuuuuu111110. */ -+{ "setlol", 0x5C7C703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlol<.f><.cc> 0,ximm,u6 0101110011111100F111uuuuuu1QQQQQ. */ -+{ "setlol", 0x5CFC7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlol<.f> OPERAND_RA,limm,RC 0101111000111100F111ccccccaaaaaa. */ -+{ "setlol", 0x5E3C7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlol<.f> OPERAND_RA,RB,limm 01011bbb00111100FBBB111110aaaaaa. */ -+{ "setlol", 0x583C0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlol<.f> 0,limm,RC 0101111000111100F111cccccc111110. */ -+{ "setlol", 0x5E3C703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlol<.f> 0,RB,limm 01011bbb00111100FBBB111110111110. */ -+{ "setlol", 0x583C0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlol<.f><.cc> 0,limm,RC 0101111011111100F111cccccc0QQQQQ. */ -+{ "setlol", 0x5EFC7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlol<.f><.cc> OPERAND_RB,RB,limm 01011bbb11111100FBBB1111100QQQQQ. */ -+{ "setlol", 0x58FC0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setlol<.f> OPERAND_RA,limm,u6 0101111001111100F111uuuuuuaaaaaa. */ -+{ "setlol", 0x5E7C7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlol<.f> 0,limm,u6 0101111001111100F111uuuuuu111110. */ -+{ "setlol", 0x5E7C703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlol<.f><.cc> 0,limm,u6 0101111011111100F111uuuuuu1QQQQQ. */ -+{ "setlol", 0x5EFC7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlol<.f> 0,ximm,s12 0101110010111100F111ssssssSSSSSS. */ -+{ "setlol", 0x5CBC7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlol<.f> 0,limm,s12 0101111010111100F111ssssssSSSSSS. */ -+{ "setlol", 0x5EBC7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlol<.f> OPERAND_RA,ximm,ximm 0101110000111100F111111100aaaaaa. */ -+{ "setlol", 0x5C3C7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setlol<.f> 0,ximm,ximm 0101110000111100F111111100111110. */ -+{ "setlol", 0x5C3C7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setlol<.f><.cc> 0,ximm,ximm 0101110011111100F1111111000QQQQQ. */ -+{ "setlol", 0x5CFC7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* setlol<.f> OPERAND_RA,limm,limm 0101111000111100F111111110aaaaaa. */ -+{ "setlol", 0x5E3C7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlol<.f> 0,limm,limm 0101111000111100F111111110111110. */ -+{ "setlol", 0x5E3C7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlol<.f><.cc> 0,limm,limm 0101111011111100F1111111100QQQQQ. */ -+{ "setlol", 0x5EFC7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setlt<.f> a,b,c 00100bbb00111010FBBBCCCCCCAAAAAA. */ -+{ "setlt", 0x203A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlt<.f> 0,b,c 00100bbb00111010FBBBCCCCCC111110. */ -+{ "setlt", 0x203A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlt<.f><.cc> b,b,c 00100bbb11111010FBBBCCCCCC0QQQQQ. */ -+{ "setlt", 0x20FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlt<.f> a,b,u6 00100bbb01111010FBBBuuuuuuAAAAAA. */ -+{ "setlt", 0x207A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlt<.f> 0,b,u6 00100bbb01111010FBBBuuuuuu111110. */ -+{ "setlt", 0x207A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlt<.f><.cc> b,b,u6 00100bbb11111010FBBBuuuuuu1QQQQQ. */ -+{ "setlt", 0x20FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlt<.f> b,b,s12 00100bbb10111010FBBBssssssSSSSSS. */ -+{ "setlt", 0x20BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlt<.f> a,limm,c 0010011000111010F111CCCCCCAAAAAA. */ -+{ "setlt", 0x263A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlt<.f> a,b,limm 00100bbb00111010FBBB111110AAAAAA. */ -+{ "setlt", 0x203A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlt<.f> 0,limm,c 0010011000111010F111CCCCCC111110. */ -+{ "setlt", 0x263A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlt<.f> 0,b,limm 00100bbb00111010FBBB111110111110. */ -+{ "setlt", 0x203A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlt<.f><.cc> b,b,limm 00100bbb11111010FBBB1111100QQQQQ. */ -+{ "setlt", 0x20FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setlt<.f><.cc> 0,limm,c 0010011011111010F111CCCCCC0QQQQQ. */ -+{ "setlt", 0x26FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlt<.f> a,limm,u6 0010011001111010F111uuuuuuAAAAAA. */ -+{ "setlt", 0x267A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlt<.f> 0,limm,u6 0010011001111010F111uuuuuu111110. */ -+{ "setlt", 0x267A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlt<.f><.cc> 0,limm,u6 0010011011111010F111uuuuuu1QQQQQ. */ -+{ "setlt", 0x26FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlt<.f> 0,limm,s12 0010011010111010F111ssssssSSSSSS. */ -+{ "setlt", 0x26BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlt<.f> a,limm,limm 0010011000111010F111111110AAAAAA. */ -+{ "setlt", 0x263A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlt<.f> 0,limm,limm 0010011000111010F111111110111110. */ -+{ "setlt", 0x263A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlt<.f><.cc> 0,limm,limm 0010011011111010F1111111100QQQQQ. */ -+{ "setlt", 0x26FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setltl<.f> OPERAND_RA,RB,RC 01011bbb00111010FBBBccccccaaaaaa. */ -+{ "setltl", 0x583A0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setltl<.f> 0,RB,RC 01011bbb00111010FBBBcccccc111110. */ -+{ "setltl", 0x583A003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setltl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11111010FBBBcccccc0QQQQQ. */ -+{ "setltl", 0x58FA0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setltl<.f> OPERAND_RA,RB,u6 01011bbb01111010FBBBuuuuuuaaaaaa. */ -+{ "setltl", 0x587A0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setltl<.f> 0,RB,u6 01011bbb01111010FBBBuuuuuu111110. */ -+{ "setltl", 0x587A003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setltl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11111010FBBBuuuuuu1QQQQQ. */ -+{ "setltl", 0x58FA0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setltl<.f> OPERAND_RB,RB,s12 01011bbb10111010FBBBssssssSSSSSS. */ -+{ "setltl", 0x58BA0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setltl<.f> OPERAND_RA,ximm,RC 0101110000111010F111ccccccaaaaaa. */ -+{ "setltl", 0x5C3A7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setltl<.f> OPERAND_RA,RB,ximm 01011bbb00111010FBBB111100aaaaaa. */ -+{ "setltl", 0x583A0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setltl<.f> 0,ximm,RC 0101110000111010F111cccccc111110. */ -+{ "setltl", 0x5C3A703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setltl<.f> 0,RB,ximm 01011bbb00111010FBBB111100111110. */ -+{ "setltl", 0x583A0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setltl<.f><.cc> 0,ximm,RC 0101110011111010F111cccccc0QQQQQ. */ -+{ "setltl", 0x5CFA7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setltl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11111010FBBB1111000QQQQQ. */ -+{ "setltl", 0x58FA0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* setltl<.f> OPERAND_RA,ximm,u6 0101110001111010F111uuuuuuaaaaaa. */ -+{ "setltl", 0x5C7A7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setltl<.f> 0,ximm,u6 0101110001111010F111uuuuuu111110. */ -+{ "setltl", 0x5C7A703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setltl<.f><.cc> 0,ximm,u6 0101110011111010F111uuuuuu1QQQQQ. */ -+{ "setltl", 0x5CFA7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setltl<.f> OPERAND_RA,limm,RC 0101111000111010F111ccccccaaaaaa. */ -+{ "setltl", 0x5E3A7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setltl<.f> OPERAND_RA,RB,limm 01011bbb00111010FBBB111110aaaaaa. */ -+{ "setltl", 0x583A0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setltl<.f> 0,limm,RC 0101111000111010F111cccccc111110. */ -+{ "setltl", 0x5E3A703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setltl<.f> 0,RB,limm 01011bbb00111010FBBB111110111110. */ -+{ "setltl", 0x583A0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setltl<.f><.cc> 0,limm,RC 0101111011111010F111cccccc0QQQQQ. */ -+{ "setltl", 0x5EFA7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setltl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11111010FBBB1111100QQQQQ. */ -+{ "setltl", 0x58FA0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setltl<.f> OPERAND_RA,limm,u6 0101111001111010F111uuuuuuaaaaaa. */ -+{ "setltl", 0x5E7A7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setltl<.f> 0,limm,u6 0101111001111010F111uuuuuu111110. */ -+{ "setltl", 0x5E7A703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setltl<.f><.cc> 0,limm,u6 0101111011111010F111uuuuuu1QQQQQ. */ -+{ "setltl", 0x5EFA7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setltl<.f> 0,ximm,s12 0101110010111010F111ssssssSSSSSS. */ -+{ "setltl", 0x5CBA7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setltl<.f> 0,limm,s12 0101111010111010F111ssssssSSSSSS. */ -+{ "setltl", 0x5EBA7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setltl<.f> OPERAND_RA,ximm,ximm 0101110000111010F111111100aaaaaa. */ -+{ "setltl", 0x5C3A7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setltl<.f> 0,ximm,ximm 0101110000111010F111111100111110. */ -+{ "setltl", 0x5C3A7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setltl<.f><.cc> 0,ximm,ximm 0101110011111010F1111111000QQQQQ. */ -+{ "setltl", 0x5CFA7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* setltl<.f> OPERAND_RA,limm,limm 0101111000111010F111111110aaaaaa. */ -+{ "setltl", 0x5E3A7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setltl<.f> 0,limm,limm 0101111000111010F111111110111110. */ -+{ "setltl", 0x5E3A7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setltl<.f><.cc> 0,limm,limm 0101111011111010F1111111100QQQQQ. */ -+{ "setltl", 0x5EFA7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setne<.f> a,b,c 00100bbb00111001FBBBCCCCCCAAAAAA. */ -+{ "setne", 0x20390000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setne<.f> 0,b,c 00100bbb00111001FBBBCCCCCC111110. */ -+{ "setne", 0x2039003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setne<.f><.cc> b,b,c 00100bbb11111001FBBBCCCCCC0QQQQQ. */ -+{ "setne", 0x20F90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setne<.f> a,b,u6 00100bbb01111001FBBBuuuuuuAAAAAA. */ -+{ "setne", 0x20790000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setne<.f> 0,b,u6 00100bbb01111001FBBBuuuuuu111110. */ -+{ "setne", 0x2079003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setne<.f><.cc> b,b,u6 00100bbb11111001FBBBuuuuuu1QQQQQ. */ -+{ "setne", 0x20F90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setne<.f> b,b,s12 00100bbb10111001FBBBssssssSSSSSS. */ -+{ "setne", 0x20B90000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setne<.f> a,limm,c 0010011000111001F111CCCCCCAAAAAA. */ -+{ "setne", 0x26397000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setne<.f> a,b,limm 00100bbb00111001FBBB111110AAAAAA. */ -+{ "setne", 0x20390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setne<.f> 0,limm,c 0010011000111001F111CCCCCC111110. */ -+{ "setne", 0x2639703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setne<.f> 0,b,limm 00100bbb00111001FBBB111110111110. */ -+{ "setne", 0x20390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setne<.f><.cc> b,b,limm 00100bbb11111001FBBB1111100QQQQQ. */ -+{ "setne", 0x20F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setne<.f><.cc> 0,limm,c 0010011011111001F111CCCCCC0QQQQQ. */ -+{ "setne", 0x26F97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setne<.f> a,limm,u6 0010011001111001F111uuuuuuAAAAAA. */ -+{ "setne", 0x26797000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setne<.f> 0,limm,u6 0010011001111001F111uuuuuu111110. */ -+{ "setne", 0x2679703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setne<.f><.cc> 0,limm,u6 0010011011111001F111uuuuuu1QQQQQ. */ -+{ "setne", 0x26F97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setne<.f> 0,limm,s12 0010011010111001F111ssssssSSSSSS. */ -+{ "setne", 0x26B97000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setne<.f> a,limm,limm 0010011000111001F111111110AAAAAA. */ -+{ "setne", 0x26397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setne<.f> 0,limm,limm 0010011000111001F111111110111110. */ -+{ "setne", 0x26397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setne<.f><.cc> 0,limm,limm 0010011011111001F1111111100QQQQQ. */ -+{ "setne", 0x26F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setnel<.f> OPERAND_RA,RB,RC 01011bbb00111001FBBBccccccaaaaaa. */ -+{ "setnel", 0x58390000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setnel<.f> 0,RB,RC 01011bbb00111001FBBBcccccc111110. */ -+{ "setnel", 0x5839003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setnel<.f><.cc> OPERAND_RB,RB,RC 01011bbb11111001FBBBcccccc0QQQQQ. */ -+{ "setnel", 0x58F90000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setnel<.f> OPERAND_RA,RB,u6 01011bbb01111001FBBBuuuuuuaaaaaa. */ -+{ "setnel", 0x58790000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setnel<.f> 0,RB,u6 01011bbb01111001FBBBuuuuuu111110. */ -+{ "setnel", 0x5879003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setnel<.f><.cc> OPERAND_RB,RB,u6 01011bbb11111001FBBBuuuuuu1QQQQQ. */ -+{ "setnel", 0x58F90020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setnel<.f> OPERAND_RB,RB,s12 01011bbb10111001FBBBssssssSSSSSS. */ -+{ "setnel", 0x58B90000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setnel<.f> OPERAND_RA,ximm,RC 0101110000111001F111ccccccaaaaaa. */ -+{ "setnel", 0x5C397000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setnel<.f> OPERAND_RA,RB,ximm 01011bbb00111001FBBB111100aaaaaa. */ -+{ "setnel", 0x58390F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setnel<.f> 0,ximm,RC 0101110000111001F111cccccc111110. */ -+{ "setnel", 0x5C39703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* setnel<.f> 0,RB,ximm 01011bbb00111001FBBB111100111110. */ -+{ "setnel", 0x58390F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* setnel<.f><.cc> 0,ximm,RC 0101110011111001F111cccccc0QQQQQ. */ -+{ "setnel", 0x5CF97000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setnel<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11111001FBBB1111000QQQQQ. */ -+{ "setnel", 0x58F90F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* setnel<.f> OPERAND_RA,ximm,u6 0101110001111001F111uuuuuuaaaaaa. */ -+{ "setnel", 0x5C797000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setnel<.f> 0,ximm,u6 0101110001111001F111uuuuuu111110. */ -+{ "setnel", 0x5C79703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setnel<.f><.cc> 0,ximm,u6 0101110011111001F111uuuuuu1QQQQQ. */ -+{ "setnel", 0x5CF97020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setnel<.f> OPERAND_RA,limm,RC 0101111000111001F111ccccccaaaaaa. */ -+{ "setnel", 0x5E397000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setnel<.f> OPERAND_RA,RB,limm 01011bbb00111001FBBB111110aaaaaa. */ -+{ "setnel", 0x58390F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setnel<.f> 0,limm,RC 0101111000111001F111cccccc111110. */ -+{ "setnel", 0x5E39703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setnel<.f> 0,RB,limm 01011bbb00111001FBBB111110111110. */ -+{ "setnel", 0x58390FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setnel<.f><.cc> 0,limm,RC 0101111011111001F111cccccc0QQQQQ. */ -+{ "setnel", 0x5EF97000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setnel<.f><.cc> OPERAND_RB,RB,limm 01011bbb11111001FBBB1111100QQQQQ. */ -+{ "setnel", 0x58F90F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setnel<.f> OPERAND_RA,limm,u6 0101111001111001F111uuuuuuaaaaaa. */ -+{ "setnel", 0x5E797000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setnel<.f> 0,limm,u6 0101111001111001F111uuuuuu111110. */ -+{ "setnel", 0x5E79703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setnel<.f><.cc> 0,limm,u6 0101111011111001F111uuuuuu1QQQQQ. */ -+{ "setnel", 0x5EF97020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setnel<.f> 0,ximm,s12 0101110010111001F111ssssssSSSSSS. */ -+{ "setnel", 0x5CB97000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setnel<.f> 0,limm,s12 0101111010111001F111ssssssSSSSSS. */ -+{ "setnel", 0x5EB97000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setnel<.f> OPERAND_RA,ximm,ximm 0101110000111001F111111100aaaaaa. */ -+{ "setnel", 0x5C397F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setnel<.f> 0,ximm,ximm 0101110000111001F111111100111110. */ -+{ "setnel", 0x5C397F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* setnel<.f><.cc> 0,ximm,ximm 0101110011111001F1111111000QQQQQ. */ -+{ "setnel", 0x5CF97F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* setnel<.f> OPERAND_RA,limm,limm 0101111000111001F111111110aaaaaa. */ -+{ "setnel", 0x5E397F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setnel<.f> 0,limm,limm 0101111000111001F111111110111110. */ -+{ "setnel", 0x5E397FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setnel<.f><.cc> 0,limm,limm 0101111011111001F1111111100QQQQQ. */ -+{ "setnel", 0x5EF97F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sexb<.f> b,c 00100bbb00101111FBBBCCCCCC000101. */ -+{ "sexb", 0x202F0005, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sexb<.f> 0,c 0010011000101111F111CCCCCC000101. */ -+{ "sexb", 0x262F7005, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sexb<.f> b,u6 00100bbb01101111FBBBuuuuuu000101. */ -+{ "sexb", 0x206F0005, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexb<.f> 0,u6 0010011001101111F111uuuuuu000101. */ -+{ "sexb", 0x266F7005, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexb<.f> b,limm 00100bbb00101111FBBB111110000101. */ -+{ "sexb", 0x202F0F85, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sexb<.f> 0,limm 0010011000101111F111111110000101. */ -+{ "sexb", 0x262F7F85, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sexbl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc000101. */ -+{ "sexbl", 0x582F0005, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sexbl<.f> 0,RC 0101111000101111F111cccccc000101. */ -+{ "sexbl", 0x5E2F7005, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sexbl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu000101. */ -+{ "sexbl", 0x586F0005, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexbl<.f> 0,u6 0101111001101111F111uuuuuu000101. */ -+{ "sexbl", 0x5E6F7005, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexbl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100000101. */ -+{ "sexbl", 0x582F0F05, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sexbl<.f> 0,ximm 0101111000101111F111111100000101. */ -+{ "sexbl", 0x5E2F7F05, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* sexbl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110000101. */ -+{ "sexbl", 0x582F0F85, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sexbl<.f> 0,limm 0101111000101111F111111110000101. */ -+{ "sexbl", 0x5E2F7F85, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sexb_s b,c 01111bbbccc01101. */ -+{ "sexb_s", 0x0000780D, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* sexh<.f> b,c 00100bbb00101111FBBBCCCCCC000110. */ -+{ "sexh", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sexh<.f> 0,c 0010011000101111F111CCCCCC000110. */ -+{ "sexh", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sexh<.f> b,u6 00100bbb01101111FBBBuuuuuu000110. */ -+{ "sexh", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexh<.f> 0,u6 0010011001101111F111uuuuuu000110. */ -+{ "sexh", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexh<.f> b,limm 00100bbb00101111FBBB111110000110. */ -+{ "sexh", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sexh<.f> 0,limm 0010011000101111F111111110000110. */ -+{ "sexh", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sexhl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc000110. */ -+{ "sexhl", 0x582F0006, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sexhl<.f> 0,RC 0101111000101111F111cccccc000110. */ -+{ "sexhl", 0x5E2F7006, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sexhl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu000110. */ -+{ "sexhl", 0x586F0006, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexhl<.f> 0,u6 0101111001101111F111uuuuuu000110. */ -+{ "sexhl", 0x5E6F7006, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexhl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100000110. */ -+{ "sexhl", 0x582F0F06, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sexhl<.f> 0,ximm 0101111000101111F111111100000110. */ -+{ "sexhl", 0x5E2F7F06, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* sexhl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110000110. */ -+{ "sexhl", 0x582F0F86, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sexhl<.f> 0,limm 0101111000101111F111111110000110. */ -+{ "sexhl", 0x5E2F7F86, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sexh_s b,c 01111bbbccc01110. */ -+{ "sexh_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* sexwl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc000111. */ -+{ "sexwl", 0x582F0007, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sexwl<.f> 0,RC 0101111000101111F111cccccc000111. */ -+{ "sexwl", 0x5E2F7007, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sexwl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu000111. */ -+{ "sexwl", 0x586F0007, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexwl<.f> 0,u6 0101111001101111F111uuuuuu000111. */ -+{ "sexwl", 0x5E6F7007, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexwl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100000111. */ -+{ "sexwl", 0x582F0F07, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sexwl<.f> 0,ximm 0101111000101111F111111100000111. */ -+{ "sexwl", 0x5E2F7F07, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* sexwl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110000111. */ -+{ "sexwl", 0x582F0F87, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sexwl<.f> 0,limm 0101111000101111F111111110000111. */ -+{ "sexwl", 0x5E2F7F87, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sleep c 00100001001011110000CCCCCC111111. */ -+{ "sleep", 0x212F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* sleep u6 00100001011011110000uuuuuu111111. */ -+{ "sleep", 0x216F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* sleep limm 00100001001011110000111110111111. */ -+{ "sleep", 0x212F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* sleep 00100001011011110000000000111111. */ -+{ "sleep", 0x216F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* sqrt<.f> b,c 00101bbb00101111FBBBCCCCCC110000. */ -+{ "sqrt", 0x282F0030, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* sqrt<.f> 0,c 0010111000101111F111CCCCCC110000. */ -+{ "sqrt", 0x2E2F7030, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sqrt<.f> b,u6 00101bbb01101111FBBBuuuuuu110000. */ -+{ "sqrt", 0x286F0030, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sqrt<.f> 0,u6 0010111001101111F111uuuuuu110000. */ -+{ "sqrt", 0x2E6F7030, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sqrt<.f> b,limm 00101bbb00101111FBBB111110110000. */ -+{ "sqrt", 0x282F0FB0, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* sqrt<.f> 0,limm 0010111000101111F111111110110000. */ -+{ "sqrt", 0x2E2F7FB0, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sqrtf<.f> b,c 00101bbb00101111FBBBCCCCCC110001. */ -+{ "sqrtf", 0x282F0031, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* sqrtf<.f> 0,c 0010111000101111F111CCCCCC110001. */ -+{ "sqrtf", 0x2E2F7031, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sqrtf<.f> b,u6 00101bbb01101111FBBBuuuuuu110001. */ -+{ "sqrtf", 0x286F0031, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sqrtf<.f> 0,u6 0010111001101111F111uuuuuu110001. */ -+{ "sqrtf", 0x2E6F7031, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sqrtf<.f> b,limm 00101bbb00101111FBBB111110110001. */ -+{ "sqrtf", 0x282F0FB1, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* sqrtf<.f> 0,limm 0010111000101111F111111110110001. */ -+{ "sqrtf", 0x2E2F7FB1, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sr b,c 00100bbb00101011RBBBCCCCCCRRRRRR. */ -+{ "sr", 0x202B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,u6 00100bbb01101011RBBBuuuuuu000000. */ -+{ "sr", 0x206B0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,s12 00100bbb10101011RBBBssssssSSSSSS. */ -+{ "sr", 0x20AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,c 0010011000101011R111CCCCCCRRRRRR. */ -+{ "sr", 0x262B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,limm 00100bbb00101011RBBB111110RRRRRR. */ -+{ "sr", 0x202B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,u6 0010011001101011R111uuuuuu000000. */ -+{ "sr", 0x266B7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,s12 0010011010101011R111ssssssSSSSSS. */ -+{ "sr", 0x26AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,limm 0010011000101011R111111110RRRRRR. */ -+{ "sr", 0x262B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* srl OPERAND_RB,RC 01011bbb001010110BBBccccccRRRRRR. */ -+{ "srl", 0x582B0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* srl OPERAND_RB,u6 01011bbb011010110BBBuuuuuuRRRRRR. */ -+{ "srl", 0x586B0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* srl OPERAND_RB,s12 01011bbb101010110BBBssssssSSSSSS. */ -+{ "srl", 0x58AB0000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* srl OPERAND_RB,ximm 01011bbb001010110BBB111100RRRRRR. */ -+{ "srl", 0x582B0F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_XIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* srl OPERAND_RB,limm 01011bbb001010110BBB111110RRRRRR. */ -+{ "srl", 0x582B0F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* st<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaaZZ0. */ -+{ "st", 0x18000000, 0xF8FF8001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaaZZ1. */ -+{ "st", 0x18000001, 0xF8FF8001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZ0. */ -+{ "st", 0x18000000, 0xF8000001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaaZZ1. */ -+{ "st", 0x18000001, 0xF8000001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di> c,limm 00011110000000000111CCCCCCDRRZZ0. */ -+{ "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }}, -+ -+/* st<.di> w6,limm 00011110000000000111wwwwwwDRRZZ1. */ -+{ "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }}, -+ -+/* st<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110DaaZZ0. */ -+{ "st", 0x18000F80, 0xF8000FC1, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaaZZ1. */ -+{ "st", 0x1E007001, 0xFF007001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> limm,limm,s9 00011110ssssssssS111111110DaaZZ0. */ -+{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* stb_sZZ_B c,b,u5 10101bbbcccuuuuu. */ -+{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* stb_sZZ_B b,SP,u7 11000bbb011uuuuu. */ -+{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* stdlZZ_D<.aa> c,b 00011bbb000000000BBBCCCCCC1aa111. */ -+{ "stdl", 0x18000027, 0xF8FF8027, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ_D, C_AA27 }}, -+ -+/* stdlZZ_D<.aa> c,b,s9 00011bbbssssssssSBBBCCCCCC1aa111. */ -+{ "stdl", 0x18000027, 0xF8000027, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_D, C_AA27 }}, -+ -+/* stdlZZ_D c,ximm 00011100000000000111CCCCCC100111. */ -+{ "stdl", 0x1C007027, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_XIMM, OPERAND_BRAKETdup }, { C_ZZ_D }}, -+ -+/* stdlZZ_D c,limm 00011110000000000111CCCCCC100111. */ -+{ "stdl", 0x1E007027, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_D }}, -+ -+/* stdlZZ_D<.aa> limm,b,s9 00011bbbssssssssSBBB1111101aa111. */ -+{ "stdl", 0x18000FA7, 0xF8000FE7, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_D, C_AA27 }}, -+ -+/* sth_sZZ_H c,b,u6 10110bbbcccuuuuu. */ -+{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* stlZZ_L<.aa> c,b 00011bbb000000000BBBCCCCCC0aa111. */ -+{ "stl", 0x18000007, 0xF8FF8027, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA27 }}, -+ -+/* stlZZ_L<.aa> c,b,s9 00011bbbssssssssSBBBCCCCCC0aa111. */ -+{ "stl", 0x18000007, 0xF8000027, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA27 }}, -+ -+/* stlZZ_L c,ximm 00011100000000000111CCCCCC000111. */ -+{ "stl", 0x1C007007, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_XIMM, OPERAND_BRAKETdup }, { C_ZZ_L }}, -+ -+/* stlZZ_L c,limm 00011110000000000111CCCCCC000111. */ -+{ "stl", 0x1E007007, 0xFFFFF03F, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ_L }}, -+ -+/* stlZZ_L<.aa> limm,b,s9 00011bbbssssssssSBBB1111100aa111. */ -+{ "stl", 0x18000F87, 0xF8000FE7, ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ_L, C_AA27 }}, -+ -+/* st_s b,SP,u7 11000bbb010uuuuu. */ -+{ "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* st_s c,b,u7 10100bbbcccuuuuu. */ -+{ "st_s", 0x0000A000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* st_s R0,GP,s11 01010SSSSSS10sss. */ -+{ "st_s", 0x00005010, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, STORE, CD2, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_13_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA. */ -+{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110. */ -+{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ. */ -+{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */ -+{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110. */ -+{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ. */ -+{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS. */ -+{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA. */ -+{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ -+{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110. */ -+{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110. */ -+{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ. */ -+{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ. */ -+{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA. */ -+{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110. */ -+{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ. */ -+{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS. */ -+{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA. */ -+{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub<.f> 0,limm,limm 0010011000000010F111111110111110. */ -+{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ. */ -+{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA. */ -+{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110. */ -+{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ. */ -+{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA. */ -+{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110. */ -+{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ. */ -+{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS. */ -+{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA. */ -+{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA. */ -+{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110. */ -+{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110. */ -+{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ. */ -+{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ. */ -+{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA. */ -+{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110. */ -+{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ. */ -+{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS. */ -+{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA. */ -+{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub1<.f> 0,limm,limm 0010011000010111F111111110111110. */ -+{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ. */ -+{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub1l<.f> OPERAND_RA,RB,RC 01011bbb00010111FBBBccccccaaaaaa. */ -+{ "sub1l", 0x58170000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub1l<.f> 0,RB,RC 01011bbb00010111FBBBcccccc111110. */ -+{ "sub1l", 0x5817003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub1l<.f><.cc> OPERAND_RB,RB,RC 01011bbb11010111FBBBcccccc0QQQQQ. */ -+{ "sub1l", 0x58D70000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub1l<.f> OPERAND_RA,RB,u6 01011bbb01010111FBBBuuuuuuaaaaaa. */ -+{ "sub1l", 0x58570000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1l<.f> 0,RB,u6 01011bbb01010111FBBBuuuuuu111110. */ -+{ "sub1l", 0x5857003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1l<.f><.cc> OPERAND_RB,RB,u6 01011bbb11010111FBBBuuuuuu1QQQQQ. */ -+{ "sub1l", 0x58D70020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub1l<.f> OPERAND_RB,RB,s12 01011bbb10010111FBBBssssssSSSSSS. */ -+{ "sub1l", 0x58970000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub1l<.f> OPERAND_RA,ximm,RC 0101110000010111F111ccccccaaaaaa. */ -+{ "sub1l", 0x5C177000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub1l<.f> OPERAND_RA,RB,ximm 01011bbb00010111FBBB111100aaaaaa. */ -+{ "sub1l", 0x58170F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sub1l<.f> 0,ximm,RC 0101110000010111F111cccccc111110. */ -+{ "sub1l", 0x5C17703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub1l<.f> 0,RB,ximm 01011bbb00010111FBBB111100111110. */ -+{ "sub1l", 0x58170F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sub1l<.f><.cc> 0,ximm,RC 0101110011010111F111cccccc0QQQQQ. */ -+{ "sub1l", 0x5CD77000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub1l<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11010111FBBB1111000QQQQQ. */ -+{ "sub1l", 0x58D70F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* sub1l<.f> OPERAND_RA,ximm,u6 0101110001010111F111uuuuuuaaaaaa. */ -+{ "sub1l", 0x5C577000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1l<.f> 0,ximm,u6 0101110001010111F111uuuuuu111110. */ -+{ "sub1l", 0x5C57703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1l<.f><.cc> 0,ximm,u6 0101110011010111F111uuuuuu1QQQQQ. */ -+{ "sub1l", 0x5CD77020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub1l<.f> OPERAND_RA,limm,RC 0101111000010111F111ccccccaaaaaa. */ -+{ "sub1l", 0x5E177000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub1l<.f> OPERAND_RA,RB,limm 01011bbb00010111FBBB111110aaaaaa. */ -+{ "sub1l", 0x58170F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub1l<.f> 0,limm,RC 0101111000010111F111cccccc111110. */ -+{ "sub1l", 0x5E17703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub1l<.f> 0,RB,limm 01011bbb00010111FBBB111110111110. */ -+{ "sub1l", 0x58170FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub1l<.f><.cc> 0,limm,RC 0101111011010111F111cccccc0QQQQQ. */ -+{ "sub1l", 0x5ED77000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub1l<.f><.cc> OPERAND_RB,RB,limm 01011bbb11010111FBBB1111100QQQQQ. */ -+{ "sub1l", 0x58D70F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub1l<.f> OPERAND_RA,limm,u6 0101111001010111F111uuuuuuaaaaaa. */ -+{ "sub1l", 0x5E577000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1l<.f> 0,limm,u6 0101111001010111F111uuuuuu111110. */ -+{ "sub1l", 0x5E57703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1l<.f><.cc> 0,limm,u6 0101111011010111F111uuuuuu1QQQQQ. */ -+{ "sub1l", 0x5ED77020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub1l<.f> 0,ximm,s12 0101110010010111F111ssssssSSSSSS. */ -+{ "sub1l", 0x5C977000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub1l<.f> 0,limm,s12 0101111010010111F111ssssssSSSSSS. */ -+{ "sub1l", 0x5E977000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub1l<.f> OPERAND_RA,ximm,ximm 0101110000010111F111111100aaaaaa. */ -+{ "sub1l", 0x5C177F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sub1l<.f> 0,ximm,ximm 0101110000010111F111111100111110. */ -+{ "sub1l", 0x5C177F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sub1l<.f><.cc> 0,ximm,ximm 0101110011010111F1111111000QQQQQ. */ -+{ "sub1l", 0x5CD77F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* sub1l<.f> OPERAND_RA,limm,limm 0101111000010111F111111110aaaaaa. */ -+{ "sub1l", 0x5E177F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub1l<.f> 0,limm,limm 0101111000010111F111111110111110. */ -+{ "sub1l", 0x5E177FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub1l<.f><.cc> 0,limm,limm 0101111011010111F1111111100QQQQQ. */ -+{ "sub1l", 0x5ED77F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA. */ -+{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110. */ -+{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ. */ -+{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA. */ -+{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110. */ -+{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ. */ -+{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS. */ -+{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA. */ -+{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA. */ -+{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110. */ -+{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110. */ -+{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ. */ -+{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ. */ -+{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA. */ -+{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110. */ -+{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ. */ -+{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS. */ -+{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA. */ -+{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub2<.f> 0,limm,limm 0010011000011000F111111110111110. */ -+{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ. */ -+{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub2l<.f> OPERAND_RA,RB,RC 01011bbb00011000FBBBccccccaaaaaa. */ -+{ "sub2l", 0x58180000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub2l<.f> 0,RB,RC 01011bbb00011000FBBBcccccc111110. */ -+{ "sub2l", 0x5818003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub2l<.f><.cc> OPERAND_RB,RB,RC 01011bbb11011000FBBBcccccc0QQQQQ. */ -+{ "sub2l", 0x58D80000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub2l<.f> OPERAND_RA,RB,u6 01011bbb01011000FBBBuuuuuuaaaaaa. */ -+{ "sub2l", 0x58580000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2l<.f> 0,RB,u6 01011bbb01011000FBBBuuuuuu111110. */ -+{ "sub2l", 0x5858003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2l<.f><.cc> OPERAND_RB,RB,u6 01011bbb11011000FBBBuuuuuu1QQQQQ. */ -+{ "sub2l", 0x58D80020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub2l<.f> OPERAND_RB,RB,s12 01011bbb10011000FBBBssssssSSSSSS. */ -+{ "sub2l", 0x58980000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub2l<.f> OPERAND_RA,ximm,RC 0101110000011000F111ccccccaaaaaa. */ -+{ "sub2l", 0x5C187000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub2l<.f> OPERAND_RA,RB,ximm 01011bbb00011000FBBB111100aaaaaa. */ -+{ "sub2l", 0x58180F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sub2l<.f> 0,ximm,RC 0101110000011000F111cccccc111110. */ -+{ "sub2l", 0x5C18703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub2l<.f> 0,RB,ximm 01011bbb00011000FBBB111100111110. */ -+{ "sub2l", 0x58180F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sub2l<.f><.cc> 0,ximm,RC 0101110011011000F111cccccc0QQQQQ. */ -+{ "sub2l", 0x5CD87000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub2l<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11011000FBBB1111000QQQQQ. */ -+{ "sub2l", 0x58D80F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* sub2l<.f> OPERAND_RA,ximm,u6 0101110001011000F111uuuuuuaaaaaa. */ -+{ "sub2l", 0x5C587000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2l<.f> 0,ximm,u6 0101110001011000F111uuuuuu111110. */ -+{ "sub2l", 0x5C58703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2l<.f><.cc> 0,ximm,u6 0101110011011000F111uuuuuu1QQQQQ. */ -+{ "sub2l", 0x5CD87020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub2l<.f> OPERAND_RA,limm,RC 0101111000011000F111ccccccaaaaaa. */ -+{ "sub2l", 0x5E187000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub2l<.f> OPERAND_RA,RB,limm 01011bbb00011000FBBB111110aaaaaa. */ -+{ "sub2l", 0x58180F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub2l<.f> 0,limm,RC 0101111000011000F111cccccc111110. */ -+{ "sub2l", 0x5E18703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub2l<.f> 0,RB,limm 01011bbb00011000FBBB111110111110. */ -+{ "sub2l", 0x58180FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub2l<.f><.cc> 0,limm,RC 0101111011011000F111cccccc0QQQQQ. */ -+{ "sub2l", 0x5ED87000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub2l<.f><.cc> OPERAND_RB,RB,limm 01011bbb11011000FBBB1111100QQQQQ. */ -+{ "sub2l", 0x58D80F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub2l<.f> OPERAND_RA,limm,u6 0101111001011000F111uuuuuuaaaaaa. */ -+{ "sub2l", 0x5E587000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2l<.f> 0,limm,u6 0101111001011000F111uuuuuu111110. */ -+{ "sub2l", 0x5E58703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2l<.f><.cc> 0,limm,u6 0101111011011000F111uuuuuu1QQQQQ. */ -+{ "sub2l", 0x5ED87020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub2l<.f> 0,ximm,s12 0101110010011000F111ssssssSSSSSS. */ -+{ "sub2l", 0x5C987000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub2l<.f> 0,limm,s12 0101111010011000F111ssssssSSSSSS. */ -+{ "sub2l", 0x5E987000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub2l<.f> OPERAND_RA,ximm,ximm 0101110000011000F111111100aaaaaa. */ -+{ "sub2l", 0x5C187F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sub2l<.f> 0,ximm,ximm 0101110000011000F111111100111110. */ -+{ "sub2l", 0x5C187F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sub2l<.f><.cc> 0,ximm,ximm 0101110011011000F1111111000QQQQQ. */ -+{ "sub2l", 0x5CD87F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* sub2l<.f> OPERAND_RA,limm,limm 0101111000011000F111111110aaaaaa. */ -+{ "sub2l", 0x5E187F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub2l<.f> 0,limm,limm 0101111000011000F111111110111110. */ -+{ "sub2l", 0x5E187FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub2l<.f><.cc> 0,limm,limm 0101111011011000F1111111100QQQQQ. */ -+{ "sub2l", 0x5ED87F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA. */ -+{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110. */ -+{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ. */ -+{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA. */ -+{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110. */ -+{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ. */ -+{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS. */ -+{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA. */ -+{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA. */ -+{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110. */ -+{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110. */ -+{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ. */ -+{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ. */ -+{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA. */ -+{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110. */ -+{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ. */ -+{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS. */ -+{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA. */ -+{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub3<.f> 0,limm,limm 0010011000011001F111111110111110. */ -+{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ. */ -+{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub3l<.f> OPERAND_RA,RB,RC 01011bbb00011001FBBBccccccaaaaaa. */ -+{ "sub3l", 0x58190000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub3l<.f> 0,RB,RC 01011bbb00011001FBBBcccccc111110. */ -+{ "sub3l", 0x5819003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub3l<.f><.cc> OPERAND_RB,RB,RC 01011bbb11011001FBBBcccccc0QQQQQ. */ -+{ "sub3l", 0x58D90000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub3l<.f> OPERAND_RA,RB,u6 01011bbb01011001FBBBuuuuuuaaaaaa. */ -+{ "sub3l", 0x58590000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3l<.f> 0,RB,u6 01011bbb01011001FBBBuuuuuu111110. */ -+{ "sub3l", 0x5859003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3l<.f><.cc> OPERAND_RB,RB,u6 01011bbb11011001FBBBuuuuuu1QQQQQ. */ -+{ "sub3l", 0x58D90020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub3l<.f> OPERAND_RB,RB,s12 01011bbb10011001FBBBssssssSSSSSS. */ -+{ "sub3l", 0x58990000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub3l<.f> OPERAND_RA,ximm,RC 0101110000011001F111ccccccaaaaaa. */ -+{ "sub3l", 0x5C197000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub3l<.f> OPERAND_RA,RB,ximm 01011bbb00011001FBBB111100aaaaaa. */ -+{ "sub3l", 0x58190F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sub3l<.f> 0,ximm,RC 0101110000011001F111cccccc111110. */ -+{ "sub3l", 0x5C19703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub3l<.f> 0,RB,ximm 01011bbb00011001FBBB111100111110. */ -+{ "sub3l", 0x58190F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* sub3l<.f><.cc> 0,ximm,RC 0101110011011001F111cccccc0QQQQQ. */ -+{ "sub3l", 0x5CD97000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub3l<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11011001FBBB1111000QQQQQ. */ -+{ "sub3l", 0x58D90F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* sub3l<.f> OPERAND_RA,ximm,u6 0101110001011001F111uuuuuuaaaaaa. */ -+{ "sub3l", 0x5C597000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3l<.f> 0,ximm,u6 0101110001011001F111uuuuuu111110. */ -+{ "sub3l", 0x5C59703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3l<.f><.cc> 0,ximm,u6 0101110011011001F111uuuuuu1QQQQQ. */ -+{ "sub3l", 0x5CD97020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub3l<.f> OPERAND_RA,limm,RC 0101111000011001F111ccccccaaaaaa. */ -+{ "sub3l", 0x5E197000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub3l<.f> OPERAND_RA,RB,limm 01011bbb00011001FBBB111110aaaaaa. */ -+{ "sub3l", 0x58190F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub3l<.f> 0,limm,RC 0101111000011001F111cccccc111110. */ -+{ "sub3l", 0x5E19703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub3l<.f> 0,RB,limm 01011bbb00011001FBBB111110111110. */ -+{ "sub3l", 0x58190FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub3l<.f><.cc> 0,limm,RC 0101111011011001F111cccccc0QQQQQ. */ -+{ "sub3l", 0x5ED97000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub3l<.f><.cc> OPERAND_RB,RB,limm 01011bbb11011001FBBB1111100QQQQQ. */ -+{ "sub3l", 0x58D90F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub3l<.f> OPERAND_RA,limm,u6 0101111001011001F111uuuuuuaaaaaa. */ -+{ "sub3l", 0x5E597000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3l<.f> 0,limm,u6 0101111001011001F111uuuuuu111110. */ -+{ "sub3l", 0x5E59703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3l<.f><.cc> 0,limm,u6 0101111011011001F111uuuuuu1QQQQQ. */ -+{ "sub3l", 0x5ED97020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub3l<.f> 0,ximm,s12 0101110010011001F111ssssssSSSSSS. */ -+{ "sub3l", 0x5C997000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub3l<.f> 0,limm,s12 0101111010011001F111ssssssSSSSSS. */ -+{ "sub3l", 0x5E997000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub3l<.f> OPERAND_RA,ximm,ximm 0101110000011001F111111100aaaaaa. */ -+{ "sub3l", 0x5C197F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sub3l<.f> 0,ximm,ximm 0101110000011001F111111100111110. */ -+{ "sub3l", 0x5C197F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* sub3l<.f><.cc> 0,ximm,ximm 0101110011011001F1111111000QQQQQ. */ -+{ "sub3l", 0x5CD97F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* sub3l<.f> OPERAND_RA,limm,limm 0101111000011001F111111110aaaaaa. */ -+{ "sub3l", 0x5E197F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub3l<.f> 0,limm,limm 0101111000011001F111111110111110. */ -+{ "sub3l", 0x5E197FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub3l<.f><.cc> 0,limm,limm 0101111011011001F1111111100QQQQQ. */ -+{ "sub3l", 0x5ED97F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* subl<.f> OPERAND_RA,RB,RC 01011bbb00000010FBBBccccccaaaaaa. */ -+{ "subl", 0x58020000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* subl<.f> 0,RB,RC 01011bbb00000010FBBBcccccc111110. */ -+{ "subl", 0x5802003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* subl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11000010FBBBcccccc0QQQQQ. */ -+{ "subl", 0x58C20000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* subl<.f> OPERAND_RA,RB,u6 01011bbb01000010FBBBuuuuuuaaaaaa. */ -+{ "subl", 0x58420000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subl<.f> 0,RB,u6 01011bbb01000010FBBBuuuuuu111110. */ -+{ "subl", 0x5842003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11000010FBBBuuuuuu1QQQQQ. */ -+{ "subl", 0x58C20020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* subl<.f> OPERAND_RB,RB,s12 01011bbb10000010FBBBssssssSSSSSS. */ -+{ "subl", 0x58820000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* subl<.f> OPERAND_RA,ximm,RC 0101110000000010F111ccccccaaaaaa. */ -+{ "subl", 0x5C027000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* subl<.f> OPERAND_RA,RB,ximm 01011bbb00000010FBBB111100aaaaaa. */ -+{ "subl", 0x58020F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* subl<.f> 0,ximm,RC 0101110000000010F111cccccc111110. */ -+{ "subl", 0x5C02703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* subl<.f> 0,RB,ximm 01011bbb00000010FBBB111100111110. */ -+{ "subl", 0x58020F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* subl<.f><.cc> 0,ximm,RC 0101110011000010F111cccccc0QQQQQ. */ -+{ "subl", 0x5CC27000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* subl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11000010FBBB1111000QQQQQ. */ -+{ "subl", 0x58C20F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* subl<.f> OPERAND_RA,ximm,u6 0101110001000010F111uuuuuuaaaaaa. */ -+{ "subl", 0x5C427000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subl<.f> 0,ximm,u6 0101110001000010F111uuuuuu111110. */ -+{ "subl", 0x5C42703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subl<.f><.cc> 0,ximm,u6 0101110011000010F111uuuuuu1QQQQQ. */ -+{ "subl", 0x5CC27020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* subl<.f> OPERAND_RA,limm,RC 0101111000000010F111ccccccaaaaaa. */ -+{ "subl", 0x5E027000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subl<.f> OPERAND_RA,RB,limm 01011bbb00000010FBBB111110aaaaaa. */ -+{ "subl", 0x58020F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* subl<.f> 0,limm,RC 0101111000000010F111cccccc111110. */ -+{ "subl", 0x5E02703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subl<.f> 0,RB,limm 01011bbb00000010FBBB111110111110. */ -+{ "subl", 0x58020FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* subl<.f><.cc> 0,limm,RC 0101111011000010F111cccccc0QQQQQ. */ -+{ "subl", 0x5EC27000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* subl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11000010FBBB1111100QQQQQ. */ -+{ "subl", 0x58C20F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* subl<.f> OPERAND_RA,limm,u6 0101111001000010F111uuuuuuaaaaaa. */ -+{ "subl", 0x5E427000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subl<.f> 0,limm,u6 0101111001000010F111uuuuuu111110. */ -+{ "subl", 0x5E42703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subl<.f><.cc> 0,limm,u6 0101111011000010F111uuuuuu1QQQQQ. */ -+{ "subl", 0x5EC27020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* subl<.f> 0,ximm,s12 0101110010000010F111ssssssSSSSSS. */ -+{ "subl", 0x5C827000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* subl<.f> 0,limm,s12 0101111010000010F111ssssssSSSSSS. */ -+{ "subl", 0x5E827000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* subl<.f> OPERAND_RA,ximm,ximm 0101110000000010F111111100aaaaaa. */ -+{ "subl", 0x5C027F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* subl<.f> 0,ximm,ximm 0101110000000010F111111100111110. */ -+{ "subl", 0x5C027F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* subl<.f><.cc> 0,ximm,ximm 0101110011000010F1111111000QQQQQ. */ -+{ "subl", 0x5CC27F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* subl<.f> OPERAND_RA,limm,limm 0101111000000010F111111110aaaaaa. */ -+{ "subl", 0x5E027F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* subl<.f> 0,limm,limm 0101111000000010F111111110111110. */ -+{ "subl", 0x5E027FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* subl<.f><.cc> 0,limm,limm 0101111011000010F1111111100QQQQQ. */ -+{ "subl", 0x5EC27F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* subl_s SP,SP,u9 11000UU1101uuuuu. */ -+{ "subl_s", 0x0000C1A0, 0x0000F9E0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM9_A32_11_S }, { 0 }}, -+ -+/* subl_s b,b,c 01111bbbccc00011. */ -+{ "subl_s", 0x00007803, 0x0000F81F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* subs<.f> a,b,c 00101bbb00000111FBBBCCCCCCAAAAAA. */ -+{ "subs", 0x28070000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f> 0,b,c 00101bbb00000111FBBBCCCCCC111110. */ -+{ "subs", 0x2807003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f><.cc> b,b,c 00101bbb11000111FBBBCCCCCC0QQQQQ. */ -+{ "subs", 0x28C70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* subs<.f> a,b,u6 00101bbb01000111FBBBuuuuuuAAAAAA. */ -+{ "subs", 0x28470000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subs<.f> 0,b,u6 00101bbb01000111FBBBuuuuuu111110. */ -+{ "subs", 0x2847003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subs<.f><.cc> b,b,u6 00101bbb11000111FBBBuuuuuu1QQQQQ. */ -+{ "subs", 0x28C70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* subs<.f> b,b,s12 00101bbb10000111FBBBssssssSSSSSS. */ -+{ "subs", 0x28870000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */ -+{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f> a,b,limm 00101bbb00000111FBBB111110AAAAAA. */ -+{ "subs", 0x28070F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* subs<.f> 0,limm,c 0010111000000111F111CCCCCC111110. */ -+{ "subs", 0x2E07703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f> 0,b,limm 00101bbb00000111FBBB111110111110. */ -+{ "subs", 0x28070FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */ -+{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f><.cc> b,b,limm 00101bbb11000111FBBB1111100QQQQQ. */ -+{ "subs", 0x28C70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* subs<.f><.cc> 0,limm,c 0010111011000111F111CCCCCC0QQQQQ. */ -+{ "subs", 0x2EC77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* subs<.f> a,limm,u6 0010111001000111F111uuuuuuAAAAAA. */ -+{ "subs", 0x2E477000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subs<.f> 0,limm,u6 0010111001000111F111uuuuuu111110. */ -+{ "subs", 0x2E47703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subs<.f><.cc> 0,limm,u6 0010111011000111F111uuuuuu1QQQQQ. */ -+{ "subs", 0x2EC77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* subs<.f> 0,limm,s12 0010111010000111F111ssssssSSSSSS. */ -+{ "subs", 0x2E877000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* subs<.f> a,limm,limm 0010111000000111F111111110AAAAAA. */ -+{ "subs", 0x2E077F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* subs<.f> 0,limm,limm 0010111000000111F111111110111110. */ -+{ "subs", 0x2E077FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* subs<.f><.cc> 0,limm,limm 0010111011000111F1111111100QQQQQ. */ -+{ "subs", 0x2EC77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub_s.NE b,b,b 01111bbb11000000. */ -+{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RB_Sdup }, { C_NE }}, -+ -+/* sub_s b,b,c 01111bbbccc00010. */ -+{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* sub_s a,b,c 01001bbbccc10aaa. */ -+{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, CD2, { OPERAND_RA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* sub_s c,b,u3 01101bbbccc01uuu. */ -+{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, -+ -+/* sub_s b,b,u5 10111bbb011uuuuu. */ -+{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000. */ -+{ "swap", 0x282F0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* swap<.f> 0,c 0010111000101111F111CCCCCC000000. */ -+{ "swap", 0x2E2F7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* swap<.f> b,u6 00101bbb01101111FBBBuuuuuu000000. */ -+{ "swap", 0x286F0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swap<.f> 0,u6 0010111001101111F111uuuuuu000000. */ -+{ "swap", 0x2E6F7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swap<.f> b,limm 00101bbb00101111FBBB111110000000. */ -+{ "swap", 0x282F0F80, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* swap<.f> 0,limm 0010111000101111F111111110000000. */ -+{ "swap", 0x2E2F7F80, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* swape<.f> b,c 00101bbb00101111FBBBCCCCCC001001. */ -+{ "swape", 0x282F0009, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* swape<.f> 0,c 0010111000101111F111CCCCCC001001. */ -+{ "swape", 0x2E2F7009, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* swape<.f> b,u6 00101bbb01101111FBBBuuuuuu001001. */ -+{ "swape", 0x286F0009, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swape<.f> 0,u6 0010111001101111F111uuuuuu001001. */ -+{ "swape", 0x2E6F7009, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swape<.f> b,limm 00101bbb00101111FBBB111110001001. */ -+{ "swape", 0x282F0F89, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* swape<.f> 0,limm 0010111000101111F111111110001001. */ -+{ "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* swapel<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc101001. */ -+{ "swapel", 0x582F0029, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* swapel<.f> 0,RC 0101111000101111F111cccccc101001. */ -+{ "swapel", 0x5E2F7029, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* swapel<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu101001. */ -+{ "swapel", 0x586F0029, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swapel<.f> 0,u6 0101111001101111F111uuuuuu101001. */ -+{ "swapel", 0x5E6F7029, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swapel<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100101001. */ -+{ "swapel", 0x582F0F29, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* swapel<.f> 0,ximm 0101111000101111F111111100101001. */ -+{ "swapel", 0x5E2F7F29, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* swapel<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110101001. */ -+{ "swapel", 0x582F0FA9, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* swapel<.f> 0,limm 0101111000101111F111111110101001. */ -+{ "swapel", 0x5E2F7FA9, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* swapl<.f> OPERAND_RB,RC 01011bbb00101111FBBBcccccc100000. */ -+{ "swapl", 0x582F0020, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* swapl<.f> 0,RC 0101111000101111F111cccccc100000. */ -+{ "swapl", 0x5E2F7020, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* swapl<.f> OPERAND_RB,u6 01011bbb01101111FBBBuuuuuu100000. */ -+{ "swapl", 0x586F0020, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swapl<.f> 0,u6 0101111001101111F111uuuuuu100000. */ -+{ "swapl", 0x5E6F7020, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swapl<.f> OPERAND_RB,ximm 01011bbb00101111FBBB111100100000. */ -+{ "swapl", 0x582F0F20, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* swapl<.f> 0,ximm 0101111000101111F111111100100000. */ -+{ "swapl", 0x5E2F7F20, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM }, { C_F }}, -+ -+/* swapl<.f> OPERAND_RB,limm 01011bbb00101111FBBB111110100000. */ -+{ "swapl", 0x582F0FA0, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* swapl<.f> 0,limm 0101111000101111F111111110100000. */ -+{ "swapl", 0x5E2F7FA0, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* swi 00100010011011110000000000111111. */ -+{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* swi_s 0111101011100000. */ -+{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* swi_s u6 01111uuuuuu11111. */ -+{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { OPERAND_UIMM6_5_S }, { 0 }}, -+ -+/* sync 00100011011011110000000000111111. */ -+{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* trap_s u6 01111uuuuuu11110. */ -+{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { OPERAND_UIMM6_5_S }, { 0 }}, -+ -+/* tst b,c 00100bbb000010111BBBCCCCCCRRRRRR. */ -+{ "tst", 0x200B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* tst<.cc> b,c 00100bbb110010111BBBCCCCCC0QQQQQ. */ -+{ "tst", 0x20CB8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* tst b,u6 00100bbb010010111BBBuuuuuuRRRRRR. */ -+{ "tst", 0x204B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* tst<.cc> b,u6 00100bbb110010111BBBuuuuuu1QQQQQ. */ -+{ "tst", 0x20CB8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* tst b,s12 00100bbb100010111BBBssssssSSSSSS. */ -+{ "tst", 0x208B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* tst limm,c 00100110000010111111CCCCCCRRRRRR. */ -+{ "tst", 0x260BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* tst b,limm 00100bbb000010111BBB111110RRRRRR. */ -+{ "tst", 0x200B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* tst<.cc> b,limm 00100bbb110010111BBB1111100QQQQQ. */ -+{ "tst", 0x20CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* tst<.cc> limm,c 00100110110010111111CCCCCC0QQQQQ. */ -+{ "tst", 0x26CBF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* tst limm,u6 00100110010010111111uuuuuuRRRRRR. */ -+{ "tst", 0x264BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* tst<.cc> limm,u6 00100110110010111111uuuuuu1QQQQQ. */ -+{ "tst", 0x26CBF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* tst limm,s12 00100110100010111111ssssssSSSSSS. */ -+{ "tst", 0x268BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* tst limm,limm 00100110000010111111111110RRRRRR. */ -+{ "tst", 0x260BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* tst<.cc> limm,limm 001001101100101111111111100QQQQQ. */ -+{ "tst", 0x26CBFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* tstl OPERAND_RB,RC 01011bbb000010111BBBccccccRRRRRR. */ -+{ "tstl", 0x580B8000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* tstl<.cc> OPERAND_RB,RC 01011bbb110010111BBBcccccc0QQQQQ. */ -+{ "tstl", 0x58CB8000, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* tstl OPERAND_RB,u6 01011bbb010010111BBBuuuuuuRRRRRR. */ -+{ "tstl", 0x584B8000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* tstl<.cc> OPERAND_RB,u6 01011bbb110010111BBBuuuuuu1QQQQQ. */ -+{ "tstl", 0x58CB8020, 0xF8FF8020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* tstl OPERAND_RB,s12 01011bbb100010111BBBssssssSSSSSS. */ -+{ "tstl", 0x588B8000, 0xF8FF8000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* tstl OPERAND_RB,ximm 01011bbb000010111BBB111100RRRRRR. */ -+{ "tstl", 0x580B8F00, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { 0 }}, -+ -+/* tstl<.cc> OPERAND_RB,ximm 01011bbb110010111BBB1111000QQQQQ. */ -+{ "tstl", 0x58CB8F00, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_XIMM }, { C_CC }}, -+ -+/* tstl OPERAND_RB,limm 01011bbb000010111BBB111110RRRRRR. */ -+{ "tstl", 0x580B8F80, 0xF8FF8FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* tstl<.cc> OPERAND_RB,limm 01011bbb110010111BBB1111100QQQQQ. */ -+{ "tstl", 0x58CB8F80, 0xF8FF8FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* tst_s b,c 01111bbbccc01011. */ -+{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* unimp_s 0111100111100000. */ -+{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* vabs2h b,c 00101bbb001011110BBBCCCCCC101000. */ -+{ "vabs2h", 0x282F0028, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vabs2h 0,c 00101110001011110111CCCCCC101000. */ -+{ "vabs2h", 0x2E2F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vabs2h b,u6 00101bbb011011110BBBuuuuuu101000. */ -+{ "vabs2h", 0x286F0028, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vabs2h 0,u6 00101110011011110111uuuuuu101000. */ -+{ "vabs2h", 0x2E6F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vabs2h b,limm 00101bbb001011110BBB111110101000. */ -+{ "vabs2h", 0x282F0FA8, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vabs2h 0,limm 00101110001011110111111110101000. */ -+{ "vabs2h", 0x2E2F7FA8, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vabss2h b,c 00101bbb001011110BBBCCCCCC101001. */ -+{ "vabss2h", 0x282F0029, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vabss2h 0,c 00101110001011110111CCCCCC101001. */ -+{ "vabss2h", 0x2E2F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vabss2h b,u6 00101bbb011011110BBBuuuuuu101001. */ -+{ "vabss2h", 0x286F0029, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vabss2h 0,u6 00101110011011110111uuuuuu101001. */ -+{ "vabss2h", 0x2E6F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vabss2h b,limm 00101bbb001011110BBB111110101001. */ -+{ "vabss2h", 0x282F0FA9, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vabss2h 0,limm 00101110001011110111111110101001. */ -+{ "vabss2h", 0x2E2F7FA9, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA. */ -+{ "vadd2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd2 0,b,c 00101bbb001111000BBBCCCCCC111110. */ -+{ "vadd2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ. */ -+{ "vadd2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadd2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA. */ -+{ "vadd2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2 0,b,u6 00101bbb011111000BBBuuuuuu111110. */ -+{ "vadd2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ. */ -+{ "vadd2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd2 b,b,s12 00101bbb101111000BBBssssssSSSSSS. */ -+{ "vadd2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd2 a,limm,c 00101110001111000111CCCCCCAAAAAA. */ -+{ "vadd2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd2 a,b,limm 00101bbb001111000BBB111110AAAAAA. */ -+{ "vadd2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2 0,limm,c 00101110001111000111CCCCCC111110. */ -+{ "vadd2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd2 0,b,limm 00101bbb001111000BBB111110111110. */ -+{ "vadd2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ. */ -+{ "vadd2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadd2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ. */ -+{ "vadd2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadd2 a,limm,u6 00101110011111000111uuuuuuAAAAAA. */ -+{ "vadd2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2 0,limm,u6 00101110011111000111uuuuuu111110. */ -+{ "vadd2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ. */ -+{ "vadd2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd2 0,limm,s12 00101110101111000111ssssssSSSSSS. */ -+{ "vadd2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd2 a,limm,limm 00101110001111000111111110AAAAAA. */ -+{ "vadd2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd2 0,limm,limm 00101110001111000111111110111110. */ -+{ "vadd2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ. */ -+{ "vadd2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadd2h a,b,c 00101bbb000101000BBBCCCCCCAAAAAA. */ -+{ "vadd2h", 0x28140000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd2h 0,b,c 00101bbb000101000BBBCCCCCC111110. */ -+{ "vadd2h", 0x2814003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd2h<.cc> b,b,c 00101bbb110101000BBBCCCCCC0QQQQQ. */ -+{ "vadd2h", 0x28D40000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadd2h a,b,u6 00101bbb010101000BBBuuuuuuAAAAAA. */ -+{ "vadd2h", 0x28540000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2h 0,b,u6 00101bbb010101000BBBuuuuuu111110. */ -+{ "vadd2h", 0x2854003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2h<.cc> b,b,u6 00101bbb110101000BBBuuuuuu1QQQQQ. */ -+{ "vadd2h", 0x28D40020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd2h b,b,s12 00101bbb100101000BBBssssssSSSSSS. */ -+{ "vadd2h", 0x28940000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd2h a,limm,c 00101110000101000111CCCCCCAAAAAA. */ -+{ "vadd2h", 0x2E147000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd2h a,b,limm 00101bbb000101000BBB111110AAAAAA. */ -+{ "vadd2h", 0x28140F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2h 0,limm,c 00101110000101000111CCCCCC111110. */ -+{ "vadd2h", 0x2E14703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd2h 0,b,limm 00101bbb000101000BBB111110111110. */ -+{ "vadd2h", 0x28140FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2h<.cc> b,b,limm 00101bbb110101000BBB1111100QQQQQ. */ -+{ "vadd2h", 0x28D40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadd2h<.cc> 0,limm,c 00101110110101000111CCCCCC0QQQQQ. */ -+{ "vadd2h", 0x2ED47000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadd2h a,limm,u6 00101110010101000111uuuuuuAAAAAA. */ -+{ "vadd2h", 0x2E547000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2h 0,limm,u6 00101110010101000111uuuuuu111110. */ -+{ "vadd2h", 0x2E54703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2h<.cc> 0,limm,u6 00101110110101000111uuuuuu1QQQQQ. */ -+{ "vadd2h", 0x2ED47020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd2h 0,limm,s12 00101110100101000111ssssssSSSSSS. */ -+{ "vadd2h", 0x2E947000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd2h a,limm,limm 00101110000101000111111110AAAAAA. */ -+{ "vadd2h", 0x2E147F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd2h 0,limm,limm 00101110000101000111111110111110. */ -+{ "vadd2h", 0x2E147FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd2h<.cc> 0,limm,limm 001011101101010001111111100QQQQQ. */ -+{ "vadd2h", 0x2ED47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadd4b a,b,c 00101bbb001001000BBBCCCCCCAAAAAA. */ -+{ "vadd4b", 0x28240000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd4b 0,b,c 00101bbb001001000BBBCCCCCC111110. */ -+{ "vadd4b", 0x2824003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd4b<.cc> b,b,c 00101bbb111001000BBBCCCCCC0QQQQQ. */ -+{ "vadd4b", 0x28E40000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadd4b a,b,u6 00101bbb011001000BBBuuuuuuAAAAAA. */ -+{ "vadd4b", 0x28640000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4b 0,b,u6 00101bbb011001000BBBuuuuuu111110. */ -+{ "vadd4b", 0x2864003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4b<.cc> b,b,u6 00101bbb111001000BBBuuuuuu1QQQQQ. */ -+{ "vadd4b", 0x28E40020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd4b b,b,s12 00101bbb101001000BBBssssssSSSSSS. */ -+{ "vadd4b", 0x28A40000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd4b a,limm,c 00101110001001000111CCCCCCAAAAAA. */ -+{ "vadd4b", 0x2E247000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd4b a,b,limm 00101bbb001001000BBB111110AAAAAA. */ -+{ "vadd4b", 0x28240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd4b 0,limm,c 00101110011001000111CCCCCC111110. */ -+{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd4b 0,b,limm 00101bbb001001000BBB111110111110. */ -+{ "vadd4b", 0x28240FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd4b<.cc> b,b,limm 00101bbb111001000BBB1111100QQQQQ. */ -+{ "vadd4b", 0x28E40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadd4b<.cc> 0,limm,c 00101110111001000111CCCCCC0QQQQQ. */ -+{ "vadd4b", 0x2EE47000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadd4b a,limm,u6 00101110011001000111uuuuuuAAAAAA. */ -+{ "vadd4b", 0x2E647000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4b 0,limm,u6 00101110011001000111uuuuuu111110. */ -+{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4b<.cc> 0,limm,u6 00101110111001000111uuuuuu1QQQQQ. */ -+{ "vadd4b", 0x2EE47020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd4b 0,limm,s12 00101110101001000111ssssssSSSSSS. */ -+{ "vadd4b", 0x2EA47000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd4b a,limm,limm 00101110001001000111111110AAAAAA. */ -+{ "vadd4b", 0x2E247F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd4b 0,limm,limm 00101110001001000111111110111110. */ -+{ "vadd4b", 0x2E247FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd4b<.cc> 0,limm,limm 001011101110010001111111100QQQQQ. */ -+{ "vadd4b", 0x2EE47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadd4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA. */ -+{ "vadd4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd4h 0,b,c 00101bbb001110000BBBCCCCCC111110. */ -+{ "vadd4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ. */ -+{ "vadd4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadd4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA. */ -+{ "vadd4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4h 0,b,u6 00101bbb011110000BBBuuuuuu111110. */ -+{ "vadd4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ. */ -+{ "vadd4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd4h b,b,s12 00101bbb101110000BBBssssssSSSSSS. */ -+{ "vadd4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd4h a,limm,c 00101110001110000111CCCCCCAAAAAA. */ -+{ "vadd4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd4h a,b,limm 00101bbb001110000BBB111110AAAAAA. */ -+{ "vadd4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd4h 0,limm,c 00101110001110000111CCCCCC111110. */ -+{ "vadd4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd4h 0,b,limm 00101bbb001110000BBB111110111110. */ -+{ "vadd4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ. */ -+{ "vadd4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadd4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ. */ -+{ "vadd4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadd4h a,limm,u6 00101110011110000111uuuuuuAAAAAA. */ -+{ "vadd4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4h 0,limm,u6 00101110011110000111uuuuuu111110. */ -+{ "vadd4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ. */ -+{ "vadd4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd4h 0,limm,s12 00101110101110000111ssssssSSSSSS. */ -+{ "vadd4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd4h a,limm,limm 00101110001110000111111110AAAAAA. */ -+{ "vadd4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd4h 0,limm,limm 00101110001110000111111110111110. */ -+{ "vadd4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ. */ -+{ "vadd4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadds2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA. */ -+{ "vadds2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds2 0,b,c 00101bbb001111000BBBCCCCCC111110. */ -+{ "vadds2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ. */ -+{ "vadds2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadds2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA. */ -+{ "vadds2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2 0,b,u6 00101bbb011111000BBBuuuuuu111110. */ -+{ "vadds2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ. */ -+{ "vadds2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds2 b,b,s12 00101bbb101111000BBBssssssSSSSSS. */ -+{ "vadds2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds2 a,limm,c 00101110001111000111CCCCCCAAAAAA. */ -+{ "vadds2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds2 a,b,limm 00101bbb001111000BBB111110AAAAAA. */ -+{ "vadds2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds2 0,limm,c 00101110001111000111CCCCCC111110. */ -+{ "vadds2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds2 0,b,limm 00101bbb001111000BBB111110111110. */ -+{ "vadds2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ. */ -+{ "vadds2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadds2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ. */ -+{ "vadds2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadds2 a,limm,u6 00101110011111000111uuuuuuAAAAAA. */ -+{ "vadds2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2 0,limm,u6 00101110011111000111uuuuuu111110. */ -+{ "vadds2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ. */ -+{ "vadds2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds2 0,limm,s12 00101110101111000111ssssssSSSSSS. */ -+{ "vadds2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds2 a,limm,limm 00101110001111000111111110AAAAAA. */ -+{ "vadds2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds2 0,limm,limm 00101110001111000111111110111110. */ -+{ "vadds2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ. */ -+{ "vadds2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadds2h a,b,c 00101bbb000101001BBBCCCCCCAAAAAA. */ -+{ "vadds2h", 0x28148000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds2h 0,b,c 00101bbb000101001BBBCCCCCC111110. */ -+{ "vadds2h", 0x2814803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds2h<.cc> b,b,c 00101bbb110101001BBBCCCCCC0QQQQQ. */ -+{ "vadds2h", 0x28D48000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadds2h a,b,u6 00101bbb010101001BBBuuuuuuAAAAAA. */ -+{ "vadds2h", 0x28548000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2h 0,b,u6 00101bbb010101001BBBuuuuuu111110. */ -+{ "vadds2h", 0x2854803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2h<.cc> b,b,u6 00101bbb110101001BBBuuuuuu1QQQQQ. */ -+{ "vadds2h", 0x28D48020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds2h b,b,s12 00101bbb100101001BBBssssssSSSSSS. */ -+{ "vadds2h", 0x28948000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds2h a,limm,c 00101110000101001111CCCCCCAAAAAA. */ -+{ "vadds2h", 0x2E14F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds2h a,b,limm 00101bbb000101001BBB111110AAAAAA. */ -+{ "vadds2h", 0x28148F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds2h 0,limm,c 00101110000101001111CCCCCC111110. */ -+{ "vadds2h", 0x2E14F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds2h 0,b,limm 00101bbb000101001BBB111110111110. */ -+{ "vadds2h", 0x28148FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds2h<.cc> b,b,limm 00101bbb110101001BBB1111100QQQQQ. */ -+{ "vadds2h", 0x28D48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadds2h<.cc> 0,limm,c 00101110110101001111CCCCCC0QQQQQ. */ -+{ "vadds2h", 0x2ED4F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadds2h a,limm,u6 00101110010101001111uuuuuuAAAAAA. */ -+{ "vadds2h", 0x2E54F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2h 0,limm,u6 00101110010101001111uuuuuu111110. */ -+{ "vadds2h", 0x2E54F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2h<.cc> 0,limm,u6 00101110110101001111uuuuuu1QQQQQ. */ -+{ "vadds2h", 0x2ED4F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds2h 0,limm,s12 00101110100101001111ssssssSSSSSS. */ -+{ "vadds2h", 0x2E94F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds2h a,limm,limm 00101110000101001111111110AAAAAA. */ -+{ "vadds2h", 0x2E14FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds2h 0,limm,limm 00101110000101001111111110111110. */ -+{ "vadds2h", 0x2E14FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds2h<.cc> 0,limm,limm 001011101101010011111111100QQQQQ. */ -+{ "vadds2h", 0x2ED4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadds4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA. */ -+{ "vadds4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds4h 0,b,c 00101bbb001110000BBBCCCCCC111110. */ -+{ "vadds4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ. */ -+{ "vadds4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadds4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA. */ -+{ "vadds4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds4h 0,b,u6 00101bbb011110000BBBuuuuuu111110. */ -+{ "vadds4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ. */ -+{ "vadds4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds4h b,b,s12 00101bbb101110000BBBssssssSSSSSS. */ -+{ "vadds4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds4h a,limm,c 00101110001110000111CCCCCCAAAAAA. */ -+{ "vadds4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds4h a,b,limm 00101bbb001110000BBB111110AAAAAA. */ -+{ "vadds4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds4h 0,limm,c 00101110001110000111CCCCCC111110. */ -+{ "vadds4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds4h 0,b,limm 00101bbb001110000BBB111110111110. */ -+{ "vadds4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ. */ -+{ "vadds4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadds4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ. */ -+{ "vadds4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadds4h a,limm,u6 00101110011110000111uuuuuuAAAAAA. */ -+{ "vadds4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds4h 0,limm,u6 00101110011110000111uuuuuu111110. */ -+{ "vadds4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ. */ -+{ "vadds4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds4h 0,limm,s12 00101110101110000111ssssssSSSSSS. */ -+{ "vadds4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds4h a,limm,limm 00101110001110000111111110AAAAAA. */ -+{ "vadds4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds4h 0,limm,limm 00101110001110000111111110111110. */ -+{ "vadds4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ. */ -+{ "vadds4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsub a,b,c 00101bbb001111100BBBCCCCCCAAAAAA. */ -+{ "vaddsub", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub 0,b,c 00101bbb001111100BBBCCCCCC111110. */ -+{ "vaddsub", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ. */ -+{ "vaddsub", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA. */ -+{ "vaddsub", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub 0,b,u6 00101bbb011111100BBBuuuuuu111110. */ -+{ "vaddsub", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ. */ -+{ "vaddsub", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub b,b,s12 00101bbb101111100BBBssssssSSSSSS. */ -+{ "vaddsub", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub a,limm,c 00101110001111100111CCCCCCAAAAAA. */ -+{ "vaddsub", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub a,b,limm 00101bbb001111100BBB111110AAAAAA. */ -+{ "vaddsub", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub 0,limm,c 00101110001111100111CCCCCC111110. */ -+{ "vaddsub", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub 0,b,limm 00101bbb001111100BBB111110111110. */ -+{ "vaddsub", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ. */ -+{ "vaddsub", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsub<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ. */ -+{ "vaddsub", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub a,limm,u6 00101110011111100111uuuuuuAAAAAA. */ -+{ "vaddsub", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub 0,limm,u6 00101110011111100111uuuuuu111110. */ -+{ "vaddsub", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ. */ -+{ "vaddsub", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub 0,limm,s12 00101110101111100111ssssssSSSSSS. */ -+{ "vaddsub", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub a,limm,limm 00101110001111100111111110AAAAAA. */ -+{ "vaddsub", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub 0,limm,limm 00101110001111100111111110111110. */ -+{ "vaddsub", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub<.cc> 0,limm,limm 001011101111111001111111100QQQQQ. */ -+{ "vaddsub", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsub2h a,b,c 00101bbb000101100BBBCCCCCCAAAAAA. */ -+{ "vaddsub2h", 0x28160000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub2h 0,b,c 00101bbb000101100BBBCCCCCC111110. */ -+{ "vaddsub2h", 0x2816003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub2h<.cc> b,b,c 00101bbb110101100BBBCCCCCC0QQQQQ. */ -+{ "vaddsub2h", 0x28D60000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub2h a,b,u6 00101bbb010101100BBBuuuuuuAAAAAA. */ -+{ "vaddsub2h", 0x28560000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub2h 0,b,u6 00101bbb010101100BBBuuuuuu111110. */ -+{ "vaddsub2h", 0x2856003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub2h<.cc> b,b,u6 00101bbb110101100BBBuuuuuu1QQQQQ. */ -+{ "vaddsub2h", 0x28D60020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub2h b,b,s12 00101bbb100101100BBBssssssSSSSSS. */ -+{ "vaddsub2h", 0x28960000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub2h a,limm,c 00101110000101100111CCCCCCAAAAAA. */ -+{ "vaddsub2h", 0x2E167000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub2h a,b,limm 00101bbb000101100BBB111110AAAAAA. */ -+{ "vaddsub2h", 0x28160F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub2h 0,limm,c 00101110000101100111CCCCCC111110. */ -+{ "vaddsub2h", 0x2E16703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub2h 0,b,limm 00101bbb000101100BBB111110111110. */ -+{ "vaddsub2h", 0x28160FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub2h<.cc> b,b,limm 00101bbb110101100BBB1111100QQQQQ. */ -+{ "vaddsub2h", 0x28D60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsub2h<.cc> 0,limm,c 00101110110101100111CCCCCC0QQQQQ. */ -+{ "vaddsub2h", 0x2ED67000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub2h a,limm,u6 00101110010101100111uuuuuuAAAAAA. */ -+{ "vaddsub2h", 0x2E567000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub2h 0,limm,u6 00101110010101100111uuuuuu111110. */ -+{ "vaddsub2h", 0x2E56703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub2h<.cc> 0,limm,u6 00101110110101100111uuuuuu1QQQQQ. */ -+{ "vaddsub2h", 0x2ED67020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub2h 0,limm,s12 00101110100101100111ssssssSSSSSS. */ -+{ "vaddsub2h", 0x2E967000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub2h a,limm,limm 00101110000101100111111110AAAAAA. */ -+{ "vaddsub2h", 0x2E167F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub2h 0,limm,limm 00101110000101100111111110111110. */ -+{ "vaddsub2h", 0x2E167FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub2h<.cc> 0,limm,limm 001011101101011001111111100QQQQQ. */ -+{ "vaddsub2h", 0x2ED67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsub4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA. */ -+{ "vaddsub4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub4h 0,b,c 00101bbb001110100BBBCCCCCC111110. */ -+{ "vaddsub4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ. */ -+{ "vaddsub4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA. */ -+{ "vaddsub4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub4h 0,b,u6 00101bbb011110100BBBuuuuuu111110. */ -+{ "vaddsub4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ. */ -+{ "vaddsub4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub4h b,b,s12 00101bbb101110100BBBssssssSSSSSS. */ -+{ "vaddsub4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub4h a,limm,c 00101110001110100111CCCCCCAAAAAA. */ -+{ "vaddsub4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub4h a,b,limm 00101bbb001110100BBB111110AAAAAA. */ -+{ "vaddsub4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub4h 0,limm,c 00101110001110100111CCCCCC111110. */ -+{ "vaddsub4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub4h 0,b,limm 00101bbb001110100BBB111110111110. */ -+{ "vaddsub4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ. */ -+{ "vaddsub4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsub4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ. */ -+{ "vaddsub4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub4h a,limm,u6 00101110011110100111uuuuuuAAAAAA. */ -+{ "vaddsub4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub4h 0,limm,u6 00101110011110100111uuuuuu111110. */ -+{ "vaddsub4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ. */ -+{ "vaddsub4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub4h 0,limm,s12 00101110101110100111ssssssSSSSSS. */ -+{ "vaddsub4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub4h a,limm,limm 00101110001110100111111110AAAAAA. */ -+{ "vaddsub4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub4h 0,limm,limm 00101110001110100111111110111110. */ -+{ "vaddsub4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ. */ -+{ "vaddsub4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsubs a,b,c 00101bbb001111100BBBCCCCCCAAAAAA. */ -+{ "vaddsubs", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs 0,b,c 00101bbb001111100BBBCCCCCC111110. */ -+{ "vaddsubs", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ. */ -+{ "vaddsubs", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA. */ -+{ "vaddsubs", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs 0,b,u6 00101bbb011111100BBBuuuuuu111110. */ -+{ "vaddsubs", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ. */ -+{ "vaddsubs", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs b,b,s12 00101bbb101111100BBBssssssSSSSSS. */ -+{ "vaddsubs", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs a,limm,c 00101110001111100111CCCCCCAAAAAA. */ -+{ "vaddsubs", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs a,b,limm 00101bbb001111100BBB111110AAAAAA. */ -+{ "vaddsubs", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs 0,limm,c 00101110001111100111CCCCCC111110. */ -+{ "vaddsubs", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs 0,b,limm 00101bbb001111100BBB111110111110. */ -+{ "vaddsubs", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ. */ -+{ "vaddsubs", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsubs<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ. */ -+{ "vaddsubs", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs a,limm,u6 00101110011111100111uuuuuuAAAAAA. */ -+{ "vaddsubs", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs 0,limm,u6 00101110011111100111uuuuuu111110. */ -+{ "vaddsubs", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ. */ -+{ "vaddsubs", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs 0,limm,s12 00101110101111100111ssssssSSSSSS. */ -+{ "vaddsubs", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs a,limm,limm 00101110001111100111111110AAAAAA. */ -+{ "vaddsubs", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs 0,limm,limm 00101110001111100111111110111110. */ -+{ "vaddsubs", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs<.cc> 0,limm,limm 001011101111111001111111100QQQQQ. */ -+{ "vaddsubs", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsubs2h a,b,c 00101bbb000101101BBBCCCCCCAAAAAA. */ -+{ "vaddsubs2h", 0x28168000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs2h 0,b,c 00101bbb000101101BBBCCCCCC111110. */ -+{ "vaddsubs2h", 0x2816803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs2h<.cc> b,b,c 00101bbb110101101BBBCCCCCC0QQQQQ. */ -+{ "vaddsubs2h", 0x28D68000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs2h a,b,u6 00101bbb010101101BBBuuuuuuAAAAAA. */ -+{ "vaddsubs2h", 0x28568000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs2h 0,b,u6 00101bbb010101101BBBuuuuuu111110. */ -+{ "vaddsubs2h", 0x2856803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs2h<.cc> b,b,u6 00101bbb110101101BBBuuuuuu1QQQQQ. */ -+{ "vaddsubs2h", 0x28D68020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs2h b,b,s12 00101bbb100101101BBBssssssSSSSSS. */ -+{ "vaddsubs2h", 0x28968000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs2h a,limm,c 00101110000101101111CCCCCCAAAAAA. */ -+{ "vaddsubs2h", 0x2E16F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs2h a,b,limm 00101bbb000101101BBB111110AAAAAA. */ -+{ "vaddsubs2h", 0x28168F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs2h 0,limm,c 00101110000101101111CCCCCC111110. */ -+{ "vaddsubs2h", 0x2E16F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs2h 0,b,limm 00101bbb000101101BBB111110111110. */ -+{ "vaddsubs2h", 0x28168FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs2h<.cc> b,b,limm 00101bbb110101101BBB1111100QQQQQ. */ -+{ "vaddsubs2h", 0x28D68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsubs2h<.cc> 0,limm,c 00101110110101101111CCCCCC0QQQQQ. */ -+{ "vaddsubs2h", 0x2ED6F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs2h a,limm,u6 00101110010101101111uuuuuuAAAAAA. */ -+{ "vaddsubs2h", 0x2E56F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs2h 0,limm,u6 00101110010101101111uuuuuu111110. */ -+{ "vaddsubs2h", 0x2E56F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs2h<.cc> 0,limm,u6 00101110110101101111uuuuuu1QQQQQ. */ -+{ "vaddsubs2h", 0x2ED6F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs2h 0,limm,s12 00101110100101101111ssssssSSSSSS. */ -+{ "vaddsubs2h", 0x2E96F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs2h a,limm,limm 00101110000101101111111110AAAAAA. */ -+{ "vaddsubs2h", 0x2E16FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs2h 0,limm,limm 00101110000101101111111110111110. */ -+{ "vaddsubs2h", 0x2E16FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs2h<.cc> 0,limm,limm 001011101101011011111111100QQQQQ. */ -+{ "vaddsubs2h", 0x2ED6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsubs4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA. */ -+{ "vaddsubs4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs4h 0,b,c 00101bbb001110100BBBCCCCCC111110. */ -+{ "vaddsubs4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ. */ -+{ "vaddsubs4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA. */ -+{ "vaddsubs4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs4h 0,b,u6 00101bbb011110100BBBuuuuuu111110. */ -+{ "vaddsubs4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ. */ -+{ "vaddsubs4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs4h b,b,s12 00101bbb101110100BBBssssssSSSSSS. */ -+{ "vaddsubs4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs4h a,limm,c 00101110001110100111CCCCCCAAAAAA. */ -+{ "vaddsubs4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs4h a,b,limm 00101bbb001110100BBB111110AAAAAA. */ -+{ "vaddsubs4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs4h 0,limm,c 00101110001110100111CCCCCC111110. */ -+{ "vaddsubs4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs4h 0,b,limm 00101bbb001110100BBB111110111110. */ -+{ "vaddsubs4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ. */ -+{ "vaddsubs4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsubs4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ. */ -+{ "vaddsubs4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs4h a,limm,u6 00101110011110100111uuuuuuAAAAAA. */ -+{ "vaddsubs4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs4h 0,limm,u6 00101110011110100111uuuuuu111110. */ -+{ "vaddsubs4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ. */ -+{ "vaddsubs4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs4h 0,limm,s12 00101110101110100111ssssssSSSSSS. */ -+{ "vaddsubs4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs4h a,limm,limm 00101110001110100111111110AAAAAA. */ -+{ "vaddsubs4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs4h 0,limm,limm 00101110001110100111111110111110. */ -+{ "vaddsubs4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ. */ -+{ "vaddsubs4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* valgn2h a,b,c 00101bbb000011010BBBCCCCCCAAAAAA. */ -+{ "valgn2h", 0x280D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* valgn2h 0,b,c 00101bbb000011010BBBCCCCCC111110. */ -+{ "valgn2h", 0x280D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* valgn2h<.cc> b,b,c 00101bbb110011010BBBCCCCCC0QQQQQ. */ -+{ "valgn2h", 0x28CD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* valgn2h a,b,u6 00101bbb010011010BBBuuuuuuAAAAAA. */ -+{ "valgn2h", 0x284D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* valgn2h 0,b,u6 00101bbb010011010BBBuuuuuu111110. */ -+{ "valgn2h", 0x284D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* valgn2h<.cc> b,b,u6 00101bbb110011010BBBuuuuuu1QQQQQ. */ -+{ "valgn2h", 0x28CD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* valgn2h b,b,s12 00101bbb100011010BBBssssssSSSSSS. */ -+{ "valgn2h", 0x288D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* valgn2h a,limm,c 00101110000011010111CCCCCCAAAAAA. */ -+{ "valgn2h", 0x2E0D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* valgn2h a,b,limm 00101bbb000011010BBB111110AAAAAA. */ -+{ "valgn2h", 0x280D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* valgn2h 0,limm,c 00101110000011010111CCCCCC111110. */ -+{ "valgn2h", 0x2E0D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* valgn2h 0,b,limm 00101bbb000011010BBB111110111110. */ -+{ "valgn2h", 0x280D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* valgn2h<.cc> b,b,limm 00101bbb110011010BBB1111100QQQQQ. */ -+{ "valgn2h", 0x28CD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* valgn2h<.cc> 0,limm,c 00101110110011010111CCCCCC0QQQQQ. */ -+{ "valgn2h", 0x2ECD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* valgn2h a,limm,u6 00101110010011010111uuuuuuAAAAAA. */ -+{ "valgn2h", 0x2E4D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* valgn2h 0,limm,u6 00101110010011010111uuuuuu111110. */ -+{ "valgn2h", 0x2E4D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* valgn2h<.cc> 0,limm,u6 00101110110011010111uuuuuu1QQQQQ. */ -+{ "valgn2h", 0x2ECD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* valgn2h 0,limm,s12 00101110100011010111ssssssSSSSSS. */ -+{ "valgn2h", 0x2E8D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* valgn2h a,limm,limm 00101110000011010111111110AAAAAA. */ -+{ "valgn2h", 0x2E0D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* valgn2h 0,limm,limm 00101110000011010111111110111110. */ -+{ "valgn2h", 0x2E0D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* valgn2h<.cc> 0,limm,limm 001011101100110101111111100QQQQQ. */ -+{ "valgn2h", 0x2ECD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasl2h a,b,c 00101bbb001000010BBBCCCCCCAAAAAA. */ -+{ "vasl2h", 0x28210000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasl2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */ -+{ "vasl2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasl2h<.cc> b,b,c 00101bbb111000010BBBCCCCCC0QQQQQ. */ -+{ "vasl2h", 0x28E10000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasl2h a,b,u6 00101bbb011000010BBBuuuuuuAAAAAA. */ -+{ "vasl2h", 0x28610000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasl2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */ -+{ "vasl2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasl2h<.cc> b,b,u6 00101bbb111000010BBBuuuuuu1QQQQQ. */ -+{ "vasl2h", 0x28E10020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasl2h b,b,s12 00101bbb101000010BBBssssssSSSSSS. */ -+{ "vasl2h", 0x28A10000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasl2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */ -+{ "vasl2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasl2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */ -+{ "vasl2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasl2h 0,limm,c 00101110011000010111CCCCCC111110. */ -+{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasl2h 0,b,limm 00101bbb001000010BBB111110111110. */ -+{ "vasl2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasl2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */ -+{ "vasl2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasl2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */ -+{ "vasl2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasl2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */ -+{ "vasl2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasl2h 0,limm,u6 00101110011000010111uuuuuu111110. */ -+{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasl2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */ -+{ "vasl2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasl2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */ -+{ "vasl2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasl2h a,limm,limm 00101110001000010111111110AAAAAA. */ -+{ "vasl2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasl2h 0,limm,limm 00101110001000010111111110111110. */ -+{ "vasl2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasl2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */ -+{ "vasl2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasls2h a,b,c 00101bbb001000011BBBCCCCCCAAAAAA. */ -+{ "vasls2h", 0x28218000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasls2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */ -+{ "vasls2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasls2h<.cc> b,b,c 00101bbb111000011BBBCCCCCC0QQQQQ. */ -+{ "vasls2h", 0x28E18000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasls2h a,b,u6 00101bbb011000011BBBuuuuuuAAAAAA. */ -+{ "vasls2h", 0x28618000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasls2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */ -+{ "vasls2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasls2h<.cc> b,b,u6 00101bbb111000011BBBuuuuuu1QQQQQ. */ -+{ "vasls2h", 0x28E18020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasls2h b,b,s12 00101bbb101000011BBBssssssSSSSSS. */ -+{ "vasls2h", 0x28A18000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasls2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */ -+{ "vasls2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasls2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */ -+{ "vasls2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasls2h 0,limm,c 00101110011000010111CCCCCC111110. */ -+{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasls2h 0,b,limm 00101bbb001000010BBB111110111110. */ -+{ "vasls2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasls2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */ -+{ "vasls2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasls2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */ -+{ "vasls2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasls2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */ -+{ "vasls2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasls2h 0,limm,u6 00101110011000010111uuuuuu111110. */ -+{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasls2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */ -+{ "vasls2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasls2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */ -+{ "vasls2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasls2h a,limm,limm 00101110001000010111111110AAAAAA. */ -+{ "vasls2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasls2h 0,limm,limm 00101110001000010111111110111110. */ -+{ "vasls2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasls2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */ -+{ "vasls2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasr2h a,b,c 00101bbb001000100BBBCCCCCCAAAAAA. */ -+{ "vasr2h", 0x28220000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasr2h 0,b,c 00101bbb001000100BBBCCCCCC111110. */ -+{ "vasr2h", 0x2822003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasr2h<.cc> b,b,c 00101bbb111000100BBBCCCCCC0QQQQQ. */ -+{ "vasr2h", 0x28E20000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasr2h a,b,u6 00101bbb011000100BBBuuuuuuAAAAAA. */ -+{ "vasr2h", 0x28620000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasr2h 0,b,u6 00101bbb011000100BBBuuuuuu111110. */ -+{ "vasr2h", 0x2862003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasr2h<.cc> b,b,u6 00101bbb111000100BBBuuuuuu1QQQQQ. */ -+{ "vasr2h", 0x28E20020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasr2h b,b,s12 00101bbb101000100BBBssssssSSSSSS. */ -+{ "vasr2h", 0x28A20000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasr2h a,limm,c 00101110001000100111CCCCCCAAAAAA. */ -+{ "vasr2h", 0x2E227000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasr2h a,b,limm 00101bbb001000100BBB111110AAAAAA. */ -+{ "vasr2h", 0x28220F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasr2h 0,limm,c 00101110011000100111CCCCCC111110. */ -+{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasr2h 0,b,limm 00101bbb001000100BBB111110111110. */ -+{ "vasr2h", 0x28220FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasr2h<.cc> b,b,limm 00101bbb111000100BBB1111100QQQQQ. */ -+{ "vasr2h", 0x28E20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasr2h<.cc> 0,limm,c 00101110111000100111CCCCCC0QQQQQ. */ -+{ "vasr2h", 0x2EE27000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasr2h a,limm,u6 00101110011000100111uuuuuuAAAAAA. */ -+{ "vasr2h", 0x2E627000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasr2h 0,limm,u6 00101110011000100111uuuuuu111110. */ -+{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasr2h<.cc> 0,limm,u6 00101110111000100111uuuuuu1QQQQQ. */ -+{ "vasr2h", 0x2EE27020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasr2h 0,limm,s12 00101110101000100111ssssssSSSSSS. */ -+{ "vasr2h", 0x2EA27000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasr2h a,limm,limm 00101110001000100111111110AAAAAA. */ -+{ "vasr2h", 0x2E227F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasr2h 0,limm,limm 00101110001000100111111110111110. */ -+{ "vasr2h", 0x2E227FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasr2h<.cc> 0,limm,limm 001011101110001001111111100QQQQQ. */ -+{ "vasr2h", 0x2EE27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasrs2h a,b,c 00101bbb001000101BBBCCCCCCAAAAAA. */ -+{ "vasrs2h", 0x28228000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasrs2h 0,b,c 00101bbb001000101BBBCCCCCC111110. */ -+{ "vasrs2h", 0x2822803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasrs2h<.cc> b,b,c 00101bbb111000101BBBCCCCCC0QQQQQ. */ -+{ "vasrs2h", 0x28E28000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasrs2h a,b,u6 00101bbb011000101BBBuuuuuuAAAAAA. */ -+{ "vasrs2h", 0x28628000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrs2h 0,b,u6 00101bbb011000101BBBuuuuuu111110. */ -+{ "vasrs2h", 0x2862803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrs2h<.cc> b,b,u6 00101bbb111000101BBBuuuuuu1QQQQQ. */ -+{ "vasrs2h", 0x28E28020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasrs2h b,b,s12 00101bbb101000101BBBssssssSSSSSS. */ -+{ "vasrs2h", 0x28A28000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasrs2h a,limm,c 00101110001000101111CCCCCCAAAAAA. */ -+{ "vasrs2h", 0x2E22F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasrs2h a,b,limm 00101bbb001000101BBB111110AAAAAA. */ -+{ "vasrs2h", 0x28228F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasrs2h 0,limm,c 00101110011000101111CCCCCC111110. */ -+{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasrs2h 0,b,limm 00101bbb001000101BBB111110111110. */ -+{ "vasrs2h", 0x28228FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasrs2h<.cc> b,b,limm 00101bbb111000101BBB1111100QQQQQ. */ -+{ "vasrs2h", 0x28E28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasrs2h<.cc> 0,limm,c 00101110111000101111CCCCCC0QQQQQ. */ -+{ "vasrs2h", 0x2EE2F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasrs2h a,limm,u6 00101110011000101111uuuuuuAAAAAA. */ -+{ "vasrs2h", 0x2E62F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrs2h 0,limm,u6 00101110011000101111uuuuuu111110. */ -+{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrs2h<.cc> 0,limm,u6 00101110111000101111uuuuuu1QQQQQ. */ -+{ "vasrs2h", 0x2EE2F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasrs2h 0,limm,s12 00101110101000101111ssssssSSSSSS. */ -+{ "vasrs2h", 0x2EA2F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasrs2h a,limm,limm 00101110001000101111111110AAAAAA. */ -+{ "vasrs2h", 0x2E22FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasrs2h 0,limm,limm 00101110001000101111111110111110. */ -+{ "vasrs2h", 0x2E22FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasrs2h<.cc> 0,limm,limm 001011101110001011111111100QQQQQ. */ -+{ "vasrs2h", 0x2EE2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasrsr2h a,b,c 00101bbb001000111BBBCCCCCCAAAAAA. */ -+{ "vasrsr2h", 0x28238000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasrsr2h 0,b,c 00101bbb001000111BBBCCCCCC111110. */ -+{ "vasrsr2h", 0x2823803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasrsr2h<.cc> b,b,c 00101bbb111000111BBBCCCCCC0QQQQQ. */ -+{ "vasrsr2h", 0x28E38000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasrsr2h a,b,u6 00101bbb011000111BBBuuuuuuAAAAAA. */ -+{ "vasrsr2h", 0x28638000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrsr2h 0,b,u6 00101bbb011000111BBBuuuuuu111110. */ -+{ "vasrsr2h", 0x2863803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrsr2h<.cc> b,b,u6 00101bbb111000111BBBuuuuuu1QQQQQ. */ -+{ "vasrsr2h", 0x28E38020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasrsr2h b,b,s12 00101bbb101000111BBBssssssSSSSSS. */ -+{ "vasrsr2h", 0x28A38000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasrsr2h a,limm,c 00101110001000111111CCCCCCAAAAAA. */ -+{ "vasrsr2h", 0x2E23F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasrsr2h a,b,limm 00101bbb001000111BBB111110AAAAAA. */ -+{ "vasrsr2h", 0x28238F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasrsr2h 0,limm,c 00101110011000111111CCCCCC111110. */ -+{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasrsr2h 0,b,limm 00101bbb001000111BBB111110111110. */ -+{ "vasrsr2h", 0x28238FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasrsr2h<.cc> b,b,limm 00101bbb111000111BBB1111100QQQQQ. */ -+{ "vasrsr2h", 0x28E38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasrsr2h<.cc> 0,limm,c 00101110111000111111CCCCCC0QQQQQ. */ -+{ "vasrsr2h", 0x2EE3F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasrsr2h a,limm,u6 00101110011000111111uuuuuuAAAAAA. */ -+{ "vasrsr2h", 0x2E63F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrsr2h 0,limm,u6 00101110011000111111uuuuuu111110. */ -+{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrsr2h<.cc> 0,limm,u6 00101110111000111111uuuuuu1QQQQQ. */ -+{ "vasrsr2h", 0x2EE3F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasrsr2h 0,limm,s12 00101110101000111111ssssssSSSSSS. */ -+{ "vasrsr2h", 0x2EA3F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasrsr2h a,limm,limm 00101110001000111111111110AAAAAA. */ -+{ "vasrsr2h", 0x2E23FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasrsr2h 0,limm,limm 00101110001000111111111110111110. */ -+{ "vasrsr2h", 0x2E23FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasrsr2h<.cc> 0,limm,limm 001011101110001111111111100QQQQQ. */ -+{ "vasrsr2h", 0x2EE3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vext2bhl b,c 00101bbb001011110BBBCCCCCC100100. */ -+{ "vext2bhl", 0x282F0024, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhl 0,c 00101110001011110111CCCCCC100100. */ -+{ "vext2bhl", 0x2E2F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhl b,u6 00101bbb011011110BBBuuuuuu100100. */ -+{ "vext2bhl", 0x286F0024, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhl 0,u6 00101110011011110111uuuuuu100100. */ -+{ "vext2bhl", 0x2E6F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhl b,limm 00101bbb001011110BBB111110100100. */ -+{ "vext2bhl", 0x282F0FA4, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhl 0,limm 00101110001011110111111110100100. */ -+{ "vext2bhl", 0x2E2F7FA4, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhlf b,c 00101bbb001011110BBBCCCCCC100000. */ -+{ "vext2bhlf", 0x282F0020, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhlf 0,c 00101110001011110111CCCCCC100000. */ -+{ "vext2bhlf", 0x2E2F7020, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhlf b,u6 00101bbb011011110BBBuuuuuu100000. */ -+{ "vext2bhlf", 0x286F0020, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhlf 0,u6 00101110011011110111uuuuuu100000. */ -+{ "vext2bhlf", 0x2E6F7020, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhlf b,limm 00101bbb001011110BBB111110100000. */ -+{ "vext2bhlf", 0x282F0FA0, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhlf 0,limm 00101110001011110111111110100000. */ -+{ "vext2bhlf", 0x2E2F7FA0, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhm b,c 00101bbb001011110BBBCCCCCC100101. */ -+{ "vext2bhm", 0x282F0025, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhm 0,c 00101110001011110111CCCCCC100101. */ -+{ "vext2bhm", 0x2E2F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhm b,u6 00101bbb011011110BBBuuuuuu100101. */ -+{ "vext2bhm", 0x286F0025, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhm 0,u6 00101110011011110111uuuuuu100101. */ -+{ "vext2bhm", 0x2E6F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhm b,limm 00101bbb001011110BBB111110100101. */ -+{ "vext2bhm", 0x282F0FA5, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhm 0,limm 00101110001011110111111110100101. */ -+{ "vext2bhm", 0x2E2F7FA5, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhmf b,c 00101bbb001011110BBBCCCCCC100001. */ -+{ "vext2bhmf", 0x282F0021, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhmf 0,c 00101110001011110111CCCCCC100001. */ -+{ "vext2bhmf", 0x2E2F7021, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhmf b,u6 00101bbb011011110BBBuuuuuu100001. */ -+{ "vext2bhmf", 0x286F0021, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhmf 0,u6 00101110011011110111uuuuuu100001. */ -+{ "vext2bhmf", 0x2E6F7021, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhmf b,limm 00101bbb001011110BBB111110100001. */ -+{ "vext2bhmf", 0x282F0FA1, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhmf 0,limm 00101110001011110111111110100001. */ -+{ "vext2bhmf", 0x2E2F7FA1, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vlsr2h a,b,c 00101bbb001000110BBBCCCCCCAAAAAA. */ -+{ "vlsr2h", 0x28230000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vlsr2h 0,b,c 00101bbb001000110BBBCCCCCC111110. */ -+{ "vlsr2h", 0x2823003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vlsr2h<.cc> b,b,c 00101bbb111000110BBBCCCCCC0QQQQQ. */ -+{ "vlsr2h", 0x28E30000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vlsr2h a,b,u6 00101bbb011000110BBBuuuuuuAAAAAA. */ -+{ "vlsr2h", 0x28630000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vlsr2h 0,b,u6 00101bbb011000110BBBuuuuuu111110. */ -+{ "vlsr2h", 0x2863003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vlsr2h<.cc> b,b,u6 00101bbb111000110BBBuuuuuu1QQQQQ. */ -+{ "vlsr2h", 0x28E30020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vlsr2h b,b,s12 00101bbb101000110BBBssssssSSSSSS. */ -+{ "vlsr2h", 0x28A30000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vlsr2h a,limm,c 00101110001000110111CCCCCCAAAAAA. */ -+{ "vlsr2h", 0x2E237000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vlsr2h a,b,limm 00101bbb001000110BBB111110AAAAAA. */ -+{ "vlsr2h", 0x28230F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vlsr2h 0,limm,c 00101110011000110111CCCCCC111110. */ -+{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vlsr2h 0,b,limm 00101bbb001000110BBB111110111110. */ -+{ "vlsr2h", 0x28230FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vlsr2h<.cc> b,b,limm 00101bbb111000110BBB1111100QQQQQ. */ -+{ "vlsr2h", 0x28E30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vlsr2h<.cc> 0,limm,c 00101110111000110111CCCCCC0QQQQQ. */ -+{ "vlsr2h", 0x2EE37000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vlsr2h a,limm,u6 00101110011000110111uuuuuuAAAAAA. */ -+{ "vlsr2h", 0x2E637000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vlsr2h 0,limm,u6 00101110011000110111uuuuuu111110. */ -+{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vlsr2h<.cc> 0,limm,u6 00101110111000110111uuuuuu1QQQQQ. */ -+{ "vlsr2h", 0x2EE37020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vlsr2h 0,limm,s12 00101110101000110111ssssssSSSSSS. */ -+{ "vlsr2h", 0x2EA37000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vlsr2h a,limm,limm 00101110001000110111111110AAAAAA. */ -+{ "vlsr2h", 0x2E237F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vlsr2h 0,limm,limm 00101110001000110111111110111110. */ -+{ "vlsr2h", 0x2E237FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vlsr2h<.cc> 0,limm,limm 001011101110001101111111100QQQQQ. */ -+{ "vlsr2h", 0x2EE37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2h a,b,c 00101bbb000111100BBBCCCCCCAAAAAA. */ -+{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2h 0,b,c 00101bbb000111100BBBCCCCCC111110. */ -+{ "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2h<.cc> b,b,c 00101bbb110111100BBBCCCCCC0QQQQQ. */ -+{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2h a,b,u6 00101bbb010111100BBBuuuuuuAAAAAA. */ -+{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2h 0,b,u6 00101bbb010111100BBBuuuuuu111110. */ -+{ "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2h<.cc> b,b,u6 00101bbb110111100BBBuuuuuu1QQQQQ. */ -+{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2h b,b,s12 00101bbb100111100BBBssssssSSSSSS. */ -+{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2h a,limm,c 00101110000111100111CCCCCCAAAAAA. */ -+{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2h a,b,limm 00101bbb000111100BBB111110AAAAAA. */ -+{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2h 0,limm,c 00101110000111100111CCCCCC111110. */ -+{ "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2h 0,b,limm 00101bbb000111100BBB111110111110. */ -+{ "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2h<.cc> b,b,limm 00101bbb110111100BBB1111100QQQQQ. */ -+{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2h<.cc> 0,limm,c 00101110110111100111CCCCCC0QQQQQ. */ -+{ "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2h a,limm,u6 00101110010111100111uuuuuuAAAAAA. */ -+{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2h 0,limm,u6 00101110010111100111uuuuuu111110. */ -+{ "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2h<.cc> 0,limm,u6 00101110110111100111uuuuuu1QQQQQ. */ -+{ "vmac2h", 0x2EDE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2h 0,limm,s12 00101110100111100111ssssssSSSSSS. */ -+{ "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2h a,limm,limm 00101110000111100111111110AAAAAA. */ -+{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2h 0,limm,limm 00101110000111100111111110111110. */ -+{ "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2h<.cc> 0,limm,limm 001011101101111001111111100QQQQQ. */ -+{ "vmac2h", 0x2EDE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2hf a,b,c 00101bbb000111101BBBCCCCCCAAAAAA. */ -+{ "vmac2hf", 0x281E8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hf 0,b,c 00101bbb000111101BBBCCCCCC111110. */ -+{ "vmac2hf", 0x281E803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hf<.cc> b,b,c 00101bbb110111101BBBCCCCCC0QQQQQ. */ -+{ "vmac2hf", 0x28DE8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hf a,b,u6 00101bbb010111101BBBuuuuuuAAAAAA. */ -+{ "vmac2hf", 0x285E8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hf 0,b,u6 00101bbb010111101BBBuuuuuu111110. */ -+{ "vmac2hf", 0x285E803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hf<.cc> b,b,u6 00101bbb110111101BBBuuuuuu1QQQQQ. */ -+{ "vmac2hf", 0x28DE8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hf b,b,s12 00101bbb100111101BBBssssssSSSSSS. */ -+{ "vmac2hf", 0x289E8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hf a,limm,c 00101110000111101111CCCCCCAAAAAA. */ -+{ "vmac2hf", 0x2E1EF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hf a,b,limm 00101bbb000111101BBB111110AAAAAA. */ -+{ "vmac2hf", 0x281E8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hf 0,limm,c 00101110000111101111CCCCCC111110. */ -+{ "vmac2hf", 0x2E1EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hf 0,b,limm 00101bbb000111101BBB111110111110. */ -+{ "vmac2hf", 0x281E8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hf<.cc> b,b,limm 00101bbb110111101BBB1111100QQQQQ. */ -+{ "vmac2hf", 0x28DE8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2hf<.cc> 0,limm,c 00101110110111101111CCCCCC0QQQQQ. */ -+{ "vmac2hf", 0x2EDEF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hf a,limm,u6 00101110010111101111uuuuuuAAAAAA. */ -+{ "vmac2hf", 0x2E5EF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hf 0,limm,u6 00101110010111101111uuuuuu111110. */ -+{ "vmac2hf", 0x2E5EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hf<.cc> 0,limm,u6 00101110110111101111uuuuuu1QQQQQ. */ -+{ "vmac2hf", 0x2EDEF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hf 0,limm,s12 00101110100111101111ssssssSSSSSS. */ -+{ "vmac2hf", 0x2E9EF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hf a,limm,limm 00101110000111101111111110AAAAAA. */ -+{ "vmac2hf", 0x2E1EFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hf 0,limm,limm 00101110000111101111111110111110. */ -+{ "vmac2hf", 0x2E1EFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hf<.cc> 0,limm,limm 001011101101111011111111100QQQQQ. */ -+{ "vmac2hf", 0x2EDEFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2hfr a,b,c 00101bbb000111111BBBCCCCCCAAAAAA. */ -+{ "vmac2hfr", 0x281F8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hfr 0,b,c 00101bbb000111111BBBCCCCCC111110. */ -+{ "vmac2hfr", 0x281F803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hfr<.cc> b,b,c 00101bbb110111111BBBCCCCCC0QQQQQ. */ -+{ "vmac2hfr", 0x28DF8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hfr a,b,u6 00101bbb010111111BBBuuuuuuAAAAAA. */ -+{ "vmac2hfr", 0x285F8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hfr 0,b,u6 00101bbb010111111BBBuuuuuu111110. */ -+{ "vmac2hfr", 0x285F803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hfr<.cc> b,b,u6 00101bbb110111111BBBuuuuuu1QQQQQ. */ -+{ "vmac2hfr", 0x28DF8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hfr b,b,s12 00101bbb100111111BBBssssssSSSSSS. */ -+{ "vmac2hfr", 0x289F8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hfr a,limm,c 00101110000111111111CCCCCCAAAAAA. */ -+{ "vmac2hfr", 0x2E1FF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hfr a,b,limm 00101bbb000111111BBB111110AAAAAA. */ -+{ "vmac2hfr", 0x281F8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hfr 0,limm,c 00101110000111111111CCCCCC111110. */ -+{ "vmac2hfr", 0x2E1FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hfr 0,b,limm 00101bbb000111111BBB111110111110. */ -+{ "vmac2hfr", 0x281F8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hfr<.cc> b,b,limm 00101bbb110111111BBB1111100QQQQQ. */ -+{ "vmac2hfr", 0x28DF8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2hfr<.cc> 0,limm,c 00101110110111111111CCCCCC0QQQQQ. */ -+{ "vmac2hfr", 0x2EDFF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hfr a,limm,u6 00101110010111111111uuuuuuAAAAAA. */ -+{ "vmac2hfr", 0x2E5FF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hfr 0,limm,u6 00101110010111111111uuuuuu111110. */ -+{ "vmac2hfr", 0x2E5FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hfr<.cc> 0,limm,u6 00101110110111111111uuuuuu1QQQQQ. */ -+{ "vmac2hfr", 0x2EDFF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hfr 0,limm,s12 00101110100111111111ssssssSSSSSS. */ -+{ "vmac2hfr", 0x2E9FF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hfr a,limm,limm 00101110000111111111111110AAAAAA. */ -+{ "vmac2hfr", 0x2E1FFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hfr 0,limm,limm 00101110000111111111111110111110. */ -+{ "vmac2hfr", 0x2E1FFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hfr<.cc> 0,limm,limm 001011101101111111111111100QQQQQ. */ -+{ "vmac2hfr", 0x2EDFFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2hnfr a,b,c 00110bbb000100010BBBCCCCCCAAAAAA. */ -+{ "vmac2hnfr", 0x30110000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hnfr 0,b,c 00110bbb000100010BBBCCCCCC111110. */ -+{ "vmac2hnfr", 0x3011003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hnfr<.cc> b,b,c 00110bbb110100010BBBCCCCCC0QQQQQ. */ -+{ "vmac2hnfr", 0x30D10000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hnfr a,b,u6 00110bbb010100010BBBuuuuuuAAAAAA. */ -+{ "vmac2hnfr", 0x30510000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hnfr 0,b,u6 00110bbb010100010BBBuuuuuu111110. */ -+{ "vmac2hnfr", 0x3051003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hnfr<.cc> b,b,u6 00110bbb110100010BBBuuuuuu1QQQQQ. */ -+{ "vmac2hnfr", 0x30D10020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hnfr b,b,s12 00110bbb100100010BBBssssssSSSSSS. */ -+{ "vmac2hnfr", 0x30910000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hnfr a,limm,c 00110110000100010111CCCCCCAAAAAA. */ -+{ "vmac2hnfr", 0x36117000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hnfr a,b,limm 00110bbb000100010BBB111110AAAAAA. */ -+{ "vmac2hnfr", 0x30110F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hnfr 0,limm,c 00110110000100010111CCCCCC111110. */ -+{ "vmac2hnfr", 0x3611703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hnfr 0,b,limm 00110bbb000100010BBB111110111110. */ -+{ "vmac2hnfr", 0x30110FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hnfr<.cc> b,b,limm 00110bbb110100010BBB1111100QQQQQ. */ -+{ "vmac2hnfr", 0x30D10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2hnfr<.cc> 0,limm,c 00110110110100010111CCCCCC0QQQQQ. */ -+{ "vmac2hnfr", 0x36D17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hnfr a,limm,u6 00110110010100010111uuuuuuAAAAAA. */ -+{ "vmac2hnfr", 0x36517000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hnfr 0,limm,u6 00110110010100010111uuuuuu111110. */ -+{ "vmac2hnfr", 0x3651703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hnfr<.cc> 0,limm,u6 00110110110100010111uuuuuu1QQQQQ. */ -+{ "vmac2hnfr", 0x36D17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hnfr 0,limm,s12 00110110100100010111ssssssSSSSSS. */ -+{ "vmac2hnfr", 0x36917000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hnfr a,limm,limm 00110110000100010111111110AAAAAA. */ -+{ "vmac2hnfr", 0x36117F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hnfr 0,limm,limm 00110110000100010111111110111110. */ -+{ "vmac2hnfr", 0x36117FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hnfr<.cc> 0,limm,limm 001101101101000101111111100QQQQQ. */ -+{ "vmac2hnfr", 0x36D17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2hu a,b,c 00101bbb000111110BBBCCCCCCAAAAAA. */ -+{ "vmac2hu", 0x281F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hu 0,b,c 00101bbb000111110BBBCCCCCC111110. */ -+{ "vmac2hu", 0x281F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hu<.cc> b,b,c 00101bbb110111110BBBCCCCCC0QQQQQ. */ -+{ "vmac2hu", 0x28DF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hu a,b,u6 00101bbb010111110BBBuuuuuuAAAAAA. */ -+{ "vmac2hu", 0x285F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hu 0,b,u6 00101bbb010111110BBBuuuuuu111110. */ -+{ "vmac2hu", 0x285F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hu<.cc> b,b,u6 00101bbb110111110BBBuuuuuu1QQQQQ. */ -+{ "vmac2hu", 0x28DF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hu b,b,s12 00101bbb100111110BBBssssssSSSSSS. */ -+{ "vmac2hu", 0x289F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hu a,limm,c 00101110000111110111CCCCCCAAAAAA. */ -+{ "vmac2hu", 0x2E1F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hu a,b,limm 00101bbb000111110BBB111110AAAAAA. */ -+{ "vmac2hu", 0x281F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hu 0,limm,c 00101110000111110111CCCCCC111110. */ -+{ "vmac2hu", 0x2E1F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hu 0,b,limm 00101bbb000111110BBB111110111110. */ -+{ "vmac2hu", 0x281F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hu<.cc> b,b,limm 00101bbb110111110BBB1111100QQQQQ. */ -+{ "vmac2hu", 0x28DF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2hu<.cc> 0,limm,c 00101110110111110111CCCCCC0QQQQQ. */ -+{ "vmac2hu", 0x2EDF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hu a,limm,u6 00101110010111110111uuuuuuAAAAAA. */ -+{ "vmac2hu", 0x2E5F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hu 0,limm,u6 00101110010111110111uuuuuu111110. */ -+{ "vmac2hu", 0x2E5F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hu<.cc> 0,limm,u6 00101110110111110111uuuuuu1QQQQQ. */ -+{ "vmac2hu", 0x2EDF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hu 0,limm,s12 00101110100111110111ssssssSSSSSS. */ -+{ "vmac2hu", 0x2E9F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hu a,limm,limm 00101110000111110111111110AAAAAA. */ -+{ "vmac2hu", 0x2E1F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hu 0,limm,limm 00101110000111110111111110111110. */ -+{ "vmac2hu", 0x2E1F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hu<.cc> 0,limm,limm 001011101101111101111111100QQQQQ. */ -+{ "vmac2hu", 0x2EDF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmax2h a,b,c 00101bbb001001001BBBCCCCCCAAAAAA. */ -+{ "vmax2h", 0x28248000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmax2h 0,b,c 00101bbb001001001BBBCCCCCC111110. */ -+{ "vmax2h", 0x2824803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmax2h<.cc> b,b,c 00101bbb111001001BBBCCCCCC0QQQQQ. */ -+{ "vmax2h", 0x28E48000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmax2h a,b,u6 00101bbb011001001BBBuuuuuuAAAAAA. */ -+{ "vmax2h", 0x28648000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmax2h 0,b,u6 00101bbb011001001BBBuuuuuu111110. */ -+{ "vmax2h", 0x2864803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmax2h<.cc> b,b,u6 00101bbb111001001BBBuuuuuu1QQQQQ. */ -+{ "vmax2h", 0x28E48020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmax2h b,b,s12 00101bbb101001001BBBssssssSSSSSS. */ -+{ "vmax2h", 0x28A48000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmax2h a,limm,c 00101110001001001111CCCCCCAAAAAA. */ -+{ "vmax2h", 0x2E24F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmax2h a,b,limm 00101bbb001001001BBB111110AAAAAA. */ -+{ "vmax2h", 0x28248F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmax2h 0,limm,c 00101110011001001111CCCCCC111110. */ -+{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmax2h 0,b,limm 00101bbb001001001BBB111110111110. */ -+{ "vmax2h", 0x28248FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmax2h<.cc> b,b,limm 00101bbb111001001BBB1111100QQQQQ. */ -+{ "vmax2h", 0x28E48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmax2h<.cc> 0,limm,c 00101110111001001111CCCCCC0QQQQQ. */ -+{ "vmax2h", 0x2EE4F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmax2h a,limm,u6 00101110011001001111uuuuuuAAAAAA. */ -+{ "vmax2h", 0x2E64F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmax2h 0,limm,u6 00101110011001001111uuuuuu111110. */ -+{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmax2h<.cc> 0,limm,u6 00101110111001001111uuuuuu1QQQQQ. */ -+{ "vmax2h", 0x2EE4F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmax2h 0,limm,s12 00101110101001001111ssssssSSSSSS. */ -+{ "vmax2h", 0x2EA4F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmax2h a,limm,limm 00101110001001001111111110AAAAAA. */ -+{ "vmax2h", 0x2E24FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmax2h 0,limm,limm 00101110001001001111111110111110. */ -+{ "vmax2h", 0x2E24FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmax2h<.cc> 0,limm,limm 001011101110010011111111100QQQQQ. */ -+{ "vmax2h", 0x2EE4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmin2h a,b,c 00101bbb001001011BBBCCCCCCAAAAAA. */ -+{ "vmin2h", 0x28258000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmin2h 0,b,c 00101bbb001001011BBBCCCCCC111110. */ -+{ "vmin2h", 0x2825803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmin2h<.cc> b,b,c 00101bbb111001011BBBCCCCCC0QQQQQ. */ -+{ "vmin2h", 0x28E58000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmin2h a,b,u6 00101bbb011001011BBBuuuuuuAAAAAA. */ -+{ "vmin2h", 0x28658000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmin2h 0,b,u6 00101bbb011001011BBBuuuuuu111110. */ -+{ "vmin2h", 0x2865803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmin2h<.cc> b,b,u6 00101bbb111001011BBBuuuuuu1QQQQQ. */ -+{ "vmin2h", 0x28E58020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmin2h b,b,s12 00101bbb101001011BBBssssssSSSSSS. */ -+{ "vmin2h", 0x28A58000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmin2h a,limm,c 00101110001001011111CCCCCCAAAAAA. */ -+{ "vmin2h", 0x2E25F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmin2h a,b,limm 00101bbb001001011BBB111110AAAAAA. */ -+{ "vmin2h", 0x28258F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmin2h 0,limm,c 00101110011001011111CCCCCC111110. */ -+{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmin2h 0,b,limm 00101bbb001001011BBB111110111110. */ -+{ "vmin2h", 0x28258FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmin2h<.cc> b,b,limm 00101bbb111001011BBB1111100QQQQQ. */ -+{ "vmin2h", 0x28E58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmin2h<.cc> 0,limm,c 00101110111001011111CCCCCC0QQQQQ. */ -+{ "vmin2h", 0x2EE5F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmin2h a,limm,u6 00101110011001011111uuuuuuAAAAAA. */ -+{ "vmin2h", 0x2E65F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmin2h 0,limm,u6 00101110011001011111uuuuuu111110. */ -+{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmin2h<.cc> 0,limm,u6 00101110111001011111uuuuuu1QQQQQ. */ -+{ "vmin2h", 0x2EE5F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmin2h 0,limm,s12 00101110101001011111ssssssSSSSSS. */ -+{ "vmin2h", 0x2EA5F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmin2h a,limm,limm 00101110001001011111111110AAAAAA. */ -+{ "vmin2h", 0x2E25FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmin2h 0,limm,limm 00101110001001011111111110111110. */ -+{ "vmin2h", 0x2E25FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmin2h<.cc> 0,limm,limm 001011101110010111111111100QQQQQ. */ -+{ "vmin2h", 0x2EE5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */ -+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */ -+{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */ -+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */ -+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */ -+{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */ -+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */ -+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */ -+{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */ -+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */ -+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */ -+{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */ -+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */ -+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */ -+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */ -+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */ -+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */ -+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */ -+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */ -+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */ -+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */ -+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */ -+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */ -+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */ -+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */ -+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */ -+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */ -+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */ -+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */ -+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */ -+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */ -+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */ -+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */ -+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */ -+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */ -+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */ -+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */ -+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */ -+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */ -+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */ -+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hf a,b,c 00101bbb000111001BBBCCCCCCAAAAAA. */ -+{ "vmpy2hf", 0x281C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hf 0,b,c 00101bbb000111001BBBCCCCCC111110. */ -+{ "vmpy2hf", 0x281C803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hf<.cc> b,b,c 00101bbb110111001BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hf", 0x28DC8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hf a,b,u6 00101bbb010111001BBBuuuuuuAAAAAA. */ -+{ "vmpy2hf", 0x285C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hf 0,b,u6 00101bbb010111001BBBuuuuuu111110. */ -+{ "vmpy2hf", 0x285C803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hf<.cc> b,b,u6 00101bbb110111001BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hf", 0x28DC8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hf b,b,s12 00101bbb100111001BBBssssssSSSSSS. */ -+{ "vmpy2hf", 0x289C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hf a,limm,c 00101110000111001111CCCCCCAAAAAA. */ -+{ "vmpy2hf", 0x2E1CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hf a,b,limm 00101bbb000111001BBB111110AAAAAA. */ -+{ "vmpy2hf", 0x281C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hf 0,limm,c 00101110000111001111CCCCCC111110. */ -+{ "vmpy2hf", 0x2E1CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hf 0,b,limm 00101bbb000111001BBB111110111110. */ -+{ "vmpy2hf", 0x281C8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hf<.cc> b,b,limm 00101bbb110111001BBB1111100QQQQQ. */ -+{ "vmpy2hf", 0x28DC8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hf<.cc> 0,limm,c 00101110110111001111CCCCCC0QQQQQ. */ -+{ "vmpy2hf", 0x2EDCF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hf a,limm,u6 00101110010111001111uuuuuuAAAAAA. */ -+{ "vmpy2hf", 0x2E5CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hf 0,limm,u6 00101110010111001111uuuuuu111110. */ -+{ "vmpy2hf", 0x2E5CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hf<.cc> 0,limm,u6 00101110110111001111uuuuuu1QQQQQ. */ -+{ "vmpy2hf", 0x2EDCF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hf 0,limm,s12 00101110100111001111ssssssSSSSSS. */ -+{ "vmpy2hf", 0x2E9CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hf a,limm,limm 00101110000111001111111110AAAAAA. */ -+{ "vmpy2hf", 0x2E1CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hf 0,limm,limm 00101110000111001111111110111110. */ -+{ "vmpy2hf", 0x2E1CFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hf<.cc> 0,limm,limm 001011101101110011111111100QQQQQ. */ -+{ "vmpy2hf", 0x2EDCFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hfr a,b,c 00101bbb000111011BBBCCCCCCAAAAAA. */ -+{ "vmpy2hfr", 0x281D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hfr 0,b,c 00101bbb000111011BBBCCCCCC111110. */ -+{ "vmpy2hfr", 0x281D803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hfr<.cc> b,b,c 00101bbb110111011BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hfr", 0x28DD8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hfr a,b,u6 00101bbb010111011BBBuuuuuuAAAAAA. */ -+{ "vmpy2hfr", 0x285D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hfr 0,b,u6 00101bbb010111011BBBuuuuuu111110. */ -+{ "vmpy2hfr", 0x285D803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hfr<.cc> b,b,u6 00101bbb110111011BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hfr", 0x28DD8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hfr b,b,s12 00101bbb100111011BBBssssssSSSSSS. */ -+{ "vmpy2hfr", 0x289D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hfr a,limm,c 00101110000111011111CCCCCCAAAAAA. */ -+{ "vmpy2hfr", 0x2E1DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hfr a,b,limm 00101bbb000111011BBB111110AAAAAA. */ -+{ "vmpy2hfr", 0x281D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hfr 0,limm,c 00101110000111011111CCCCCC111110. */ -+{ "vmpy2hfr", 0x2E1DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hfr 0,b,limm 00101bbb000111011BBB111110111110. */ -+{ "vmpy2hfr", 0x281D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hfr<.cc> b,b,limm 00101bbb110111011BBB1111100QQQQQ. */ -+{ "vmpy2hfr", 0x28DD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hfr<.cc> 0,limm,c 00101110110111011111CCCCCC0QQQQQ. */ -+{ "vmpy2hfr", 0x2EDDF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hfr a,limm,u6 00101110010111011111uuuuuuAAAAAA. */ -+{ "vmpy2hfr", 0x2E5DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hfr 0,limm,u6 00101110010111011111uuuuuu111110. */ -+{ "vmpy2hfr", 0x2E5DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hfr<.cc> 0,limm,u6 00101110110111011111uuuuuu1QQQQQ. */ -+{ "vmpy2hfr", 0x2EDDF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hfr 0,limm,s12 00101110100111011111ssssssSSSSSS. */ -+{ "vmpy2hfr", 0x2E9DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hfr a,limm,limm 00101110000111011111111110AAAAAA. */ -+{ "vmpy2hfr", 0x2E1DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hfr 0,limm,limm 00101110000111011111111110111110. */ -+{ "vmpy2hfr", 0x2E1DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hfr<.cc> 0,limm,limm 001011101101110111111111100QQQQQ. */ -+{ "vmpy2hfr", 0x2EDDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */ -+{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */ -+{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */ -+{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */ -+{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */ -+{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */ -+{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */ -+{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */ -+{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */ -+{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */ -+{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */ -+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */ -+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */ -+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */ -+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */ -+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */ -+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */ -+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */ -+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */ -+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */ -+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */ -+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */ -+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */ -+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */ -+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */ -+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */ -+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */ -+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */ -+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */ -+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */ -+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hwf a,b,c 00101bbb001000000BBBCCCCCCAAAAAA. */ -+{ "vmpy2hwf", 0x28200000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hwf 0,b,c 00101bbb001000000BBBCCCCCC111110. */ -+{ "vmpy2hwf", 0x2820003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hwf<.cc> b,b,c 00101bbb111000000BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hwf", 0x28E00000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hwf a,b,u6 00101bbb011000000BBBuuuuuuAAAAAA. */ -+{ "vmpy2hwf", 0x28600000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hwf 0,b,u6 00101bbb011000000BBBuuuuuu111110. */ -+{ "vmpy2hwf", 0x2860003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hwf<.cc> b,b,u6 00101bbb111000000BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hwf", 0x28E00020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hwf b,b,s12 00101bbb101000000BBBssssssSSSSSS. */ -+{ "vmpy2hwf", 0x28A00000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hwf a,limm,c 00101110001000000111CCCCCCAAAAAA. */ -+{ "vmpy2hwf", 0x2E207000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hwf a,b,limm 00101bbb001000000BBB111110AAAAAA. */ -+{ "vmpy2hwf", 0x28200F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hwf 0,limm,c 00101110011000000111CCCCCC111110. */ -+{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hwf 0,b,limm 00101bbb001000000BBB111110111110. */ -+{ "vmpy2hwf", 0x28200FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hwf<.cc> b,b,limm 00101bbb111000000BBB1111100QQQQQ. */ -+{ "vmpy2hwf", 0x28E00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hwf<.cc> 0,limm,c 00101110111000000111CCCCCC0QQQQQ. */ -+{ "vmpy2hwf", 0x2EE07000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hwf a,limm,u6 00101110011000000111uuuuuuAAAAAA. */ -+{ "vmpy2hwf", 0x2E607000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hwf 0,limm,u6 00101110011000000111uuuuuu111110. */ -+{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hwf<.cc> 0,limm,u6 00101110111000000111uuuuuu1QQQQQ. */ -+{ "vmpy2hwf", 0x2EE07020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hwf 0,limm,s12 00101110101000000111ssssssSSSSSS. */ -+{ "vmpy2hwf", 0x2EA07000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hwf a,limm,limm 00101110001000000111111110AAAAAA. */ -+{ "vmpy2hwf", 0x2E207F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hwf 0,limm,limm 00101110001000000111111110111110. */ -+{ "vmpy2hwf", 0x2E207FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hwf<.cc> 0,limm,limm 001011101110000001111111100QQQQQ. */ -+{ "vmpy2hwf", 0x2EE07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmsub2hf a,b,c 00110bbb000001000BBBCCCCCCAAAAAA. */ -+{ "vmsub2hf", 0x30040000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hf 0,b,c 00110bbb000001000BBBCCCCCC111110. */ -+{ "vmsub2hf", 0x3004003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hf<.cc> b,b,c 00110bbb110001000BBBCCCCCC0QQQQQ. */ -+{ "vmsub2hf", 0x30C40000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hf a,b,u6 00110bbb010001000BBBuuuuuuAAAAAA. */ -+{ "vmsub2hf", 0x30440000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hf 0,b,u6 00110bbb010001000BBBuuuuuu111110. */ -+{ "vmsub2hf", 0x3044003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hf<.cc> b,b,u6 00110bbb110001000BBBuuuuuu1QQQQQ. */ -+{ "vmsub2hf", 0x30C40020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hf b,b,s12 00110bbb100001000BBBssssssSSSSSS. */ -+{ "vmsub2hf", 0x30840000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hf a,limm,c 00110110000001000111CCCCCCAAAAAA. */ -+{ "vmsub2hf", 0x36047000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hf a,b,limm 00110bbb000001000BBB111110AAAAAA. */ -+{ "vmsub2hf", 0x30040F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hf 0,limm,c 00110110000001000111CCCCCC111110. */ -+{ "vmsub2hf", 0x3604703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hf 0,b,limm 00110bbb000001000BBB111110111110. */ -+{ "vmsub2hf", 0x30040FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hf<.cc> b,b,limm 00110bbb110001000BBB1111100QQQQQ. */ -+{ "vmsub2hf", 0x30C40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmsub2hf<.cc> 0,limm,c 00110110110001000111CCCCCC0QQQQQ. */ -+{ "vmsub2hf", 0x36C47000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hf a,limm,u6 00110110010001000111uuuuuuAAAAAA. */ -+{ "vmsub2hf", 0x36447000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hf 0,limm,u6 00110110010001000111uuuuuu111110. */ -+{ "vmsub2hf", 0x3644703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hf<.cc> 0,limm,u6 00110110110001000111uuuuuu1QQQQQ. */ -+{ "vmsub2hf", 0x36C47020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hf 0,limm,s12 00110110100001000111ssssssSSSSSS. */ -+{ "vmsub2hf", 0x36847000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hf a,limm,limm 00110110000001000111111110AAAAAA. */ -+{ "vmsub2hf", 0x36047F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hf 0,limm,limm 00110110000001000111111110111110. */ -+{ "vmsub2hf", 0x36047FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hf<.cc> 0,limm,limm 001101101100010001111111100QQQQQ. */ -+{ "vmsub2hf", 0x36C47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmsub2hfr a,b,c 00110bbb000000110BBBCCCCCCAAAAAA. */ -+{ "vmsub2hfr", 0x30030000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hfr 0,b,c 00110bbb000000110BBBCCCCCC111110. */ -+{ "vmsub2hfr", 0x3003003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hfr<.cc> b,b,c 00110bbb110000110BBBCCCCCC0QQQQQ. */ -+{ "vmsub2hfr", 0x30C30000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hfr a,b,u6 00110bbb010000110BBBuuuuuuAAAAAA. */ -+{ "vmsub2hfr", 0x30430000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hfr 0,b,u6 00110bbb010000110BBBuuuuuu111110. */ -+{ "vmsub2hfr", 0x3043003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hfr<.cc> b,b,u6 00110bbb110000110BBBuuuuuu1QQQQQ. */ -+{ "vmsub2hfr", 0x30C30020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hfr b,b,s12 00110bbb100000110BBBssssssSSSSSS. */ -+{ "vmsub2hfr", 0x30830000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hfr a,limm,c 00110110000000110111CCCCCCAAAAAA. */ -+{ "vmsub2hfr", 0x36037000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hfr a,b,limm 00110bbb000000110BBB111110AAAAAA. */ -+{ "vmsub2hfr", 0x30030F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hfr 0,limm,c 00110110000000110111CCCCCC111110. */ -+{ "vmsub2hfr", 0x3603703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hfr 0,b,limm 00110bbb000000110BBB111110111110. */ -+{ "vmsub2hfr", 0x30030FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hfr<.cc> b,b,limm 00110bbb110000110BBB1111100QQQQQ. */ -+{ "vmsub2hfr", 0x30C30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmsub2hfr<.cc> 0,limm,c 00110110110000110111CCCCCC0QQQQQ. */ -+{ "vmsub2hfr", 0x36C37000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hfr a,limm,u6 00110110010000110111uuuuuuAAAAAA. */ -+{ "vmsub2hfr", 0x36437000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hfr 0,limm,u6 00110110010000110111uuuuuu111110. */ -+{ "vmsub2hfr", 0x3643703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hfr<.cc> 0,limm,u6 00110110110000110111uuuuuu1QQQQQ. */ -+{ "vmsub2hfr", 0x36C37020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hfr 0,limm,s12 00110110100000110111ssssssSSSSSS. */ -+{ "vmsub2hfr", 0x36837000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hfr a,limm,limm 00110110000000110111111110AAAAAA. */ -+{ "vmsub2hfr", 0x36037F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hfr 0,limm,limm 00110110000000110111111110111110. */ -+{ "vmsub2hfr", 0x36037FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hfr<.cc> 0,limm,limm 001101101100001101111111100QQQQQ. */ -+{ "vmsub2hfr", 0x36C37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmsub2hnfr a,b,c 00110bbb000100011BBBCCCCCCAAAAAA. */ -+{ "vmsub2hnfr", 0x30118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hnfr 0,b,c 00110bbb000100011BBBCCCCCC111110. */ -+{ "vmsub2hnfr", 0x3011803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> b,b,c 00110bbb110100011BBBCCCCCC0QQQQQ. */ -+{ "vmsub2hnfr", 0x30D18000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hnfr a,b,u6 00110bbb010100011BBBuuuuuuAAAAAA. */ -+{ "vmsub2hnfr", 0x30518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hnfr 0,b,u6 00110bbb010100011BBBuuuuuu111110. */ -+{ "vmsub2hnfr", 0x3051803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> b,b,u6 00110bbb110100011BBBuuuuuu1QQQQQ. */ -+{ "vmsub2hnfr", 0x30D18020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hnfr b,b,s12 00110bbb100100011BBBssssssSSSSSS. */ -+{ "vmsub2hnfr", 0x30918000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hnfr a,limm,c 00110110000100011111CCCCCCAAAAAA. */ -+{ "vmsub2hnfr", 0x3611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hnfr a,b,limm 00110bbb000100011BBB111110AAAAAA. */ -+{ "vmsub2hnfr", 0x30118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hnfr 0,limm,c 00110110000100011111CCCCCC111110. */ -+{ "vmsub2hnfr", 0x3611F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hnfr 0,b,limm 00110bbb000100011BBB111110111110. */ -+{ "vmsub2hnfr", 0x30118FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> b,b,limm 00110bbb110100011BBB1111100QQQQQ. */ -+{ "vmsub2hnfr", 0x30D18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmsub2hnfr<.cc> 0,limm,c 00110110110100011111CCCCCC0QQQQQ. */ -+{ "vmsub2hnfr", 0x36D1F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hnfr a,limm,u6 00110110010100011111uuuuuuAAAAAA. */ -+{ "vmsub2hnfr", 0x3651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hnfr 0,limm,u6 00110110010100011111uuuuuu111110. */ -+{ "vmsub2hnfr", 0x3651F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> 0,limm,u6 00110110110100011111uuuuuu1QQQQQ. */ -+{ "vmsub2hnfr", 0x36D1F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hnfr 0,limm,s12 00110110100100011111ssssssSSSSSS. */ -+{ "vmsub2hnfr", 0x3691F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hnfr a,limm,limm 00110110000100011111111110AAAAAA. */ -+{ "vmsub2hnfr", 0x3611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hnfr 0,limm,limm 00110110000100011111111110111110. */ -+{ "vmsub2hnfr", 0x3611FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> 0,limm,limm 001101101101000111111111100QQQQQ. */ -+{ "vmsub2hnfr", 0x36D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vneg2h b,c 00101bbb001011110BBBCCCCCC101010. */ -+{ "vneg2h", 0x282F002A, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vneg2h 0,c 00101110001011110111CCCCCC101010. */ -+{ "vneg2h", 0x2E2F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vneg2h b,u6 00101bbb011011110BBBuuuuuu101010. */ -+{ "vneg2h", 0x286F002A, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vneg2h 0,u6 00101110011011110111uuuuuu101010. */ -+{ "vneg2h", 0x2E6F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vneg2h b,limm 00101bbb001011110BBB111110101010. */ -+{ "vneg2h", 0x282F0FAA, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vneg2h 0,limm 00101110001011110111111110101010. */ -+{ "vneg2h", 0x2E2F7FAA, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vnegs2h b,c 00101bbb001011110BBBCCCCCC101011. */ -+{ "vnegs2h", 0x282F002B, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vnegs2h 0,c 00101110001011110111CCCCCC101011. */ -+{ "vnegs2h", 0x2E2F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vnegs2h b,u6 00101bbb011011110BBBuuuuuu101011. */ -+{ "vnegs2h", 0x286F002B, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vnegs2h 0,u6 00101110011011110111uuuuuu101011. */ -+{ "vnegs2h", 0x2E6F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vnegs2h b,limm 00101bbb001011110BBB111110101011. */ -+{ "vnegs2h", 0x282F0FAB, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vnegs2h 0,limm 00101110001011110111111110101011. */ -+{ "vnegs2h", 0x2E2F7FAB, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vnorm2h b,c 00101bbb001011110BBBCCCCCC101100. */ -+{ "vnorm2h", 0x282F002C, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vnorm2h 0,c 00101110001011110111CCCCCC101100. */ -+{ "vnorm2h", 0x2E2F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vnorm2h b,u6 00101bbb011011110BBBuuuuuu101100. */ -+{ "vnorm2h", 0x286F002C, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vnorm2h 0,u6 00101110011011110111uuuuuu101100. */ -+{ "vnorm2h", 0x2E6F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vnorm2h b,limm 00101bbb001011110BBB111110101100. */ -+{ "vnorm2h", 0x282F0FAC, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vnorm2h 0,limm 00101110001011110111111110101100. */ -+{ "vnorm2h", 0x2E2F7FAC, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbl b,c 00101bbb001011110BBBCCCCCC011100. */ -+{ "vpack2hbl", 0x282F001C, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbl 0,c 00101110001011110111CCCCCC011100. */ -+{ "vpack2hbl", 0x2E2F701C, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbl b,u6 00101bbb011011110BBBuuuuuu011100. */ -+{ "vpack2hbl", 0x286F001C, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbl 0,u6 00101110011011110111uuuuuu011100. */ -+{ "vpack2hbl", 0x2E6F701C, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbl b,limm 00101bbb001011110BBB111110011100. */ -+{ "vpack2hbl", 0x282F0F9C, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbl 0,limm 00101110001011110111111110011100. */ -+{ "vpack2hbl", 0x2E2F7F9C, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hblf b,c 00101bbb001011110BBBCCCCCC011110. */ -+{ "vpack2hblf", 0x282F001E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hblf 0,c 00101110001011110111CCCCCC011110. */ -+{ "vpack2hblf", 0x2E2F701E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hblf b,u6 00101bbb011011110BBBuuuuuu011110. */ -+{ "vpack2hblf", 0x286F001E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hblf 0,u6 00101110011011110111uuuuuu011110. */ -+{ "vpack2hblf", 0x2E6F701E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hblf b,limm 00101bbb001011110BBB111110011110. */ -+{ "vpack2hblf", 0x282F0F9E, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hblf 0,limm 00101110001011110111111110011110. */ -+{ "vpack2hblf", 0x2E2F7F9E, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbm b,c 00101bbb001011110BBBCCCCCC011101. */ -+{ "vpack2hbm", 0x282F001D, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbm 0,c 00101110001011110111CCCCCC011101. */ -+{ "vpack2hbm", 0x2E2F701D, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbm b,u6 00101bbb011011110BBBuuuuuu011101. */ -+{ "vpack2hbm", 0x286F001D, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbm 0,u6 00101110011011110111uuuuuu011101. */ -+{ "vpack2hbm", 0x2E6F701D, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbm b,limm 00101bbb001011110BBB111110011101. */ -+{ "vpack2hbm", 0x282F0F9D, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbm 0,limm 00101110001011110111111110011101. */ -+{ "vpack2hbm", 0x2E2F7F9D, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbmf b,c 00101bbb001011110BBBCCCCCC011111. */ -+{ "vpack2hbmf", 0x282F001F, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbmf 0,c 00101110001011110111CCCCCC011111. */ -+{ "vpack2hbmf", 0x2E2F701F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbmf b,u6 00101bbb011011110BBBuuuuuu011111. */ -+{ "vpack2hbmf", 0x286F001F, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbmf 0,u6 00101110011011110111uuuuuu011111. */ -+{ "vpack2hbmf", 0x2E6F701F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbmf b,limm 00101bbb001011110BBB111110011111. */ -+{ "vpack2hbmf", 0x282F0F9F, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbmf 0,limm 00101110001011110111111110011111. */ -+{ "vpack2hbmf", 0x2E2F7F9F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hl a,b,c 00101bbb001010010BBBCCCCCCAAAAAA. */ -+{ "vpack2hl", 0x28290000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hl 0,b,c 00101bbb001010010BBBCCCCCC111110. */ -+{ "vpack2hl", 0x2829003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hl<.cc> b,b,c 00101bbb111010010BBBCCCCCC0QQQQQ. */ -+{ "vpack2hl", 0x28E90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vpack2hl a,b,u6 00101bbb011010010BBBuuuuuuAAAAAA. */ -+{ "vpack2hl", 0x28690000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hl 0,b,u6 00101bbb011010010BBBuuuuuu111110. */ -+{ "vpack2hl", 0x2869003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hl<.cc> b,b,u6 00101bbb111010010BBBuuuuuu1QQQQQ. */ -+{ "vpack2hl", 0x28E90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vpack2hl b,b,s12 00101bbb101010010BBBssssssSSSSSS. */ -+{ "vpack2hl", 0x28A90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vpack2hl a,limm,c 00101110001010010111CCCCCCAAAAAA. */ -+{ "vpack2hl", 0x2E297000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hl a,b,limm 00101bbb001010010BBB111110AAAAAA. */ -+{ "vpack2hl", 0x28290F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hl 0,limm,c 00101110011010010111CCCCCC111110. */ -+{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hl 0,b,limm 00101bbb001010010BBB111110111110. */ -+{ "vpack2hl", 0x28290FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hl<.cc> b,b,limm 00101bbb111010010BBB1111100QQQQQ. */ -+{ "vpack2hl", 0x28E90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vpack2hl<.cc> 0,limm,c 00101110111010010111CCCCCC0QQQQQ. */ -+{ "vpack2hl", 0x2EE97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vpack2hl a,limm,u6 00101110011010010111uuuuuuAAAAAA. */ -+{ "vpack2hl", 0x2E697000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hl 0,limm,u6 00101110011010010111uuuuuu111110. */ -+{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hl<.cc> 0,limm,u6 00101110111010010111uuuuuu1QQQQQ. */ -+{ "vpack2hl", 0x2EE97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vpack2hl 0,limm,s12 00101110101010010111ssssssSSSSSS. */ -+{ "vpack2hl", 0x2EA97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vpack2hl a,limm,limm 00101110001010010111111110AAAAAA. */ -+{ "vpack2hl", 0x2E297F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vpack2hl 0,limm,limm 00101110001010010111111110111110. */ -+{ "vpack2hl", 0x2E297FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vpack2hl<.cc> 0,limm,limm 001011101110100101111111100QQQQQ. */ -+{ "vpack2hl", 0x2EE97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vpack2hm a,b,c 00101bbb001010011BBBCCCCCCAAAAAA. */ -+{ "vpack2hm", 0x28298000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hm 0,b,c 00101bbb001010011BBBCCCCCC111110. */ -+{ "vpack2hm", 0x2829803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hm<.cc> b,b,c 00101bbb111010011BBBCCCCCC0QQQQQ. */ -+{ "vpack2hm", 0x28E98000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vpack2hm a,b,u6 00101bbb011010011BBBuuuuuuAAAAAA. */ -+{ "vpack2hm", 0x28698000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hm 0,b,u6 00101bbb011010011BBBuuuuuu111110. */ -+{ "vpack2hm", 0x2869803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hm<.cc> b,b,u6 00101bbb111010011BBBuuuuuu1QQQQQ. */ -+{ "vpack2hm", 0x28E98020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vpack2hm b,b,s12 00101bbb101010011BBBssssssSSSSSS. */ -+{ "vpack2hm", 0x28A98000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vpack2hm a,limm,c 00101110001010011111CCCCCCAAAAAA. */ -+{ "vpack2hm", 0x2E29F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hm a,b,limm 00101bbb001010011BBB111110AAAAAA. */ -+{ "vpack2hm", 0x28298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hm 0,limm,c 00101110011010011111CCCCCC111110. */ -+{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hm 0,b,limm 00101bbb001010011BBB111110111110. */ -+{ "vpack2hm", 0x28298FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hm<.cc> b,b,limm 00101bbb111010011BBB1111100QQQQQ. */ -+{ "vpack2hm", 0x28E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vpack2hm<.cc> 0,limm,c 00101110111010011111CCCCCC0QQQQQ. */ -+{ "vpack2hm", 0x2EE9F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vpack2hm a,limm,u6 00101110011010011111uuuuuuAAAAAA. */ -+{ "vpack2hm", 0x2E69F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hm 0,limm,u6 00101110011010011111uuuuuu111110. */ -+{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hm<.cc> 0,limm,u6 00101110111010011111uuuuuu1QQQQQ. */ -+{ "vpack2hm", 0x2EE9F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vpack2hm 0,limm,s12 00101110101010011111ssssssSSSSSS. */ -+{ "vpack2hm", 0x2EA9F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vpack2hm a,limm,limm 00101110001010011111111110AAAAAA. */ -+{ "vpack2hm", 0x2E29FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vpack2hm 0,limm,limm 00101110001010011111111110111110. */ -+{ "vpack2hm", 0x2E29FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vpack2hm<.cc> 0,limm,limm 001011101110100111111111100QQQQQ. */ -+{ "vpack2hm", 0x2EE9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vperm a,b,c 00101bbb001011100BBBCCCCCCAAAAAA. */ -+{ "vperm", 0x282E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vperm 0,b,c 00101bbb001011100BBBCCCCCC111110. */ -+{ "vperm", 0x282E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vperm<.cc> b,b,c 00101bbb111011100BBBCCCCCC0QQQQQ. */ -+{ "vperm", 0x28EE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vperm a,b,u6 00101bbb011011100BBBuuuuuuAAAAAA. */ -+{ "vperm", 0x286E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vperm 0,b,u6 00101bbb011011100BBBuuuuuu111110. */ -+{ "vperm", 0x286E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vperm<.cc> b,b,u6 00101bbb111011100BBBuuuuuu1QQQQQ. */ -+{ "vperm", 0x28EE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vperm b,b,s12 00101bbb101011100BBBssssssSSSSSS. */ -+{ "vperm", 0x28AE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vperm a,limm,c 00101110001011100111CCCCCCAAAAAA. */ -+{ "vperm", 0x2E2E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vperm a,b,limm 00101bbb001011100BBB111110AAAAAA. */ -+{ "vperm", 0x282E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vperm 0,limm,c 00101110011011100111CCCCCC111110. */ -+{ "vperm", 0x2E6E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vperm 0,b,limm 00101bbb001011100BBB111110111110. */ -+{ "vperm", 0x282E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vperm<.cc> b,b,limm 00101bbb111011100BBB1111100QQQQQ. */ -+{ "vperm", 0x28EE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vperm<.cc> 0,limm,c 00101110111011100111CCCCCC0QQQQQ. */ -+{ "vperm", 0x2EEE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vperm a,limm,u6 00101110011011100111uuuuuuAAAAAA. */ -+{ "vperm", 0x2E6E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vperm 0,limm,u6 00101110011011100111uuuuuu111110. */ -+{ "vperm", 0x2E6E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vperm<.cc> 0,limm,u6 00101110111011100111uuuuuu1QQQQQ. */ -+{ "vperm", 0x2EEE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vperm 0,limm,s12 00101110101011100111ssssssSSSSSS. */ -+{ "vperm", 0x2EAE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vperm a,limm,limm 00101110001011100111111110AAAAAA. */ -+{ "vperm", 0x2E2E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vperm 0,limm,limm 00101110001011100111111110111110. */ -+{ "vperm", 0x2E2E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vperm<.cc> 0,limm,limm 001011101110111001111111100QQQQQ. */ -+{ "vperm", 0x2EEE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vrep2hl b,c 00101bbb001011110BBBCCCCCC100010. */ -+{ "vrep2hl", 0x282F0022, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vrep2hl 0,c 00101110001011110111CCCCCC100010. */ -+{ "vrep2hl", 0x2E2F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vrep2hl b,u6 00101bbb011011110BBBuuuuuu100010. */ -+{ "vrep2hl", 0x286F0022, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vrep2hl 0,u6 00101110011011110111uuuuuu100010. */ -+{ "vrep2hl", 0x2E6F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vrep2hl b,limm 00101bbb001011110BBB111110100010. */ -+{ "vrep2hl", 0x282F0FA2, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vrep2hl 0,limm 00101110001011110111111110100010. */ -+{ "vrep2hl", 0x2E2F7FA2, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vrep2hm b,c 00101bbb001011110BBBCCCCCC100011. */ -+{ "vrep2hm", 0x282F0023, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vrep2hm 0,c 00101110001011110111CCCCCC100011. */ -+{ "vrep2hm", 0x2E2F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vrep2hm b,u6 00101bbb011011110BBBuuuuuu100011. */ -+{ "vrep2hm", 0x286F0023, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vrep2hm 0,u6 00101110011011110111uuuuuu100011. */ -+{ "vrep2hm", 0x2E6F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vrep2hm b,limm 00101bbb001011110BBB111110100011. */ -+{ "vrep2hm", 0x282F0FA3, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vrep2hm 0,limm 00101110001011110111111110100011. */ -+{ "vrep2hm", 0x2E2F7FA3, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vsext2bhl b,c 00101bbb001011110BBBCCCCCC100110. */ -+{ "vsext2bhl", 0x282F0026, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vsext2bhl 0,c 00101110001011110111CCCCCC100110. */ -+{ "vsext2bhl", 0x2E2F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vsext2bhl b,u6 00101bbb011011110BBBuuuuuu100110. */ -+{ "vsext2bhl", 0x286F0026, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsext2bhl 0,u6 00101110011011110111uuuuuu100110. */ -+{ "vsext2bhl", 0x2E6F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsext2bhl b,limm 00101bbb001011110BBB111110100110. */ -+{ "vsext2bhl", 0x282F0FA6, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vsext2bhl 0,limm 00101110001011110111111110100110. */ -+{ "vsext2bhl", 0x2E2F7FA6, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vsext2bhm b,c 00101bbb001011110BBBCCCCCC100111. */ -+{ "vsext2bhm", 0x282F0027, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vsext2bhm 0,c 00101110001011110111CCCCCC100111. */ -+{ "vsext2bhm", 0x2E2F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vsext2bhm b,u6 00101bbb011011110BBBuuuuuu100111. */ -+{ "vsext2bhm", 0x286F0027, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsext2bhm 0,u6 00101110011011110111uuuuuu100111. */ -+{ "vsext2bhm", 0x2E6F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsext2bhm b,limm 00101bbb001011110BBB111110100111. */ -+{ "vsext2bhm", 0x282F0FA7, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vsext2bhm 0,limm 00101110001011110111111110100111. */ -+{ "vsext2bhm", 0x2E2F7FA7, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA. */ -+{ "vsub2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub2 0,b,c 00101bbb001111010BBBCCCCCC111110. */ -+{ "vsub2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ. */ -+{ "vsub2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsub2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA. */ -+{ "vsub2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2 0,b,u6 00101bbb011111010BBBuuuuuu111110. */ -+{ "vsub2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ. */ -+{ "vsub2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub2 b,b,s12 00101bbb101111010BBBssssssSSSSSS. */ -+{ "vsub2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub2 a,limm,c 00101110001111010111CCCCCCAAAAAA. */ -+{ "vsub2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub2 a,b,limm 00101bbb001111010BBB111110AAAAAA. */ -+{ "vsub2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2 0,limm,c 00101110001111010111CCCCCC111110. */ -+{ "vsub2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub2 0,b,limm 00101bbb001111010BBB111110111110. */ -+{ "vsub2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ. */ -+{ "vsub2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsub2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ. */ -+{ "vsub2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsub2 a,limm,u6 00101110011111010111uuuuuuAAAAAA. */ -+{ "vsub2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2 0,limm,u6 00101110011111010111uuuuuu111110. */ -+{ "vsub2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ. */ -+{ "vsub2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub2 0,limm,s12 00101110101111010111ssssssSSSSSS. */ -+{ "vsub2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub2 a,limm,limm 00101110001111010111111110AAAAAA. */ -+{ "vsub2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub2 0,limm,limm 00101110001111010111111110111110. */ -+{ "vsub2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ. */ -+{ "vsub2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsub2h a,b,c 00101bbb000101010BBBCCCCCCAAAAAA. */ -+{ "vsub2h", 0x28150000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub2h 0,b,c 00101bbb000101010BBBCCCCCC111110. */ -+{ "vsub2h", 0x2815003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub2h<.cc> b,b,c 00101bbb110101010BBBCCCCCC0QQQQQ. */ -+{ "vsub2h", 0x28D50000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsub2h a,b,u6 00101bbb010101010BBBuuuuuuAAAAAA. */ -+{ "vsub2h", 0x28550000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2h 0,b,u6 00101bbb010101010BBBuuuuuu111110. */ -+{ "vsub2h", 0x2855003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2h<.cc> b,b,u6 00101bbb110101010BBBuuuuuu1QQQQQ. */ -+{ "vsub2h", 0x28D50020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub2h b,b,s12 00101bbb100101010BBBssssssSSSSSS. */ -+{ "vsub2h", 0x28950000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub2h a,limm,c 00101110000101010111CCCCCCAAAAAA. */ -+{ "vsub2h", 0x2E157000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub2h a,b,limm 00101bbb000101010BBB111110AAAAAA. */ -+{ "vsub2h", 0x28150F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2h 0,limm,c 00101110000101010111CCCCCC111110. */ -+{ "vsub2h", 0x2E15703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub2h 0,b,limm 00101bbb000101010BBB111110111110. */ -+{ "vsub2h", 0x28150FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2h<.cc> b,b,limm 00101bbb110101010BBB1111100QQQQQ. */ -+{ "vsub2h", 0x28D50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsub2h<.cc> 0,limm,c 00101110110101010111CCCCCC0QQQQQ. */ -+{ "vsub2h", 0x2ED57000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsub2h a,limm,u6 00101110010101010111uuuuuuAAAAAA. */ -+{ "vsub2h", 0x2E557000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2h 0,limm,u6 00101110010101010111uuuuuu111110. */ -+{ "vsub2h", 0x2E55703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2h<.cc> 0,limm,u6 00101110110101010111uuuuuu1QQQQQ. */ -+{ "vsub2h", 0x2ED57020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub2h 0,limm,s12 00101110100101010111ssssssSSSSSS. */ -+{ "vsub2h", 0x2E957000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub2h a,limm,limm 00101110000101010111111110AAAAAA. */ -+{ "vsub2h", 0x2E157F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub2h 0,limm,limm 00101110000101010111111110111110. */ -+{ "vsub2h", 0x2E157FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub2h<.cc> 0,limm,limm 001011101101010101111111100QQQQQ. */ -+{ "vsub2h", 0x2ED57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsub4b a,b,c 00101bbb001001010BBBCCCCCCAAAAAA. */ -+{ "vsub4b", 0x28250000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub4b 0,b,c 00101bbb001001010BBBCCCCCC111110. */ -+{ "vsub4b", 0x2825003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub4b<.cc> b,b,c 00101bbb111001010BBBCCCCCC0QQQQQ. */ -+{ "vsub4b", 0x28E50000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsub4b a,b,u6 00101bbb011001010BBBuuuuuuAAAAAA. */ -+{ "vsub4b", 0x28650000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4b 0,b,u6 00101bbb011001010BBBuuuuuu111110. */ -+{ "vsub4b", 0x2865003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4b<.cc> b,b,u6 00101bbb111001010BBBuuuuuu1QQQQQ. */ -+{ "vsub4b", 0x28E50020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub4b b,b,s12 00101bbb101001010BBBssssssSSSSSS. */ -+{ "vsub4b", 0x28A50000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub4b a,limm,c 00101110001001010111CCCCCCAAAAAA. */ -+{ "vsub4b", 0x2E257000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub4b a,b,limm 00101bbb001001010BBB111110AAAAAA. */ -+{ "vsub4b", 0x28250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub4b 0,limm,c 00101110011001010111CCCCCC111110. */ -+{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub4b 0,b,limm 00101bbb001001010BBB111110111110. */ -+{ "vsub4b", 0x28250FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub4b<.cc> b,b,limm 00101bbb111001010BBB1111100QQQQQ. */ -+{ "vsub4b", 0x28E50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsub4b<.cc> 0,limm,c 00101110111001010111CCCCCC0QQQQQ. */ -+{ "vsub4b", 0x2EE57000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsub4b a,limm,u6 00101110011001010111uuuuuuAAAAAA. */ -+{ "vsub4b", 0x2E657000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4b 0,limm,u6 00101110011001010111uuuuuu111110. */ -+{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4b<.cc> 0,limm,u6 00101110111001010111uuuuuu1QQQQQ. */ -+{ "vsub4b", 0x2EE57020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub4b 0,limm,s12 00101110101001010111ssssssSSSSSS. */ -+{ "vsub4b", 0x2EA57000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub4b a,limm,limm 00101110001001010111111110AAAAAA. */ -+{ "vsub4b", 0x2E257F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub4b 0,limm,limm 00101110001001010111111110111110. */ -+{ "vsub4b", 0x2E257FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub4b<.cc> 0,limm,limm 001011101110010101111111100QQQQQ. */ -+{ "vsub4b", 0x2EE57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsub4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA. */ -+{ "vsub4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub4h 0,b,c 00101bbb001110010BBBCCCCCC111110. */ -+{ "vsub4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ. */ -+{ "vsub4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsub4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA. */ -+{ "vsub4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4h 0,b,u6 00101bbb011110010BBBuuuuuu111110. */ -+{ "vsub4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ. */ -+{ "vsub4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub4h b,b,s12 00101bbb101110010BBBssssssSSSSSS. */ -+{ "vsub4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub4h a,limm,c 00101110001110010111CCCCCCAAAAAA. */ -+{ "vsub4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub4h a,b,limm 00101bbb001110010BBB111110AAAAAA. */ -+{ "vsub4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub4h 0,limm,c 00101110001110010111CCCCCC111110. */ -+{ "vsub4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub4h 0,b,limm 00101bbb001110010BBB111110111110. */ -+{ "vsub4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ. */ -+{ "vsub4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsub4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ. */ -+{ "vsub4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsub4h a,limm,u6 00101110011110010111uuuuuuAAAAAA. */ -+{ "vsub4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4h 0,limm,u6 00101110011110010111uuuuuu111110. */ -+{ "vsub4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ. */ -+{ "vsub4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub4h 0,limm,s12 00101110101110010111ssssssSSSSSS. */ -+{ "vsub4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub4h a,limm,limm 00101110001110010111111110AAAAAA. */ -+{ "vsub4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub4h 0,limm,limm 00101110001110010111111110111110. */ -+{ "vsub4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ. */ -+{ "vsub4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadd a,b,c 00101bbb001111110BBBCCCCCCAAAAAA. */ -+{ "vsubadd", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd 0,b,c 00101bbb001111110BBBCCCCCC111110. */ -+{ "vsubadd", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ. */ -+{ "vsubadd", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA. */ -+{ "vsubadd", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd 0,b,u6 00101bbb011111110BBBuuuuuu111110. */ -+{ "vsubadd", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ. */ -+{ "vsubadd", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd b,b,s12 00101bbb101111110BBBssssssSSSSSS. */ -+{ "vsubadd", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd a,limm,c 00101110001111110111CCCCCCAAAAAA. */ -+{ "vsubadd", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd a,b,limm 00101bbb001111110BBB111110AAAAAA. */ -+{ "vsubadd", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd 0,limm,c 00101110001111110111CCCCCC111110. */ -+{ "vsubadd", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd 0,b,limm 00101bbb001111110BBB111110111110. */ -+{ "vsubadd", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ. */ -+{ "vsubadd", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadd<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ. */ -+{ "vsubadd", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd a,limm,u6 00101110011111110111uuuuuuAAAAAA. */ -+{ "vsubadd", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd 0,limm,u6 00101110011111110111uuuuuu111110. */ -+{ "vsubadd", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ. */ -+{ "vsubadd", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd 0,limm,s12 00101110101111110111ssssssSSSSSS. */ -+{ "vsubadd", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd a,limm,limm 00101110001111110111111110AAAAAA. */ -+{ "vsubadd", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd 0,limm,limm 00101110001111110111111110111110. */ -+{ "vsubadd", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd<.cc> 0,limm,limm 001011101111111101111111100QQQQQ. */ -+{ "vsubadd", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadd2h a,b,c 00101bbb000101110BBBCCCCCCAAAAAA. */ -+{ "vsubadd2h", 0x28170000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd2h 0,b,c 00101bbb000101110BBBCCCCCC111110. */ -+{ "vsubadd2h", 0x2817003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd2h<.cc> b,b,c 00101bbb110101110BBBCCCCCC0QQQQQ. */ -+{ "vsubadd2h", 0x28D70000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd2h a,b,u6 00101bbb010101110BBBuuuuuuAAAAAA. */ -+{ "vsubadd2h", 0x28570000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd2h 0,b,u6 00101bbb010101110BBBuuuuuu111110. */ -+{ "vsubadd2h", 0x2857003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd2h<.cc> b,b,u6 00101bbb110101110BBBuuuuuu1QQQQQ. */ -+{ "vsubadd2h", 0x28D70020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd2h b,b,s12 00101bbb100101110BBBssssssSSSSSS. */ -+{ "vsubadd2h", 0x28970000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd2h a,limm,c 00101110000101110111CCCCCCAAAAAA. */ -+{ "vsubadd2h", 0x2E177000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd2h a,b,limm 00101bbb000101110BBB111110AAAAAA. */ -+{ "vsubadd2h", 0x28170F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd2h 0,limm,c 00101110000101110111CCCCCC111110. */ -+{ "vsubadd2h", 0x2E17703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd2h 0,b,limm 00101bbb000101110BBB111110111110. */ -+{ "vsubadd2h", 0x28170FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd2h<.cc> b,b,limm 00101bbb110101110BBB1111100QQQQQ. */ -+{ "vsubadd2h", 0x28D70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadd2h<.cc> 0,limm,c 00101110110101110111CCCCCC0QQQQQ. */ -+{ "vsubadd2h", 0x2ED77000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd2h a,limm,u6 00101110010101110111uuuuuuAAAAAA. */ -+{ "vsubadd2h", 0x2E577000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd2h 0,limm,u6 00101110010101110111uuuuuu111110. */ -+{ "vsubadd2h", 0x2E57703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd2h<.cc> 0,limm,u6 00101110110101110111uuuuuu1QQQQQ. */ -+{ "vsubadd2h", 0x2ED77020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd2h 0,limm,s12 00101110100101110111ssssssSSSSSS. */ -+{ "vsubadd2h", 0x2E977000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd2h a,limm,limm 00101110000101110111111110AAAAAA. */ -+{ "vsubadd2h", 0x2E177F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd2h 0,limm,limm 00101110000101110111111110111110. */ -+{ "vsubadd2h", 0x2E177FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd2h<.cc> 0,limm,limm 001011101101011101111111100QQQQQ. */ -+{ "vsubadd2h", 0x2ED77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadd4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA. */ -+{ "vsubadd4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd4h 0,b,c 00101bbb001110110BBBCCCCCC111110. */ -+{ "vsubadd4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ. */ -+{ "vsubadd4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA. */ -+{ "vsubadd4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd4h 0,b,u6 00101bbb011110110BBBuuuuuu111110. */ -+{ "vsubadd4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ. */ -+{ "vsubadd4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd4h b,b,s12 00101bbb101110110BBBssssssSSSSSS. */ -+{ "vsubadd4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd4h a,limm,c 00101110001110110111CCCCCCAAAAAA. */ -+{ "vsubadd4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd4h a,b,limm 00101bbb001110110BBB111110AAAAAA. */ -+{ "vsubadd4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd4h 0,limm,c 00101110001110110111CCCCCC111110. */ -+{ "vsubadd4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd4h 0,b,limm 00101bbb001110110BBB111110111110. */ -+{ "vsubadd4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ. */ -+{ "vsubadd4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadd4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ. */ -+{ "vsubadd4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd4h a,limm,u6 00101110011110110111uuuuuuAAAAAA. */ -+{ "vsubadd4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd4h 0,limm,u6 00101110011110110111uuuuuu111110. */ -+{ "vsubadd4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ. */ -+{ "vsubadd4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd4h 0,limm,s12 00101110101110110111ssssssSSSSSS. */ -+{ "vsubadd4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd4h a,limm,limm 00101110001110110111111110AAAAAA. */ -+{ "vsubadd4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd4h 0,limm,limm 00101110001110110111111110111110. */ -+{ "vsubadd4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ. */ -+{ "vsubadd4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadds a,b,c 00101bbb001111110BBBCCCCCCAAAAAA. */ -+{ "vsubadds", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds 0,b,c 00101bbb001111110BBBCCCCCC111110. */ -+{ "vsubadds", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ. */ -+{ "vsubadds", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA. */ -+{ "vsubadds", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds 0,b,u6 00101bbb011111110BBBuuuuuu111110. */ -+{ "vsubadds", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ. */ -+{ "vsubadds", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds b,b,s12 00101bbb101111110BBBssssssSSSSSS. */ -+{ "vsubadds", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds a,limm,c 00101110001111110111CCCCCCAAAAAA. */ -+{ "vsubadds", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds a,b,limm 00101bbb001111110BBB111110AAAAAA. */ -+{ "vsubadds", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds 0,limm,c 00101110001111110111CCCCCC111110. */ -+{ "vsubadds", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds 0,b,limm 00101bbb001111110BBB111110111110. */ -+{ "vsubadds", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ. */ -+{ "vsubadds", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadds<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ. */ -+{ "vsubadds", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds a,limm,u6 00101110011111110111uuuuuuAAAAAA. */ -+{ "vsubadds", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds 0,limm,u6 00101110011111110111uuuuuu111110. */ -+{ "vsubadds", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ. */ -+{ "vsubadds", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds 0,limm,s12 00101110101111110111ssssssSSSSSS. */ -+{ "vsubadds", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds a,limm,limm 00101110001111110111111110AAAAAA. */ -+{ "vsubadds", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds 0,limm,limm 00101110001111110111111110111110. */ -+{ "vsubadds", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds<.cc> 0,limm,limm 001011101111111101111111100QQQQQ. */ -+{ "vsubadds", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadds2h a,b,c 00101bbb000101111BBBCCCCCCAAAAAA. */ -+{ "vsubadds2h", 0x28178000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds2h 0,b,c 00101bbb000101111BBBCCCCCC111110. */ -+{ "vsubadds2h", 0x2817803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds2h<.cc> b,b,c 00101bbb110101111BBBCCCCCC0QQQQQ. */ -+{ "vsubadds2h", 0x28D78000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds2h a,b,u6 00101bbb010101111BBBuuuuuuAAAAAA. */ -+{ "vsubadds2h", 0x28578000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds2h 0,b,u6 00101bbb010101111BBBuuuuuu111110. */ -+{ "vsubadds2h", 0x2857803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds2h<.cc> b,b,u6 00101bbb110101111BBBuuuuuu1QQQQQ. */ -+{ "vsubadds2h", 0x28D78020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds2h b,b,s12 00101bbb100101111BBBssssssSSSSSS. */ -+{ "vsubadds2h", 0x28978000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds2h a,limm,c 00101110000101111111CCCCCCAAAAAA. */ -+{ "vsubadds2h", 0x2E17F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds2h a,b,limm 00101bbb000101111BBB111110AAAAAA. */ -+{ "vsubadds2h", 0x28178F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds2h 0,limm,c 00101110000101111111CCCCCC111110. */ -+{ "vsubadds2h", 0x2E17F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds2h 0,b,limm 00101bbb000101111BBB111110111110. */ -+{ "vsubadds2h", 0x28178FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds2h<.cc> b,b,limm 00101bbb110101111BBB1111100QQQQQ. */ -+{ "vsubadds2h", 0x28D78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadds2h<.cc> 0,limm,c 00101110110101111111CCCCCC0QQQQQ. */ -+{ "vsubadds2h", 0x2ED7F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds2h a,limm,u6 00101110010101111111uuuuuuAAAAAA. */ -+{ "vsubadds2h", 0x2E57F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds2h 0,limm,u6 00101110010101111111uuuuuu111110. */ -+{ "vsubadds2h", 0x2E57F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds2h<.cc> 0,limm,u6 00101110110101111111uuuuuu1QQQQQ. */ -+{ "vsubadds2h", 0x2ED7F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds2h 0,limm,s12 00101110100101111111ssssssSSSSSS. */ -+{ "vsubadds2h", 0x2E97F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds2h a,limm,limm 00101110000101111111111110AAAAAA. */ -+{ "vsubadds2h", 0x2E17FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds2h 0,limm,limm 00101110000101111111111110111110. */ -+{ "vsubadds2h", 0x2E17FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds2h<.cc> 0,limm,limm 001011101101011111111111100QQQQQ. */ -+{ "vsubadds2h", 0x2ED7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadds4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA. */ -+{ "vsubadds4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds4h 0,b,c 00101bbb001110110BBBCCCCCC111110. */ -+{ "vsubadds4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ. */ -+{ "vsubadds4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA. */ -+{ "vsubadds4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds4h 0,b,u6 00101bbb011110110BBBuuuuuu111110. */ -+{ "vsubadds4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ. */ -+{ "vsubadds4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds4h b,b,s12 00101bbb101110110BBBssssssSSSSSS. */ -+{ "vsubadds4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds4h a,limm,c 00101110001110110111CCCCCCAAAAAA. */ -+{ "vsubadds4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds4h a,b,limm 00101bbb001110110BBB111110AAAAAA. */ -+{ "vsubadds4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds4h 0,limm,c 00101110001110110111CCCCCC111110. */ -+{ "vsubadds4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds4h 0,b,limm 00101bbb001110110BBB111110111110. */ -+{ "vsubadds4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ. */ -+{ "vsubadds4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadds4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ. */ -+{ "vsubadds4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds4h a,limm,u6 00101110011110110111uuuuuuAAAAAA. */ -+{ "vsubadds4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds4h 0,limm,u6 00101110011110110111uuuuuu111110. */ -+{ "vsubadds4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ. */ -+{ "vsubadds4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds4h 0,limm,s12 00101110101110110111ssssssSSSSSS. */ -+{ "vsubadds4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds4h a,limm,limm 00101110001110110111111110AAAAAA. */ -+{ "vsubadds4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds4h 0,limm,limm 00101110001110110111111110111110. */ -+{ "vsubadds4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ. */ -+{ "vsubadds4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubs2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA. */ -+{ "vsubs2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2 0,b,c 00101bbb001111010BBBCCCCCC111110. */ -+{ "vsubs2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ. */ -+{ "vsubs2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA. */ -+{ "vsubs2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2 0,b,u6 00101bbb011111010BBBuuuuuu111110. */ -+{ "vsubs2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ. */ -+{ "vsubs2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs2 b,b,s12 00101bbb101111010BBBssssssSSSSSS. */ -+{ "vsubs2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs2 a,limm,c 00101110001111010111CCCCCCAAAAAA. */ -+{ "vsubs2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2 a,b,limm 00101bbb001111010BBB111110AAAAAA. */ -+{ "vsubs2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs2 0,limm,c 00101110001111010111CCCCCC111110. */ -+{ "vsubs2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2 0,b,limm 00101bbb001111010BBB111110111110. */ -+{ "vsubs2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ. */ -+{ "vsubs2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubs2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ. */ -+{ "vsubs2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs2 a,limm,u6 00101110011111010111uuuuuuAAAAAA. */ -+{ "vsubs2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2 0,limm,u6 00101110011111010111uuuuuu111110. */ -+{ "vsubs2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ. */ -+{ "vsubs2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs2 0,limm,s12 00101110101111010111ssssssSSSSSS. */ -+{ "vsubs2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs2 a,limm,limm 00101110001111010111111110AAAAAA. */ -+{ "vsubs2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs2 0,limm,limm 00101110001111010111111110111110. */ -+{ "vsubs2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ. */ -+{ "vsubs2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubs2h a,b,c 00101bbb000101011BBBCCCCCCAAAAAA. */ -+{ "vsubs2h", 0x28158000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2h 0,b,c 00101bbb000101011BBBCCCCCC111110. */ -+{ "vsubs2h", 0x2815803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2h<.cc> b,b,c 00101bbb110101011BBBCCCCCC0QQQQQ. */ -+{ "vsubs2h", 0x28D58000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs2h a,b,u6 00101bbb010101011BBBuuuuuuAAAAAA. */ -+{ "vsubs2h", 0x28558000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2h 0,b,u6 00101bbb010101011BBBuuuuuu111110. */ -+{ "vsubs2h", 0x2855803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2h<.cc> b,b,u6 00101bbb110101011BBBuuuuuu1QQQQQ. */ -+{ "vsubs2h", 0x28D58020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs2h b,b,s12 00101bbb100101011BBBssssssSSSSSS. */ -+{ "vsubs2h", 0x28958000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs2h a,limm,c 00101110000101011111CCCCCCAAAAAA. */ -+{ "vsubs2h", 0x2E15F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2h a,b,limm 00101bbb000101011BBB111110AAAAAA. */ -+{ "vsubs2h", 0x28158F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs2h 0,limm,c 00101110000101011111CCCCCC111110. */ -+{ "vsubs2h", 0x2E15F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2h 0,b,limm 00101bbb000101011BBB111110111110. */ -+{ "vsubs2h", 0x28158FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs2h<.cc> b,b,limm 00101bbb110101011BBB1111100QQQQQ. */ -+{ "vsubs2h", 0x28D58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubs2h<.cc> 0,limm,c 00101110110101011111CCCCCC0QQQQQ. */ -+{ "vsubs2h", 0x2ED5F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs2h a,limm,u6 00101110010101011111uuuuuuAAAAAA. */ -+{ "vsubs2h", 0x2E55F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2h 0,limm,u6 00101110010101011111uuuuuu111110. */ -+{ "vsubs2h", 0x2E55F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2h<.cc> 0,limm,u6 00101110110101011111uuuuuu1QQQQQ. */ -+{ "vsubs2h", 0x2ED5F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs2h 0,limm,s12 00101110100101011111ssssssSSSSSS. */ -+{ "vsubs2h", 0x2E95F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs2h a,limm,limm 00101110000101011111111110AAAAAA. */ -+{ "vsubs2h", 0x2E15FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs2h 0,limm,limm 00101110000101011111111110111110. */ -+{ "vsubs2h", 0x2E15FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs2h<.cc> 0,limm,limm 001011101101010111111111100QQQQQ. */ -+{ "vsubs2h", 0x2ED5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubs4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA. */ -+{ "vsubs4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs4h 0,b,c 00101bbb001110010BBBCCCCCC111110. */ -+{ "vsubs4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ. */ -+{ "vsubs4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA. */ -+{ "vsubs4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs4h 0,b,u6 00101bbb011110010BBBuuuuuu111110. */ -+{ "vsubs4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ. */ -+{ "vsubs4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs4h b,b,s12 00101bbb101110010BBBssssssSSSSSS. */ -+{ "vsubs4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs4h a,limm,c 00101110001110010111CCCCCCAAAAAA. */ -+{ "vsubs4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs4h a,b,limm 00101bbb001110010BBB111110AAAAAA. */ -+{ "vsubs4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs4h 0,limm,c 00101110001110010111CCCCCC111110. */ -+{ "vsubs4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs4h 0,b,limm 00101bbb001110010BBB111110111110. */ -+{ "vsubs4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ. */ -+{ "vsubs4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubs4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ. */ -+{ "vsubs4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs4h a,limm,u6 00101110011110010111uuuuuuAAAAAA. */ -+{ "vsubs4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs4h 0,limm,u6 00101110011110010111uuuuuu111110. */ -+{ "vsubs4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ. */ -+{ "vsubs4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs4h 0,limm,s12 00101110101110010111ssssssSSSSSS. */ -+{ "vsubs4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs4h a,limm,limm 00101110001110010111111110AAAAAA. */ -+{ "vsubs4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs4h 0,limm,limm 00101110001110010111111110111110. */ -+{ "vsubs4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ. */ -+{ "vsubs4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* wevt c 00100000001011110001CCCCCC111111. */ -+{ "wevt", 0x202F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* wevt 00100000011011110001000000111111. */ -+{ "wevt", 0x206F103F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* wevt u6 00100000011011110001uuuuuu111111. */ -+{ "wevt", 0x206F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* wlfc c 00100001001011110001CCCCCC111111. */ -+{ "wlfc", 0x212F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* wlfc u6 00100001011011110001uuuuuu111111. */ -+{ "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA. */ -+{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xbfu<.f> 0,b,c 00100bbb00101101FBBBCCCCCC111110. */ -+{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xbfu<.f><.cc> b,b,c 00100bbb11101101FBBBCCCCCC0QQQQQ. */ -+{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xbfu<.f> a,b,u6 00100bbb01101101FBBBuuuuuuAAAAAA. */ -+{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbfu<.f> 0,b,u6 00100bbb01101101FBBBuuuuuu111110. */ -+{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbfu<.f><.cc> b,b,u6 00100bbb11101101FBBBuuuuuu1QQQQQ. */ -+{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xbfu<.f> b,b,s12 00100bbb10101101FBBBssssssSSSSSS. */ -+{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xbfu<.f> a,limm,c 0010011000101101F111CCCCCCAAAAAA. */ -+{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xbfu<.f> a,b,limm 00100bbb00101101FBBB111110AAAAAA. */ -+{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xbfu<.f> 0,limm,c 0010011000101101F111CCCCCC111110. */ -+{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xbfu<.f> 0,b,limm 00100bbb00101101FBBB111110111110. */ -+{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xbfu<.f><.cc> b,b,limm 00100bbb11101101FBBB1111100QQQQQ. */ -+{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* xbfu<.f><.cc> 0,limm,c 0010011011101101F111CCCCCC0QQQQQ. */ -+{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xbfu<.f> a,limm,u6 0010011001101101F111uuuuuuAAAAAA. */ -+{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbfu<.f> 0,limm,u6 0010011001101101F111uuuuuu111110. */ -+{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbfu<.f><.cc> 0,limm,u6 0010011011101101F111uuuuuu1QQQQQ. */ -+{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xbfu<.f> 0,limm,s12 0010011010101101F111ssssssSSSSSS. */ -+{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xbfu<.f> a,limm,limm 0010011000101101F111111110AAAAAA. */ -+{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xbfu<.f> 0,limm,limm 0010011000101101F111111110111110. */ -+{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xbfu<.f><.cc> 0,limm,limm 0010011011101101F1111111100QQQQQ. */ -+{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* xbful<.f> OPERAND_RA,RB,RC 01011bbb00101101FBBBccccccaaaaaa. */ -+{ "xbful", 0x582D0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xbful<.f> 0,RB,RC 01011bbb00101101FBBBcccccc111110. */ -+{ "xbful", 0x582D003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xbful<.f><.cc> OPERAND_RB,RB,RC 01011bbb11101101FBBBcccccc0QQQQQ. */ -+{ "xbful", 0x58ED0000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xbful<.f> OPERAND_RA,RB,u6 01011bbb01101101FBBBuuuuuuaaaaaa. */ -+{ "xbful", 0x586D0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbful<.f> 0,RB,u6 01011bbb01101101FBBBuuuuuu111110. */ -+{ "xbful", 0x586D003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbful<.f><.cc> OPERAND_RB,RB,u6 01011bbb11101101FBBBuuuuuu1QQQQQ. */ -+{ "xbful", 0x58ED0020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xbful<.f> OPERAND_RB,RB,s12 01011bbb10101101FBBBssssssSSSSSS. */ -+{ "xbful", 0x58AD0000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xbful<.f> OPERAND_RA,ximm,RC 0101110000101101F111ccccccaaaaaa. */ -+{ "xbful", 0x5C2D7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* xbful<.f> OPERAND_RA,RB,ximm 01011bbb00101101FBBB111100aaaaaa. */ -+{ "xbful", 0x582D0F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* xbful<.f> 0,ximm,RC 0101110000101101F111cccccc111110. */ -+{ "xbful", 0x5C2D703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* xbful<.f> 0,RB,ximm 01011bbb00101101FBBB111100111110. */ -+{ "xbful", 0x582D0F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* xbful<.f><.cc> 0,ximm,RC 0101110011101101F111cccccc0QQQQQ. */ -+{ "xbful", 0x5CED7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xbful<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11101101FBBB1111000QQQQQ. */ -+{ "xbful", 0x58ED0F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* xbful<.f> OPERAND_RA,ximm,u6 0101110001101101F111uuuuuuaaaaaa. */ -+{ "xbful", 0x5C6D7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbful<.f> 0,ximm,u6 0101110001101101F111uuuuuu111110. */ -+{ "xbful", 0x5C6D703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbful<.f><.cc> 0,ximm,u6 0101110011101101F111uuuuuu1QQQQQ. */ -+{ "xbful", 0x5CED7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xbful<.f> OPERAND_RA,limm,RC 0101111000101101F111ccccccaaaaaa. */ -+{ "xbful", 0x5E2D7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xbful<.f> OPERAND_RA,RB,limm 01011bbb00101101FBBB111110aaaaaa. */ -+{ "xbful", 0x582D0F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xbful<.f> 0,limm,RC 0101111000101101F111cccccc111110. */ -+{ "xbful", 0x5E2D703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xbful<.f> 0,RB,limm 01011bbb00101101FBBB111110111110. */ -+{ "xbful", 0x582D0FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xbful<.f><.cc> 0,limm,RC 0101111011101101F111cccccc0QQQQQ. */ -+{ "xbful", 0x5EED7000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xbful<.f><.cc> OPERAND_RB,RB,limm 01011bbb11101101FBBB1111100QQQQQ. */ -+{ "xbful", 0x58ED0F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* xbful<.f> OPERAND_RA,limm,u6 0101111001101101F111uuuuuuaaaaaa. */ -+{ "xbful", 0x5E6D7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbful<.f> 0,limm,u6 0101111001101101F111uuuuuu111110. */ -+{ "xbful", 0x5E6D703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbful<.f><.cc> 0,limm,u6 0101111011101101F111uuuuuu1QQQQQ. */ -+{ "xbful", 0x5EED7020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xbful<.f> 0,ximm,s12 0101110010101101F111ssssssSSSSSS. */ -+{ "xbful", 0x5CAD7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xbful<.f> 0,limm,s12 0101111010101101F111ssssssSSSSSS. */ -+{ "xbful", 0x5EAD7000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xbful<.f> OPERAND_RA,ximm,ximm 0101110000101101F111111100aaaaaa. */ -+{ "xbful", 0x5C2D7F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* xbful<.f> 0,ximm,ximm 0101110000101101F111111100111110. */ -+{ "xbful", 0x5C2D7F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* xbful<.f><.cc> 0,ximm,ximm 0101110011101101F1111111000QQQQQ. */ -+{ "xbful", 0x5CED7F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* xbful<.f> OPERAND_RA,limm,limm 0101111000101101F111111110aaaaaa. */ -+{ "xbful", 0x5E2D7F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xbful<.f> 0,limm,limm 0101111000101101F111111110111110. */ -+{ "xbful", 0x5E2D7FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xbful<.f><.cc> 0,limm,limm 0101111011101101F1111111100QQQQQ. */ -+{ "xbful", 0x5EED7F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA. */ -+{ "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xor<.f> 0,b,c 00100bbb00000111FBBBCCCCCC111110. */ -+{ "xor", 0x2007003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xor<.f><.cc> b,b,c 00100bbb11000111FBBBCCCCCC0QQQQQ. */ -+{ "xor", 0x20C70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xor<.f> a,b,u6 00100bbb01000111FBBBuuuuuuAAAAAA. */ -+{ "xor", 0x20470000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xor<.f> 0,b,u6 00100bbb01000111FBBBuuuuuu111110. */ -+{ "xor", 0x2047003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xor<.f><.cc> b,b,u6 00100bbb11000111FBBBuuuuuu1QQQQQ. */ -+{ "xor", 0x20C70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xor<.f> b,b,s12 00100bbb10000111FBBBssssssSSSSSS. */ -+{ "xor", 0x20870000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xor<.f> a,limm,c 0010011000000111F111CCCCCCAAAAAA. */ -+{ "xor", 0x26077000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xor<.f> a,b,limm 00100bbb00000111FBBB111110AAAAAA. */ -+{ "xor", 0x20070F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xor<.f> 0,limm,c 0010011000000111F111CCCCCC111110. */ -+{ "xor", 0x2607703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xor<.f> 0,b,limm 00100bbb00000111FBBB111110111110. */ -+{ "xor", 0x20070FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xor<.f><.cc> 0,limm,c 0010011011000111F111CCCCCC0QQQQQ. */ -+{ "xor", 0x26C77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xor<.f><.cc> b,b,limm 00100bbb11000111FBBB1111100QQQQQ. */ -+{ "xor", 0x20C70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* xor<.f> a,limm,u6 0010011001000111F111uuuuuuAAAAAA. */ -+{ "xor", 0x26477000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xor<.f> 0,limm,u6 0010011001000111F111uuuuuu111110. */ -+{ "xor", 0x2647703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xor<.f><.cc> 0,limm,u6 0010011011000111F111uuuuuu1QQQQQ. */ -+{ "xor", 0x26C77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xor<.f> 0,limm,s12 0010011010000111F111ssssssSSSSSS. */ -+{ "xor", 0x26877000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xor<.f> a,limm,limm 0010011000000111F111111110AAAAAA. */ -+{ "xor", 0x26077F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xor<.f> 0,limm,limm 0010011000000111F111111110111110. */ -+{ "xor", 0x26077FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xor<.f><.cc> 0,limm,limm 0010011011000111F1111111100QQQQQ. */ -+{ "xor", 0x26C77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* xorl<.f> OPERAND_RA,RB,RC 01011bbb00000111FBBBccccccaaaaaa. */ -+{ "xorl", 0x58070000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xorl<.f> 0,RB,RC 01011bbb00000111FBBBcccccc111110. */ -+{ "xorl", 0x5807003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xorl<.f><.cc> OPERAND_RB,RB,RC 01011bbb11000111FBBBcccccc0QQQQQ. */ -+{ "xorl", 0x58C70000, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xorl<.f> OPERAND_RA,RB,u6 01011bbb01000111FBBBuuuuuuaaaaaa. */ -+{ "xorl", 0x58470000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xorl<.f> 0,RB,u6 01011bbb01000111FBBBuuuuuu111110. */ -+{ "xorl", 0x5847003E, 0xF8FF003F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xorl<.f><.cc> OPERAND_RB,RB,u6 01011bbb11000111FBBBuuuuuu1QQQQQ. */ -+{ "xorl", 0x58C70020, 0xF8FF0020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xorl<.f> OPERAND_RB,RB,s12 01011bbb10000111FBBBssssssSSSSSS. */ -+{ "xorl", 0x58870000, 0xF8FF0000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xorl<.f> OPERAND_RA,ximm,RC 0101110000000111F111ccccccaaaaaa. */ -+{ "xorl", 0x5C077000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* xorl<.f> OPERAND_RA,RB,ximm 01011bbb00000111FBBB111100aaaaaa. */ -+{ "xorl", 0x58070F00, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* xorl<.f> 0,ximm,RC 0101110000000111F111cccccc111110. */ -+{ "xorl", 0x5C07703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F }}, -+ -+/* xorl<.f> 0,RB,ximm 01011bbb00000111FBBB111100111110. */ -+{ "xorl", 0x58070F3E, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_XIMM }, { C_F }}, -+ -+/* xorl<.f><.cc> 0,ximm,RC 0101110011000111F111cccccc0QQQQQ. */ -+{ "xorl", 0x5CC77000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xorl<.f><.cc> OPERAND_RB,RB,ximm 01011bbb11000111FBBB1111000QQQQQ. */ -+{ "xorl", 0x58C70F00, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_XIMM }, { C_F, C_CC }}, -+ -+/* xorl<.f> OPERAND_RA,ximm,u6 0101110001000111F111uuuuuuaaaaaa. */ -+{ "xorl", 0x5C477000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xorl<.f> 0,ximm,u6 0101110001000111F111uuuuuu111110. */ -+{ "xorl", 0x5C47703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xorl<.f><.cc> 0,ximm,u6 0101110011000111F111uuuuuu1QQQQQ. */ -+{ "xorl", 0x5CC77020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xorl<.f> OPERAND_RA,limm,RC 0101111000000111F111ccccccaaaaaa. */ -+{ "xorl", 0x5E077000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xorl<.f> OPERAND_RA,RB,limm 01011bbb00000111FBBB111110aaaaaa. */ -+{ "xorl", 0x58070F80, 0xF8FF0FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xorl<.f> 0,limm,RC 0101111000000111F111cccccc111110. */ -+{ "xorl", 0x5E07703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xorl<.f> 0,RB,limm 01011bbb00000111FBBB111110111110. */ -+{ "xorl", 0x58070FBE, 0xF8FF0FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xorl<.f><.cc> 0,limm,RC 0101111011000111F111cccccc0QQQQQ. */ -+{ "xorl", 0x5EC77000, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xorl<.f><.cc> OPERAND_RB,RB,limm 01011bbb11000111FBBB1111100QQQQQ. */ -+{ "xorl", 0x58C70F80, 0xF8FF0FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* xorl<.f> OPERAND_RA,limm,u6 0101111001000111F111uuuuuuaaaaaa. */ -+{ "xorl", 0x5E477000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xorl<.f> 0,limm,u6 0101111001000111F111uuuuuu111110. */ -+{ "xorl", 0x5E47703E, 0xFFFF703F, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xorl<.f><.cc> 0,limm,u6 0101111011000111F111uuuuuu1QQQQQ. */ -+{ "xorl", 0x5EC77020, 0xFFFF7020, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xorl<.f> 0,ximm,s12 0101110010000111F111ssssssSSSSSS. */ -+{ "xorl", 0x5C877000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xorl<.f> 0,limm,s12 0101111010000111F111ssssssSSSSSS. */ -+{ "xorl", 0x5E877000, 0xFFFF7000, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xorl<.f> OPERAND_RA,ximm,ximm 0101110000000111F111111100aaaaaa. */ -+{ "xorl", 0x5C077F00, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* xorl<.f> 0,ximm,ximm 0101110000000111F111111100111110. */ -+{ "xorl", 0x5C077F3E, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F }}, -+ -+/* xorl<.f><.cc> 0,ximm,ximm 0101110011000111F1111111000QQQQQ. */ -+{ "xorl", 0x5CC77F00, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_XIMM, OPERAND_XIMMdup }, { C_F, C_CC }}, -+ -+/* xorl<.f> OPERAND_RA,limm,limm 0101111000000111F111111110aaaaaa. */ -+{ "xorl", 0x5E077F80, 0xFFFF7FC0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xorl<.f> 0,limm,limm 0101111000000111F111111110111110. */ -+{ "xorl", 0x5E077FBE, 0xFFFF7FFF, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xorl<.f><.cc> 0,limm,limm 0101111011000111F1111111100QQQQQ. */ -+{ "xorl", 0x5EC77F80, 0xFFFF7FE0, ARC_OPCODE_V3_ARC64, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* xor_s b,b,c 01111bbbccc00111. */ -+{ "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_V3_ARC64, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -diff --git a/target/arc/opcodes.def b/target/arc/opcodes.def -new file mode 100644 -index 0000000000..ee831a4bb7 ---- /dev/null -+++ b/target/arc/opcodes.def -@@ -0,0 +1,19976 @@ -+/* -+ * ARC instruction defintions. -+ * Copyright (C) 2020 Free Software Foundation, Inc. -+ * -+ * Contributed by Claudiu Zissulescu (claziss@synopsys.com) -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the OPERAND_GNU OPERAND_General Public -+ * License as published by the Free Software Foundation; either -+ * version 3, or (at your option) any later version. -+ * -+ * It is distributed in the hope that it will be useful, but -+ * OPERAND_WITHOUT ANY OPERAND_WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -+ * See the OPERAND_GNU OPERAND_General Public License for more -+ * details. -+ * -+ * You should have received a copy of the OPERAND_GNU OPERAND_General -+ * Public License along with this program; if not, write to the Free -+ * Software Foundation, Inc., 51 Franklin Street - Fifth Floor, -+ * Boston, MA 02110-1301, USA. -+ */ -+ -+/* abs<.f> b,c 00100bbb00101111FBBBCCCCCC001001. */ -+{ "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* abs<.f> 0,c 0010011000101111F111CCCCCC001001. */ -+{ "abs", 0x262F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* abs<.f> b,u6 00100bbb01101111FBBBuuuuuu001001. */ -+{ "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abs<.f> 0,u6 0010011001101111F111uuuuuu001001. */ -+{ "abs", 0x266F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abs<.f> b,limm 00100bbb00101111FBBB111110001001. */ -+{ "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* abs<.f> 0,limm 0010011000101111F111111110001001. */ -+{ "abs", 0x262F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* abss<.f> b,c 00101bbb00101111FBBBCCCCCC000101. */ -+{ "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* abss<.f> 0,c 0010111000101111F111CCCCCC000101. */ -+{ "abss", 0x2E2F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* abss<.f> b,u6 00101bbb01101111FBBBuuuuuu000101. */ -+{ "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abss<.f> 0,u6 0010111001101111F111uuuuuu000101. */ -+{ "abss", 0x2E6F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abss<.f> b,limm 00101bbb00101111FBBB111110000101. */ -+{ "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* abss<.f> 0,limm 0010111000101111F111111110000101. */ -+{ "abss", 0x2E2F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* abssh<.f> b,c 00101bbb00101111FBBBCCCCCC000100. */ -+{ "abssh", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* abssh<.f> 0,c 0010111000101111F111CCCCCC000100. */ -+{ "abssh", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* abssh<.f> b,u6 00101bbb01101111FBBBuuuuuu000100. */ -+{ "abssh", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abssh<.f> 0,u6 0010111001101111F111uuuuuu000100. */ -+{ "abssh", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abssh<.f> b,limm 00101bbb00101111FBBB111110000100. */ -+{ "abssh", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* abssh<.f> 0,limm 0010111000101111F111111110000100. */ -+{ "abssh", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* abssw<.f> b,c 00101bbb00101111FBBBCCCCCC000100. */ -+{ "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* abssw<.f> 0,c 0010111000101111F111CCCCCC000100. */ -+{ "abssw", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* abssw<.f> b,u6 00101bbb01101111FBBBuuuuuu000100. */ -+{ "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abssw<.f> 0,u6 0010111001101111F111uuuuuu000100. */ -+{ "abssw", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* abssw<.f> b,limm 00101bbb00101111FBBB111110000100. */ -+{ "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* abssw<.f> 0,limm 0010111000101111F111111110000100. */ -+{ "abssw", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* abs_s b,c 01111bbbccc10001. */ -+{ "abs_s", 0x00007811, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* acm<.f> a,b,c 00110bbb00101000FBBBCCCCCCAAAAAA. */ -+{ "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* acm<.f><.cc> b,b,c 00110bbb11101000FBBBCCCCCC0QQQQQ. */ -+{ "acm", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* acm<.f> a,b,u6 00110bbb01101000FBBBuuuuuuAAAAAA. */ -+{ "acm", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* acm<.f><.cc> b,b,u6 00110bbb11101000FBBBuuuuuu1QQQQQ. */ -+{ "acm", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* acm<.f> b,b,s12 00110bbb10101000FBBBssssssSSSSSS. */ -+{ "acm", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* acm<.f> a,limm,c 0011011000101000F111CCCCCCAAAAAA. */ -+{ "acm", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* acm<.f> a,b,limm 00110bbb00101000FBBB111110AAAAAA. */ -+{ "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* acm<.f><.cc> b,b,limm 00110bbb11101000FBBB1111100QQQQQ. */ -+{ "acm", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* adc<.f> a,b,c 00100bbb00000001FBBBCCCCCCAAAAAA. */ -+{ "adc", 0x20010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adc<.f> 0,b,c 00100bbb00000001FBBBCCCCCC111110. */ -+{ "adc", 0x2001003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adc<.f><.cc> b,b,c 00100bbb11000001FBBBCCCCCC0QQQQQ. */ -+{ "adc", 0x20C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adc<.f> a,b,u6 00100bbb01000001FBBBuuuuuuAAAAAA. */ -+{ "adc", 0x20410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adc<.f> 0,b,u6 00100bbb01000001FBBBuuuuuu111110. */ -+{ "adc", 0x2041003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adc<.f><.cc> b,b,u6 00100bbb11000001FBBBuuuuuu1QQQQQ. */ -+{ "adc", 0x20C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adc<.f> b,b,s12 00100bbb10000001FBBBssssssSSSSSS. */ -+{ "adc", 0x20810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adc<.f> a,limm,c 0010011000000001F111CCCCCCAAAAAA. */ -+{ "adc", 0x26017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adc<.f> a,b,limm 00100bbb00000001FBBB111110AAAAAA. */ -+{ "adc", 0x20010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adc<.f> 0,limm,c 0010011000000001F111CCCCCC111110. */ -+{ "adc", 0x2601703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adc<.f> 0,b,limm 00100bbb00000001FBBB111110111110. */ -+{ "adc", 0x20010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adc<.f><.cc> b,b,limm 00100bbb11000001FBBB1111100QQQQQ. */ -+{ "adc", 0x20C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* adc<.f><.cc> 0,limm,c 0010011011000001F111CCCCCC0QQQQQ. */ -+{ "adc", 0x26C17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adc<.f> a,limm,u6 0010011001000001F111uuuuuuAAAAAA. */ -+{ "adc", 0x26417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adc<.f> 0,limm,u6 0010011001000001F111uuuuuu111110. */ -+{ "adc", 0x2641703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adc<.f><.cc> 0,limm,u6 0010011011000001F111uuuuuu1QQQQQ. */ -+{ "adc", 0x26C17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adc<.f> 0,limm,s12 0010011010000001F111ssssssSSSSSS. */ -+{ "adc", 0x26817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA. */ -+{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adc<.f> 0,limm,limm 0010011000000001F111111110111110. */ -+{ "adc", 0x26017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ. */ -+{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ */ -+{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA */ -+{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adcs<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ */ -+{ "adcs", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adcs<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA */ -+{ "adcs", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adcs<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110 */ -+{ "adcs", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adcs<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110 */ -+{ "adcs", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcs<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA */ -+{ "adcs", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcs<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ */ -+{ "adcs", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adcs<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS */ -+{ "adcs", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adcs<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ */ -+{ "adcs", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* adcs<.f><.cc> 0,limm,c 0010111011100110F111CCCCCC0QQQQQ */ -+{ "adcs", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adcs<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA */ -+{ "adcs", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adcs<.f> 0,limm,c 0010111001100110F111CCCCCC111110 */ -+{ "adcs", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adcs<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA */ -+{ "adcs", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adcs<.f> 0,b,limm 00101bbb00100110FBBB111110111110 */ -+{ "adcs", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adcs<.f><.cc> 0,limm,u6 0010111011100110F111uuuuuu1QQQQQ */ -+{ "adcs", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adcs<.f> 0,limm,u6 0010111001100110F111uuuuuu111110 */ -+{ "adcs", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcs<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA */ -+{ "adcs", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adcs<.f> 0,limm,s12 0010111010100110F111ssssssSSSSSS */ -+{ "adcs", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adcs<.f> 0,limm,limm 0010111000100110F111111110111110 */ -+{ "adcs", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adcs<.f><.cc> 0,limm,limm 0010111011100110F1111111100QQQQQ */ -+{ "adcs", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* adcs<.f> a,limm,limm 0010111000100110F111111110AAAAAA */ -+{ "adcs", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add<.f> a,b,c 00100bbb00000000FBBBCCCCCCAAAAAA. */ -+{ "add", 0x20000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add<.f> 0,b,c 00100bbb00000000FBBBCCCCCC111110. */ -+{ "add", 0x2000003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add<.f><.cc> b,b,c 00100bbb11000000FBBBCCCCCC0QQQQQ. */ -+{ "add", 0x20C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */ -+{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add<.f> 0,b,u6 00100bbb01000000FBBBuuuuuu111110. */ -+{ "add", 0x2040003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */ -+{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add<.f> b,b,s12 00100bbb10000000FBBBssssssSSSSSS. */ -+{ "add", 0x20800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add<.f> a,limm,c 0010011000000000F111CCCCCCAAAAAA. */ -+{ "add", 0x26007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ -+{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add<.f> 0,limm,c 0010011000000000F111CCCCCC111110. */ -+{ "add", 0x2600703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add<.f> 0,b,limm 00100bbb00000000FBBB111110111110. */ -+{ "add", 0x20000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ -+{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add<.f><.cc> 0,limm,c 0010011011000000F111CCCCCC0QQQQQ. */ -+{ "add", 0x26C07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add<.f> a,limm,u6 0010011001000000F111uuuuuuAAAAAA. */ -+{ "add", 0x26407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add<.f> 0,limm,u6 0010011001000000F111uuuuuu111110. */ -+{ "add", 0x2640703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add<.f><.cc> 0,limm,u6 0010011011000000F111uuuuuu1QQQQQ. */ -+{ "add", 0x26C07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add<.f> 0,limm,s12 0010011010000000F111ssssssSSSSSS. */ -+{ "add", 0x26807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add<.f> a,limm,limm 0010011000000000F111111110AAAAAA. */ -+{ "add", 0x26007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add<.f> 0,limm,limm 0010011000000000F111111110111110. */ -+{ "add", 0x26007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add<.f><.cc> 0,limm,limm 0010011011000000F1111111100QQQQQ. */ -+{ "add", 0x26C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add1<.f> a,b,c 00100bbb00010100FBBBCCCCCCAAAAAA. */ -+{ "add1", 0x20140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add1<.f> 0,b,c 00100bbb00010100FBBBCCCCCC111110. */ -+{ "add1", 0x2014003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add1<.f><.cc> b,b,c 00100bbb11010100FBBBCCCCCC0QQQQQ. */ -+{ "add1", 0x20D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add1<.f> a,b,u6 00100bbb01010100FBBBuuuuuuAAAAAA. */ -+{ "add1", 0x20540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1<.f> 0,b,u6 00100bbb01010100FBBBuuuuuu111110. */ -+{ "add1", 0x2054003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1<.f><.cc> b,b,u6 00100bbb11010100FBBBuuuuuu1QQQQQ. */ -+{ "add1", 0x20D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add1<.f> b,b,s12 00100bbb10010100FBBBssssssSSSSSS. */ -+{ "add1", 0x20940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add1<.f> a,limm,c 0010011000010100F111CCCCCCAAAAAA. */ -+{ "add1", 0x26147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add1<.f> a,b,limm 00100bbb00010100FBBB111110AAAAAA. */ -+{ "add1", 0x20140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add1<.f> 0,limm,c 0010011000010100F111CCCCCC111110. */ -+{ "add1", 0x2614703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add1<.f> 0,b,limm 00100bbb00010100FBBB111110111110. */ -+{ "add1", 0x20140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add1<.f><.cc> b,b,limm 00100bbb11010100FBBB1111100QQQQQ. */ -+{ "add1", 0x20D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add1<.f><.cc> 0,limm,c 0010011011010100F111CCCCCC0QQQQQ. */ -+{ "add1", 0x26D47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add1<.f> a,limm,u6 0010011001010100F111uuuuuuAAAAAA. */ -+{ "add1", 0x26547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1<.f> 0,limm,u6 0010011001010100F111uuuuuu111110. */ -+{ "add1", 0x2654703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add1<.f><.cc> 0,limm,u6 0010011011010100F111uuuuuu1QQQQQ. */ -+{ "add1", 0x26D47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add1<.f> 0,limm,s12 0010011010010100F111ssssssSSSSSS. */ -+{ "add1", 0x26947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add1<.f> a,limm,limm 0010011000010100F111111110AAAAAA. */ -+{ "add1", 0x26147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add1<.f> 0,limm,limm 0010011000010100F111111110111110. */ -+{ "add1", 0x26147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add1<.f><.cc> 0,limm,limm 0010011011010100F1111111100QQQQQ. */ -+{ "add1", 0x26D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add1_s b,b,c 01111bbbccc10100. */ -+{ "add1_s", 0x00007814, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* add2<.f> a,b,c 00100bbb00010101FBBBCCCCCCAAAAAA. */ -+{ "add2", 0x20150000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add2<.f> 0,b,c 00100bbb00010101FBBBCCCCCC111110. */ -+{ "add2", 0x2015003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add2<.f><.cc> b,b,c 00100bbb11010101FBBBCCCCCC0QQQQQ. */ -+{ "add2", 0x20D50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add2<.f> a,b,u6 00100bbb01010101FBBBuuuuuuAAAAAA. */ -+{ "add2", 0x20550000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2<.f> 0,b,u6 00100bbb01010101FBBBuuuuuu111110. */ -+{ "add2", 0x2055003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2<.f><.cc> b,b,u6 00100bbb11010101FBBBuuuuuu1QQQQQ. */ -+{ "add2", 0x20D50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add2<.f> b,b,s12 00100bbb10010101FBBBssssssSSSSSS. */ -+{ "add2", 0x20950000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add2<.f> a,limm,c 0010011000010101F111CCCCCCAAAAAA. */ -+{ "add2", 0x26157000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add2<.f> a,b,limm 00100bbb00010101FBBB111110AAAAAA. */ -+{ "add2", 0x20150F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add2<.f> 0,limm,c 0010011000010101F111CCCCCC111110. */ -+{ "add2", 0x2615703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add2<.f> 0,b,limm 00100bbb00010101FBBB111110111110. */ -+{ "add2", 0x20150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add2<.f><.cc> b,b,limm 00100bbb11010101FBBB1111100QQQQQ. */ -+{ "add2", 0x20D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add2<.f><.cc> 0,limm,c 0010011011010101F111CCCCCC0QQQQQ. */ -+{ "add2", 0x26D57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add2<.f> a,limm,u6 0010011001010101F111uuuuuuAAAAAA. */ -+{ "add2", 0x26557000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2<.f> 0,limm,u6 0010011001010101F111uuuuuu111110. */ -+{ "add2", 0x2655703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add2<.f><.cc> 0,limm,u6 0010011011010101F111uuuuuu1QQQQQ. */ -+{ "add2", 0x26D57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add2<.f> 0,limm,s12 0010011010010101F111ssssssSSSSSS. */ -+{ "add2", 0x26957000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add2<.f> a,limm,limm 0010011000010101F111111110AAAAAA. */ -+{ "add2", 0x26157F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add2<.f> 0,limm,limm 0010011000010101F111111110111110. */ -+{ "add2", 0x26157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add2<.f><.cc> 0,limm,limm 0010011011010101F1111111100QQQQQ. */ -+{ "add2", 0x26D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add2_s b,b,c 01111bbbccc10101. */ -+{ "add2_s", 0x00007815, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* add3<.f> a,b,c 00100bbb00010110FBBBCCCCCCAAAAAA. */ -+{ "add3", 0x20160000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add3<.f> 0,b,c 00100bbb00010110FBBBCCCCCC111110. */ -+{ "add3", 0x2016003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* add3<.f><.cc> b,b,c 00100bbb11010110FBBBCCCCCC0QQQQQ. */ -+{ "add3", 0x20D60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add3<.f> a,b,u6 00100bbb01010110FBBBuuuuuuAAAAAA. */ -+{ "add3", 0x20560000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3<.f> 0,b,u6 00100bbb01010110FBBBuuuuuu111110. */ -+{ "add3", 0x2056003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3<.f><.cc> b,b,u6 00100bbb11010110FBBBuuuuuu1QQQQQ. */ -+{ "add3", 0x20D60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add3<.f> b,b,s12 00100bbb10010110FBBBssssssSSSSSS. */ -+{ "add3", 0x20960000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add3<.f> a,limm,c 0010011000010110F111CCCCCCAAAAAA. */ -+{ "add3", 0x26167000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add3<.f> a,b,limm 00100bbb00010110FBBB111110AAAAAA. */ -+{ "add3", 0x20160F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add3<.f> 0,limm,c 0010011000010110F111CCCCCC111110. */ -+{ "add3", 0x2616703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* add3<.f> 0,b,limm 00100bbb00010110FBBB111110111110. */ -+{ "add3", 0x20160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* add3<.f><.cc> b,b,limm 00100bbb11010110FBBB1111100QQQQQ. */ -+{ "add3", 0x20D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* add3<.f><.cc> 0,limm,c 0010011011010110F111CCCCCC0QQQQQ. */ -+{ "add3", 0x26D67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* add3<.f> a,limm,u6 0010011001010110F111uuuuuuAAAAAA. */ -+{ "add3", 0x26567000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3<.f> 0,limm,u6 0010011001010110F111uuuuuu111110. */ -+{ "add3", 0x2656703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* add3<.f><.cc> 0,limm,u6 0010011011010110F111uuuuuu1QQQQQ. */ -+{ "add3", 0x26D67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* add3<.f> 0,limm,s12 0010011010010110F111ssssssSSSSSS. */ -+{ "add3", 0x26967000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* add3<.f> a,limm,limm 0010011000010110F111111110AAAAAA. */ -+{ "add3", 0x26167F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add3<.f> 0,limm,limm 0010011000010110F111111110111110. */ -+{ "add3", 0x26167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* add3<.f><.cc> 0,limm,limm 0010011011010110F1111111100QQQQQ. */ -+{ "add3", 0x26D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add3_s b,b,c 01111bbbccc10110. */ -+{ "add3_s", 0x00007816, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* addqbs<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA. */ -+{ "addqbs", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* addqbs<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ. */ -+{ "addqbs", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* addqbs<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA. */ -+{ "addqbs", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addqbs<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ. */ -+{ "addqbs", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* addqbs<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS. */ -+{ "addqbs", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* addqbs<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA. */ -+{ "addqbs", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* addqbs<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA. */ -+{ "addqbs", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* addqbs<.f><.cc> b,b,limm 00110bbb11100100FBBB1111100QQQQQ. */ -+{ "addqbs", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* adds<.f> a,b,c 00101bbb00000110FBBBCCCCCCAAAAAA. */ -+{ "adds", 0x28060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adds<.f> 0,b,c 00101bbb00000110FBBBCCCCCC111110. */ -+{ "adds", 0x2806003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* adds<.f><.cc> b,b,c 00101bbb11000110FBBBCCCCCC0QQQQQ. */ -+{ "adds", 0x28C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adds<.f> a,b,u6 00101bbb01000110FBBBuuuuuuAAAAAA. */ -+{ "adds", 0x28460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adds<.f> 0,b,u6 00101bbb01000110FBBBuuuuuu111110. */ -+{ "adds", 0x2846003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adds<.f><.cc> b,b,u6 00101bbb11000110FBBBuuuuuu1QQQQQ. */ -+{ "adds", 0x28C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adds<.f> b,b,s12 00101bbb10000110FBBBssssssSSSSSS. */ -+{ "adds", 0x28860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adds<.f> a,limm,c 0010111000000110F111CCCCCCAAAAAA. */ -+{ "adds", 0x2E067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adds<.f> a,b,limm 00101bbb00000110FBBB111110AAAAAA. */ -+{ "adds", 0x28060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adds<.f> 0,limm,c 0010111000000110F111CCCCCC111110. */ -+{ "adds", 0x2E06703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* adds<.f> 0,b,limm 00101bbb00000110FBBB111110111110. */ -+{ "adds", 0x28060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* adds<.f><.cc> b,b,limm 00101bbb11000110FBBB1111100QQQQQ. */ -+{ "adds", 0x28C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* adds<.f><.cc> 0,limm,c 0010111011000110F111CCCCCC0QQQQQ. */ -+{ "adds", 0x2EC67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* adds<.f> a,limm,u6 0010111001000110F111uuuuuuAAAAAA. */ -+{ "adds", 0x2E467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adds<.f> 0,limm,u6 0010111001000110F111uuuuuu111110. */ -+{ "adds", 0x2E46703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* adds<.f><.cc> 0,limm,u6 0010111011000110F111uuuuuu1QQQQQ. */ -+{ "adds", 0x2EC67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* adds<.f> 0,limm,s12 0010111010000110F111ssssssSSSSSS. */ -+{ "adds", 0x2E867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* adds<.f> a,limm,limm 0010111000000110F111111110AAAAAA. */ -+{ "adds", 0x2E067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adds<.f> 0,limm,limm 0010111000000110F111111110111110. */ -+{ "adds", 0x2E067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* adds<.f><.cc> 0,limm,limm 0010111011000110F1111111100QQQQQ. */ -+{ "adds", 0x2EC67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* addsdw<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA. */ -+{ "addsdw", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* addsdw<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110. */ -+{ "addsdw", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* addsdw<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ. */ -+{ "addsdw", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* addsdw<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA. */ -+{ "addsdw", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addsdw<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110. */ -+{ "addsdw", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addsdw<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ. */ -+{ "addsdw", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* addsdw<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS. */ -+{ "addsdw", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* addsdw<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA. */ -+{ "addsdw", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* addsdw<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA. */ -+{ "addsdw", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* addsdw<.f> 0,limm,c 0010111000101000F111CCCCCC111110. */ -+{ "addsdw", 0x2E28703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* addsdw<.f> 0,b,limm 00101bbb00101000FBBB111110111110. */ -+{ "addsdw", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* addsdw<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ. */ -+{ "addsdw", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* addsdw<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ. */ -+{ "addsdw", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* addsdw<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA. */ -+{ "addsdw", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addsdw<.f> 0,limm,u6 0010111001101000F111uuuuuu111110. */ -+{ "addsdw", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* addsdw<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ. */ -+{ "addsdw", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* addsdw<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS. */ -+{ "addsdw", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* addsdw<.f> a,limm,limm 0010111000101000F111111110AAAAAA. */ -+{ "addsdw", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* addsdw<.f> 0,limm,limm 0010111000101000F111111110111110. */ -+{ "addsdw", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* addsdw<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ. */ -+{ "addsdw", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* add_s a,b,c 01100bbbccc11aaa. */ -+{ "add_s", 0x00006018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* add_s b,b,h 01110bbbhhh00HHH. */ -+{ "add_s", 0x00007000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_R6H }, { 0 }}, -+ -+/* add_s b,b,h 01110bbbhhh000HH. */ -+{ "add_s", 0x00007000, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RH_S }, { 0 }}, -+ -+/* add_s h,h,s3 01110ssshhh001HH. */ -+{ "add_s", 0x00007004, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RH_S, OPERAND_RH_Sdup, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* add_s c,b,u3 01101bbbccc00uuu. */ -+{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, -+ -+/* add_s OPERAND_R0,b,u6 01001bbb0UUU1uuu. */ -+{ "add_s", 0x00004808, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { OPERAND_R0_S, OPERAND_RB_S, OPERAND_UIMM6_13_S }, { 0 }}, -+ -+/* add_s OPERAND_R1,b,u6 01001bbb1UUU1uuu. */ -+{ "add_s", 0x00004888, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { OPERAND_R1_S, OPERAND_RB_S, OPERAND_UIMM6_13_S }, { 0 }}, -+ -+/* add_s b,sp,u7 11000bbb100uuuuu. */ -+{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S }, { 0 }}, -+ -+/* add_s b,b,u7 11100bbb0uuuuuuu. */ -+{ "add_s", 0x0000E000, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM7_9_S }, { 0 }}, -+ -+/* add_s SP,SP,u7 11000000101uuuuu. */ -+{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM7_A32_11_S }, { 0 }}, -+ -+/* add_s OPERAND_R0,GP,s11 1100111sssssssss. */ -+{ "add_s", 0x0000CE00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_R0_S, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S }, { 0 }}, -+ -+/* add_s b,b,limm 01110bbb11000111. */ -+{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_LIMM_S }, { 0 }}, -+ -+/* add_s b,b,limm 01110bbb11000011. */ -+{ "add_s", 0x000070C3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_LIMM_S }, { 0 }}, -+ -+/* add_s 0,limm,s3 01110sss11000111. */ -+{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA_S, OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR. */ -+{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> b,c 00100bbb11100111RBBBCCCCCC0QQQQQ. */ -+{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex b,u6 00100bbb01100111RBBBuuuuuuRRRRRR. */ -+{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> b,u6 00100bbb11100111RBBBuuuuuu1QQQQQ. */ -+{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex b,s12 00100bbb10100111RBBBssssssSSSSSS. */ -+{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex limm,c 0010011000100111R111CCCCCCRRRRRR. */ -+{ "aex", 0x26277000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex b,limm 00100bbb00100111RBBB111110RRRRRR. */ -+{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> limm,c 0010011011100111R111CCCCCC0QQQQQ. */ -+{ "aex", 0x26E77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex<.cc> b,limm 00100bbb11100111RBBB1111100QQQQQ. */ -+{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex limm,u6 0010011001100111R111uuuuuuRRRRRR. */ -+{ "aex", 0x26677000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> limm,u6 0010011011100111R111uuuuuu1QQQQQ. */ -+{ "aex", 0x26E77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* aex limm,s12 0010011010100111R111ssssssSSSSSS. */ -+{ "aex", 0x26A77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex limm,limm 0010011000100111R111111110RRRRRR. */ -+{ "aex", 0x26277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* aex<.cc> limm,limm 0010011011100111R1111111100QQQQQ. */ -+{ "aex", 0x26E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* and<.f> a,b,c 00100bbb00000100FBBBCCCCCCAAAAAA. */ -+{ "and", 0x20040000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* and<.f> 0,b,c 00100bbb00000100FBBBCCCCCC111110. */ -+{ "and", 0x2004003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* and<.f><.cc> b,b,c 00100bbb11000100FBBBCCCCCC0QQQQQ. */ -+{ "and", 0x20C40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* and<.f> a,b,u6 00100bbb01000100FBBBuuuuuuAAAAAA. */ -+{ "and", 0x20440000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* and<.f> 0,b,u6 00100bbb01000100FBBBuuuuuu111110. */ -+{ "and", 0x2044003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* and<.f><.cc> b,b,u6 00100bbb11000100FBBBuuuuuu1QQQQQ. */ -+{ "and", 0x20C40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* and<.f> b,b,s12 00100bbb10000100FBBBssssssSSSSSS. */ -+{ "and", 0x20840000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* and<.f> a,limm,c 0010011000000100F111CCCCCCAAAAAA. */ -+{ "and", 0x26047000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* and<.f> a,b,limm 00100bbb00000100FBBB111110AAAAAA. */ -+{ "and", 0x20040F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* and<.f> 0,limm,c 0010011000000100F111CCCCCC111110. */ -+{ "and", 0x2604703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* and<.f> 0,b,limm 00100bbb00000100FBBB111110111110. */ -+{ "and", 0x20040FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* and<.f><.cc> b,b,limm 00100bbb11000100FBBB1111100QQQQQ. */ -+{ "and", 0x20C40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* and<.f><.cc> 0,limm,c 0010011011000100F111CCCCCC0QQQQQ. */ -+{ "and", 0x26C47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* and<.f> a,limm,u6 0010011001000100F111uuuuuuAAAAAA. */ -+{ "and", 0x26447000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* and<.f> 0,limm,u6 0010011001000100F111uuuuuu111110. */ -+{ "and", 0x2644703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* and<.f><.cc> 0,limm,u6 0010011011000100F111uuuuuu1QQQQQ. */ -+{ "and", 0x26C47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* and<.f> 0,limm,s12 0010011010000100F111ssssssSSSSSS. */ -+{ "and", 0x26847000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* and<.f> a,limm,limm 0010011000000100F111111110AAAAAA. */ -+{ "and", 0x26047F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* and<.f> 0,limm,limm 0010011000000100F111111110111110. */ -+{ "and", 0x26047FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* and<.f><.cc> 0,limm,limm 0010011011000100F1111111100QQQQQ. */ -+{ "and", 0x26C47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* and_s b,b,c 01111bbbccc00100. */ -+{ "and_s", 0x00007804, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* asl<.f> b,c 00100bbb00101111FBBBCCCCCC000000. */ -+{ "asl", 0x202F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> 0,c 0010011000101111F111CCCCCC000000. */ -+{ "asl", 0x262F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> a,b,c 00101bbb00000000FBBBCCCCCCAAAAAA. */ -+{ "asl", 0x28000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> 0,b,c 00101bbb00000000FBBBCCCCCC111110. */ -+{ "asl", 0x2800003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f><.cc> b,b,c 00101bbb11000000FBBBCCCCCC0QQQQQ. */ -+{ "asl", 0x28C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asl<.f> b,u6 00100bbb01101111FBBBuuuuuu000000. */ -+{ "asl", 0x206F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f> 0,u6 0010011001101111F111uuuuuu000000. */ -+{ "asl", 0x266F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f> a,b,u6 00101bbb01000000FBBBuuuuuuAAAAAA. */ -+{ "asl", 0x28400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f> 0,b,u6 00101bbb01000000FBBBuuuuuu111110. */ -+{ "asl", 0x2840003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f><.cc> b,b,u6 00101bbb11000000FBBBuuuuuu1QQQQQ. */ -+{ "asl", 0x28C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asl<.f> b,b,s12 00101bbb10000000FBBBssssssSSSSSS. */ -+{ "asl", 0x28800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asl<.f> b,limm 00100bbb00101111FBBB111110000000. */ -+{ "asl", 0x202F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asl<.f> 0,limm 0010011000101111F111111110000000. */ -+{ "asl", 0x262F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asl<.f> a,limm,c 0010111000000000F111CCCCCCAAAAAA. */ -+{ "asl", 0x2E007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> a,b,limm 00101bbb00000000FBBB111110AAAAAA. */ -+{ "asl", 0x28000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asl<.f> 0,limm,c 0010111000000000F111CCCCCC111110. */ -+{ "asl", 0x2E00703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asl<.f> 0,b,limm 00101bbb00000000FBBB111110111110. */ -+{ "asl", 0x28000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asl<.f><.cc> b,b,limm 00101bbb11000000FBBB1111100QQQQQ. */ -+{ "asl", 0x28C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asl<.f><.cc> 0,limm,c 0010111011000000F111CCCCCC0QQQQQ. */ -+{ "asl", 0x2EC07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asl<.f> a,limm,u6 0010111001000000F111uuuuuuAAAAAA. */ -+{ "asl", 0x2E407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f> 0,limm,u6 0010111001000000F111uuuuuu111110. */ -+{ "asl", 0x2E40703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asl<.f><.cc> 0,limm,u6 0010111011000000F111uuuuuu1QQQQQ. */ -+{ "asl", 0x2EC07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asl<.f> 0,limm,s12 0010111010000000F111ssssssSSSSSS. */ -+{ "asl", 0x2E807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asl<.f> a,limm,limm 0010111000000000F111111110AAAAAA. */ -+{ "asl", 0x2E007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asl<.f> 0,limm,limm 0010111000000000F111111110111110. */ -+{ "asl", 0x2E007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asl<.f><.cc> 0,limm,limm 0010111011000000F1111111100QQQQQ. */ -+{ "asl", 0x2EC07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* aslacc c 00101000001011110000CCCCCC111111. */ -+{ "aslacc", 0x282F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* aslacc u6 00101000011011110000uuuuuu111111. */ -+{ "aslacc", 0x286F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* asldw<.f> a,b,c 00101bbb00100001FBBBCCCCCCAAAAAA. */ -+{ "asldw", 0x28210000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asldw<.f> 0,b,c 00101bbb00100001FBBBCCCCCC111110. */ -+{ "asldw", 0x2821003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asldw<.f><.cc> b,b,c 00101bbb11100001FBBBCCCCCC0QQQQQ. */ -+{ "asldw", 0x28E10000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asldw<.f> a,b,u6 00101bbb01100001FBBBuuuuuuAAAAAA. */ -+{ "asldw", 0x28610000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asldw<.f> 0,b,u6 00101bbb01100001FBBBuuuuuu111110. */ -+{ "asldw", 0x2861003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asldw<.f><.cc> b,b,u6 00101bbb11100001FBBBuuuuuu1QQQQQ. */ -+{ "asldw", 0x28E10020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asldw<.f> b,b,s12 00101bbb10100001FBBBssssssSSSSSS. */ -+{ "asldw", 0x28A10000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asldw<.f> a,limm,c 0010111000100001F111CCCCCCAAAAAA. */ -+{ "asldw", 0x2E217000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asldw<.f> a,b,limm 00101bbb00100001FBBB111110AAAAAA. */ -+{ "asldw", 0x28210F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asldw<.f> 0,limm,c 0010111000100001F111CCCCCC111110. */ -+{ "asldw", 0x2E21703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asldw<.f> 0,b,limm 00101bbb00100001FBBB111110111110. */ -+{ "asldw", 0x28210FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asldw<.f><.cc> 0,limm,c 0010111011100001F111CCCCCC0QQQQQ. */ -+{ "asldw", 0x2EE17000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asldw<.f><.cc> b,b,limm 00101bbb11100001FBBB1111100QQQQQ. */ -+{ "asldw", 0x28E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asldw<.f> a,limm,u6 0010111001100001F111uuuuuuAAAAAA. */ -+{ "asldw", 0x2E617000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asldw<.f> 0,limm,u6 0010111001100001F111uuuuuu111110. */ -+{ "asldw", 0x2E61703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asldw<.f><.cc> 0,limm,u6 0010111011100001F111uuuuuu1QQQQQ. */ -+{ "asldw", 0x2EE17020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asldw<.f> 0,limm,s12 0010111010100001F111ssssssSSSSSS. */ -+{ "asldw", 0x2EA17000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asldw<.f> a,limm,limm 0010111000100001F111111110AAAAAA. */ -+{ "asldw", 0x2E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asldw<.f> 0,limm,limm 0010111000100001F111111110111110. */ -+{ "asldw", 0x2E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asldw<.f><.cc> 0,limm,limm 0010111011100001F1111111100QQQQQ. */ -+{ "asldw", 0x2EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asls<.f> a,b,c 00101bbb00001010FBBBCCCCCCAAAAAA. */ -+{ "asls", 0x280A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asls<.f> 0,b,c 00101bbb00001010FBBBCCCCCC111110. */ -+{ "asls", 0x280A003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asls<.f><.cc> b,b,c 00101bbb11001010FBBBCCCCCC0QQQQQ. */ -+{ "asls", 0x28CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asls<.f> a,b,u6 00101bbb01001010FBBBuuuuuuAAAAAA. */ -+{ "asls", 0x284A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asls<.f> 0,b,u6 00101bbb01001010FBBBuuuuuu111110. */ -+{ "asls", 0x284A003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asls<.f><.cc> b,b,u6 00101bbb11001010FBBBuuuuuu1QQQQQ. */ -+{ "asls", 0x28CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asls<.f> b,b,s12 00101bbb10001010FBBBssssssSSSSSS. */ -+{ "asls", 0x288A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asls<.f> a,limm,c 0010111000001010F111CCCCCCAAAAAA. */ -+{ "asls", 0x2E0A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asls<.f> a,b,limm 00101bbb00001010FBBB111110AAAAAA. */ -+{ "asls", 0x280A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asls<.f> 0,limm,c 0010111000001010F111CCCCCC111110. */ -+{ "asls", 0x2E0A703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asls<.f> 0,b,limm 00101bbb00001010FBBB111110111110. */ -+{ "asls", 0x280A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asls<.f><.cc> b,b,limm 00101bbb11001010FBBB1111100QQQQQ. */ -+{ "asls", 0x28CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asls<.f><.cc> 0,limm,c 0010111011001010F111CCCCCC0QQQQQ. */ -+{ "asls", 0x2ECA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asls<.f> a,limm,u6 0010111001001010F111uuuuuuAAAAAA. */ -+{ "asls", 0x2E4A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asls<.f> 0,limm,u6 0010111001001010F111uuuuuu111110. */ -+{ "asls", 0x2E4A703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asls<.f><.cc> 0,limm,u6 0010111011001010F111uuuuuu1QQQQQ. */ -+{ "asls", 0x2ECA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asls<.f> 0,limm,s12 0010111010001010F111ssssssSSSSSS. */ -+{ "asls", 0x2E8A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asls<.f> a,limm,limm 0010111000001010F111111110AAAAAA. */ -+{ "asls", 0x2E0A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asls<.f> 0,limm,limm 0010111000001010F111111110111110. */ -+{ "asls", 0x2E0A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asls<.f><.cc> 0,limm,limm 0010111011001010F1111111100QQQQQ. */ -+{ "asls", 0x2ECA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* aslsacc c 00101001001011110000CCCCCC111111. */ -+{ "aslsacc", 0x292F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* aslsacc u6 00101001011011110000uuuuuu111111. */ -+{ "aslsacc", 0x296F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* aslsdw<.f> a,b,c 00101bbb00100100FBBBCCCCCCAAAAAA. */ -+{ "aslsdw", 0x28240000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* aslsdw<.f> 0,b,c 00101bbb00100100FBBBCCCCCC111110. */ -+{ "aslsdw", 0x2824003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* aslsdw<.f><.cc> b,b,c 00101bbb11100100FBBBCCCCCC0QQQQQ. */ -+{ "aslsdw", 0x28E40000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* aslsdw<.f> a,b,u6 00101bbb01100100FBBBuuuuuuAAAAAA. */ -+{ "aslsdw", 0x28640000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* aslsdw<.f> 0,b,u6 00101bbb01100100FBBBuuuuuu111110. */ -+{ "aslsdw", 0x2864003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* aslsdw<.f><.cc> b,b,u6 00101bbb11100100FBBBuuuuuu1QQQQQ. */ -+{ "aslsdw", 0x28E40020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* aslsdw<.f> b,b,s12 00101bbb10100100FBBBssssssSSSSSS. */ -+{ "aslsdw", 0x28A40000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* aslsdw<.f> a,limm,c 0010111000100100F111CCCCCCAAAAAA. */ -+{ "aslsdw", 0x2E247000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* aslsdw<.f> a,b,limm 00101bbb00100100FBBB111110AAAAAA. */ -+{ "aslsdw", 0x28240F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* aslsdw<.f> 0,limm,c 0010111000100100F111CCCCCC111110. */ -+{ "aslsdw", 0x2E24703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* aslsdw<.f> 0,b,limm 00101bbb00100100FBBB111110111110. */ -+{ "aslsdw", 0x28240FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* aslsdw<.f><.cc> 0,limm,c 0010111011100100F111CCCCCC0QQQQQ. */ -+{ "aslsdw", 0x2EE47000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* aslsdw<.f><.cc> b,b,limm 00101bbb11100100FBBB1111100QQQQQ. */ -+{ "aslsdw", 0x28E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* aslsdw<.f> a,limm,u6 0010111001100100F111uuuuuuAAAAAA. */ -+{ "aslsdw", 0x2E647000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* aslsdw<.f> 0,limm,u6 0010111001100100F111uuuuuu111110. */ -+{ "aslsdw", 0x2E64703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* aslsdw<.f><.cc> 0,limm,u6 0010111011100100F111uuuuuu1QQQQQ. */ -+{ "aslsdw", 0x2EE47020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* aslsdw<.f> 0,limm,s12 0010111010100100F111ssssssSSSSSS. */ -+{ "aslsdw", 0x2EA47000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* aslsdw<.f> a,limm,limm 0010111000100100F111111110AAAAAA. */ -+{ "aslsdw", 0x2E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* aslsdw<.f> 0,limm,limm 0010111000100100F111111110111110. */ -+{ "aslsdw", 0x2E247FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* aslsdw<.f><.cc> 0,limm,limm 0010111011100100F1111111100QQQQQ. */ -+{ "aslsdw", 0x2EE47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asl_s b,c 01111bbbccc11011. */ -+{ "asl_s", 0x0000781B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* asl_s b,b,c 01111bbbccc11000. */ -+{ "asl_s", 0x00007818, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* asl_s c,b,u3 01101bbbccc10uuu. */ -+{ "asl_s", 0x00006810, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, -+ -+/* asl_s b,b,u5 10111bbb000uuuuu. */ -+{ "asl_s", 0x0000B800, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* asr<.f> b,c 00100bbb00101111FBBBCCCCCC000001. */ -+{ "asr", 0x202F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> 0,c 0010011000101111F111CCCCCC000001. */ -+{ "asr", 0x262F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> a,b,c 00101bbb00000010FBBBCCCCCCAAAAAA. */ -+{ "asr", 0x28020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> 0,b,c 00101bbb00000010FBBBCCCCCC111110. */ -+{ "asr", 0x2802003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f><.cc> b,b,c 00101bbb11000010FBBBCCCCCC0QQQQQ. */ -+{ "asr", 0x28C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asr<.f> b,u6 00100bbb01101111FBBBuuuuuu000001. */ -+{ "asr", 0x206F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f> 0,u6 0010011001101111F111uuuuuu000001. */ -+{ "asr", 0x266F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f> a,b,u6 00101bbb01000010FBBBuuuuuuAAAAAA. */ -+{ "asr", 0x28420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f> 0,b,u6 00101bbb01000010FBBBuuuuuu111110. */ -+{ "asr", 0x2842003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f><.cc> b,b,u6 00101bbb11000010FBBBuuuuuu1QQQQQ. */ -+{ "asr", 0x28C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asr<.f> b,b,s12 00101bbb10000010FBBBssssssSSSSSS. */ -+{ "asr", 0x28820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asr<.f> b,limm 00100bbb00101111FBBB111110000001. */ -+{ "asr", 0x202F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr<.f> 0,limm 0010011000101111F111111110000001. */ -+{ "asr", 0x262F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asr<.f> a,limm,c 0010111000000010F111CCCCCCAAAAAA. */ -+{ "asr", 0x2E027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> a,b,limm 00101bbb00000010FBBB111110AAAAAA. */ -+{ "asr", 0x28020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr<.f> 0,limm,c 0010111000000010F111CCCCCC111110. */ -+{ "asr", 0x2E02703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asr<.f> 0,b,limm 00101bbb00000010FBBB111110111110. */ -+{ "asr", 0x28020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr<.f><.cc> b,b,limm 00101bbb11000010FBBB1111100QQQQQ. */ -+{ "asr", 0x28C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asr<.f><.cc> 0,limm,c 0010111011000010F111CCCCCC0QQQQQ. */ -+{ "asr", 0x2EC27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asr<.f> a,limm,u6 0010111001000010F111uuuuuuAAAAAA. */ -+{ "asr", 0x2E427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f> 0,limm,u6 0010111001000010F111uuuuuu111110. */ -+{ "asr", 0x2E42703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr<.f><.cc> 0,limm,u6 0010111011000010F111uuuuuu1QQQQQ. */ -+{ "asr", 0x2EC27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asr<.f> 0,limm,s12 0010111010000010F111ssssssSSSSSS. */ -+{ "asr", 0x2E827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asr<.f> a,limm,limm 0010111000000010F111111110AAAAAA. */ -+{ "asr", 0x2E027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asr<.f> 0,limm,limm 0010111000000010F111111110111110. */ -+{ "asr", 0x2E027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asr<.f><.cc> 0,limm,limm 0010111011000010F1111111100QQQQQ. */ -+{ "asr", 0x2EC27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asr16<.f> b,c 00101bbb00101111FBBBCCCCCC001100. */ -+{ "asr16", 0x282F000C, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr16<.f> 0,c 0010111000101111F111CCCCCC001100. */ -+{ "asr16", 0x2E2F700C, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001100. */ -+{ "asr16", 0x286F000C, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr16<.f> 0,u6 0010111001101111F111uuuuuu001100. */ -+{ "asr16", 0x2E6F700C, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr16<.f> b,limm 00101bbb00101111FBBB111110001100. */ -+{ "asr16", 0x282F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr16<.f> 0,limm 0010111000101111F111111110001100. */ -+{ "asr16", 0x2E2F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asr8<.f> b,c 00101bbb00101111FBBBCCCCCC001101. */ -+{ "asr8", 0x282F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asr8<.f> 0,c 0010111000101111F111CCCCCC001101. */ -+{ "asr8", 0x2E2F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* asr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001101. */ -+{ "asr8", 0x286F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr8<.f> 0,u6 0010111001101111F111uuuuuu001101. */ -+{ "asr8", 0x2E6F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asr8<.f> b,limm 00101bbb00101111FBBB111110001101. */ -+{ "asr8", 0x282F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asr8<.f> 0,limm 0010111000101111F111111110001101. */ -+{ "asr8", 0x2E2F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* asrdw<.f> a,b,c 00101bbb00100010FBBBCCCCCCAAAAAA. */ -+{ "asrdw", 0x28220000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrdw<.f> 0,b,c 00101bbb00100010FBBBCCCCCC111110. */ -+{ "asrdw", 0x2822003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrdw<.f><.cc> b,b,c 00101bbb11100010FBBBCCCCCC0QQQQQ. */ -+{ "asrdw", 0x28E20000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrdw<.f> a,b,u6 00101bbb01100010FBBBuuuuuuAAAAAA. */ -+{ "asrdw", 0x28620000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrdw<.f> 0,b,u6 00101bbb01100010FBBBuuuuuu111110. */ -+{ "asrdw", 0x2862003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrdw<.f><.cc> b,b,u6 00101bbb11100010FBBBuuuuuu1QQQQQ. */ -+{ "asrdw", 0x28E20020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrdw<.f> b,b,s12 00101bbb10100010FBBBssssssSSSSSS. */ -+{ "asrdw", 0x28A20000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrdw<.f> a,limm,c 0010111000100010F111CCCCCCAAAAAA. */ -+{ "asrdw", 0x2E227000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrdw<.f> a,b,limm 00101bbb00100010FBBB111110AAAAAA. */ -+{ "asrdw", 0x28220F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrdw<.f> 0,limm,c 0010111000100010F111CCCCCC111110. */ -+{ "asrdw", 0x2E22703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrdw<.f> 0,b,limm 00101bbb00100010FBBB111110111110. */ -+{ "asrdw", 0x28220FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrdw<.f><.cc> 0,limm,c 0010111011100010F111CCCCCC0QQQQQ. */ -+{ "asrdw", 0x2EE27000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrdw<.f><.cc> b,b,limm 00101bbb11100010FBBB1111100QQQQQ. */ -+{ "asrdw", 0x28E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asrdw<.f> a,limm,u6 0010111001100010F111uuuuuuAAAAAA. */ -+{ "asrdw", 0x2E627000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrdw<.f> 0,limm,u6 0010111001100010F111uuuuuu111110. */ -+{ "asrdw", 0x2E62703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrdw<.f><.cc> 0,limm,u6 0010111011100010F111uuuuuu1QQQQQ. */ -+{ "asrdw", 0x2EE27020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrdw<.f> 0,limm,s12 0010111010100010F111ssssssSSSSSS. */ -+{ "asrdw", 0x2EA27000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrdw<.f> a,limm,limm 0010111000100010F111111110AAAAAA. */ -+{ "asrdw", 0x2E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrdw<.f> 0,limm,limm 0010111000100010F111111110111110. */ -+{ "asrdw", 0x2E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrdw<.f><.cc> 0,limm,limm 0010111011100010F1111111100QQQQQ. */ -+{ "asrdw", 0x2EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asrs<.f> a,b,c 00101bbb00001011FBBBCCCCCCAAAAAA. */ -+{ "asrs", 0x280B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrs<.f> 0,b,c 00101bbb00001011FBBBCCCCCC111110. */ -+{ "asrs", 0x280B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrs<.f><.cc> b,b,c 00101bbb11001011FBBBCCCCCC0QQQQQ. */ -+{ "asrs", 0x28CB0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrs<.f> a,b,u6 00101bbb01001011FBBBuuuuuuAAAAAA. */ -+{ "asrs", 0x284B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrs<.f> 0,b,u6 00101bbb01001011FBBBuuuuuu111110. */ -+{ "asrs", 0x284B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrs<.f><.cc> b,b,u6 00101bbb11001011FBBBuuuuuu1QQQQQ. */ -+{ "asrs", 0x28CB0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrs<.f> b,b,s12 00101bbb10001011FBBBssssssSSSSSS. */ -+{ "asrs", 0x288B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrs<.f> a,limm,c 0010111000001011F111CCCCCCAAAAAA. */ -+{ "asrs", 0x2E0B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrs<.f> a,b,limm 00101bbb00001011FBBB111110AAAAAA. */ -+{ "asrs", 0x280B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrs<.f> 0,limm,c 0010111000001011F111CCCCCC111110. */ -+{ "asrs", 0x2E0B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrs<.f> 0,b,limm 00101bbb00001011FBBB111110111110. */ -+{ "asrs", 0x280B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrs<.f><.cc> b,b,limm 00101bbb11001011FBBB1111100QQQQQ. */ -+{ "asrs", 0x28CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asrs<.f><.cc> 0,limm,c 0010111011001011F111CCCCCC0QQQQQ. */ -+{ "asrs", 0x2ECB7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrs<.f> a,limm,u6 0010111001001011F111uuuuuuAAAAAA. */ -+{ "asrs", 0x2E4B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrs<.f> 0,limm,u6 0010111001001011F111uuuuuu111110. */ -+{ "asrs", 0x2E4B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrs<.f><.cc> 0,limm,u6 0010111011001011F111uuuuuu1QQQQQ. */ -+{ "asrs", 0x2ECB7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrs<.f> 0,limm,s12 0010111010001011F111ssssssSSSSSS. */ -+{ "asrs", 0x2E8B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrs<.f> a,limm,limm 0010111000001011F111111110AAAAAA. */ -+{ "asrs", 0x2E0B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrs<.f> 0,limm,limm 0010111000001011F111111110111110. */ -+{ "asrs", 0x2E0B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrs<.f><.cc> 0,limm,limm 0010111011001011F1111111100QQQQQ. */ -+{ "asrs", 0x2ECB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asrsdw<.f> a,b,c 00101bbb00100101FBBBCCCCCCAAAAAA. */ -+{ "asrsdw", 0x28250000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrsdw<.f> 0,b,c 00101bbb00100101FBBBCCCCCC111110. */ -+{ "asrsdw", 0x2825003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrsdw<.f><.cc> b,b,c 00101bbb11100101FBBBCCCCCC0QQQQQ. */ -+{ "asrsdw", 0x28E50000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrsdw<.f> a,b,u6 00101bbb01100101FBBBuuuuuuAAAAAA. */ -+{ "asrsdw", 0x28650000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsdw<.f> 0,b,u6 00101bbb01100101FBBBuuuuuu111110. */ -+{ "asrsdw", 0x2865003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsdw<.f><.cc> b,b,u6 00101bbb11100101FBBBuuuuuu1QQQQQ. */ -+{ "asrsdw", 0x28E50020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrsdw<.f> b,b,s12 00101bbb10100101FBBBssssssSSSSSS. */ -+{ "asrsdw", 0x28A50000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrsdw<.f> a,limm,c 0010111000100101F111CCCCCCAAAAAA. */ -+{ "asrsdw", 0x2E257000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrsdw<.f> a,b,limm 00101bbb00100101FBBB111110AAAAAA. */ -+{ "asrsdw", 0x28250F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrsdw<.f> 0,limm,c 0010111000100101F111CCCCCC111110. */ -+{ "asrsdw", 0x2E25703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrsdw<.f> 0,b,limm 00101bbb00100101FBBB111110111110. */ -+{ "asrsdw", 0x28250FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrsdw<.f><.cc> 0,limm,c 0010111011100101F111CCCCCC0QQQQQ. */ -+{ "asrsdw", 0x2EE57000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrsdw<.f><.cc> b,b,limm 00101bbb11100101FBBB1111100QQQQQ. */ -+{ "asrsdw", 0x28E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asrsdw<.f> a,limm,u6 0010111001100101F111uuuuuuAAAAAA. */ -+{ "asrsdw", 0x2E657000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsdw<.f> 0,limm,u6 0010111001100101F111uuuuuu111110. */ -+{ "asrsdw", 0x2E65703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsdw<.f><.cc> 0,limm,u6 0010111011100101F111uuuuuu1QQQQQ. */ -+{ "asrsdw", 0x2EE57020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrsdw<.f> 0,limm,s12 0010111010100101F111ssssssSSSSSS. */ -+{ "asrsdw", 0x2EA57000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrsdw<.f> a,limm,limm 0010111000100101F111111110AAAAAA. */ -+{ "asrsdw", 0x2E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrsdw<.f> 0,limm,limm 0010111000100101F111111110111110. */ -+{ "asrsdw", 0x2E257FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrsdw<.f><.cc> 0,limm,limm 0010111011100101F1111111100QQQQQ. */ -+{ "asrsdw", 0x2EE57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asrsr<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA. */ -+{ "asrsr", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrsr<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110. */ -+{ "asrsr", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* asrsr<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ. */ -+{ "asrsr", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrsr<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA. */ -+{ "asrsr", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsr<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110. */ -+{ "asrsr", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsr<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ. */ -+{ "asrsr", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrsr<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS. */ -+{ "asrsr", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrsr<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA. */ -+{ "asrsr", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrsr<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA. */ -+{ "asrsr", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrsr<.f> 0,limm,c 0010111000001100F111CCCCCC111110. */ -+{ "asrsr", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* asrsr<.f> 0,b,limm 00101bbb00001100FBBB111110111110. */ -+{ "asrsr", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* asrsr<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ. */ -+{ "asrsr", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* asrsr<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ. */ -+{ "asrsr", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* asrsr<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA. */ -+{ "asrsr", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsr<.f> 0,limm,u6 0010111001001100F111uuuuuu111110. */ -+{ "asrsr", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* asrsr<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ. */ -+{ "asrsr", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* asrsr<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS. */ -+{ "asrsr", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* asrsr<.f> a,limm,limm 0010111000001100F111111110AAAAAA. */ -+{ "asrsr", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrsr<.f> 0,limm,limm 0010111000001100F111111110111110. */ -+{ "asrsr", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* asrsr<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ. */ -+{ "asrsr", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* asr_s b,c 01111bbbccc11100. */ -+{ "asr_s", 0x0000781C, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* asr_s b,b,c 01111bbbccc11010. */ -+{ "asr_s", 0x0000781A, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* asr_s c,b,u3 01101bbbccc11uuu. */ -+{ "asr_s", 0x00006818, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, -+ -+/* asr_s b,b,u5 10111bbb010uuuuu. */ -+{ "asr_s", 0x0000B840, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* avgqb<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA. */ -+{ "avgqb", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* avgqb<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ. */ -+{ "avgqb", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* avgqb<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA. */ -+{ "avgqb", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* avgqb<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ. */ -+{ "avgqb", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* avgqb<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS. */ -+{ "avgqb", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* avgqb<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA. */ -+{ "avgqb", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* avgqb<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA. */ -+{ "avgqb", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* avgqb<.f><.cc> b,b,limm 00110bbb11100011FBBB1111100QQQQQ. */ -+{ "avgqb", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ -+{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM25_A16_5 }, { C_D }}, -+ -+/* b<.d> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ. */ -+{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM21_A16_5 }, { C_CC, C_D }}, -+ -+/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */ -+{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit0<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y110. */ -+{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T }}, -+ -+/* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110. */ -+{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit0<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y110. */ -+{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T }}, -+ -+/* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110001110. */ -+{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC001110. */ -+{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y110. */ -+{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T }}, -+ -+/* bbit0<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y110. */ -+{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T }}, -+ -+/* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu011110. */ -+{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y110. */ -+{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T }}, -+ -+/* bbit0 limm,limm,s9 00001110sssssss1S111111110001110. */ -+{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit0<.T> limm,limm,s9 00001110sssssss1S11111111000Y110. */ -+{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T }}, -+ -+/* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111. */ -+{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit1<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y111. */ -+{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T }}, -+ -+/* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111. */ -+{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, -+ -+/* bbit1<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y111. */ -+{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T }}, -+ -+/* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110001111. */ -+{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC001111. */ -+{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y111. */ -+{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T }}, -+ -+/* bbit1<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y111. */ -+{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T }}, -+ -+/* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu011111. */ -+{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y111. */ -+{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T }}, -+ -+/* bbit1 limm,limm,s9 00001110sssssss1S111111110001111. */ -+{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { 0 }}, -+ -+/* bbit1<.T> limm,limm,s9 00001110sssssss1S11111111000Y111. */ -+{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T }}, -+ -+/* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA. */ -+{ "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bclr<.f> 0,b,c 00100bbb00010000FBBBCCCCCC111110. */ -+{ "bclr", 0x2010003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bclr<.f><.cc> b,b,c 00100bbb11010000FBBBCCCCCC0QQQQQ. */ -+{ "bclr", 0x20D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bclr<.f> a,b,u6 00100bbb01010000FBBBuuuuuuAAAAAA. */ -+{ "bclr", 0x20500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclr<.f> 0,b,u6 00100bbb01010000FBBBuuuuuu111110. */ -+{ "bclr", 0x2050003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclr<.f><.cc> b,b,u6 00100bbb11010000FBBBuuuuuu1QQQQQ. */ -+{ "bclr", 0x20D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bclr<.f> b,b,s12 00100bbb10010000FBBBssssssSSSSSS. */ -+{ "bclr", 0x20900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bclr<.f> a,limm,c 0010011000010000F111CCCCCCAAAAAA. */ -+{ "bclr", 0x26107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bclr<.f> a,b,limm 00100bbb00010000FBBB111110AAAAAA. */ -+{ "bclr", 0x20100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bclr<.f> 0,limm,c 0010011000010000F111CCCCCC111110. */ -+{ "bclr", 0x2610703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bclr<.f> 0,b,limm 00100bbb00010000FBBB111110111110. */ -+{ "bclr", 0x20100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bclr<.f><.cc> b,b,limm 00100bbb11010000FBBB1111100QQQQQ. */ -+{ "bclr", 0x20D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bclr<.f><.cc> 0,limm,c 0010011011010000F111CCCCCC0QQQQQ. */ -+{ "bclr", 0x26D07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bclr<.f> a,limm,u6 0010011001010000F111uuuuuuAAAAAA. */ -+{ "bclr", 0x26507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclr<.f> 0,limm,u6 0010011001010000F111uuuuuu111110. */ -+{ "bclr", 0x2650703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bclr<.f><.cc> 0,limm,u6 0010011011010000F111uuuuuu1QQQQQ. */ -+{ "bclr", 0x26D07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bclr<.f> 0,limm,s12 0010011010010000F111ssssssSSSSSS. */ -+{ "bclr", 0x26907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bclr<.f> a,limm,limm 0010011000010000F111111110AAAAAA. */ -+{ "bclr", 0x26107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bclr<.f> 0,limm,limm 0010011000010000F111111110111110. */ -+{ "bclr", 0x26107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bclr<.f><.cc> 0,limm,limm 0010011011010000F1111111100QQQQQ. */ -+{ "bclr", 0x26D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bclr_s b,b,u5 10111bbb101uuuuu. */ -+{ "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* beq_s s10 1111001sssssssss. */ -+{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM10_A16_7_S }, { C_CC_EQ }}, -+ -+/* bge_s s7 1111011001ssssss. */ -+{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_GE }}, -+ -+/* bgt_s s7 1111011000ssssss. */ -+{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_GT }}, -+ -+/* bhi_s s7 1111011100ssssss. */ -+{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_HI }}, -+ -+/* bhs_s s7 1111011101ssssss. */ -+{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_HS }}, -+ -+/* bi c 00100RRR001001000RRRCCCCCCRRRRRR. */ -+{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BI, CD1, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* bi limm 00100RRR001001000RRR111110RRRRRR. */ -+{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BI, CD1, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA. */ -+{ "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bic<.f> 0,b,c 00100bbb00000110FBBBCCCCCC111110. */ -+{ "bic", 0x2006003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bic<.f><.cc> b,b,c 00100bbb11000110FBBBCCCCCC0QQQQQ. */ -+{ "bic", 0x20C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bic<.f> a,b,u6 00100bbb01000110FBBBuuuuuuAAAAAA. */ -+{ "bic", 0x20460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bic<.f> 0,b,u6 00100bbb01000110FBBBuuuuuu111110. */ -+{ "bic", 0x2046003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bic<.f><.cc> b,b,u6 00100bbb11000110FBBBuuuuuu1QQQQQ. */ -+{ "bic", 0x20C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bic<.f> b,b,s12 00100bbb10000110FBBBssssssSSSSSS. */ -+{ "bic", 0x20860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bic<.f> a,limm,c 0010011000000110F111CCCCCCAAAAAA. */ -+{ "bic", 0x26067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bic<.f> a,b,limm 00100bbb00000110FBBB111110AAAAAA. */ -+{ "bic", 0x20060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bic<.f> 0,limm,c 0010011000000110F111CCCCCC111110. */ -+{ "bic", 0x2606703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bic<.f> 0,b,limm 00100bbb00000110FBBB111110111110. */ -+{ "bic", 0x20060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bic<.f><.cc> b,b,limm 00100bbb11000110FBBB1111100QQQQQ. */ -+{ "bic", 0x20C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bic<.f><.cc> 0,limm,c 0010011011000110F111CCCCCC0QQQQQ. */ -+{ "bic", 0x26C67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bic<.f> a,limm,u6 0010011001000110F111uuuuuuAAAAAA. */ -+{ "bic", 0x26467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bic<.f> 0,limm,u6 0010011001000110F111uuuuuu111110. */ -+{ "bic", 0x2646703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bic<.f><.cc> 0,limm,u6 0010011011000110F111uuuuuu1QQQQQ. */ -+{ "bic", 0x26C67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bic<.f> 0,limm,s12 0010011010000110F111ssssssSSSSSS. */ -+{ "bic", 0x26867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bic<.f> a,limm,limm 0010011000000110F111111110AAAAAA. */ -+{ "bic", 0x26067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bic<.f> 0,limm,limm 0010011000000110F111111110111110. */ -+{ "bic", 0x26067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bic<.f><.cc> 0,limm,limm 0010011011000110F1111111100QQQQQ. */ -+{ "bic", 0x26C67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bic_s b,b,c 01111bbbccc00110. */ -+{ "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* bih c 00100RRR001001010RRRCCCCCCRRRRRR. */ -+{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BIH, CD1, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* bih limm 00100RRR001001010RRR111110RRRRRR. */ -+{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BIH, CD1, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ -+{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM25_A32_5 }, { C_D }}, -+ -+/* bl<.cc><.d> s21 00001sssssssss00SSSSSSSSSSNQQQQQ. */ -+{ "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM21_A32_5 }, { C_CC, C_D }}, -+ -+/* ble_s s7 1111011011ssssss. */ -+{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LE }}, -+ -+/* blo_s s7 1111011110ssssss. */ -+{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LO }}, -+ -+/* bls_s s7 1111011111ssssss. */ -+{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LS }}, -+ -+/* blt_s s7 1111011010ssssss. */ -+{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LT }}, -+ -+/* bl_s s13 11111sssssssssss. */ -+{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM13_A32_5_S }, { 0 }}, -+ -+/* bmsk<.f> a,b,c 00100bbb00010011FBBBCCCCCCAAAAAA. */ -+{ "bmsk", 0x20130000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmsk<.f> 0,b,c 00100bbb00010011FBBBCCCCCC111110. */ -+{ "bmsk", 0x2013003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmsk<.f><.cc> b,b,c 00100bbb11010011FBBBCCCCCC0QQQQQ. */ -+{ "bmsk", 0x20D30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmsk<.f> a,b,u6 00100bbb01010011FBBBuuuuuuAAAAAA. */ -+{ "bmsk", 0x20530000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsk<.f> 0,b,u6 00100bbb01010011FBBBuuuuuu111110. */ -+{ "bmsk", 0x2053003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsk<.f><.cc> b,b,u6 00100bbb11010011FBBBuuuuuu1QQQQQ. */ -+{ "bmsk", 0x20D30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmsk<.f> b,b,s12 00100bbb10010011FBBBssssssSSSSSS. */ -+{ "bmsk", 0x20930000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmsk<.f> a,limm,c 0010011000010011F111CCCCCCAAAAAA. */ -+{ "bmsk", 0x26137000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmsk<.f> a,b,limm 00100bbb00010011FBBB111110AAAAAA. */ -+{ "bmsk", 0x20130F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmsk<.f> 0,limm,c 0010011000010011F111CCCCCC111110. */ -+{ "bmsk", 0x2613703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmsk<.f> 0,b,limm 00100bbb00010011FBBB111110111110. */ -+{ "bmsk", 0x20130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmsk<.f><.cc> b,b,limm 00100bbb11010011FBBB1111100QQQQQ. */ -+{ "bmsk", 0x20D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bmsk<.f><.cc> 0,limm,c 0010011011010011F111CCCCCC0QQQQQ. */ -+{ "bmsk", 0x26D37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmsk<.f> a,limm,u6 0010011001010011F111uuuuuuAAAAAA. */ -+{ "bmsk", 0x26537000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsk<.f> 0,limm,u6 0010011001010011F111uuuuuu111110. */ -+{ "bmsk", 0x2653703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmsk<.f><.cc> 0,limm,u6 0010011011010011F111uuuuuu1QQQQQ. */ -+{ "bmsk", 0x26D37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmsk<.f> 0,limm,s12 0010011010010011F111ssssssSSSSSS. */ -+{ "bmsk", 0x26937000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmsk<.f> a,limm,limm 0010011000010011F111111110AAAAAA. */ -+{ "bmsk", 0x26137F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmsk<.f> 0,limm,limm 0010011000010011F111111110111110. */ -+{ "bmsk", 0x26137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmsk<.f><.cc> 0,limm,limm 0010011011010011F1111111100QQQQQ. */ -+{ "bmsk", 0x26D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bmskn<.f> a,b,c 00100bbb00101100FBBBCCCCCCAAAAAA. */ -+{ "bmskn", 0x202C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmskn<.f> 0,b,c 00100bbb00101100FBBBCCCCCC111110. */ -+{ "bmskn", 0x202C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bmskn<.f><.cc> b,b,c 00100bbb11101100FBBBCCCCCC0QQQQQ. */ -+{ "bmskn", 0x20EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmskn<.f> a,b,u6 00100bbb01101100FBBBuuuuuuAAAAAA. */ -+{ "bmskn", 0x206C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskn<.f> 0,b,u6 00100bbb01101100FBBBuuuuuu111110. */ -+{ "bmskn", 0x206C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskn<.f><.cc> b,b,u6 00100bbb11101100FBBBuuuuuu1QQQQQ. */ -+{ "bmskn", 0x20EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmskn<.f> b,b,s12 00100bbb10101100FBBBssssssSSSSSS. */ -+{ "bmskn", 0x20AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmskn<.f> a,limm,c 0010011000101100F111CCCCCCAAAAAA. */ -+{ "bmskn", 0x262C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmskn<.f> a,b,limm 00100bbb00101100FBBB111110AAAAAA. */ -+{ "bmskn", 0x202C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmskn<.f> 0,limm,c 0010011000101100F111CCCCCC111110. */ -+{ "bmskn", 0x262C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bmskn<.f> 0,b,limm 00100bbb00101100FBBB111110111110. */ -+{ "bmskn", 0x202C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bmskn<.f><.cc> b,b,limm 00100bbb11101100FBBB1111100QQQQQ. */ -+{ "bmskn", 0x20EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bmskn<.f><.cc> 0,limm,c 0010011011101100F111CCCCCC0QQQQQ. */ -+{ "bmskn", 0x26EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bmskn<.f> a,limm,u6 0010011001101100F111uuuuuuAAAAAA. */ -+{ "bmskn", 0x266C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskn<.f> 0,limm,u6 0010011001101100F111uuuuuu111110. */ -+{ "bmskn", 0x266C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bmskn<.f><.cc> 0,limm,u6 0010011011101100F111uuuuuu1QQQQQ. */ -+{ "bmskn", 0x26EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bmskn<.f> 0,limm,s12 0010011010101100F111ssssssSSSSSS. */ -+{ "bmskn", 0x26AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bmskn<.f> a,limm,limm 0010011000101100F111111110AAAAAA. */ -+{ "bmskn", 0x262C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmskn<.f> 0,limm,limm 0010011000101100F111111110111110. */ -+{ "bmskn", 0x262C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bmskn<.f><.cc> 0,limm,limm 0010011011101100F1111111100QQQQQ. */ -+{ "bmskn", 0x26EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bmsk_s b,b,u5 10111bbb110uuuuu. */ -+{ "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* bne_s s10 1111010sssssssss. */ -+{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM10_A16_7_S }, { C_CC_NE }}, -+ -+/* breq<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000. */ -+{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_EQ }}, -+ -+/* breq<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y000. */ -+{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_EQ }}, -+ -+/* breq<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000. */ -+{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_EQ }}, -+ -+/* breq<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y000. */ -+{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_EQ }}, -+ -+/* breq b,limm,s9 00001bbbsssssss1SBBB111110000000. */ -+{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, -+ -+/* breq limm,c,s9 00001110sssssss1S111CCCCCC000000. */ -+{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, -+ -+/* breq<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y000. */ -+{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_EQ }}, -+ -+/* breq<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y000. */ -+{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_EQ }}, -+ -+/* breq limm,u6,s9 00001110sssssss1S111uuuuuu010000. */ -+{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, -+ -+/* breq<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y000. */ -+{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_EQ }}, -+ -+/* breq<.T> limm,limm,s9 00001110sssssss1S11111111000Y000. */ -+{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_EQ }}, -+ -+/* breq_s b,0,s8 11101bbb0sssssss. */ -+{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB_S, OPERAND_ZB_S, OPERAND_SIMM8_A16_9_S }, { C_CC_EQ }}, -+ -+/* brge<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011. */ -+{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_GE }}, -+ -+/* brge<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y011. */ -+{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_GE }}, -+ -+/* brge<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011. */ -+{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_GE }}, -+ -+/* brge<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y011. */ -+{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_GE }}, -+ -+/* brge b,limm,s9 00001bbbsssssss1SBBB111110000011. */ -+{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, -+ -+/* brge limm,c,s9 00001110sssssss1S111CCCCCC000011. */ -+{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, -+ -+/* brge<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y011. */ -+{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_GE }}, -+ -+/* brge<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y011. */ -+{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_GE }}, -+ -+/* brge limm,u6,s9 00001110sssssss1S111uuuuuu010011. */ -+{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, -+ -+/* brge<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y011. */ -+{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_GE }}, -+ -+/* brge<.T> limm,limm,s9 00001110sssssss1S11111111000Y011. */ -+{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_GE }}, -+ -+/* brhs<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101. */ -+{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_HS }}, -+ -+/* brhs<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y101. */ -+{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_HS }}, -+ -+/* brhs<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101. */ -+{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_HS }}, -+ -+/* brhs<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y101. */ -+{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_HS }}, -+ -+/* brhs b,limm,s9 00001bbbsssssss1SBBB111110000101. */ -+{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, -+ -+/* brhs limm,c,s9 00001110sssssss1S111CCCCCC000101. */ -+{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, -+ -+/* brhs<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y101. */ -+{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_HS }}, -+ -+/* brhs<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y101. */ -+{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_HS }}, -+ -+/* brhs limm,u6,s9 00001110sssssss1S111uuuuuu010101. */ -+{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, -+ -+/* brhs<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y101. */ -+{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_HS }}, -+ -+/* brhs<.T> limm,limm,s9 00001110sssssss1S11111111000Y101. */ -+{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_HS }}, -+ -+/* brk 00100101011011110000000000111111. */ -+{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { C_CC_HS }}, -+ -+/* brk_s 0111111111111111. */ -+{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */ -+{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LO }}, -+ -+/* brlo<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y100. */ -+{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_LO }}, -+ -+/* brlo<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100. */ -+{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LO }}, -+ -+/* brlo<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y100. */ -+{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_LO }}, -+ -+/* brlo b,limm,s9 00001bbbsssssss1SBBB111110000100. */ -+{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, -+ -+/* brlo limm,c,s9 00001110sssssss1S111CCCCCC000100. */ -+{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, -+ -+/* brlo<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y100. */ -+{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LO }}, -+ -+/* brlo<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y100. */ -+{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LO }}, -+ -+/* brlo limm,u6,s9 00001110sssssss1S111uuuuuu010100. */ -+{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, -+ -+/* brlo<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y100. */ -+{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LO }}, -+ -+/* brlo<.T> limm,limm,s9 00001110sssssss1S11111111000Y100. */ -+{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LO }}, -+ -+/* brlt<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010. */ -+{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LT }}, -+ -+/* brlt<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y010. */ -+{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_LT }}, -+ -+/* brlt<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010. */ -+{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LT }}, -+ -+/* brlt<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y010. */ -+{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_LT }}, -+ -+/* brlt b,limm,s9 00001bbbsssssss1SBBB111110000010. */ -+{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, -+ -+/* brlt limm,c,s9 00001110sssssss1S111CCCCCC000010. */ -+{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, -+ -+/* brlt<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y010. */ -+{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LT }}, -+ -+/* brlt<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y010. */ -+{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LT }}, -+ -+/* brlt limm,u6,s9 00001110sssssss1S111uuuuuu010010. */ -+{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, -+ -+/* brlt<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y010. */ -+{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LT }}, -+ -+/* brlt<.T> limm,limm,s9 00001110sssssss1S11111111000Y010. */ -+{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LT }}, -+ -+/* brne<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001. */ -+{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_NE }}, -+ -+/* brne<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y001. */ -+{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_NE }}, -+ -+/* brne<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN10001. */ -+{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_NE }}, -+ -+/* brne<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y001. */ -+{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_NE }}, -+ -+/* brne b,limm,s9 00001bbbsssssss1SBBB111110000001. */ -+{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, -+ -+/* brne limm,c,s9 00001110sssssss1S111CCCCCC000001. */ -+{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, -+ -+/* brne<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y001. */ -+{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_NE }}, -+ -+/* brne<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y001. */ -+{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_NE }}, -+ -+/* brne limm,u6,s9 00001110sssssss1S111uuuuuu010001. */ -+{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, -+ -+/* brne<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y001. */ -+{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_NE }}, -+ -+/* brne<.T> limm,limm,s9 00001110sssssss1S11111111000Y001. */ -+{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_NE }}, -+ -+/* brne_s b,0,s8 11101bbb1sssssss. */ -+{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB_S, OPERAND_ZB_S, OPERAND_SIMM8_A16_9_S }, { C_CC_NE }}, -+ -+/* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA. */ -+{ "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bset<.f> 0,b,c 00100bbb00001111FBBBCCCCCC111110. */ -+{ "bset", 0x200F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bset<.f><.cc> b,b,c 00100bbb11001111FBBBCCCCCC0QQQQQ. */ -+{ "bset", 0x20CF0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bset<.f> a,b,u6 00100bbb01001111FBBBuuuuuuAAAAAA. */ -+{ "bset", 0x204F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bset<.f> 0,b,u6 00100bbb01001111FBBBuuuuuu111110. */ -+{ "bset", 0x204F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bset<.f><.cc> b,b,u6 00100bbb11001111FBBBuuuuuu1QQQQQ. */ -+{ "bset", 0x20CF0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bset<.f> b,b,s12 00100bbb10001111FBBBssssssSSSSSS. */ -+{ "bset", 0x208F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bset<.f> a,limm,c 0010011000001111F111CCCCCCAAAAAA. */ -+{ "bset", 0x260F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bset<.f> a,b,limm 00100bbb00001111FBBB111110AAAAAA. */ -+{ "bset", 0x200F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bset<.f> 0,limm,c 0010011000001111F111CCCCCC111110. */ -+{ "bset", 0x260F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bset<.f> 0,b,limm 00100bbb00001111FBBB111110111110. */ -+{ "bset", 0x200F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bset<.f><.cc> b,b,limm 00100bbb11001111FBBB1111100QQQQQ. */ -+{ "bset", 0x20CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bset<.f><.cc> 0,limm,c 0010011011001111F111CCCCCC0QQQQQ. */ -+{ "bset", 0x26CF7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bset<.f> a,limm,u6 0010011001001111F111uuuuuuAAAAAA. */ -+{ "bset", 0x264F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bset<.f> 0,limm,u6 0010011001001111F111uuuuuu111110. */ -+{ "bset", 0x264F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bset<.f><.cc> 0,limm,u6 0010011011001111F111uuuuuu1QQQQQ. */ -+{ "bset", 0x26CF7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bset<.f> 0,limm,s12 0010011010001111F111ssssssSSSSSS. */ -+{ "bset", 0x268F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bset<.f> a,limm,limm 0010011000001111F111111110AAAAAA. */ -+{ "bset", 0x260F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bset<.f> 0,limm,limm 0010011000001111F111111110111110. */ -+{ "bset", 0x260F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bset<.f><.cc> 0,limm,limm 0010011011001111F1111111100QQQQQ. */ -+{ "bset", 0x26CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* bset_s b,b,u5 10111bbb100uuuuu. */ -+{ "bset_s", 0x0000B880, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* btst b,c 00100bbb000100011BBBCCCCCCRRRRRR. */ -+{ "btst", 0x20118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* btst b,c 00100bbb000100011BBBCCCCCC000000. */ -+{ "btst", 0x20118000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* btst<.cc> b,c 00100bbb110100011BBBCCCCCC0QQQQQ. */ -+{ "btst", 0x20D18000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* btst b,u6 00100bbb010100011BBBuuuuuuRRRRRR. */ -+{ "btst", 0x20518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* btst b,u6 00100bbb010100011BBBuuuuuu000000. */ -+{ "btst", 0x20518000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* btst<.cc> b,u6 00100bbb110100011BBBuuuuuu1QQQQQ. */ -+{ "btst", 0x20D18020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* btst b,s12 00100bbb100100011BBBssssssSSSSSS. */ -+{ "btst", 0x20918000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* btst limm,c 00100110000100011111CCCCCCRRRRRR. */ -+{ "btst", 0x2611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* btst b,limm 00100bbb000100011BBB111110RRRRRR. */ -+{ "btst", 0x20118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* btst limm,c 00100110000100011111CCCCCC000000. */ -+{ "btst", 0x2611F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* btst b,limm 00100bbb000100011BBB111110000000. */ -+{ "btst", 0x20118F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* btst<.cc> b,limm 00100bbb110100011BBB1111100QQQQQ. */ -+{ "btst", 0x20D18F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* btst<.cc> limm,c 00100110110100011111CCCCCC0QQQQQ. */ -+{ "btst", 0x26D1F000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* btst limm,u6 00100110010100011111uuuuuuRRRRRR. */ -+{ "btst", 0x2651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* btst limm,u6 00100110010100011111uuuuuu000000. */ -+{ "btst", 0x2651F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* btst<.cc> limm,u6 00100110110100011111uuuuuu1QQQQQ. */ -+{ "btst", 0x26D1F020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* btst limm,s12 00100110100100011111ssssssSSSSSS. */ -+{ "btst", 0x2691F000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* btst limm,limm 00100110000100011111111110RRRRRR. */ -+{ "btst", 0x2611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* btst limm,limm 00100110000100011111111110000000. */ -+{ "btst", 0x2611FF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* btst<.cc> limm,limm 001001101101000111111111100QQQQQ. */ -+{ "btst", 0x26D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* btst_s b,u5 10111bbb111uuuuu. */ -+{ "btst_s", 0x0000B8E0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* bxor<.f> a,b,c 00100bbb00010010FBBBCCCCCCAAAAAA. */ -+{ "bxor", 0x20120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bxor<.f> 0,b,c 00100bbb00010010FBBBCCCCCC111110. */ -+{ "bxor", 0x2012003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* bxor<.f><.cc> b,b,c 00100bbb11010010FBBBCCCCCC0QQQQQ. */ -+{ "bxor", 0x20D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bxor<.f> a,b,u6 00100bbb01010010FBBBuuuuuuAAAAAA. */ -+{ "bxor", 0x20520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxor<.f> 0,b,u6 00100bbb01010010FBBBuuuuuu111110. */ -+{ "bxor", 0x2052003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxor<.f><.cc> b,b,u6 00100bbb11010010FBBBuuuuuu1QQQQQ. */ -+{ "bxor", 0x20D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bxor<.f> b,b,s12 00100bbb10010010FBBBssssssSSSSSS. */ -+{ "bxor", 0x20920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bxor<.f> a,limm,c 0010011000010010F111CCCCCCAAAAAA. */ -+{ "bxor", 0x26127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bxor<.f> a,b,limm 00100bbb00010010FBBB111110AAAAAA. */ -+{ "bxor", 0x20120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bxor<.f> 0,limm,c 0010011000010010F111CCCCCC111110. */ -+{ "bxor", 0x2612703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* bxor<.f> 0,b,limm 00100bbb00010010FBBB111110111110. */ -+{ "bxor", 0x20120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* bxor<.f><.cc> b,b,limm 00100bbb11010010FBBB1111100QQQQQ. */ -+{ "bxor", 0x20D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* bxor<.f><.cc> 0,limm,c 0010011011010010F111CCCCCC0QQQQQ. */ -+{ "bxor", 0x26D27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* bxor<.f> a,limm,u6 0010011001010010F111uuuuuuAAAAAA. */ -+{ "bxor", 0x26527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxor<.f> 0,limm,u6 0010011001010010F111uuuuuu111110. */ -+{ "bxor", 0x2652703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* bxor<.f><.cc> 0,limm,u6 0010011011010010F111uuuuuu1QQQQQ. */ -+{ "bxor", 0x26D27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* bxor<.f> 0,limm,s12 0010011010010010F111ssssssSSSSSS. */ -+{ "bxor", 0x26927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* bxor<.f> a,limm,limm 0010011000010010F111111110AAAAAA. */ -+{ "bxor", 0x26127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bxor<.f> 0,limm,limm 0010011000010010F111111110111110. */ -+{ "bxor", 0x26127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* bxor<.f><.cc> 0,limm,limm 0010011011010010F1111111100QQQQQ. */ -+{ "bxor", 0x26D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* b_s s10 1111000sssssssss. */ -+{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM10_A16_7_S }, { 0 }}, -+ -+/* cbflyhf0r a,b,c 00110bbb000110111BBBCCCCCCAAAAAA. */ -+{ "cbflyhf0r", 0x301B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf0r 0,b,c 00110bbb000110111BBBCCCCCC111110. */ -+{ "cbflyhf0r", 0x301B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf0r<.cc> b,b,c 00110bbb110110111BBBCCCCCC0QQQQQ. */ -+{ "cbflyhf0r", 0x30DB8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cbflyhf0r a,b,u6 00110bbb010110111BBBuuuuuuAAAAAA. */ -+{ "cbflyhf0r", 0x305B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf0r 0,b,u6 00110bbb010110111BBBuuuuuu111110. */ -+{ "cbflyhf0r", 0x305B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf0r<.cc> b,b,u6 00110bbb110110111BBBuuuuuu1QQQQQ. */ -+{ "cbflyhf0r", 0x30DB8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cbflyhf0r b,b,s12 00110bbb100110111BBBssssssSSSSSS. */ -+{ "cbflyhf0r", 0x309B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cbflyhf0r a,limm,c 00110110000110111111CCCCCCAAAAAA. */ -+{ "cbflyhf0r", 0x361BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf0r a,b,limm 00110bbb000110111BBB111110AAAAAA. */ -+{ "cbflyhf0r", 0x301B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cbflyhf0r 0,limm,c 00110110000110111111CCCCCC111110. */ -+{ "cbflyhf0r", 0x361BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf0r 0,b,limm 00110bbb000110111BBB111110111110. */ -+{ "cbflyhf0r", 0x301B8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cbflyhf0r<.cc> b,b,limm 00110bbb110110111BBB1111100QQQQQ. */ -+{ "cbflyhf0r", 0x30DB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cbflyhf0r<.cc> 0,limm,c 00110110110110111111CCCCCC0QQQQQ. */ -+{ "cbflyhf0r", 0x36DBF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cbflyhf0r a,limm,u6 00110110010110111111uuuuuuAAAAAA. */ -+{ "cbflyhf0r", 0x365BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf0r 0,limm,u6 00110110010110111111uuuuuu111110. */ -+{ "cbflyhf0r", 0x365BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf0r<.cc> 0,limm,u6 00110110110110111111uuuuuu1QQQQQ. */ -+{ "cbflyhf0r", 0x36DBF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cbflyhf0r 0,limm,s12 00110110100110111111ssssssSSSSSS. */ -+{ "cbflyhf0r", 0x369BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cbflyhf0r a,limm,limm 00110110000110111111111110AAAAAA. */ -+{ "cbflyhf0r", 0x361BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cbflyhf0r 0,limm,limm 00110110000110111111111110111110. */ -+{ "cbflyhf0r", 0x361BFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cbflyhf0r<.cc> 0,limm,limm 001101101101101111111111100QQQQQ. */ -+{ "cbflyhf0r", 0x36DBFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cbflyhf1r b,c 00110bbb001011110BBBCCCCCC111001. */ -+{ "cbflyhf1r", 0x302F0039, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf1r 0,c 00110110001011110111CCCCCC011001. */ -+{ "cbflyhf1r", 0x362F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* cbflyhf1r b,u6 00110bbb011011110BBBuuuuuu011001. */ -+{ "cbflyhf1r", 0x306F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf1r 0,u6 00110110011011110111uuuuuu011001. */ -+{ "cbflyhf1r", 0x366F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cbflyhf1r b,limm 00110bbb001011110BBB111110011001. */ -+{ "cbflyhf1r", 0x302F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* cbflyhf1r 0,limm 00110110001011110111111110011001. */ -+{ "cbflyhf1r", 0x362F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* clamp<.f> a,b,c 00110bbb00101010FBBBCCCCCCAAAAAA. */ -+{ "clamp", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* clamp<.f><.cc> b,b,c 00110bbb11101010FBBBCCCCCC0QQQQQ. */ -+{ "clamp", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* clamp<.f> a,b,u6 00110bbb01101010FBBBuuuuuuAAAAAA. */ -+{ "clamp", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* clamp<.f><.cc> b,b,u6 00110bbb11101010FBBBuuuuuu1QQQQQ. */ -+{ "clamp", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* clamp<.f> b,b,s12 00110bbb10101010FBBBssssssSSSSSS. */ -+{ "clamp", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* clamp<.f> a,limm,c 0011011000101010F111CCCCCCAAAAAA. */ -+{ "clamp", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* clamp<.f> a,b,limm 00110bbb00101010FBBB111110AAAAAA. */ -+{ "clamp", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* clamp<.f><.cc> b,b,limm 00110bbb11101010FBBB1111100QQQQQ. */ -+{ "clamp", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* clri c 00100111001011110000CCCCCC111111. */ -+{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* clri u6 00100111011011110000uuuuuu111111. */ -+{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* clri 00100111011011110000uuuuuu111111. */ -+{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA. */ -+{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmacchfr 0,b,c 00110bbb000010011BBBCCCCCC111110. */ -+{ "cmacchfr", 0x3009803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmacchfr<.cc> b,b,c 00110bbb110010011BBBCCCCCC0QQQQQ. */ -+{ "cmacchfr", 0x30C98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmacchfr a,b,u6 00110bbb010010011BBBuuuuuuAAAAAA. */ -+{ "cmacchfr", 0x30498000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchfr 0,b,u6 00110bbb010010011BBBuuuuuu111110. */ -+{ "cmacchfr", 0x3049803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchfr<.cc> b,b,u6 00110bbb110010011BBBuuuuuu1QQQQQ. */ -+{ "cmacchfr", 0x30C98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmacchfr b,b,s12 00110bbb100010011BBBssssssSSSSSS. */ -+{ "cmacchfr", 0x30898000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmacchfr a,limm,c 00110110000010011111CCCCCCAAAAAA. */ -+{ "cmacchfr", 0x3609F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmacchfr a,b,limm 00110bbb000010011BBB111110AAAAAA. */ -+{ "cmacchfr", 0x30098F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmacchfr 0,limm,c 00110110000010011111CCCCCC111110. */ -+{ "cmacchfr", 0x3609F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmacchfr 0,b,limm 00110bbb000010011BBB111110111110. */ -+{ "cmacchfr", 0x30098FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmacchfr<.cc> 0,limm,c 00110bbb110010011BBB1111100QQQQQ. */ -+{ "cmacchfr", 0x30C98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmacchfr<.cc> b,b,limm 00110110110010011111CCCCCC0QQQQQ. */ -+{ "cmacchfr", 0x36C9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmacchfr a,limm,u6 00110110010010011111uuuuuuAAAAAA. */ -+{ "cmacchfr", 0x3649F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchfr 0,limm,u6 00110110010010011111uuuuuu111110. */ -+{ "cmacchfr", 0x3649F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchfr<.cc> 0,limm,u6 00110110110010011111uuuuuu1QQQQQ. */ -+{ "cmacchfr", 0x36C9F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmacchfr 0,limm,s12 00110110100010011111ssssssSSSSSS. */ -+{ "cmacchfr", 0x3689F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmacchfr a,limm,limm 00110110000010011111111110AAAAAA. */ -+{ "cmacchfr", 0x3609FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmacchfr 0,limm,limm 00110110000010011111111110111110. */ -+{ "cmacchfr", 0x3609FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmacchfr<.cc> 0,limm,limm 001101101100100111111111100QQQQQ. */ -+{ "cmacchfr", 0x36C9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmacchnfr a,b,c 00110bbb000010001BBBCCCCCCAAAAAA. */ -+{ "cmacchnfr", 0x30088000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmacchnfr 0,b,c 00110bbb000010001BBBCCCCCC111110. */ -+{ "cmacchnfr", 0x3008803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmacchnfr<.cc> b,b,c 00110bbb110010001BBBCCCCCC0QQQQQ. */ -+{ "cmacchnfr", 0x30C88000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmacchnfr a,b,u6 00110bbb010010001BBBuuuuuuAAAAAA. */ -+{ "cmacchnfr", 0x30488000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchnfr 0,b,u6 00110bbb010010001BBBuuuuuu111110. */ -+{ "cmacchnfr", 0x3048803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchnfr<.cc> b,b,u6 00110bbb110010001BBBuuuuuu1QQQQQ. */ -+{ "cmacchnfr", 0x30C88020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmacchnfr b,b,s12 00110bbb100010001BBBssssssSSSSSS. */ -+{ "cmacchnfr", 0x30888000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmacchnfr a,limm,c 00110110000010001111CCCCCCAAAAAA. */ -+{ "cmacchnfr", 0x3608F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmacchnfr a,b,limm 00110bbb000010001BBB111110AAAAAA. */ -+{ "cmacchnfr", 0x30088F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmacchnfr 0,limm,c 00110110000010001111CCCCCC111110. */ -+{ "cmacchnfr", 0x3608F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmacchnfr 0,b,limm 00110bbb000010001BBB111110111110. */ -+{ "cmacchnfr", 0x30088FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmacchnfr<.cc> 0,limm,c 00110bbb110010001BBB1111100QQQQQ. */ -+{ "cmacchnfr", 0x30C88F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmacchnfr<.cc> b,b,limm 00110110110010001111CCCCCC0QQQQQ. */ -+{ "cmacchnfr", 0x36C8F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmacchnfr a,limm,u6 00110110010010001111uuuuuuAAAAAA. */ -+{ "cmacchnfr", 0x3648F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchnfr 0,limm,u6 00110110010010001111uuuuuu111110. */ -+{ "cmacchnfr", 0x3648F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmacchnfr<.cc> 0,limm,u6 00110110110010001111uuuuuu1QQQQQ. */ -+{ "cmacchnfr", 0x36C8F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmacchnfr 0,limm,s12 00110110100010001111ssssssSSSSSS. */ -+{ "cmacchnfr", 0x3688F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmacchnfr a,limm,limm 00110110000010001111111110AAAAAA. */ -+{ "cmacchnfr", 0x3608FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmacchnfr 0,limm,limm 00110110000010001111111110111110. */ -+{ "cmacchnfr", 0x3608FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmacchnfr<.cc> 0,limm,limm 001101101100100011111111100QQQQQ. */ -+{ "cmacchnfr", 0x36C8FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmachfr a,b,c 00110bbb000001111BBBCCCCCCAAAAAA. */ -+{ "cmachfr", 0x30078000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmachfr 0,b,c 00110bbb000001111BBBCCCCCC111110. */ -+{ "cmachfr", 0x3007803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmachfr<.cc> b,b,c 00110bbb110001111BBBCCCCCC0QQQQQ. */ -+{ "cmachfr", 0x30C78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmachfr a,b,u6 00110bbb010001111BBBuuuuuuAAAAAA. */ -+{ "cmachfr", 0x30478000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachfr 0,b,u6 00110bbb010001111BBBuuuuuu111110. */ -+{ "cmachfr", 0x3047803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachfr<.cc> b,b,u6 00110bbb110001111BBBuuuuuu1QQQQQ. */ -+{ "cmachfr", 0x30C78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmachfr b,b,s12 00110bbb100001111BBBssssssSSSSSS. */ -+{ "cmachfr", 0x30878000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmachfr a,limm,c 00110110000001111111CCCCCCAAAAAA. */ -+{ "cmachfr", 0x3607F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmachfr a,b,limm 00110bbb000001111BBB111110AAAAAA. */ -+{ "cmachfr", 0x30078F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmachfr 0,limm,c 00110110000001111111CCCCCC111110. */ -+{ "cmachfr", 0x3607F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmachfr 0,b,limm 00110bbb000001111BBB111110111110. */ -+{ "cmachfr", 0x30078FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmachfr<.cc> 0,limm,c 00110bbb110001111BBB1111100QQQQQ. */ -+{ "cmachfr", 0x30C78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmachfr<.cc> b,b,limm 00110110110001111111CCCCCC0QQQQQ. */ -+{ "cmachfr", 0x36C7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmachfr a,limm,u6 00110110010001111111uuuuuuAAAAAA. */ -+{ "cmachfr", 0x3647F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachfr 0,limm,u6 00110110010001111111uuuuuu111110. */ -+{ "cmachfr", 0x3647F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachfr<.cc> 0,limm,u6 00110110110001111111uuuuuu1QQQQQ. */ -+{ "cmachfr", 0x36C7F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmachfr 0,limm,s12 00110110100001111111ssssssSSSSSS. */ -+{ "cmachfr", 0x3687F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmachfr a,limm,limm 00110110000001111111111110AAAAAA. */ -+{ "cmachfr", 0x3607FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmachfr 0,limm,limm 00110110000001111111111110111110. */ -+{ "cmachfr", 0x3607FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmachfr<.cc> 0,limm,limm 001101101100011111111111100QQQQQ. */ -+{ "cmachfr", 0x36C7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmachnfr a,b,c 00110bbb000001101BBBCCCCCCAAAAAA. */ -+{ "cmachnfr", 0x30068000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmachnfr 0,b,c 00110bbb000001101BBBCCCCCC111110. */ -+{ "cmachnfr", 0x3006803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmachnfr<.cc> b,b,c 00110bbb110001101BBBCCCCCC0QQQQQ. */ -+{ "cmachnfr", 0x30C68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmachnfr a,b,u6 00110bbb010001101BBBuuuuuuAAAAAA. */ -+{ "cmachnfr", 0x30468000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachnfr 0,b,u6 00110bbb010001101BBBuuuuuu111110. */ -+{ "cmachnfr", 0x3046803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachnfr<.cc> b,b,u6 00110bbb110001101BBBuuuuuu1QQQQQ. */ -+{ "cmachnfr", 0x30C68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmachnfr b,b,s12 00110bbb100001101BBBssssssSSSSSS. */ -+{ "cmachnfr", 0x30868000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmachnfr a,limm,c 00110110000001101111CCCCCCAAAAAA. */ -+{ "cmachnfr", 0x3606F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmachnfr a,b,limm 00110bbb000001101BBB111110AAAAAA. */ -+{ "cmachnfr", 0x30068F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmachnfr 0,limm,c 00110110000001101111CCCCCC111110. */ -+{ "cmachnfr", 0x3606F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmachnfr 0,b,limm 00110bbb000001101BBB111110111110. */ -+{ "cmachnfr", 0x30068FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmachnfr<.cc> 0,limm,c 00110bbb110001101BBB1111100QQQQQ. */ -+{ "cmachnfr", 0x30C68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmachnfr<.cc> b,b,limm 00110110110001101111CCCCCC0QQQQQ. */ -+{ "cmachnfr", 0x36C6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmachnfr a,limm,u6 00110110010001101111uuuuuuAAAAAA. */ -+{ "cmachnfr", 0x3646F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachnfr 0,limm,u6 00110110010001101111uuuuuu111110. */ -+{ "cmachnfr", 0x3646F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmachnfr<.cc> 0,limm,u6 00110110110001101111uuuuuu1QQQQQ. */ -+{ "cmachnfr", 0x36C6F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmachnfr 0,limm,s12 00110110100001101111ssssssSSSSSS. */ -+{ "cmachnfr", 0x3686F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmachnfr a,limm,limm 00110110000001101111111110AAAAAA. */ -+{ "cmachnfr", 0x3606FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmachnfr 0,limm,limm 00110110000001101111111110111110. */ -+{ "cmachnfr", 0x3606FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmachnfr<.cc> 0,limm,limm 001101101100011011111111100QQQQQ. */ -+{ "cmachnfr", 0x36C6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmacrdw<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA. */ -+{ "cmacrdw", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* cmacrdw<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110. */ -+{ "cmacrdw", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* cmacrdw<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ. */ -+{ "cmacrdw", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* cmacrdw<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA. */ -+{ "cmacrdw", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* cmacrdw<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110. */ -+{ "cmacrdw", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* cmacrdw<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ. */ -+{ "cmacrdw", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* cmacrdw<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS. */ -+{ "cmacrdw", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* cmacrdw<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA. */ -+{ "cmacrdw", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* cmacrdw<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA. */ -+{ "cmacrdw", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* cmacrdw<.f> 0,limm,c 0010111000100110F111CCCCCC111110. */ -+{ "cmacrdw", 0x2E26703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* cmacrdw<.f> 0,b,limm 00101bbb00100110FBBB111110111110. */ -+{ "cmacrdw", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* cmacrdw<.f><.cc> 0,limm,c 0010111011100110F111CCCCCC0QQQQQ. */ -+{ "cmacrdw", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* cmacrdw<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ. */ -+{ "cmacrdw", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* cmacrdw<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA. */ -+{ "cmacrdw", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* cmacrdw<.f> 0,limm,u6 0010111001100110F111uuuuuu111110. */ -+{ "cmacrdw", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* cmacrdw<.f><.cc> 0,limm,u6 0010111011100110F111uuuuuu1QQQQQ. */ -+{ "cmacrdw", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* cmacrdw<.f> 0,limm,s12 0010111010100110F111ssssssSSSSSS. */ -+{ "cmacrdw", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* cmacrdw<.f> a,limm,limm 0010111000100110F111111110AAAAAA. */ -+{ "cmacrdw", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* cmacrdw<.f> 0,limm,limm 0010111000100110F111111110111110. */ -+{ "cmacrdw", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* cmacrdw<.f><.cc> 0,limm,limm 0010111011100110F1111111100QQQQQ. */ -+{ "cmacrdw", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* cmp b,c 00100bbb000011001BBBCCCCCCRRRRRR. */ -+{ "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmp b,c 00100bbb000011001BBBCCCCCC000000. */ -+{ "cmp", 0x200C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmp<.cc> b,c 00100bbb110011001BBBCCCCCC0QQQQQ. */ -+{ "cmp", 0x20CC8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* cmp b,u6 00100bbb010011001BBBuuuuuuRRRRRR. */ -+{ "cmp", 0x204C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmp b,u6 00100bbb010011001BBBuuuuuu000000. */ -+{ "cmp", 0x204C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmp<.cc> b,u6 00100bbb110011001BBBuuuuuu1QQQQQ. */ -+{ "cmp", 0x20CC8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmp b,s12 00100bbb100011001BBBssssssSSSSSS. */ -+{ "cmp", 0x208C8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmp limm,c 00100110000011001111CCCCCCRRRRRR. */ -+{ "cmp", 0x260CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmp b,limm 00100bbb000011001BBB111110RRRRRR. */ -+{ "cmp", 0x200C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmp limm,c 00100110000011001111CCCCCC000000. */ -+{ "cmp", 0x260CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmp b,limm 00100bbb000011001BBB111110000000. */ -+{ "cmp", 0x200C8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmp<.cc> b,limm 00100bbb110011001BBB1111100QQQQQ. */ -+{ "cmp", 0x20CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmp<.cc> limm,c 00100110110011001111CCCCCC0QQQQQ. */ -+{ "cmp", 0x26CCF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmp limm,u6 00100110010011001111uuuuuuRRRRRR. */ -+{ "cmp", 0x264CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmp limm,u6 00100110010011001111uuuuuu000000. */ -+{ "cmp", 0x264CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmp<.cc> limm,u6 00100110110011001111uuuuuu1QQQQQ. */ -+{ "cmp", 0x26CCF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmp limm,s12 00100110100011001111ssssssSSSSSS. */ -+{ "cmp", 0x268CF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmp limm,limm 00100110000011001111111110RRRRRR. */ -+{ "cmp", 0x260CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmp limm,limm 00100110000011001111111110000000. */ -+{ "cmp", 0x260CFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmp<.cc> limm,limm 001001101100110011111111100QQQQQ. */ -+{ "cmp", 0x26CCFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpychfr a,b,c 00110bbb000001011BBBCCCCCCAAAAAA. */ -+{ "cmpychfr", 0x30058000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpychfr 0,b,c 00110bbb000001011BBBCCCCCC111110. */ -+{ "cmpychfr", 0x3005803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpychfr<.cc> b,b,c 00110bbb110001011BBBCCCCCC0QQQQQ. */ -+{ "cmpychfr", 0x30C58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpychfr a,b,u6 00110bbb010001011BBBuuuuuuAAAAAA. */ -+{ "cmpychfr", 0x30458000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychfr 0,b,u6 00110bbb010001011BBBuuuuuu111110. */ -+{ "cmpychfr", 0x3045803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychfr<.cc> b,b,u6 00110bbb110001011BBBuuuuuu1QQQQQ. */ -+{ "cmpychfr", 0x30C58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpychfr b,b,s12 00110bbb100001011BBBssssssSSSSSS. */ -+{ "cmpychfr", 0x30858000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpychfr a,limm,c 00110110000001011111CCCCCCAAAAAA. */ -+{ "cmpychfr", 0x3605F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpychfr a,b,limm 00110bbb000001011BBB111110AAAAAA. */ -+{ "cmpychfr", 0x30058F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpychfr 0,limm,c 00110110000001011111CCCCCC111110. */ -+{ "cmpychfr", 0x3605F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpychfr 0,b,limm 00110bbb000001011BBB111110111110. */ -+{ "cmpychfr", 0x30058FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpychfr<.cc> 0,limm,c 00110bbb110001011BBB1111100QQQQQ. */ -+{ "cmpychfr", 0x30C58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpychfr<.cc> b,b,limm 00110110110001011111CCCCCC0QQQQQ. */ -+{ "cmpychfr", 0x36C5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpychfr a,limm,u6 00110110010001011111uuuuuuAAAAAA. */ -+{ "cmpychfr", 0x3645F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychfr 0,limm,u6 00110110010001011111uuuuuu111110. */ -+{ "cmpychfr", 0x3645F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychfr<.cc> 0,limm,u6 00110110110001011111uuuuuu1QQQQQ. */ -+{ "cmpychfr", 0x36C5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpychfr 0,limm,s12 00110110100001011111ssssssSSSSSS. */ -+{ "cmpychfr", 0x3685F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpychfr a,limm,limm 00110110000001011111111110AAAAAA. */ -+{ "cmpychfr", 0x3605FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpychfr 0,limm,limm 00110110000001011111111110111110. */ -+{ "cmpychfr", 0x3605FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpychfr<.cc> 0,limm,limm 001101101100010111111111100QQQQQ. */ -+{ "cmpychfr", 0x36C5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpychnfr a,b,c 00110bbb000000101BBBCCCCCCAAAAAA. */ -+{ "cmpychnfr", 0x30028000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpychnfr 0,b,c 00110bbb000000001BBBCCCCCC111110. */ -+{ "cmpychnfr", 0x3000803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpychnfr<.cc> b,b,c 00110bbb110000001BBBCCCCCC0QQQQQ. */ -+{ "cmpychnfr", 0x30C08000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpychnfr a,b,u6 00110bbb010000001BBBuuuuuuAAAAAA. */ -+{ "cmpychnfr", 0x30408000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychnfr 0,b,u6 00110bbb010000001BBBuuuuuu111110. */ -+{ "cmpychnfr", 0x3040803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychnfr<.cc> b,b,u6 00110bbb110000001BBBuuuuuu1QQQQQ. */ -+{ "cmpychnfr", 0x30C08020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpychnfr b,b,s12 00110bbb100000001BBBssssssSSSSSS. */ -+{ "cmpychnfr", 0x30808000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpychnfr a,limm,c 00110110000000001111CCCCCCAAAAAA. */ -+{ "cmpychnfr", 0x3600F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpychnfr a,b,limm 00110bbb000000001BBB111110AAAAAA. */ -+{ "cmpychnfr", 0x30008F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpychnfr 0,limm,c 00110110000000001111CCCCCC111110. */ -+{ "cmpychnfr", 0x3600F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpychnfr 0,b,limm 00110bbb000000001BBB111110111110. */ -+{ "cmpychnfr", 0x30008FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpychnfr<.cc> 0,limm,c 00110bbb110000001BBB1111100QQQQQ. */ -+{ "cmpychnfr", 0x30C08F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpychnfr<.cc> b,b,limm 00110110110000001111CCCCCC0QQQQQ. */ -+{ "cmpychnfr", 0x36C0F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpychnfr a,limm,u6 00110110010000001111uuuuuuAAAAAA. */ -+{ "cmpychnfr", 0x3640F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychnfr 0,limm,u6 00110110010000001111uuuuuu111110. */ -+{ "cmpychnfr", 0x3640F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpychnfr<.cc> 0,limm,u6 00110110110000001111uuuuuu1QQQQQ. */ -+{ "cmpychnfr", 0x36C0F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpychnfr 0,limm,s12 00110110100000001111ssssssSSSSSS. */ -+{ "cmpychnfr", 0x3680F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpychnfr a,limm,limm 00110110000000001111111110AAAAAA. */ -+{ "cmpychnfr", 0x3600FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpychnfr 0,limm,limm 00110110000000001111111110111110. */ -+{ "cmpychnfr", 0x3600FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpychnfr<.cc> 0,limm,limm 001101101100000011111111100QQQQQ. */ -+{ "cmpychnfr", 0x36C0FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpyhfmr a,b,c 00110bbb000110110BBBCCCCCCAAAAAA. */ -+{ "cmpyhfmr", 0x301B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfmr 0,b,c 00110bbb000110110BBBCCCCCC111110. */ -+{ "cmpyhfmr", 0x301B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfmr<.cc> b,b,c 00110bbb110110110BBBCCCCCC0QQQQQ. */ -+{ "cmpyhfmr", 0x30DB0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhfmr a,b,u6 00110bbb010110110BBBuuuuuuAAAAAA. */ -+{ "cmpyhfmr", 0x305B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfmr 0,b,u6 00110bbb010110110BBBuuuuuu111110. */ -+{ "cmpyhfmr", 0x305B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfmr<.cc> b,b,u6 00110bbb110110110BBBuuuuuu1QQQQQ. */ -+{ "cmpyhfmr", 0x30DB0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhfmr b,b,s12 00110bbb100110110BBBssssssSSSSSS. */ -+{ "cmpyhfmr", 0x309B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhfmr a,limm,c 00110110000110110111CCCCCCAAAAAA. */ -+{ "cmpyhfmr", 0x361B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfmr a,b,limm 00110bbb000110110BBB111110AAAAAA. */ -+{ "cmpyhfmr", 0x301B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhfmr 0,limm,c 00110110000110110111CCCCCC111110. */ -+{ "cmpyhfmr", 0x361B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfmr 0,b,limm 00110bbb000110110BBB111110111110. */ -+{ "cmpyhfmr", 0x301B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhfmr<.cc> 0,limm,c 00110bbb110110110BBB1111100QQQQQ. */ -+{ "cmpyhfmr", 0x30DB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhfmr<.cc> b,b,limm 00110110110110110111CCCCCC0QQQQQ. */ -+{ "cmpyhfmr", 0x36DB7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpyhfmr a,limm,u6 00110110010110110111uuuuuuAAAAAA. */ -+{ "cmpyhfmr", 0x365B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfmr 0,limm,u6 00110110010110110111uuuuuu111110. */ -+{ "cmpyhfmr", 0x365B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfmr<.cc> 0,limm,u6 00110110110110110111uuuuuu1QQQQQ. */ -+{ "cmpyhfmr", 0x36DB7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhfmr 0,limm,s12 00110110100110110111ssssssSSSSSS. */ -+{ "cmpyhfmr", 0x369B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhfmr a,limm,limm 00110110000110110111111110AAAAAA. */ -+{ "cmpyhfmr", 0x361B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhfmr 0,limm,limm 00110110000110110111111110111110. */ -+{ "cmpyhfmr", 0x361B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhfmr<.cc> 0,limm,limm 001101101101101101111111100QQQQQ. */ -+{ "cmpyhfmr", 0x36DB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpyhfr a,b,c 00110bbb000000011BBBCCCCCCAAAAAA. */ -+{ "cmpyhfr", 0x30018000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfr 0,b,c 00110bbb000000011BBBCCCCCC111110. */ -+{ "cmpyhfr", 0x3001803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfr<.cc> b,b,c 00110bbb110000011BBBCCCCCC0QQQQQ. */ -+{ "cmpyhfr", 0x30C18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhfr a,b,u6 00110bbb010000011BBBuuuuuuAAAAAA. */ -+{ "cmpyhfr", 0x30418000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfr 0,b,u6 00110bbb010000011BBBuuuuuu111110. */ -+{ "cmpyhfr", 0x3041803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfr<.cc> b,b,u6 00110bbb110000011BBBuuuuuu1QQQQQ. */ -+{ "cmpyhfr", 0x30C18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhfr b,b,s12 00110bbb100000011BBBssssssSSSSSS. */ -+{ "cmpyhfr", 0x30818000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhfr a,limm,c 00110110000000011111CCCCCCAAAAAA. */ -+{ "cmpyhfr", 0x3601F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfr a,b,limm 00110bbb000000011BBB111110AAAAAA. */ -+{ "cmpyhfr", 0x30018F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhfr 0,limm,c 00110110000000011111CCCCCC111110. */ -+{ "cmpyhfr", 0x3601F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhfr 0,b,limm 00110bbb000000011BBB111110111110. */ -+{ "cmpyhfr", 0x30018FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhfr<.cc> 0,limm,c 00110bbb110000011BBB1111100QQQQQ. */ -+{ "cmpyhfr", 0x30C18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhfr<.cc> b,b,limm 00110110110000011111CCCCCC0QQQQQ. */ -+{ "cmpyhfr", 0x36C1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpyhfr a,limm,u6 00110110010000011111uuuuuuAAAAAA. */ -+{ "cmpyhfr", 0x3641F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfr 0,limm,u6 00110110010000011111uuuuuu111110. */ -+{ "cmpyhfr", 0x3641F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhfr<.cc> 0,limm,u6 00110110110000011111uuuuuu1QQQQQ. */ -+{ "cmpyhfr", 0x36C1F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhfr 0,limm,s12 00110110100000011111ssssssSSSSSS. */ -+{ "cmpyhfr", 0x3681F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhfr a,limm,limm 00110110000000011111111110AAAAAA. */ -+{ "cmpyhfr", 0x3601FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhfr 0,limm,limm 00110110000000011111111110111110. */ -+{ "cmpyhfr", 0x3601FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhfr<.cc> 0,limm,limm 001101101100000111111111100QQQQQ. */ -+{ "cmpyhfr", 0x36C1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmpyhnfr a,b,c 00110bbb000000001BBBCCCCCCAAAAAA. */ -+{ "cmpyhnfr", 0x30008000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhnfr 0,b,c 00110bbb000000101BBBCCCCCC111110. */ -+{ "cmpyhnfr", 0x3002803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhnfr<.cc> b,b,c 00110bbb110000101BBBCCCCCC0QQQQQ. */ -+{ "cmpyhnfr", 0x30C28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhnfr a,b,u6 00110bbb010000101BBBuuuuuuAAAAAA. */ -+{ "cmpyhnfr", 0x30428000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhnfr 0,b,u6 00110bbb010000101BBBuuuuuu111110. */ -+{ "cmpyhnfr", 0x3042803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhnfr<.cc> b,b,u6 00110bbb110000101BBBuuuuuu1QQQQQ. */ -+{ "cmpyhnfr", 0x30C28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhnfr b,b,s12 00110bbb100000101BBBssssssSSSSSS. */ -+{ "cmpyhnfr", 0x30828000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhnfr a,limm,c 00110110000000101111CCCCCCAAAAAA. */ -+{ "cmpyhnfr", 0x3602F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhnfr a,b,limm 00110bbb000000101BBB111110AAAAAA. */ -+{ "cmpyhnfr", 0x30028F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhnfr 0,limm,c 00110110000000101111CCCCCC111110. */ -+{ "cmpyhnfr", 0x3602F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* cmpyhnfr 0,b,limm 00110bbb000000101BBB111110111110. */ -+{ "cmpyhnfr", 0x30028FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* cmpyhnfr<.cc> 0,limm,c 00110bbb110000101BBB1111100QQQQQ. */ -+{ "cmpyhnfr", 0x30C28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* cmpyhnfr<.cc> b,b,limm 00110110110000101111CCCCCC0QQQQQ. */ -+{ "cmpyhnfr", 0x36C2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* cmpyhnfr a,limm,u6 00110110010000101111uuuuuuAAAAAA. */ -+{ "cmpyhnfr", 0x3642F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhnfr 0,limm,u6 00110110010000101111uuuuuu111110. */ -+{ "cmpyhnfr", 0x3642F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* cmpyhnfr<.cc> 0,limm,u6 00110110110000101111uuuuuu1QQQQQ. */ -+{ "cmpyhnfr", 0x36C2F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* cmpyhnfr 0,limm,s12 00110110100000101111ssssssSSSSSS. */ -+{ "cmpyhnfr", 0x3682F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* cmpyhnfr a,limm,limm 00110110000000101111111110AAAAAA. */ -+{ "cmpyhnfr", 0x3602FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhnfr 0,limm,limm 00110110000000101111111110111110. */ -+{ "cmpyhnfr", 0x3602FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* cmpyhnfr<.cc> 0,limm,limm 001101101100001011111111100QQQQQ. */ -+{ "cmpyhnfr", 0x36C2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* cmp_s b,h 01110bbbhhh10HHH. */ -+{ "cmp_s", 0x00007010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_R6H }, { 0 }}, -+ -+/* cmp_s b,h 01110bbbhhh100HH. */ -+{ "cmp_s", 0x00007010, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { 0 }}, -+ -+/* cmp_s h,s3 01110ssshhh101HH. */ -+{ "cmp_s", 0x00007014, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* cmp_s b,u7 11100bbb1uuuuuuu. */ -+{ "cmp_s", 0x0000E080, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_UIMM7_9_S }, { 0 }}, -+ -+/* cmp_s b,limm 01110bbb11010111. */ -+{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* cmp_s b,limm 01110bbb11010011. */ -+{ "cmp_s", 0x000070D3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* cmp_s limm,s3 01110sss11010111. */ -+{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* crc<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA. */ -+{ "crc", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* crc<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110. */ -+{ "crc", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* crc<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ. */ -+{ "crc", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* crc<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA. */ -+{ "crc", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* crc<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110. */ -+{ "crc", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* crc<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ. */ -+{ "crc", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* crc<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS. */ -+{ "crc", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* crc<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA. */ -+{ "crc", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* crc<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA. */ -+{ "crc", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* crc<.f> 0,limm,c 0010111000101100F111CCCCCC111110. */ -+{ "crc", 0x2E2C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* crc<.f> 0,b,limm 00101bbb00101100FBBB111110111110. */ -+{ "crc", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* crc<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ. */ -+{ "crc", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* crc<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ. */ -+{ "crc", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* crc<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA. */ -+{ "crc", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* crc<.f> 0,limm,u6 0010111001101100F111uuuuuu111110. */ -+{ "crc", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* crc<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ. */ -+{ "crc", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* crc<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS. */ -+{ "crc", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* crc<.f> a,limm,limm 0010111000101100F111111110AAAAAA. */ -+{ "crc", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* crc<.f> 0,limm,limm 0010111000101100F111111110111110. */ -+{ "crc", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* crc<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ. */ -+{ "crc", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* daddh11<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA. */ -+{ "daddh11", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh11<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110. */ -+{ "daddh11", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh11<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ. */ -+{ "daddh11", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh11<.f> a,b,c 00110bbb00110100FBBBCCCCCCAAAAAA. */ -+{ "daddh11", 0x30340000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh11<.f> 0,b,c 00110bbb00110100FBBBCCCCCC111110. */ -+{ "daddh11", 0x3034003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh11<.f><.cc> b,b,c 00110bbb11110100FBBBCCCCCC0QQQQQ. */ -+{ "daddh11", 0x30F40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh11<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA. */ -+{ "daddh11", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh11<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110. */ -+{ "daddh11", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh11<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ. */ -+{ "daddh11", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh11<.f> a,b,u6 00110bbb01110100FBBBuuuuuuAAAAAA. */ -+{ "daddh11", 0x30740000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh11<.f> 0,b,u6 00110bbb01110100FBBBuuuuuu111110. */ -+{ "daddh11", 0x3074003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh11<.f><.cc> b,b,u6 00110bbb11110100FBBBuuuuuu1QQQQQ. */ -+{ "daddh11", 0x30F40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh11<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS. */ -+{ "daddh11", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh11<.f> b,b,s12 00110bbb10110100FBBBssssssSSSSSS. */ -+{ "daddh11", 0x30B40000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh11<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA. */ -+{ "daddh11", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh11<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA. */ -+{ "daddh11", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh11<.f> 0,limm,c 0011011000001100F111CCCCCC111110. */ -+{ "daddh11", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh11<.f> 0,b,limm 00110bbb00001100FBBB111110111110. */ -+{ "daddh11", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh11<.f><.cc> 0,limm,c 0011011011001100F111CCCCCC0QQQQQ. */ -+{ "daddh11", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh11<.f><.cc> b,b,limm 00110bbb11001100FBBB1111100QQQQQ. */ -+{ "daddh11", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* daddh11<.f> a,limm,c 0011011000110100F111CCCCCCAAAAAA. */ -+{ "daddh11", 0x36347000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh11<.f> a,b,limm 00110bbb00110100FBBB111110AAAAAA. */ -+{ "daddh11", 0x30340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh11<.f> 0,limm,c 0011011000110100F111CCCCCC111110. */ -+{ "daddh11", 0x3634703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh11<.f> 0,b,limm 00110bbb00110100FBBB111110111110. */ -+{ "daddh11", 0x30340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh11<.f><.cc> 0,limm,c 0011011011110100F111CCCCCC0QQQQQ. */ -+{ "daddh11", 0x36F47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh11<.f><.cc> b,b,limm 00110bbb11110100FBBB1111100QQQQQ. */ -+{ "daddh11", 0x30F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* daddh11<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA. */ -+{ "daddh11", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh11<.f> 0,limm,u6 0011011001001100F111uuuuuu111110. */ -+{ "daddh11", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh11<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ. */ -+{ "daddh11", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh11<.f> a,limm,u6 0011011001110100F111uuuuuuAAAAAA. */ -+{ "daddh11", 0x36747000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh11<.f> 0,limm,u6 0011011001110100F111uuuuuu111110. */ -+{ "daddh11", 0x3674703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh11<.f><.cc> 0,limm,u6 0011011011110100F111uuuuuu1QQQQQ. */ -+{ "daddh11", 0x36F47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh11<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS. */ -+{ "daddh11", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh11<.f> 0,limm,s12 0011011010110100F111ssssssSSSSSS. */ -+{ "daddh11", 0x36B47000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh11<.f> a,limm,limm 0011011000001100F111111110AAAAAA. */ -+{ "daddh11", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh11<.f> 0,limm,limm 0011011000001100F111111110111110. */ -+{ "daddh11", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh11<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ. */ -+{ "daddh11", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* daddh11<.f> a,limm,limm 0011011000110100F111111110AAAAAA. */ -+{ "daddh11", 0x36347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh11<.f> 0,limm,limm 0011011000110100F111111110111110. */ -+{ "daddh11", 0x36347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh11<.f><.cc> 0,limm,limm 0011011011110100F1111111100QQQQQ. */ -+{ "daddh11", 0x36F47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* daddh12<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA. */ -+{ "daddh12", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh12<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110. */ -+{ "daddh12", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh12<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ. */ -+{ "daddh12", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh12<.f> a,b,c 00110bbb00110101FBBBCCCCCCAAAAAA. */ -+{ "daddh12", 0x30350000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh12<.f> 0,b,c 00110bbb00110101FBBBCCCCCC111110. */ -+{ "daddh12", 0x3035003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh12<.f><.cc> b,b,c 00110bbb11110101FBBBCCCCCC0QQQQQ. */ -+{ "daddh12", 0x30F50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh12<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA. */ -+{ "daddh12", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh12<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110. */ -+{ "daddh12", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh12<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ. */ -+{ "daddh12", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh12<.f> a,b,u6 00110bbb01110101FBBBuuuuuuAAAAAA. */ -+{ "daddh12", 0x30750000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh12<.f> 0,b,u6 00110bbb01110101FBBBuuuuuu111110. */ -+{ "daddh12", 0x3075003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh12<.f><.cc> b,b,u6 00110bbb11110101FBBBuuuuuu1QQQQQ. */ -+{ "daddh12", 0x30F50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh12<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS. */ -+{ "daddh12", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh12<.f> b,b,s12 00110bbb10110101FBBBssssssSSSSSS. */ -+{ "daddh12", 0x30B50000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh12<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA. */ -+{ "daddh12", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh12<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA. */ -+{ "daddh12", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh12<.f> 0,limm,c 0011011000001101F111CCCCCC111110. */ -+{ "daddh12", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh12<.f> 0,b,limm 00110bbb00001101FBBB111110111110. */ -+{ "daddh12", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh12<.f><.cc> 0,limm,c 0011011011001101F111CCCCCC0QQQQQ. */ -+{ "daddh12", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh12<.f><.cc> b,b,limm 00110bbb11001101FBBB1111100QQQQQ. */ -+{ "daddh12", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* daddh12<.f> a,limm,c 0011011000110101F111CCCCCCAAAAAA. */ -+{ "daddh12", 0x36357000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh12<.f> a,b,limm 00110bbb00110101FBBB111110AAAAAA. */ -+{ "daddh12", 0x30350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh12<.f> 0,limm,c 0011011000110101F111CCCCCC111110. */ -+{ "daddh12", 0x3635703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh12<.f> 0,b,limm 00110bbb00110101FBBB111110111110. */ -+{ "daddh12", 0x30350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh12<.f><.cc> 0,limm,c 0011011011110101F111CCCCCC0QQQQQ. */ -+{ "daddh12", 0x36F57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh12<.f><.cc> b,b,limm 00110bbb11110101FBBB1111100QQQQQ. */ -+{ "daddh12", 0x30F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* daddh12<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA. */ -+{ "daddh12", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh12<.f> 0,limm,u6 0011011001001101F111uuuuuu111110. */ -+{ "daddh12", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh12<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ. */ -+{ "daddh12", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh12<.f> a,limm,u6 0011011001110101F111uuuuuuAAAAAA. */ -+{ "daddh12", 0x36757000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh12<.f> 0,limm,u6 0011011001110101F111uuuuuu111110. */ -+{ "daddh12", 0x3675703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh12<.f><.cc> 0,limm,u6 0011011011110101F111uuuuuu1QQQQQ. */ -+{ "daddh12", 0x36F57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh12<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS. */ -+{ "daddh12", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh12<.f> 0,limm,s12 0011011010110101F111ssssssSSSSSS. */ -+{ "daddh12", 0x36B57000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh12<.f> a,limm,limm 0011011000001101F111111110AAAAAA. */ -+{ "daddh12", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh12<.f> 0,limm,limm 0011011000001101F111111110111110. */ -+{ "daddh12", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh12<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ. */ -+{ "daddh12", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* daddh12<.f> a,limm,limm 0011011000110101F111111110AAAAAA. */ -+{ "daddh12", 0x36357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh12<.f> 0,limm,limm 0011011000110101F111111110111110. */ -+{ "daddh12", 0x36357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh12<.f><.cc> 0,limm,limm 0011011011110101F1111111100QQQQQ. */ -+{ "daddh12", 0x36F57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* daddh21<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA. */ -+{ "daddh21", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh21<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110. */ -+{ "daddh21", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh21<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ. */ -+{ "daddh21", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh21<.f> a,b,c 00110bbb00110110FBBBCCCCCCAAAAAA. */ -+{ "daddh21", 0x30360000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh21<.f> 0,b,c 00110bbb00110110FBBBCCCCCC111110. */ -+{ "daddh21", 0x3036003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh21<.f><.cc> b,b,c 00110bbb11110110FBBBCCCCCC0QQQQQ. */ -+{ "daddh21", 0x30F60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh21<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA. */ -+{ "daddh21", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh21<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110. */ -+{ "daddh21", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh21<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ. */ -+{ "daddh21", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh21<.f> a,b,u6 00110bbb01110110FBBBuuuuuuAAAAAA. */ -+{ "daddh21", 0x30760000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh21<.f> 0,b,u6 00110bbb01110110FBBBuuuuuu111110. */ -+{ "daddh21", 0x3076003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh21<.f><.cc> b,b,u6 00110bbb11110110FBBBuuuuuu1QQQQQ. */ -+{ "daddh21", 0x30F60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh21<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS. */ -+{ "daddh21", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh21<.f> b,b,s12 00110bbb10110110FBBBssssssSSSSSS. */ -+{ "daddh21", 0x30B60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh21<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA. */ -+{ "daddh21", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh21<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA. */ -+{ "daddh21", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh21<.f> 0,limm,c 0011011000001110F111CCCCCC111110. */ -+{ "daddh21", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh21<.f> 0,b,limm 00110bbb00001110FBBB111110111110. */ -+{ "daddh21", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh21<.f><.cc> 0,limm,c 0011011011001110F111CCCCCC0QQQQQ. */ -+{ "daddh21", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh21<.f><.cc> b,b,limm 00110bbb11001110FBBB1111100QQQQQ. */ -+{ "daddh21", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* daddh21<.f> a,limm,c 0011011000110110F111CCCCCCAAAAAA. */ -+{ "daddh21", 0x36367000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh21<.f> a,b,limm 00110bbb00110110FBBB111110AAAAAA. */ -+{ "daddh21", 0x30360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh21<.f> 0,limm,c 0011011000110110F111CCCCCC111110. */ -+{ "daddh21", 0x3636703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh21<.f> 0,b,limm 00110bbb00110110FBBB111110111110. */ -+{ "daddh21", 0x30360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh21<.f><.cc> 0,limm,c 0011011011110110F111CCCCCC0QQQQQ. */ -+{ "daddh21", 0x36F67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh21<.f><.cc> b,b,limm 00110bbb11110110FBBB1111100QQQQQ. */ -+{ "daddh21", 0x30F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* daddh21<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA. */ -+{ "daddh21", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh21<.f> 0,limm,u6 0011011001001110F111uuuuuu111110. */ -+{ "daddh21", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh21<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ. */ -+{ "daddh21", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh21<.f> a,limm,u6 0011011001110110F111uuuuuuAAAAAA. */ -+{ "daddh21", 0x36767000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh21<.f> 0,limm,u6 0011011001110110F111uuuuuu111110. */ -+{ "daddh21", 0x3676703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh21<.f><.cc> 0,limm,u6 0011011011110110F111uuuuuu1QQQQQ. */ -+{ "daddh21", 0x36F67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh21<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS. */ -+{ "daddh21", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh21<.f> 0,limm,s12 0011011010110110F111ssssssSSSSSS. */ -+{ "daddh21", 0x36B67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh21<.f> a,limm,limm 0011011000001110F111111110AAAAAA. */ -+{ "daddh21", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh21<.f> 0,limm,limm 0011011000001110F111111110111110. */ -+{ "daddh21", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh21<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ. */ -+{ "daddh21", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* daddh21<.f> a,limm,limm 0011011000110110F111111110AAAAAA. */ -+{ "daddh21", 0x36367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh21<.f> 0,limm,limm 0011011000110110F111111110111110. */ -+{ "daddh21", 0x36367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh21<.f><.cc> 0,limm,limm 0011011011110110F1111111100QQQQQ. */ -+{ "daddh21", 0x36F67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* daddh22<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA. */ -+{ "daddh22", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh22<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110. */ -+{ "daddh22", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh22<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ. */ -+{ "daddh22", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh22<.f> a,b,c 00110bbb00110111FBBBCCCCCCAAAAAA. */ -+{ "daddh22", 0x30370000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh22<.f> 0,b,c 00110bbb00110111FBBBCCCCCC111110. */ -+{ "daddh22", 0x3037003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* daddh22<.f><.cc> b,b,c 00110bbb11110111FBBBCCCCCC0QQQQQ. */ -+{ "daddh22", 0x30F70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh22<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA. */ -+{ "daddh22", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh22<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110. */ -+{ "daddh22", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh22<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ. */ -+{ "daddh22", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh22<.f> a,b,u6 00110bbb01110111FBBBuuuuuuAAAAAA. */ -+{ "daddh22", 0x30770000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh22<.f> 0,b,u6 00110bbb01110111FBBBuuuuuu111110. */ -+{ "daddh22", 0x3077003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh22<.f><.cc> b,b,u6 00110bbb11110111FBBBuuuuuu1QQQQQ. */ -+{ "daddh22", 0x30F70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh22<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS. */ -+{ "daddh22", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh22<.f> b,b,s12 00110bbb10110111FBBBssssssSSSSSS. */ -+{ "daddh22", 0x30B70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh22<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA. */ -+{ "daddh22", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh22<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA. */ -+{ "daddh22", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh22<.f> 0,limm,c 0011011000001111F111CCCCCC111110. */ -+{ "daddh22", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh22<.f> 0,b,limm 00110bbb00001111FBBB111110111110. */ -+{ "daddh22", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh22<.f><.cc> 0,limm,c 0011011011001111F111CCCCCC0QQQQQ. */ -+{ "daddh22", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh22<.f><.cc> b,b,limm 00110bbb11001111FBBB1111100QQQQQ. */ -+{ "daddh22", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* daddh22<.f> a,limm,c 0011011000110111F111CCCCCCAAAAAA. */ -+{ "daddh22", 0x36377000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh22<.f> a,b,limm 00110bbb00110111FBBB111110AAAAAA. */ -+{ "daddh22", 0x30370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh22<.f> 0,limm,c 0011011000110111F111CCCCCC111110. */ -+{ "daddh22", 0x3637703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* daddh22<.f> 0,b,limm 00110bbb00110111FBBB111110111110. */ -+{ "daddh22", 0x30370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* daddh22<.f><.cc> 0,limm,c 0011011011110111F111CCCCCC0QQQQQ. */ -+{ "daddh22", 0x36F77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* daddh22<.f><.cc> b,b,limm 00110bbb11110111FBBB1111100QQQQQ. */ -+{ "daddh22", 0x30F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* daddh22<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA. */ -+{ "daddh22", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh22<.f> 0,limm,u6 0011011001001111F111uuuuuu111110. */ -+{ "daddh22", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh22<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ. */ -+{ "daddh22", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh22<.f> a,limm,u6 0011011001110111F111uuuuuuAAAAAA. */ -+{ "daddh22", 0x36777000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh22<.f> 0,limm,u6 0011011001110111F111uuuuuu111110. */ -+{ "daddh22", 0x3677703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* daddh22<.f><.cc> 0,limm,u6 0011011011110111F111uuuuuu1QQQQQ. */ -+{ "daddh22", 0x36F77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* daddh22<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS. */ -+{ "daddh22", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh22<.f> 0,limm,s12 0011011010110111F111ssssssSSSSSS. */ -+{ "daddh22", 0x36B77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* daddh22<.f> a,limm,limm 0011011000001111F111111110AAAAAA. */ -+{ "daddh22", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh22<.f> 0,limm,limm 0011011000001111F111111110111110. */ -+{ "daddh22", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh22<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ. */ -+{ "daddh22", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* daddh22<.f> a,limm,limm 0011011000110111F111111110AAAAAA. */ -+{ "daddh22", 0x36377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh22<.f> 0,limm,limm 0011011000110111F111111110111110. */ -+{ "daddh22", 0x36377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* daddh22<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ. */ -+{ "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS. */ -+{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_RB, OPERAND_SIMM13_A16_20}, { C_DNZ_D }}, -+ -+/* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA. */ -+{ "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dexcl1<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110. */ -+{ "dexcl1", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dexcl1<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ. */ -+{ "dexcl1", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dexcl1<.f> a,b,c 00110bbb00111100FBBBCCCCCCAAAAAA. */ -+{ "dexcl1", 0x303C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dexcl1<.f> 0,b,c 00110bbb00111100FBBBCCCCCC111110. */ -+{ "dexcl1", 0x303C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dexcl1<.f><.cc> b,b,c 00110bbb11111100FBBBCCCCCC0QQQQQ. */ -+{ "dexcl1", 0x30FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dexcl1<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA. */ -+{ "dexcl1", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl1<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110. */ -+{ "dexcl1", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl1<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ. */ -+{ "dexcl1", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dexcl1<.f> a,b,u6 00110bbb01111100FBBBuuuuuuAAAAAA. */ -+{ "dexcl1", 0x307C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl1<.f> 0,b,u6 00110bbb01111100FBBBuuuuuu111110. */ -+{ "dexcl1", 0x307C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl1<.f><.cc> b,b,u6 00110bbb11111100FBBBuuuuuu1QQQQQ. */ -+{ "dexcl1", 0x30FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dexcl1<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS. */ -+{ "dexcl1", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dexcl1<.f> b,b,s12 00110bbb10111100FBBBssssssSSSSSS. */ -+{ "dexcl1", 0x30BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dexcl1<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA. */ -+{ "dexcl1", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dexcl1<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA. */ -+{ "dexcl1", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dexcl1<.f> 0,limm,c 0011011000011000F111CCCCCC111110. */ -+{ "dexcl1", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dexcl1<.f> 0,b,limm 00110bbb00011000FBBB111110111110. */ -+{ "dexcl1", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dexcl1<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ. */ -+{ "dexcl1", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dexcl1<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ. */ -+{ "dexcl1", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dexcl1<.f> a,limm,c 0011011000111100F111CCCCCCAAAAAA. */ -+{ "dexcl1", 0x363C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dexcl1<.f> a,b,limm 00110bbb00111100FBBB111110AAAAAA. */ -+{ "dexcl1", 0x303C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dexcl1<.f> 0,limm,c 0011011000111100F111CCCCCC111110. */ -+{ "dexcl1", 0x363C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dexcl1<.f> 0,b,limm 00110bbb00111100FBBB111110111110. */ -+{ "dexcl1", 0x303C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dexcl1<.f><.cc> 0,limm,c 0011011011111100F111CCCCCC0QQQQQ. */ -+{ "dexcl1", 0x36FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dexcl1<.f><.cc> b,b,limm 00110bbb11111100FBBB1111100QQQQQ. */ -+{ "dexcl1", 0x30FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dexcl1<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA. */ -+{ "dexcl1", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl1<.f> 0,limm,u6 0011011001011000F111uuuuuu111110. */ -+{ "dexcl1", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl1<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ. */ -+{ "dexcl1", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dexcl1<.f> a,limm,u6 0011011001111100F111uuuuuuAAAAAA. */ -+{ "dexcl1", 0x367C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl1<.f> 0,limm,u6 0011011001111100F111uuuuuu111110. */ -+{ "dexcl1", 0x367C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl1<.f><.cc> 0,limm,u6 0011011011111100F111uuuuuu1QQQQQ. */ -+{ "dexcl1", 0x36FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dexcl1<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS. */ -+{ "dexcl1", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dexcl1<.f> 0,limm,s12 0011011010111100F111ssssssSSSSSS. */ -+{ "dexcl1", 0x36BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dexcl1<.f> a,limm,limm 0011011000011000F111111110AAAAAA. */ -+{ "dexcl1", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dexcl1<.f> 0,limm,limm 0011011000011000F111111110111110. */ -+{ "dexcl1", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dexcl1<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ. */ -+{ "dexcl1", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dexcl1<.f> a,limm,limm 0011011000111100F111111110AAAAAA. */ -+{ "dexcl1", 0x363C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dexcl1<.f> 0,limm,limm 0011011000111100F111111110111110. */ -+{ "dexcl1", 0x363C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dexcl1<.f><.cc> 0,limm,limm 0011011011111100F1111111100QQQQQ. */ -+{ "dexcl1", 0x36FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA. */ -+{ "dexcl2", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dexcl2<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110. */ -+{ "dexcl2", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dexcl2<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ. */ -+{ "dexcl2", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> a,b,c 00110bbb00111101FBBBCCCCCCAAAAAA. */ -+{ "dexcl2", 0x303D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dexcl2<.f> 0,b,c 00110bbb00111101FBBBCCCCCC111110. */ -+{ "dexcl2", 0x303D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dexcl2<.f><.cc> b,b,c 00110bbb11111101FBBBCCCCCC0QQQQQ. */ -+{ "dexcl2", 0x30FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA. */ -+{ "dexcl2", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl2<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110. */ -+{ "dexcl2", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl2<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ. */ -+{ "dexcl2", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> a,b,u6 00110bbb01111101FBBBuuuuuuAAAAAA. */ -+{ "dexcl2", 0x307D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl2<.f> 0,b,u6 00110bbb01111101FBBBuuuuuu111110. */ -+{ "dexcl2", 0x307D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl2<.f><.cc> b,b,u6 00110bbb11111101FBBBuuuuuu1QQQQQ. */ -+{ "dexcl2", 0x30FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS. */ -+{ "dexcl2", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dexcl2<.f> b,b,s12 00110bbb10111101FBBBssssssSSSSSS. */ -+{ "dexcl2", 0x30BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dexcl2<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA. */ -+{ "dexcl2", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dexcl2<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA. */ -+{ "dexcl2", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dexcl2<.f> 0,limm,c 0011011000011001F111CCCCCC111110. */ -+{ "dexcl2", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dexcl2<.f> 0,b,limm 00110bbb00011001FBBB111110111110. */ -+{ "dexcl2", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dexcl2<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ. */ -+{ "dexcl2", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dexcl2<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ. */ -+{ "dexcl2", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> a,limm,c 0011011000111101F111CCCCCCAAAAAA. */ -+{ "dexcl2", 0x363D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dexcl2<.f> a,b,limm 00110bbb00111101FBBB111110AAAAAA. */ -+{ "dexcl2", 0x303D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dexcl2<.f> 0,limm,c 0011011000111101F111CCCCCC111110. */ -+{ "dexcl2", 0x363D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dexcl2<.f> 0,b,limm 00110bbb00111101FBBB111110111110. */ -+{ "dexcl2", 0x303D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dexcl2<.f><.cc> 0,limm,c 0011011011111101F111CCCCCC0QQQQQ. */ -+{ "dexcl2", 0x36FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dexcl2<.f><.cc> b,b,limm 00110bbb11111101FBBB1111100QQQQQ. */ -+{ "dexcl2", 0x30FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA. */ -+{ "dexcl2", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl2<.f> 0,limm,u6 0011011001011001F111uuuuuu111110. */ -+{ "dexcl2", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl2<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ. */ -+{ "dexcl2", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> a,limm,u6 0011011001111101F111uuuuuuAAAAAA. */ -+{ "dexcl2", 0x367D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl2<.f> 0,limm,u6 0011011001111101F111uuuuuu111110. */ -+{ "dexcl2", 0x367D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dexcl2<.f><.cc> 0,limm,u6 0011011011111101F111uuuuuu1QQQQQ. */ -+{ "dexcl2", 0x36FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS. */ -+{ "dexcl2", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dexcl2<.f> 0,limm,s12 0011011010111101F111ssssssSSSSSS. */ -+{ "dexcl2", 0x36BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dexcl2<.f> a,limm,limm 0011011000011001F111111110AAAAAA. */ -+{ "dexcl2", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dexcl2<.f> 0,limm,limm 0011011000011001F111111110111110. */ -+{ "dexcl2", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dexcl2<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ. */ -+{ "dexcl2", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dexcl2<.f> a,limm,limm 0011011000111101F111111110AAAAAA. */ -+{ "dexcl2", 0x363D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dexcl2<.f> 0,limm,limm 0011011000111101F111111110111110. */ -+{ "dexcl2", 0x363D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dexcl2<.f><.cc> 0,limm,limm 0011011011111101F1111111100QQQQQ. */ -+{ "dexcl2", 0x36FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA. */ -+{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110. */ -+{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ. */ -+{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA. */ -+{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110. */ -+{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ. */ -+{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS. */ -+{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA. */ -+{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA. */ -+{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110. */ -+{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110. */ -+{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ. */ -+{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ. */ -+{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA. */ -+{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110. */ -+{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ. */ -+{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS. */ -+{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA. */ -+{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* div<.f> 0,limm,limm 0010111000000100F111111110111110. */ -+{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ. */ -+{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* divacc c 00101011001011110000CCCCCC111111. */ -+{ "divacc", 0x2B2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* divacc u6 00101011011011110000uuuuuu111111. */ -+{ "divacc", 0x2B6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* divaw<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */ -+{ "divaw", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divaw<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */ -+{ "divaw", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divaw<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */ -+{ "divaw", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divaw<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */ -+{ "divaw", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divaw<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */ -+{ "divaw", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divaw<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */ -+{ "divaw", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divaw<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */ -+{ "divaw", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divaw<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */ -+{ "divaw", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divaw<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */ -+{ "divaw", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divaw<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */ -+{ "divaw", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divaw<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */ -+{ "divaw", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divaw<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */ -+{ "divaw", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* divaw<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */ -+{ "divaw", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divaw<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */ -+{ "divaw", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divaw<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */ -+{ "divaw", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divaw<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */ -+{ "divaw", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divaw<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */ -+{ "divaw", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divaw<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */ -+{ "divaw", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divaw<.f> 0,limm,limm 0010111000001000F111111110111110. */ -+{ "divaw", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divaw<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */ -+{ "divaw", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* divf<.f><.cc> b,b,c 00110bbb11010000FBBBCCCCCC0QQQQQ */ -+{ "divf", 0x30D00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divf<.f> a,b,c 00110bbb00010000FBBBCCCCCCAAAAAA */ -+{ "divf", 0x30100000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divf<.f> 0,b,c 00110bbb00010000FBBBCCCCCC111110 */ -+{ "divf", 0x3010003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divf<.f> a,b,u6 00110bbb01010000FBBBuuuuuuAAAAAA */ -+{ "divf", 0x30500000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divf<.f> 0,b,u6 00110bbb01010000FBBBuuuuuu111110 */ -+{ "divf", 0x3050003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divf<.f><.cc> b,b,u6 00110bbb11010000FBBBuuuuuu1QQQQQ */ -+{ "divf", 0x30D00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divf<.f> b,b,s12 00110bbb10010000FBBBssssssSSSSSS */ -+{ "divf", 0x30900000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divf<.f> a,b,limm 00110bbb00010000FBBB111110AAAAAA */ -+{ "divf", 0x30100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divf<.f><.cc> b,b,limm 0011011011010000F111CCCCCC0QQQQQ */ -+{ "divf", 0x36D07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* divf<.f><.cc> 0,limm,c 00110bbb11010000FBBB1111100QQQQQ */ -+{ "divf", 0x30D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divf<.f> 0,limm,c 0011011000010000F111CCCCCC111110 */ -+{ "divf", 0x3610703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divf<.f> 0,b,limm 00110bbb00010000FBBB111110111110 */ -+{ "divf", 0x30100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divf<.f> a,limm,c 0011011000010000F111CCCCCCAAAAAA */ -+{ "divf", 0x36107000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divf<.f> 0,limm,u6 0011011001010000F111uuuuuu111110 */ -+{ "divf", 0x3650703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divf<.f> a,limm,u6 0011011001010000F111uuuuuuAAAAAA */ -+{ "divf", 0x36507000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divf<.f><.cc> 0,limm,u6 0011011011010000F111uuuuuu1QQQQQ */ -+{ "divf", 0x36D07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divf<.f> 0,limm,s12 0011011010010000F111ssssssSSSSSS */ -+{ "divf", 0x36907000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divf<.f> 0,limm,limm 0011011000010000F111111110111110 */ -+{ "divf", 0x36107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divf<.f> a,limm,limm 0011011000010000F111111110AAAAAA */ -+{ "divf", 0x36107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divf<.f><.cc> 0,limm,limm 0011011011010000F1111111100QQQQQ */ -+{ "divf", 0x36D07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA. */ -+{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110. */ -+{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ. */ -+{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA. */ -+{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110. */ -+{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ. */ -+{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS. */ -+{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA. */ -+{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f> a,b,limm 00101bbb00000101FBBB111110AAAAAA. */ -+{ "divu", 0x28050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divu<.f> 0,limm,c 0010111000000101F111CCCCCC111110. */ -+{ "divu", 0x2E05703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* divu<.f> 0,b,limm 00101bbb00000101FBBB111110111110. */ -+{ "divu", 0x28050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* divu<.f><.cc> b,b,limm 00101bbb11000101FBBB1111100QQQQQ. */ -+{ "divu", 0x28C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* divu<.f><.cc> 0,limm,c 0010111011000101F111CCCCCC0QQQQQ. */ -+{ "divu", 0x2EC57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* divu<.f> a,limm,u6 0010111001000101F111uuuuuuAAAAAA. */ -+{ "divu", 0x2E457000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f> 0,limm,u6 0010111001000101F111uuuuuu111110. */ -+{ "divu", 0x2E45703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* divu<.f><.cc> 0,limm,u6 0010111011000101F111uuuuuu1QQQQQ. */ -+{ "divu", 0x2EC57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* divu<.f> 0,limm,s12 0010111010000101F111ssssssSSSSSS. */ -+{ "divu", 0x2E857000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* divu<.f> a,limm,limm 0010111000000101F111111110AAAAAA. */ -+{ "divu", 0x2E057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divu<.f> 0,limm,limm 0010111000000101F111111110111110. */ -+{ "divu", 0x2E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* divu<.f><.cc> 0,limm,limm 0010111011000101F1111111100QQQQQ. */ -+{ "divu", 0x2EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmach<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA. */ -+{ "dmach", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmach<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110. */ -+{ "dmach", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmach<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ. */ -+{ "dmach", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmach<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA. */ -+{ "dmach", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmach<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110. */ -+{ "dmach", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmach<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ. */ -+{ "dmach", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmach<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS. */ -+{ "dmach", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmach<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA. */ -+{ "dmach", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmach<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA. */ -+{ "dmach", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmach<.f> 0,limm,c 0010111000010010F111CCCCCC111110. */ -+{ "dmach", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmach<.f> 0,b,limm 00101bbb00010010FBBB111110111110. */ -+{ "dmach", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmach<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ. */ -+{ "dmach", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmach<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ. */ -+{ "dmach", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmach<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA. */ -+{ "dmach", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmach<.f> 0,limm,u6 0010111001010010F111uuuuuu111110. */ -+{ "dmach", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmach<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ. */ -+{ "dmach", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmach<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS. */ -+{ "dmach", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmach<.f> a,limm,limm 0010111000010010F111111110AAAAAA. */ -+{ "dmach", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmach<.f> 0,limm,limm 0010111000010010F111111110111110. */ -+{ "dmach", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmach<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ. */ -+{ "dmach", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA. */ -+{ "dmachbl", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachbl<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110. */ -+{ "dmachbl", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachbl<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ. */ -+{ "dmachbl", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA. */ -+{ "dmachbl", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbl<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110. */ -+{ "dmachbl", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbl<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ. */ -+{ "dmachbl", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS. */ -+{ "dmachbl", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachbl<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA. */ -+{ "dmachbl", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachbl<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA. */ -+{ "dmachbl", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachbl<.f> 0,limm,c 0011011000011000F111CCCCCC111110. */ -+{ "dmachbl", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachbl<.f> 0,b,limm 00110bbb00011000FBBB111110111110. */ -+{ "dmachbl", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachbl<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ. */ -+{ "dmachbl", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachbl<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ. */ -+{ "dmachbl", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA. */ -+{ "dmachbl", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbl<.f> 0,limm,u6 0011011001011000F111uuuuuu111110. */ -+{ "dmachbl", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbl<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ. */ -+{ "dmachbl", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachbl<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS. */ -+{ "dmachbl", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachbl<.f> a,limm,limm 0011011000011000F111111110AAAAAA. */ -+{ "dmachbl", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachbl<.f> 0,limm,limm 0011011000011000F111111110111110. */ -+{ "dmachbl", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachbl<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ. */ -+{ "dmachbl", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA. */ -+{ "dmachbm", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachbm<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110. */ -+{ "dmachbm", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachbm<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ. */ -+{ "dmachbm", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA. */ -+{ "dmachbm", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbm<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110. */ -+{ "dmachbm", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbm<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ. */ -+{ "dmachbm", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS. */ -+{ "dmachbm", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachbm<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA. */ -+{ "dmachbm", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachbm<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA. */ -+{ "dmachbm", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachbm<.f> 0,limm,c 0011011000011001F111CCCCCC111110. */ -+{ "dmachbm", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachbm<.f> 0,b,limm 00110bbb00011001FBBB111110111110. */ -+{ "dmachbm", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachbm<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ. */ -+{ "dmachbm", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachbm<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ. */ -+{ "dmachbm", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA. */ -+{ "dmachbm", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbm<.f> 0,limm,u6 0011011001011001F111uuuuuu111110. */ -+{ "dmachbm", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachbm<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ. */ -+{ "dmachbm", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachbm<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS. */ -+{ "dmachbm", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachbm<.f> a,limm,limm 0011011000011001F111111110AAAAAA. */ -+{ "dmachbm", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachbm<.f> 0,limm,limm 0011011000011001F111111110111110. */ -+{ "dmachbm", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachbm<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ. */ -+{ "dmachbm", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachf<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA. */ -+{ "dmachf", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachf<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110. */ -+{ "dmachf", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachf<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ. */ -+{ "dmachf", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachf<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA. */ -+{ "dmachf", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachf<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110. */ -+{ "dmachf", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachf<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ. */ -+{ "dmachf", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachf<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS. */ -+{ "dmachf", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachf<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA. */ -+{ "dmachf", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachf<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA. */ -+{ "dmachf", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachf<.f> 0,limm,c 0010111001101100F111CCCCCC111110. */ -+{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachf<.f> 0,b,limm 00101bbb00101100FBBB111110111110. */ -+{ "dmachf", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachf<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ. */ -+{ "dmachf", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachf<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ. */ -+{ "dmachf", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachf<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA. */ -+{ "dmachf", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachf<.f> 0,limm,u6 0010111001101100F111uuuuuu111110. */ -+{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachf<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ. */ -+{ "dmachf", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachf<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS. */ -+{ "dmachf", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachf<.f> a,limm,limm 0010111000101100F111111110AAAAAA. */ -+{ "dmachf", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachf<.f> 0,limm,limm 0010111000101100F111111110111110. */ -+{ "dmachf", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachf<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ. */ -+{ "dmachf", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> a,b,c 00101bbb00101101FBBBCCCCCCAAAAAA. */ -+{ "dmachfr", 0x282D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachfr<.f> 0,b,c 00101bbb00101101FBBBCCCCCC111110. */ -+{ "dmachfr", 0x282D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachfr<.f><.cc> b,b,c 00101bbb11101101FBBBCCCCCC0QQQQQ. */ -+{ "dmachfr", 0x28ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> a,b,u6 00101bbb01101101FBBBuuuuuuAAAAAA. */ -+{ "dmachfr", 0x286D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachfr<.f> 0,b,u6 00101bbb01101101FBBBuuuuuu111110. */ -+{ "dmachfr", 0x286D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachfr<.f><.cc> b,b,u6 00101bbb11101101FBBBuuuuuu1QQQQQ. */ -+{ "dmachfr", 0x28ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> b,b,s12 00101bbb10101101FBBBssssssSSSSSS. */ -+{ "dmachfr", 0x28AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachfr<.f> a,limm,c 0010111000101101F111CCCCCCAAAAAA. */ -+{ "dmachfr", 0x2E2D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachfr<.f> a,b,limm 00101bbb00101101FBBB111110AAAAAA. */ -+{ "dmachfr", 0x282D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachfr<.f> 0,limm,c 0010111001101101F111CCCCCC111110. */ -+{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachfr<.f> 0,b,limm 00101bbb00101101FBBB111110111110. */ -+{ "dmachfr", 0x282D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachfr<.f><.cc> b,b,limm 00101bbb11101101FBBB1111100QQQQQ. */ -+{ "dmachfr", 0x28ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachfr<.f><.cc> 0,limm,c 0010111011101101F111CCCCCC0QQQQQ. */ -+{ "dmachfr", 0x2EED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> a,limm,u6 0010111001101101F111uuuuuuAAAAAA. */ -+{ "dmachfr", 0x2E6D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachfr<.f> 0,limm,u6 0010111001101101F111uuuuuu111110. */ -+{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachfr<.f><.cc> 0,limm,u6 0010111011101101F111uuuuuu1QQQQQ. */ -+{ "dmachfr", 0x2EED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachfr<.f> 0,limm,s12 0010111010101101F111ssssssSSSSSS. */ -+{ "dmachfr", 0x2EAD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachfr<.f> a,limm,limm 0010111000101101F111111110AAAAAA. */ -+{ "dmachfr", 0x2E2D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachfr<.f> 0,limm,limm 0010111000101101F111111110111110. */ -+{ "dmachfr", 0x2E2D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachfr<.f><.cc> 0,limm,limm 0010111011101101F1111111100QQQQQ. */ -+{ "dmachfr", 0x2EED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmachu<.f> a,b,c 00101bbb00010011FBBBCCCCCCAAAAAA. */ -+{ "dmachu", 0x28130000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachu<.f> 0,b,c 00101bbb00010011FBBBCCCCCC111110. */ -+{ "dmachu", 0x2813003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmachu<.f><.cc> b,b,c 00101bbb11010011FBBBCCCCCC0QQQQQ. */ -+{ "dmachu", 0x28D30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachu<.f> a,b,u6 00101bbb01010011FBBBuuuuuuAAAAAA. */ -+{ "dmachu", 0x28530000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachu<.f> 0,b,u6 00101bbb01010011FBBBuuuuuu111110. */ -+{ "dmachu", 0x2853003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachu<.f><.cc> b,b,u6 00101bbb11010011FBBBuuuuuu1QQQQQ. */ -+{ "dmachu", 0x28D30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachu<.f> b,b,s12 00101bbb10010011FBBBssssssSSSSSS. */ -+{ "dmachu", 0x28930000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachu<.f> a,limm,c 0010111000010011F111CCCCCCAAAAAA. */ -+{ "dmachu", 0x2E137000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachu<.f> a,b,limm 00101bbb00010011FBBB111110AAAAAA. */ -+{ "dmachu", 0x28130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachu<.f> 0,limm,c 0010111000010011F111CCCCCC111110. */ -+{ "dmachu", 0x2E13703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmachu<.f> 0,b,limm 00101bbb00010011FBBB111110111110. */ -+{ "dmachu", 0x28130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmachu<.f><.cc> b,b,limm 00101bbb11010011FBBB1111100QQQQQ. */ -+{ "dmachu", 0x28D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmachu<.f><.cc> 0,limm,c 0010111011010011F111CCCCCC0QQQQQ. */ -+{ "dmachu", 0x2ED37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmachu<.f> a,limm,u6 0010111001010011F111uuuuuuAAAAAA. */ -+{ "dmachu", 0x2E537000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachu<.f> 0,limm,u6 0010111001010011F111uuuuuu111110. */ -+{ "dmachu", 0x2E53703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmachu<.f><.cc> 0,limm,u6 0010111011010011F111uuuuuu1QQQQQ. */ -+{ "dmachu", 0x2ED37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmachu<.f> 0,limm,s12 0010111010010011F111ssssssSSSSSS. */ -+{ "dmachu", 0x2E937000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmachu<.f> a,limm,limm 0010111000010011F111111110AAAAAA. */ -+{ "dmachu", 0x2E137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachu<.f> 0,limm,limm 0010111000010011F111111110111110. */ -+{ "dmachu", 0x2E137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmachu<.f><.cc> 0,limm,limm 0010111011010011F1111111100QQQQQ. */ -+{ "dmachu", 0x2ED37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmacpf<.f> a,b,c 00101bbb00111011FBBBCCCCCCAAAAAA. */ -+{ "dmacpf", 0x283B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacpf<.f><.cc> b,b,c 00101bbb11111011FBBBCCCCCC0QQQQQ. */ -+{ "dmacpf", 0x28FB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacpf<.f> 0,b,c 00101bbb00111011FBBBCCCCCC111110. */ -+{ "dmacpf", 0x283B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacpf<.f> a,b,limm 00101bbb00111011FBBB111110AAAAAA. */ -+{ "dmacpf", 0x283B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacpf<.f><.cc> b,b,limm 00101bbb11111011FBBB1111100QQQQQ. */ -+{ "dmacpf", 0x28FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA. */ -+{ "dmacwh", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwh<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110. */ -+{ "dmacwh", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwh<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ. */ -+{ "dmacwh", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA. */ -+{ "dmacwh", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwh<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110. */ -+{ "dmacwh", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwh<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ. */ -+{ "dmacwh", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS. */ -+{ "dmacwh", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwh<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA. */ -+{ "dmacwh", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwh<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA. */ -+{ "dmacwh", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwh<.f> 0,limm,c 0010111000110110F111CCCCCC111110. */ -+{ "dmacwh", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwh<.f> 0,b,limm 00101bbb00110110FBBB111110111110. */ -+{ "dmacwh", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwh<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ. */ -+{ "dmacwh", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmacwh<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ. */ -+{ "dmacwh", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA. */ -+{ "dmacwh", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwh<.f> 0,limm,u6 0010111001110110F111uuuuuu111110. */ -+{ "dmacwh", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwh<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ. */ -+{ "dmacwh", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwh<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS. */ -+{ "dmacwh", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwh<.f> a,limm,limm 0010111000110110F111111110AAAAAA. */ -+{ "dmacwh", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwh<.f> 0,limm,limm 0010111000110110F111111110111110. */ -+{ "dmacwh", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwh<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ. */ -+{ "dmacwh", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f><.cc> b,b,c 00110bbb11110111FBBBCCCCCC0QQQQQ */ -+{ "dmacwhf", 0x30F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> a,b,c 00110bbb00110111FBBBCCCCCCAAAAAA */ -+{ "dmacwhf", 0x30370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhf<.f> 0,b,c 00110bbb00110111FBBBCCCCCC111110 */ -+{ "dmacwhf", 0x3037003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> b,b,u6 00110bbb11110111FBBBuuuuuu1QQQQQ */ -+{ "dmacwhf", 0x30F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> a,b,u6 00110bbb01110111FBBBuuuuuuAAAAAA */ -+{ "dmacwhf", 0x30770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhf<.f> 0,b,u6 00110bbb01110111FBBBuuuuuu111110 */ -+{ "dmacwhf", 0x3077003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhf<.f> b,b,s12 00110bbb10110111FBBBssssssSSSSSS */ -+{ "dmacwhf", 0x30B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> 0,limm,c 0011011011110111F111CCCCCC0QQQQQ */ -+{ "dmacwhf", 0x36F77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> 0,b,limm 00110bbb00110111FBBB111110111110 */ -+{ "dmacwhf", 0x30370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> b,b,limm 00110bbb11110111FBBB1111100QQQQQ */ -+{ "dmacwhf", 0x30F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> a,b,limm 00110bbb00110111FBBB111110AAAAAA */ -+{ "dmacwhf", 0x30370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwhf<.f> a,limm,c 0011011000110111F111CCCCCCAAAAAA */ -+{ "dmacwhf", 0x36377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhf<.f> 0,limm,c 0011011000110111F111CCCCCC111110 */ -+{ "dmacwhf", 0x3637703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> 0,limm,u6 0011011011110111F111uuuuuu1QQQQQ */ -+{ "dmacwhf", 0x36F77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> a,limm,u6 0011011001110111F111uuuuuuAAAAAA */ -+{ "dmacwhf", 0x36777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhf<.f> 0,limm,u6 0011011001110111F111uuuuuu111110 */ -+{ "dmacwhf", 0x3677703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhf<.f> 0,limm,s12 0011011010110111F111ssssssSSSSSS */ -+{ "dmacwhf", 0x36B77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwhf<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ */ -+{ "dmacwhf", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmacwhf<.f> 0,limm,limm 0011011000110111F111111110111110 */ -+{ "dmacwhf", 0x36377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwhf<.f> a,limm,limm 0011011000110111F111111110AAAAAA */ -+{ "dmacwhf", 0x36377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwhu<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA. */ -+{ "dmacwhu", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhu<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110. */ -+{ "dmacwhu", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ. */ -+{ "dmacwhu", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA. */ -+{ "dmacwhu", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhu<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110. */ -+{ "dmacwhu", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ. */ -+{ "dmacwhu", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS. */ -+{ "dmacwhu", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwhu<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA. */ -+{ "dmacwhu", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhu<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA. */ -+{ "dmacwhu", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwhu<.f> 0,limm,c 0010111000110111F111CCCCCC111110. */ -+{ "dmacwhu", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmacwhu<.f> 0,b,limm 00101bbb00110111FBBB111110111110. */ -+{ "dmacwhu", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ. */ -+{ "dmacwhu", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ. */ -+{ "dmacwhu", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA. */ -+{ "dmacwhu", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhu<.f> 0,limm,u6 0010111001110111F111uuuuuu111110. */ -+{ "dmacwhu", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ. */ -+{ "dmacwhu", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmacwhu<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS. */ -+{ "dmacwhu", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmacwhu<.f> a,limm,limm 0010111000110111F111111110AAAAAA. */ -+{ "dmacwhu", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwhu<.f> 0,limm,limm 0010111000110111F111111110111110. */ -+{ "dmacwhu", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmacwhu<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ. */ -+{ "dmacwhu", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmb u3 00100011011011110001RRRuuu111111. */ -+{ "dmb", 0x236F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM3_23 }, { 0 }}, -+ -+/* dmb 00100011011011110001RRR000111111. */ -+{ "dmb", 0x236F103F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* dmpyh<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */ -+{ "dmpyh", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyh<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110. */ -+{ "dmpyh", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyh<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ. */ -+{ "dmpyh", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyh<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA. */ -+{ "dmpyh", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyh<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110. */ -+{ "dmpyh", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyh<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ. */ -+{ "dmpyh", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyh<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS. */ -+{ "dmpyh", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyh<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA. */ -+{ "dmpyh", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyh<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA. */ -+{ "dmpyh", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyh<.f> 0,limm,c 0010111000010000F111CCCCCC111110. */ -+{ "dmpyh", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyh<.f> 0,b,limm 00101bbb00010000FBBB111110111110. */ -+{ "dmpyh", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyh<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ. */ -+{ "dmpyh", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyh<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ. */ -+{ "dmpyh", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyh<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA. */ -+{ "dmpyh", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyh<.f> 0,limm,u6 0010111001010000F111uuuuuu111110. */ -+{ "dmpyh", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyh<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ. */ -+{ "dmpyh", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyh<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS. */ -+{ "dmpyh", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyh<.f> a,limm,limm 0010111000010000F111111110AAAAAA. */ -+{ "dmpyh", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyh<.f> 0,limm,limm 0010111000010000F111111110111110. */ -+{ "dmpyh", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyh<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ. */ -+{ "dmpyh", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA. */ -+{ "dmpyhbl", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110. */ -+{ "dmpyhbl", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhbl", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA. */ -+{ "dmpyhbl", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110. */ -+{ "dmpyhbl", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhbl", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS. */ -+{ "dmpyhbl", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhbl<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA. */ -+{ "dmpyhbl", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbl<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA. */ -+{ "dmpyhbl", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,limm,c 0011011000010110F111CCCCCC111110. */ -+{ "dmpyhbl", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,b,limm 00110bbb00010110FBBB111110111110. */ -+{ "dmpyhbl", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ. */ -+{ "dmpyhbl", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ. */ -+{ "dmpyhbl", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA. */ -+{ "dmpyhbl", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,limm,u6 0011011001010110F111uuuuuu111110. */ -+{ "dmpyhbl", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ. */ -+{ "dmpyhbl", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhbl<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS. */ -+{ "dmpyhbl", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhbl<.f> a,limm,limm 0011011000010110F111111110AAAAAA. */ -+{ "dmpyhbl", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhbl<.f> 0,limm,limm 0011011000010110F111111110111110. */ -+{ "dmpyhbl", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhbl<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ. */ -+{ "dmpyhbl", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA. */ -+{ "dmpyhbm", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110. */ -+{ "dmpyhbm", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhbm", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA. */ -+{ "dmpyhbm", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110. */ -+{ "dmpyhbm", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhbm", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS. */ -+{ "dmpyhbm", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhbm<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA. */ -+{ "dmpyhbm", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbm<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA. */ -+{ "dmpyhbm", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,limm,c 0011011000010111F111CCCCCC111110. */ -+{ "dmpyhbm", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,b,limm 00110bbb00010111FBBB111110111110. */ -+{ "dmpyhbm", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ. */ -+{ "dmpyhbm", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ. */ -+{ "dmpyhbm", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA. */ -+{ "dmpyhbm", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,limm,u6 0011011001010111F111uuuuuu111110. */ -+{ "dmpyhbm", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ. */ -+{ "dmpyhbm", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhbm<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS. */ -+{ "dmpyhbm", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhbm<.f> a,limm,limm 0011011000010111F111111110AAAAAA. */ -+{ "dmpyhbm", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhbm<.f> 0,limm,limm 0011011000010111F111111110111110. */ -+{ "dmpyhbm", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhbm<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ. */ -+{ "dmpyhbm", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> a,b,c 00101bbb00101010FBBBCCCCCCAAAAAA. */ -+{ "dmpyhf", 0x282A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhf<.f> 0,b,c 00101bbb00101010FBBBCCCCCC111110. */ -+{ "dmpyhf", 0x282A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> b,b,c 00101bbb11101010FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhf", 0x28EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> a,b,u6 00101bbb01101010FBBBuuuuuuAAAAAA. */ -+{ "dmpyhf", 0x286A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhf<.f> 0,b,u6 00101bbb01101010FBBBuuuuuu111110. */ -+{ "dmpyhf", 0x286A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> b,b,u6 00101bbb11101010FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhf", 0x28EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> b,b,s12 00101bbb10101010FBBBssssssSSSSSS. */ -+{ "dmpyhf", 0x28AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhf<.f> a,limm,c 0010111000101010F111CCCCCCAAAAAA. */ -+{ "dmpyhf", 0x2E2A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhf<.f> a,b,limm 00101bbb00101010FBBB111110AAAAAA. */ -+{ "dmpyhf", 0x282A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhf<.f> 0,limm,c 0010111001101010F111CCCCCC111110. */ -+{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhf<.f> 0,b,limm 00101bbb00101010FBBB111110111110. */ -+{ "dmpyhf", 0x282A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> b,b,limm 00101bbb11101010FBBB1111100QQQQQ. */ -+{ "dmpyhf", 0x28EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f><.cc> 0,limm,c 0010111011101010F111CCCCCC0QQQQQ. */ -+{ "dmpyhf", 0x2EEA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> a,limm,u6 0010111001101010F111uuuuuuAAAAAA. */ -+{ "dmpyhf", 0x2E6A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhf<.f> 0,limm,u6 0010111001101010F111uuuuuu111110. */ -+{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> 0,limm,u6 0010111011101010F111uuuuuu1QQQQQ. */ -+{ "dmpyhf", 0x2EEA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhf<.f> 0,limm,s12 0010111010101010F111ssssssSSSSSS. */ -+{ "dmpyhf", 0x2EAA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhf<.f> a,limm,limm 0010111000101010F111111110AAAAAA. */ -+{ "dmpyhf", 0x2E2A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhf<.f> 0,limm,limm 0010111000101010F111111110111110. */ -+{ "dmpyhf", 0x2E2A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhf<.f><.cc> 0,limm,limm 0010111011101010F1111111100QQQQQ. */ -+{ "dmpyhf", 0x2EEA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA. */ -+{ "dmpyhfr", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110. */ -+{ "dmpyhfr", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhfr", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA. */ -+{ "dmpyhfr", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110. */ -+{ "dmpyhfr", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhfr", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS. */ -+{ "dmpyhfr", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhfr<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA. */ -+{ "dmpyhfr", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhfr<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA. */ -+{ "dmpyhfr", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,limm,c 0010111001101011F111CCCCCC111110. */ -+{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,b,limm 00101bbb00101011FBBB111110111110. */ -+{ "dmpyhfr", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ. */ -+{ "dmpyhfr", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ. */ -+{ "dmpyhfr", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA. */ -+{ "dmpyhfr", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,limm,u6 0010111001101011F111uuuuuu111110. */ -+{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ. */ -+{ "dmpyhfr", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhfr<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS. */ -+{ "dmpyhfr", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhfr<.f> a,limm,limm 0010111000101011F111111110AAAAAA. */ -+{ "dmpyhfr", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhfr<.f> 0,limm,limm 0010111000101011F111111110111110. */ -+{ "dmpyhfr", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhfr<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ. */ -+{ "dmpyhfr", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA. */ -+{ "dmpyhu", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhu<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110. */ -+{ "dmpyhu", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhu", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA. */ -+{ "dmpyhu", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhu<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110. */ -+{ "dmpyhu", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhu", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS. */ -+{ "dmpyhu", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhu<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA. */ -+{ "dmpyhu", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhu<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA. */ -+{ "dmpyhu", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhu<.f> 0,limm,c 0010111000010001F111CCCCCC111110. */ -+{ "dmpyhu", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhu<.f> 0,b,limm 00101bbb00010001FBBB111110111110. */ -+{ "dmpyhu", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ. */ -+{ "dmpyhu", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ. */ -+{ "dmpyhu", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA. */ -+{ "dmpyhu", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhu<.f> 0,limm,u6 0010111001010001F111uuuuuu111110. */ -+{ "dmpyhu", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ. */ -+{ "dmpyhu", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhu<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS. */ -+{ "dmpyhu", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhu<.f> a,limm,limm 0010111000010001F111111110AAAAAA. */ -+{ "dmpyhu", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhu<.f> 0,limm,limm 0010111000010001F111111110111110. */ -+{ "dmpyhu", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhu<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ. */ -+{ "dmpyhu", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA. */ -+{ "dmpyhwf", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110. */ -+{ "dmpyhwf", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ. */ -+{ "dmpyhwf", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA. */ -+{ "dmpyhwf", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110. */ -+{ "dmpyhwf", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ. */ -+{ "dmpyhwf", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS. */ -+{ "dmpyhwf", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhwf<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA. */ -+{ "dmpyhwf", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhwf<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA. */ -+{ "dmpyhwf", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,limm,c 0010111001101000F111CCCCCC111110. */ -+{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,b,limm 00101bbb00101000FBBB111110111110. */ -+{ "dmpyhwf", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ. */ -+{ "dmpyhwf", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ. */ -+{ "dmpyhwf", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA. */ -+{ "dmpyhwf", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,limm,u6 0010111001101000F111uuuuuu111110. */ -+{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ. */ -+{ "dmpyhwf", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpyhwf<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS. */ -+{ "dmpyhwf", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpyhwf<.f> a,limm,limm 0010111000101000F111111110AAAAAA. */ -+{ "dmpyhwf", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhwf<.f> 0,limm,limm 0010111000101000F111111110111110. */ -+{ "dmpyhwf", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpyhwf<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ. */ -+{ "dmpyhwf", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA. */ -+{ "dmpywh", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywh<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110. */ -+{ "dmpywh", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywh<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ. */ -+{ "dmpywh", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA. */ -+{ "dmpywh", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywh<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110. */ -+{ "dmpywh", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywh<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ. */ -+{ "dmpywh", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS. */ -+{ "dmpywh", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywh<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA. */ -+{ "dmpywh", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywh<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA. */ -+{ "dmpywh", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywh<.f> 0,limm,c 0010111000110010F111CCCCCC111110. */ -+{ "dmpywh", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywh<.f> 0,b,limm 00101bbb00110010FBBB111110111110. */ -+{ "dmpywh", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywh<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ. */ -+{ "dmpywh", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpywh<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ. */ -+{ "dmpywh", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA. */ -+{ "dmpywh", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywh<.f> 0,limm,u6 0010111001110010F111uuuuuu111110. */ -+{ "dmpywh", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywh<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ. */ -+{ "dmpywh", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywh<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS. */ -+{ "dmpywh", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywh<.f> a,limm,limm 0010111000110010F111111110AAAAAA. */ -+{ "dmpywh", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywh<.f> 0,limm,limm 0010111000110010F111111110111110. */ -+{ "dmpywh", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywh<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ. */ -+{ "dmpywh", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> 0,b,c 00110bbb00110011FBBBCCCCCC111110 */ -+{ "dmpywhf", 0x3033003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> b,b,c 00110bbb11110011FBBBCCCCCC0QQQQQ */ -+{ "dmpywhf", 0x30F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> a,b,c 00110bbb00110011FBBBCCCCCCAAAAAA */ -+{ "dmpywhf", 0x30330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhf<.f> a,b,u6 00110bbb01110011FBBBuuuuuuAAAAAA */ -+{ "dmpywhf", 0x30730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> b,b,u6 00110bbb11110011FBBBuuuuuu1QQQQQ */ -+{ "dmpywhf", 0x30F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> 0,b,u6 00110bbb01110011FBBBuuuuuu111110 */ -+{ "dmpywhf", 0x3073003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhf<.f> b,b,s12 00110bbb10110011FBBBssssssSSSSSS */ -+{ "dmpywhf", 0x30B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> 0,limm,c 0011011011110011F111CCCCCC0QQQQQ */ -+{ "dmpywhf", 0x36F37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> a,limm,c 0011011000110011F111CCCCCCAAAAAA */ -+{ "dmpywhf", 0x36337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhf<.f> a,b,limm 00110bbb00110011FBBB111110AAAAAA */ -+{ "dmpywhf", 0x30330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywhf<.f> 0,limm,c 0011011000110011F111CCCCCC111110 */ -+{ "dmpywhf", 0x3633703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhf<.f> 0,b,limm 00110bbb00110011FBBB111110111110 */ -+{ "dmpywhf", 0x30330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> b,b,limm 00110bbb11110011FBBB1111100QQQQQ */ -+{ "dmpywhf", 0x30F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f><.cc> 0,limm,u6 0011011011110011F111uuuuuu1QQQQQ */ -+{ "dmpywhf", 0x36F37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywhf<.f> a,limm,u6 0011011001110011F111uuuuuuAAAAAA */ -+{ "dmpywhf", 0x36737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhf<.f> 0,limm,u6 0011011001110011F111uuuuuu111110 */ -+{ "dmpywhf", 0x3673703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhf<.f> 0,limm,s12 0011011010110011F111ssssssSSSSSS */ -+{ "dmpywhf", 0x36B37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywhf<.f> a,limm,limm 0011011000110011F111111110AAAAAA */ -+{ "dmpywhf", 0x36337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywhf<.f> 0,limm,limm 0011011000110011F111111110111110 */ -+{ "dmpywhf", 0x36337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywhf<.f><.cc> 0,limm,limm 0011011011110011F1111111100QQQQQ */ -+{ "dmpywhf", 0x36F37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA. */ -+{ "dmpywhu", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhu<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110. */ -+{ "dmpywhu", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ. */ -+{ "dmpywhu", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA. */ -+{ "dmpywhu", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhu<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110. */ -+{ "dmpywhu", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ. */ -+{ "dmpywhu", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS. */ -+{ "dmpywhu", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywhu<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA. */ -+{ "dmpywhu", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhu<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA. */ -+{ "dmpywhu", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywhu<.f> 0,limm,c 0010111000110011F111CCCCCC111110. */ -+{ "dmpywhu", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmpywhu<.f> 0,b,limm 00101bbb00110011FBBB111110111110. */ -+{ "dmpywhu", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ. */ -+{ "dmpywhu", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ. */ -+{ "dmpywhu", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA. */ -+{ "dmpywhu", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhu<.f> 0,limm,u6 0010111001110011F111uuuuuu111110. */ -+{ "dmpywhu", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ. */ -+{ "dmpywhu", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmpywhu<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS. */ -+{ "dmpywhu", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmpywhu<.f> a,limm,limm 0010111000110011F111111110AAAAAA. */ -+{ "dmpywhu", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywhu<.f> 0,limm,limm 0010111000110011F111111110111110. */ -+{ "dmpywhu", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmpywhu<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ. */ -+{ "dmpywhu", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> a,b,c 00110bbb00001000FBBBCCCCCCAAAAAA. */ -+{ "dmulh11", 0x30080000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh11<.f> 0,b,c 00110bbb00001000FBBBCCCCCC111110. */ -+{ "dmulh11", 0x3008003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh11<.f><.cc> b,b,c 00110bbb11001000FBBBCCCCCC0QQQQQ. */ -+{ "dmulh11", 0x30C80000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> a,b,c 00110bbb00110000FBBBCCCCCCAAAAAA. */ -+{ "dmulh11", 0x30300000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh11<.f> 0,b,c 00110bbb00110000FBBBCCCCCC111110. */ -+{ "dmulh11", 0x3030003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh11<.f><.cc> b,b,c 00110bbb11110000FBBBCCCCCC0QQQQQ. */ -+{ "dmulh11", 0x30F00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> a,b,u6 00110bbb01001000FBBBuuuuuuAAAAAA. */ -+{ "dmulh11", 0x30480000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh11<.f> 0,b,u6 00110bbb01001000FBBBuuuuuu111110. */ -+{ "dmulh11", 0x3048003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh11<.f><.cc> b,b,u6 00110bbb11001000FBBBuuuuuu1QQQQQ. */ -+{ "dmulh11", 0x30C80020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> a,b,u6 00110bbb01110000FBBBuuuuuuAAAAAA. */ -+{ "dmulh11", 0x30700000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh11<.f> 0,b,u6 00110bbb01110000FBBBuuuuuu111110. */ -+{ "dmulh11", 0x3070003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh11<.f><.cc> b,b,u6 00110bbb11110000FBBBuuuuuu1QQQQQ. */ -+{ "dmulh11", 0x30F00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> b,b,s12 00110bbb10001000FBBBssssssSSSSSS. */ -+{ "dmulh11", 0x30880000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh11<.f> b,b,s12 00110bbb10110000FBBBssssssSSSSSS. */ -+{ "dmulh11", 0x30B00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh11<.f> a,limm,c 0011011000001000F111CCCCCCAAAAAA. */ -+{ "dmulh11", 0x36087000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh11<.f> a,b,limm 00110bbb00001000FBBB111110AAAAAA. */ -+{ "dmulh11", 0x30080F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh11<.f> 0,limm,c 0011011000001000F111CCCCCC111110. */ -+{ "dmulh11", 0x3608703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh11<.f> 0,b,limm 00110bbb00001000FBBB111110111110. */ -+{ "dmulh11", 0x30080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh11<.f><.cc> 0,limm,c 0011011011001000F111CCCCCC0QQQQQ. */ -+{ "dmulh11", 0x36C87000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh11<.f><.cc> b,b,limm 00110bbb11001000FBBB1111100QQQQQ. */ -+{ "dmulh11", 0x30C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> a,limm,c 0011011000110000F111CCCCCCAAAAAA. */ -+{ "dmulh11", 0x36307000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh11<.f> a,b,limm 00110bbb00110000FBBB111110AAAAAA. */ -+{ "dmulh11", 0x30300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh11<.f> 0,limm,c 0011011000110000F111CCCCCC111110. */ -+{ "dmulh11", 0x3630703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh11<.f> 0,b,limm 00110bbb00110000FBBB111110111110. */ -+{ "dmulh11", 0x30300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh11<.f><.cc> 0,limm,c 0011011011110000F111CCCCCC0QQQQQ. */ -+{ "dmulh11", 0x36F07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh11<.f><.cc> b,b,limm 00110bbb11110000FBBB1111100QQQQQ. */ -+{ "dmulh11", 0x30F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> a,limm,u6 0011011001001000F111uuuuuuAAAAAA. */ -+{ "dmulh11", 0x36487000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh11<.f> 0,limm,u6 0011011001001000F111uuuuuu111110. */ -+{ "dmulh11", 0x3648703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh11<.f><.cc> 0,limm,u6 0011011011001000F111uuuuuu1QQQQQ. */ -+{ "dmulh11", 0x36C87020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> a,limm,u6 0011011001110000F111uuuuuuAAAAAA. */ -+{ "dmulh11", 0x36707000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh11<.f> 0,limm,u6 0011011001110000F111uuuuuu111110. */ -+{ "dmulh11", 0x3670703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh11<.f><.cc> 0,limm,u6 0011011011110000F111uuuuuu1QQQQQ. */ -+{ "dmulh11", 0x36F07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> 0,limm,s12 0011011010001000F111ssssssSSSSSS. */ -+{ "dmulh11", 0x36887000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh11<.f> 0,limm,s12 0011011010110000F111ssssssSSSSSS. */ -+{ "dmulh11", 0x36B07000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh11<.f> a,limm,limm 0011011000001000F111111110AAAAAA. */ -+{ "dmulh11", 0x36087F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh11<.f> 0,limm,limm 0011011000001000F111111110111110. */ -+{ "dmulh11", 0x36087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh11<.f><.cc> 0,limm,limm 0011011011001000F1111111100QQQQQ. */ -+{ "dmulh11", 0x36C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmulh11<.f> a,limm,limm 0011011000110000F111111110AAAAAA. */ -+{ "dmulh11", 0x36307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh11<.f> 0,limm,limm 0011011000110000F111111110111110. */ -+{ "dmulh11", 0x36307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh11<.f><.cc> 0,limm,limm 0011011011110000F1111111100QQQQQ. */ -+{ "dmulh11", 0x36F07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> a,b,c 00110bbb00001001FBBBCCCCCCAAAAAA. */ -+{ "dmulh12", 0x30090000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh12<.f> 0,b,c 00110bbb00001001FBBBCCCCCC111110. */ -+{ "dmulh12", 0x3009003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh12<.f><.cc> b,b,c 00110bbb11001001FBBBCCCCCC0QQQQQ. */ -+{ "dmulh12", 0x30C90000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> a,b,c 00110bbb00110001FBBBCCCCCCAAAAAA. */ -+{ "dmulh12", 0x30310000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh12<.f> 0,b,c 00110bbb00110001FBBBCCCCCC111110. */ -+{ "dmulh12", 0x3031003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh12<.f><.cc> b,b,c 00110bbb11110001FBBBCCCCCC0QQQQQ. */ -+{ "dmulh12", 0x30F10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> a,b,u6 00110bbb01001001FBBBuuuuuuAAAAAA. */ -+{ "dmulh12", 0x30490000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh12<.f> 0,b,u6 00110bbb01001001FBBBuuuuuu111110. */ -+{ "dmulh12", 0x3049003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh12<.f><.cc> b,b,u6 00110bbb11001001FBBBuuuuuu1QQQQQ. */ -+{ "dmulh12", 0x30C90020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> a,b,u6 00110bbb01110001FBBBuuuuuuAAAAAA. */ -+{ "dmulh12", 0x30710000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh12<.f> 0,b,u6 00110bbb01110001FBBBuuuuuu111110. */ -+{ "dmulh12", 0x3071003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh12<.f><.cc> b,b,u6 00110bbb11110001FBBBuuuuuu1QQQQQ. */ -+{ "dmulh12", 0x30F10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> b,b,s12 00110bbb10001001FBBBssssssSSSSSS. */ -+{ "dmulh12", 0x30890000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh12<.f> b,b,s12 00110bbb10110001FBBBssssssSSSSSS. */ -+{ "dmulh12", 0x30B10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh12<.f> a,limm,c 0011011000001001F111CCCCCCAAAAAA. */ -+{ "dmulh12", 0x36097000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh12<.f> a,b,limm 00110bbb00001001FBBB111110AAAAAA. */ -+{ "dmulh12", 0x30090F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh12<.f> 0,limm,c 0011011000001001F111CCCCCC111110. */ -+{ "dmulh12", 0x3609703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh12<.f> 0,b,limm 00110bbb00001001FBBB111110111110. */ -+{ "dmulh12", 0x30090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh12<.f><.cc> 0,limm,c 0011011011001001F111CCCCCC0QQQQQ. */ -+{ "dmulh12", 0x36C97000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh12<.f><.cc> b,b,limm 00110bbb11001001FBBB1111100QQQQQ. */ -+{ "dmulh12", 0x30C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> a,limm,c 0011011000110001F111CCCCCCAAAAAA. */ -+{ "dmulh12", 0x36317000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh12<.f> a,b,limm 00110bbb00110001FBBB111110AAAAAA. */ -+{ "dmulh12", 0x30310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh12<.f> 0,limm,c 0011011000110001F111CCCCCC111110. */ -+{ "dmulh12", 0x3631703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh12<.f> 0,b,limm 00110bbb00110001FBBB111110111110. */ -+{ "dmulh12", 0x30310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh12<.f><.cc> 0,limm,c 0011011011110001F111CCCCCC0QQQQQ. */ -+{ "dmulh12", 0x36F17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh12<.f><.cc> b,b,limm 00110bbb11110001FBBB1111100QQQQQ. */ -+{ "dmulh12", 0x30F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> a,limm,u6 0011011001001001F111uuuuuuAAAAAA. */ -+{ "dmulh12", 0x36497000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh12<.f> 0,limm,u6 0011011001001001F111uuuuuu111110. */ -+{ "dmulh12", 0x3649703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh12<.f><.cc> 0,limm,u6 0011011011001001F111uuuuuu1QQQQQ. */ -+{ "dmulh12", 0x36C97020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> a,limm,u6 0011011001110001F111uuuuuuAAAAAA. */ -+{ "dmulh12", 0x36717000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh12<.f> 0,limm,u6 0011011001110001F111uuuuuu111110. */ -+{ "dmulh12", 0x3671703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh12<.f><.cc> 0,limm,u6 0011011011110001F111uuuuuu1QQQQQ. */ -+{ "dmulh12", 0x36F17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> 0,limm,s12 0011011010001001F111ssssssSSSSSS. */ -+{ "dmulh12", 0x36897000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh12<.f> 0,limm,s12 0011011010110001F111ssssssSSSSSS. */ -+{ "dmulh12", 0x36B17000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh12<.f> a,limm,limm 0011011000001001F111111110AAAAAA. */ -+{ "dmulh12", 0x36097F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh12<.f> 0,limm,limm 0011011000001001F111111110111110. */ -+{ "dmulh12", 0x36097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh12<.f><.cc> 0,limm,limm 0011011011001001F1111111100QQQQQ. */ -+{ "dmulh12", 0x36C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmulh12<.f> a,limm,limm 0011011000110001F111111110AAAAAA. */ -+{ "dmulh12", 0x36317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh12<.f> 0,limm,limm 0011011000110001F111111110111110. */ -+{ "dmulh12", 0x36317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh12<.f><.cc> 0,limm,limm 0011011011110001F1111111100QQQQQ. */ -+{ "dmulh12", 0x36F17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA. */ -+{ "dmulh21", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh21<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110. */ -+{ "dmulh21", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh21<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ. */ -+{ "dmulh21", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> a,b,c 00110bbb00110010FBBBCCCCCCAAAAAA. */ -+{ "dmulh21", 0x30320000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh21<.f> 0,b,c 00110bbb00110010FBBBCCCCCC111110. */ -+{ "dmulh21", 0x3032003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh21<.f><.cc> b,b,c 00110bbb11110010FBBBCCCCCC0QQQQQ. */ -+{ "dmulh21", 0x30F20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA. */ -+{ "dmulh21", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh21<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110. */ -+{ "dmulh21", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh21<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ. */ -+{ "dmulh21", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> a,b,u6 00110bbb01110010FBBBuuuuuuAAAAAA. */ -+{ "dmulh21", 0x30720000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh21<.f> 0,b,u6 00110bbb01110010FBBBuuuuuu111110. */ -+{ "dmulh21", 0x3072003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh21<.f><.cc> b,b,u6 00110bbb11110010FBBBuuuuuu1QQQQQ. */ -+{ "dmulh21", 0x30F20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS. */ -+{ "dmulh21", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh21<.f> b,b,s12 00110bbb10110010FBBBssssssSSSSSS. */ -+{ "dmulh21", 0x30B20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh21<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA. */ -+{ "dmulh21", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh21<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA. */ -+{ "dmulh21", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh21<.f> 0,limm,c 0011011000001010F111CCCCCC111110. */ -+{ "dmulh21", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh21<.f> 0,b,limm 00110bbb00001010FBBB111110111110. */ -+{ "dmulh21", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh21<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ. */ -+{ "dmulh21", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh21<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ. */ -+{ "dmulh21", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> a,limm,c 0011011000110010F111CCCCCCAAAAAA. */ -+{ "dmulh21", 0x36327000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh21<.f> a,b,limm 00110bbb00110010FBBB111110AAAAAA. */ -+{ "dmulh21", 0x30320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh21<.f> 0,limm,c 0011011000110010F111CCCCCC111110. */ -+{ "dmulh21", 0x3632703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh21<.f> 0,b,limm 00110bbb00110010FBBB111110111110. */ -+{ "dmulh21", 0x30320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh21<.f><.cc> 0,limm,c 0011011011110010F111CCCCCC0QQQQQ. */ -+{ "dmulh21", 0x36F27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh21<.f><.cc> b,b,limm 00110bbb11110010FBBB1111100QQQQQ. */ -+{ "dmulh21", 0x30F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA. */ -+{ "dmulh21", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh21<.f> 0,limm,u6 0011011001001010F111uuuuuu111110. */ -+{ "dmulh21", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh21<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ. */ -+{ "dmulh21", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> a,limm,u6 0011011001110010F111uuuuuuAAAAAA. */ -+{ "dmulh21", 0x36727000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh21<.f> 0,limm,u6 0011011001110010F111uuuuuu111110. */ -+{ "dmulh21", 0x3672703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh21<.f><.cc> 0,limm,u6 0011011011110010F111uuuuuu1QQQQQ. */ -+{ "dmulh21", 0x36F27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS. */ -+{ "dmulh21", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh21<.f> 0,limm,s12 0011011010110010F111ssssssSSSSSS. */ -+{ "dmulh21", 0x36B27000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh21<.f> a,limm,limm 0011011000001010F111111110AAAAAA. */ -+{ "dmulh21", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh21<.f> 0,limm,limm 0011011000001010F111111110111110. */ -+{ "dmulh21", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh21<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ. */ -+{ "dmulh21", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmulh21<.f> a,limm,limm 0011011000110010F111111110AAAAAA. */ -+{ "dmulh21", 0x36327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh21<.f> 0,limm,limm 0011011000110010F111111110111110. */ -+{ "dmulh21", 0x36327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh21<.f><.cc> 0,limm,limm 0011011011110010F1111111100QQQQQ. */ -+{ "dmulh21", 0x36F27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA. */ -+{ "dmulh22", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh22<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110. */ -+{ "dmulh22", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh22<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ. */ -+{ "dmulh22", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> a,b,c 00110bbb00110011FBBBCCCCCCAAAAAA. */ -+{ "dmulh22", 0x30330000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh22<.f> 0,b,c 00110bbb00110011FBBBCCCCCC111110. */ -+{ "dmulh22", 0x3033003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulh22<.f><.cc> b,b,c 00110bbb11110011FBBBCCCCCC0QQQQQ. */ -+{ "dmulh22", 0x30F30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA. */ -+{ "dmulh22", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh22<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110. */ -+{ "dmulh22", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh22<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ. */ -+{ "dmulh22", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> a,b,u6 00110bbb01110011FBBBuuuuuuAAAAAA. */ -+{ "dmulh22", 0x30730000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh22<.f> 0,b,u6 00110bbb01110011FBBBuuuuuu111110. */ -+{ "dmulh22", 0x3073003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh22<.f><.cc> b,b,u6 00110bbb11110011FBBBuuuuuu1QQQQQ. */ -+{ "dmulh22", 0x30F30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS. */ -+{ "dmulh22", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh22<.f> b,b,s12 00110bbb10110011FBBBssssssSSSSSS. */ -+{ "dmulh22", 0x30B30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh22<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA. */ -+{ "dmulh22", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh22<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA. */ -+{ "dmulh22", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh22<.f> 0,limm,c 0011011000001011F111CCCCCC111110. */ -+{ "dmulh22", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh22<.f> 0,b,limm 00110bbb00001011FBBB111110111110. */ -+{ "dmulh22", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh22<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ. */ -+{ "dmulh22", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh22<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ. */ -+{ "dmulh22", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> a,limm,c 0011011000110011F111CCCCCCAAAAAA. */ -+{ "dmulh22", 0x36337000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh22<.f> a,b,limm 00110bbb00110011FBBB111110AAAAAA. */ -+{ "dmulh22", 0x30330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh22<.f> 0,limm,c 0011011000110011F111CCCCCC111110. */ -+{ "dmulh22", 0x3633703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dmulh22<.f> 0,b,limm 00110bbb00110011FBBB111110111110. */ -+{ "dmulh22", 0x30330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulh22<.f><.cc> 0,limm,c 0011011011110011F111CCCCCC0QQQQQ. */ -+{ "dmulh22", 0x36F37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulh22<.f><.cc> b,b,limm 00110bbb11110011FBBB1111100QQQQQ. */ -+{ "dmulh22", 0x30F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA. */ -+{ "dmulh22", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh22<.f> 0,limm,u6 0011011001001011F111uuuuuu111110. */ -+{ "dmulh22", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh22<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ. */ -+{ "dmulh22", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> a,limm,u6 0011011001110011F111uuuuuuAAAAAA. */ -+{ "dmulh22", 0x36737000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh22<.f> 0,limm,u6 0011011001110011F111uuuuuu111110. */ -+{ "dmulh22", 0x3673703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dmulh22<.f><.cc> 0,limm,u6 0011011011110011F111uuuuuu1QQQQQ. */ -+{ "dmulh22", 0x36F37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS. */ -+{ "dmulh22", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh22<.f> 0,limm,s12 0011011010110011F111ssssssSSSSSS. */ -+{ "dmulh22", 0x36B37000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dmulh22<.f> a,limm,limm 0011011000001011F111111110AAAAAA. */ -+{ "dmulh22", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh22<.f> 0,limm,limm 0011011000001011F111111110111110. */ -+{ "dmulh22", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh22<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ. */ -+{ "dmulh22", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmulh22<.f> a,limm,limm 0011011000110011F111111110AAAAAA. */ -+{ "dmulh22", 0x36337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh22<.f> 0,limm,limm 0011011000110011F111111110111110. */ -+{ "dmulh22", 0x36337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dmulh22<.f><.cc> 0,limm,limm 0011011011110011F1111111100QQQQQ. */ -+{ "dmulh22", 0x36F37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dmulpf<.f> a,b,c 00101bbb00111010FBBBCCCCCCAAAAAA. */ -+{ "dmulpf", 0x283A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulpf<.f><.cc> b,b,c 00101bbb11111010FBBBCCCCCC0QQQQQ. */ -+{ "dmulpf", 0x28FA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dmulpf<.f> 0,b,c 00101bbb00111010FBBBCCCCCC111110. */ -+{ "dmulpf", 0x283A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dmulpf<.f> a,b,limm 00101bbb00111010FBBB111110AAAAAA. */ -+{ "dmulpf", 0x283A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dmulpf<.f><.cc> b,b,limm 00101bbb11111010FBBB1111100QQQQQ. */ -+{ "dmulpf", 0x28FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* drsubh11<.f> a,b,c 00110bbb00010100FBBBCCCCCCAAAAAA. */ -+{ "drsubh11", 0x30140000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* drsubh11<.f> 0,b,c 00110bbb00010100FBBBCCCCCC111110. */ -+{ "drsubh11", 0x3014003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* drsubh11<.f><.cc> b,b,c 00110bbb11010100FBBBCCCCCC0QQQQQ. */ -+{ "drsubh11", 0x30D40000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* drsubh11<.f> a,b,u6 00110bbb01010100FBBBuuuuuuAAAAAA. */ -+{ "drsubh11", 0x30540000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh11<.f> 0,b,u6 00110bbb01010100FBBBuuuuuu111110. */ -+{ "drsubh11", 0x3054003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh11<.f><.cc> b,b,u6 00110bbb11010100FBBBuuuuuu1QQQQQ. */ -+{ "drsubh11", 0x30D40020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* drsubh11<.f> b,b,s12 00110bbb10010100FBBBssssssSSSSSS. */ -+{ "drsubh11", 0x30940000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* drsubh11<.f> a,limm,c 0011011000010100F111CCCCCCAAAAAA. */ -+{ "drsubh11", 0x36147000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* drsubh11<.f> a,b,limm 00110bbb00010100FBBB111110AAAAAA. */ -+{ "drsubh11", 0x30140F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* drsubh11<.f> 0,limm,c 0011011000010100F111CCCCCC111110. */ -+{ "drsubh11", 0x3614703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* drsubh11<.f> 0,b,limm 00110bbb00010100FBBB111110111110. */ -+{ "drsubh11", 0x30140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* drsubh11<.f><.cc> 0,limm,c 0011011011010100F111CCCCCC0QQQQQ. */ -+{ "drsubh11", 0x36D47000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* drsubh11<.f><.cc> b,b,limm 00110bbb11010100FBBB1111100QQQQQ. */ -+{ "drsubh11", 0x30D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* drsubh11<.f> a,limm,u6 0011011001010100F111uuuuuuAAAAAA. */ -+{ "drsubh11", 0x36547000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh11<.f> 0,limm,u6 0011011001010100F111uuuuuu111110. */ -+{ "drsubh11", 0x3654703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh11<.f><.cc> 0,limm,u6 0011011011010100F111uuuuuu1QQQQQ. */ -+{ "drsubh11", 0x36D47020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* drsubh11<.f> 0,limm,s12 0011011010010100F111ssssssSSSSSS. */ -+{ "drsubh11", 0x36947000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* drsubh11<.f> a,limm,limm 0011011000010100F111111110AAAAAA. */ -+{ "drsubh11", 0x36147F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* drsubh11<.f> 0,limm,limm 0011011000010100F111111110111110. */ -+{ "drsubh11", 0x36147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* drsubh11<.f><.cc> 0,limm,limm 0011011011010100F1111111100QQQQQ. */ -+{ "drsubh11", 0x36D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* drsubh12<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA. */ -+{ "drsubh12", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* drsubh12<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110. */ -+{ "drsubh12", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* drsubh12<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ. */ -+{ "drsubh12", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* drsubh12<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA. */ -+{ "drsubh12", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh12<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110. */ -+{ "drsubh12", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh12<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ. */ -+{ "drsubh12", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* drsubh12<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS. */ -+{ "drsubh12", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* drsubh12<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA. */ -+{ "drsubh12", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* drsubh12<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA. */ -+{ "drsubh12", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* drsubh12<.f> 0,limm,c 0011011000010101F111CCCCCC111110. */ -+{ "drsubh12", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* drsubh12<.f> 0,b,limm 00110bbb00010101FBBB111110111110. */ -+{ "drsubh12", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* drsubh12<.f><.cc> 0,limm,c 0011011011010101F111CCCCCC0QQQQQ. */ -+{ "drsubh12", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* drsubh12<.f><.cc> b,b,limm 00110bbb11010101FBBB1111100QQQQQ. */ -+{ "drsubh12", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* drsubh12<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA. */ -+{ "drsubh12", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh12<.f> 0,limm,u6 0011011001010101F111uuuuuu111110. */ -+{ "drsubh12", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh12<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ. */ -+{ "drsubh12", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* drsubh12<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS. */ -+{ "drsubh12", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* drsubh12<.f> a,limm,limm 0011011000010101F111111110AAAAAA. */ -+{ "drsubh12", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* drsubh12<.f> 0,limm,limm 0011011000010101F111111110111110. */ -+{ "drsubh12", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* drsubh12<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ. */ -+{ "drsubh12", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* drsubh21<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA. */ -+{ "drsubh21", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* drsubh21<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110. */ -+{ "drsubh21", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* drsubh21<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ. */ -+{ "drsubh21", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* drsubh21<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA. */ -+{ "drsubh21", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh21<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110. */ -+{ "drsubh21", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh21<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ. */ -+{ "drsubh21", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* drsubh21<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS. */ -+{ "drsubh21", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* drsubh21<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA. */ -+{ "drsubh21", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* drsubh21<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA. */ -+{ "drsubh21", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* drsubh21<.f> 0,limm,c 0011011000010110F111CCCCCC111110. */ -+{ "drsubh21", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* drsubh21<.f> 0,b,limm 00110bbb00010110FBBB111110111110. */ -+{ "drsubh21", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* drsubh21<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ. */ -+{ "drsubh21", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* drsubh21<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ. */ -+{ "drsubh21", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* drsubh21<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA. */ -+{ "drsubh21", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh21<.f> 0,limm,u6 0011011001010110F111uuuuuu111110. */ -+{ "drsubh21", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh21<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ. */ -+{ "drsubh21", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* drsubh21<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS. */ -+{ "drsubh21", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* drsubh21<.f> a,limm,limm 0011011000010110F111111110AAAAAA. */ -+{ "drsubh21", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* drsubh21<.f> 0,limm,limm 0011011000010110F111111110111110. */ -+{ "drsubh21", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* drsubh21<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ. */ -+{ "drsubh21", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* drsubh22<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA. */ -+{ "drsubh22", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* drsubh22<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110. */ -+{ "drsubh22", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* drsubh22<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ. */ -+{ "drsubh22", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* drsubh22<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA. */ -+{ "drsubh22", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh22<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110. */ -+{ "drsubh22", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh22<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ. */ -+{ "drsubh22", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* drsubh22<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS. */ -+{ "drsubh22", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* drsubh22<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA. */ -+{ "drsubh22", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* drsubh22<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA. */ -+{ "drsubh22", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* drsubh22<.f> 0,limm,c 0011011000010111F111CCCCCC111110. */ -+{ "drsubh22", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* drsubh22<.f> 0,b,limm 00110bbb00010111FBBB111110111110. */ -+{ "drsubh22", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* drsubh22<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ. */ -+{ "drsubh22", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* drsubh22<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ. */ -+{ "drsubh22", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* drsubh22<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA. */ -+{ "drsubh22", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh22<.f> 0,limm,u6 0011011001010111F111uuuuuu111110. */ -+{ "drsubh22", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* drsubh22<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ. */ -+{ "drsubh22", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* drsubh22<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS. */ -+{ "drsubh22", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* drsubh22<.f> a,limm,limm 0011011000010111F111111110AAAAAA. */ -+{ "drsubh22", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* drsubh22<.f> 0,limm,limm 0011011000010111F111111110111110. */ -+{ "drsubh22", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* drsubh22<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ. */ -+{ "drsubh22", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> a,b,c 00110bbb00010000FBBBCCCCCCAAAAAA. */ -+{ "dsubh11", 0x30100000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh11<.f> 0,b,c 00110bbb00010000FBBBCCCCCC111110. */ -+{ "dsubh11", 0x3010003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh11<.f><.cc> b,b,c 00110bbb11010000FBBBCCCCCC0QQQQQ. */ -+{ "dsubh11", 0x30D00000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> a,b,c 00110bbb00111000FBBBCCCCCCAAAAAA. */ -+{ "dsubh11", 0x30380000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh11<.f> 0,b,c 00110bbb00111000FBBBCCCCCC111110. */ -+{ "dsubh11", 0x3038003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh11<.f><.cc> b,b,c 00110bbb11111000FBBBCCCCCC0QQQQQ. */ -+{ "dsubh11", 0x30F80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> a,b,u6 00110bbb01010000FBBBuuuuuuAAAAAA. */ -+{ "dsubh11", 0x30500000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh11<.f> 0,b,u6 00110bbb01010000FBBBuuuuuu111110. */ -+{ "dsubh11", 0x3050003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh11<.f><.cc> b,b,u6 00110bbb11010000FBBBuuuuuu1QQQQQ. */ -+{ "dsubh11", 0x30D00020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> a,b,u6 00110bbb01111000FBBBuuuuuuAAAAAA. */ -+{ "dsubh11", 0x30780000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh11<.f> 0,b,u6 00110bbb01111000FBBBuuuuuu111110. */ -+{ "dsubh11", 0x3078003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh11<.f><.cc> b,b,u6 00110bbb11111000FBBBuuuuuu1QQQQQ. */ -+{ "dsubh11", 0x30F80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> b,b,s12 00110bbb10010000FBBBssssssSSSSSS. */ -+{ "dsubh11", 0x30900000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh11<.f> b,b,s12 00110bbb10111000FBBBssssssSSSSSS. */ -+{ "dsubh11", 0x30B80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh11<.f> a,limm,c 0011011000010000F111CCCCCCAAAAAA. */ -+{ "dsubh11", 0x36107000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh11<.f> a,b,limm 00110bbb00010000FBBB111110AAAAAA. */ -+{ "dsubh11", 0x30100F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh11<.f> 0,limm,c 0011011000010000F111CCCCCC111110. */ -+{ "dsubh11", 0x3610703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh11<.f> 0,b,limm 00110bbb00010000FBBB111110111110. */ -+{ "dsubh11", 0x30100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh11<.f><.cc> 0,limm,c 0011011011010000F111CCCCCC0QQQQQ. */ -+{ "dsubh11", 0x36D07000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh11<.f><.cc> b,b,limm 00110bbb11010000FBBB1111100QQQQQ. */ -+{ "dsubh11", 0x30D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> a,limm,c 0011011000111000F111CCCCCCAAAAAA. */ -+{ "dsubh11", 0x36387000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh11<.f> a,b,limm 00110bbb00111000FBBB111110AAAAAA. */ -+{ "dsubh11", 0x30380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh11<.f> 0,limm,c 0011011000111000F111CCCCCC111110. */ -+{ "dsubh11", 0x3638703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh11<.f> 0,b,limm 00110bbb00111000FBBB111110111110. */ -+{ "dsubh11", 0x30380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh11<.f><.cc> 0,limm,c 0011011011111000F111CCCCCC0QQQQQ. */ -+{ "dsubh11", 0x36F87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh11<.f><.cc> b,b,limm 00110bbb11111000FBBB1111100QQQQQ. */ -+{ "dsubh11", 0x30F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> a,limm,u6 0011011001010000F111uuuuuuAAAAAA. */ -+{ "dsubh11", 0x36507000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh11<.f> 0,limm,u6 0011011001010000F111uuuuuu111110. */ -+{ "dsubh11", 0x3650703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh11<.f><.cc> 0,limm,u6 0011011011010000F111uuuuuu1QQQQQ. */ -+{ "dsubh11", 0x36D07020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> a,limm,u6 0011011001111000F111uuuuuuAAAAAA. */ -+{ "dsubh11", 0x36787000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh11<.f> 0,limm,u6 0011011001111000F111uuuuuu111110. */ -+{ "dsubh11", 0x3678703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh11<.f><.cc> 0,limm,u6 0011011011111000F111uuuuuu1QQQQQ. */ -+{ "dsubh11", 0x36F87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> 0,limm,s12 0011011010010000F111ssssssSSSSSS. */ -+{ "dsubh11", 0x36907000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh11<.f> 0,limm,s12 0011011010111000F111ssssssSSSSSS. */ -+{ "dsubh11", 0x36B87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh11<.f> a,limm,limm 0011011000010000F111111110AAAAAA. */ -+{ "dsubh11", 0x36107F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh11<.f> 0,limm,limm 0011011000010000F111111110111110. */ -+{ "dsubh11", 0x36107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh11<.f><.cc> 0,limm,limm 0011011011010000F1111111100QQQQQ. */ -+{ "dsubh11", 0x36D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsubh11<.f> a,limm,limm 0011011000111000F111111110AAAAAA. */ -+{ "dsubh11", 0x36387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh11<.f> 0,limm,limm 0011011000111000F111111110111110. */ -+{ "dsubh11", 0x36387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh11<.f><.cc> 0,limm,limm 0011011011111000F1111111100QQQQQ. */ -+{ "dsubh11", 0x36F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> a,b,c 00110bbb00010001FBBBCCCCCCAAAAAA. */ -+{ "dsubh12", 0x30110000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh12<.f> 0,b,c 00110bbb00010001FBBBCCCCCC111110. */ -+{ "dsubh12", 0x3011003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh12<.f><.cc> b,b,c 00110bbb11010001FBBBCCCCCC0QQQQQ. */ -+{ "dsubh12", 0x30D10000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> a,b,c 00110bbb00111001FBBBCCCCCCAAAAAA. */ -+{ "dsubh12", 0x30390000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh12<.f> 0,b,c 00110bbb00111001FBBBCCCCCC111110. */ -+{ "dsubh12", 0x3039003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh12<.f><.cc> b,b,c 00110bbb11111001FBBBCCCCCC0QQQQQ. */ -+{ "dsubh12", 0x30F90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> a,b,u6 00110bbb01010001FBBBuuuuuuAAAAAA. */ -+{ "dsubh12", 0x30510000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh12<.f> 0,b,u6 00110bbb01010001FBBBuuuuuu111110. */ -+{ "dsubh12", 0x3051003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh12<.f><.cc> b,b,u6 00110bbb11010001FBBBuuuuuu1QQQQQ. */ -+{ "dsubh12", 0x30D10020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> a,b,u6 00110bbb01111001FBBBuuuuuuAAAAAA. */ -+{ "dsubh12", 0x30790000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh12<.f> 0,b,u6 00110bbb01111001FBBBuuuuuu111110. */ -+{ "dsubh12", 0x3079003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh12<.f><.cc> b,b,u6 00110bbb11111001FBBBuuuuuu1QQQQQ. */ -+{ "dsubh12", 0x30F90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> b,b,s12 00110bbb10010001FBBBssssssSSSSSS. */ -+{ "dsubh12", 0x30910000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh12<.f> b,b,s12 00110bbb10111001FBBBssssssSSSSSS. */ -+{ "dsubh12", 0x30B90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh12<.f> a,limm,c 0011011000010001F111CCCCCCAAAAAA. */ -+{ "dsubh12", 0x36117000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh12<.f> a,b,limm 00110bbb00010001FBBB111110AAAAAA. */ -+{ "dsubh12", 0x30110F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh12<.f> 0,limm,c 0011011000010001F111CCCCCC111110. */ -+{ "dsubh12", 0x3611703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh12<.f> 0,b,limm 00110bbb00010001FBBB111110111110. */ -+{ "dsubh12", 0x30110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh12<.f><.cc> 0,limm,c 0011011011010001F111CCCCCC0QQQQQ. */ -+{ "dsubh12", 0x36D17000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh12<.f><.cc> b,b,limm 00110bbb11010001FBBB1111100QQQQQ. */ -+{ "dsubh12", 0x30D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> a,limm,c 0011011000111001F111CCCCCCAAAAAA. */ -+{ "dsubh12", 0x36397000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh12<.f> a,b,limm 00110bbb00111001FBBB111110AAAAAA. */ -+{ "dsubh12", 0x30390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh12<.f> 0,limm,c 0011011000111001F111CCCCCC111110. */ -+{ "dsubh12", 0x3639703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh12<.f> 0,b,limm 00110bbb00111001FBBB111110111110. */ -+{ "dsubh12", 0x30390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh12<.f><.cc> 0,limm,c 0011011011111001F111CCCCCC0QQQQQ. */ -+{ "dsubh12", 0x36F97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh12<.f><.cc> b,b,limm 00110bbb11111001FBBB1111100QQQQQ. */ -+{ "dsubh12", 0x30F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> a,limm,u6 0011011001010001F111uuuuuuAAAAAA. */ -+{ "dsubh12", 0x36517000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh12<.f> 0,limm,u6 0011011001010001F111uuuuuu111110. */ -+{ "dsubh12", 0x3651703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh12<.f><.cc> 0,limm,u6 0011011011010001F111uuuuuu1QQQQQ. */ -+{ "dsubh12", 0x36D17020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> a,limm,u6 0011011001111001F111uuuuuuAAAAAA. */ -+{ "dsubh12", 0x36797000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh12<.f> 0,limm,u6 0011011001111001F111uuuuuu111110. */ -+{ "dsubh12", 0x3679703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh12<.f><.cc> 0,limm,u6 0011011011111001F111uuuuuu1QQQQQ. */ -+{ "dsubh12", 0x36F97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> 0,limm,s12 0011011010010001F111ssssssSSSSSS. */ -+{ "dsubh12", 0x36917000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh12<.f> 0,limm,s12 0011011010111001F111ssssssSSSSSS. */ -+{ "dsubh12", 0x36B97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh12<.f> a,limm,limm 0011011000010001F111111110AAAAAA. */ -+{ "dsubh12", 0x36117F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh12<.f> 0,limm,limm 0011011000010001F111111110111110. */ -+{ "dsubh12", 0x36117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh12<.f><.cc> 0,limm,limm 0011011011010001F1111111100QQQQQ. */ -+{ "dsubh12", 0x36D17F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsubh12<.f> a,limm,limm 0011011000111001F111111110AAAAAA. */ -+{ "dsubh12", 0x36397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh12<.f> 0,limm,limm 0011011000111001F111111110111110. */ -+{ "dsubh12", 0x36397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh12<.f><.cc> 0,limm,limm 0011011011111001F1111111100QQQQQ. */ -+{ "dsubh12", 0x36F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA. */ -+{ "dsubh21", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh21<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110. */ -+{ "dsubh21", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh21<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ. */ -+{ "dsubh21", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> a,b,c 00110bbb00111010FBBBCCCCCCAAAAAA. */ -+{ "dsubh21", 0x303A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh21<.f> 0,b,c 00110bbb00111010FBBBCCCCCC111110. */ -+{ "dsubh21", 0x303A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh21<.f><.cc> b,b,c 00110bbb11111010FBBBCCCCCC0QQQQQ. */ -+{ "dsubh21", 0x30FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA. */ -+{ "dsubh21", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh21<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110. */ -+{ "dsubh21", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh21<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ. */ -+{ "dsubh21", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> a,b,u6 00110bbb01111010FBBBuuuuuuAAAAAA. */ -+{ "dsubh21", 0x307A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh21<.f> 0,b,u6 00110bbb01111010FBBBuuuuuu111110. */ -+{ "dsubh21", 0x307A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh21<.f><.cc> b,b,u6 00110bbb11111010FBBBuuuuuu1QQQQQ. */ -+{ "dsubh21", 0x30FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS. */ -+{ "dsubh21", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh21<.f> b,b,s12 00110bbb10111010FBBBssssssSSSSSS. */ -+{ "dsubh21", 0x30BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh21<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA. */ -+{ "dsubh21", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh21<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA. */ -+{ "dsubh21", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh21<.f> 0,limm,c 0011011000010010F111CCCCCC111110. */ -+{ "dsubh21", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh21<.f> 0,b,limm 00110bbb00010010FBBB111110111110. */ -+{ "dsubh21", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh21<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ. */ -+{ "dsubh21", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh21<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ. */ -+{ "dsubh21", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> a,limm,c 0011011000111010F111CCCCCCAAAAAA. */ -+{ "dsubh21", 0x363A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh21<.f> a,b,limm 00110bbb00111010FBBB111110AAAAAA. */ -+{ "dsubh21", 0x303A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh21<.f> 0,limm,c 0011011000111010F111CCCCCC111110. */ -+{ "dsubh21", 0x363A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh21<.f> 0,b,limm 00110bbb00111010FBBB111110111110. */ -+{ "dsubh21", 0x303A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh21<.f><.cc> 0,limm,c 0011011011111010F111CCCCCC0QQQQQ. */ -+{ "dsubh21", 0x36FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh21<.f><.cc> b,b,limm 00110bbb11111010FBBB1111100QQQQQ. */ -+{ "dsubh21", 0x30FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA. */ -+{ "dsubh21", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh21<.f> 0,limm,u6 0011011001010010F111uuuuuu111110. */ -+{ "dsubh21", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh21<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ. */ -+{ "dsubh21", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> a,limm,u6 0011011001111010F111uuuuuuAAAAAA. */ -+{ "dsubh21", 0x367A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh21<.f> 0,limm,u6 0011011001111010F111uuuuuu111110. */ -+{ "dsubh21", 0x367A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh21<.f><.cc> 0,limm,u6 0011011011111010F111uuuuuu1QQQQQ. */ -+{ "dsubh21", 0x36FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS. */ -+{ "dsubh21", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh21<.f> 0,limm,s12 0011011010111010F111ssssssSSSSSS. */ -+{ "dsubh21", 0x36BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh21<.f> a,limm,limm 0011011000010010F111111110AAAAAA. */ -+{ "dsubh21", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh21<.f> 0,limm,limm 0011011000010010F111111110111110. */ -+{ "dsubh21", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh21<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ. */ -+{ "dsubh21", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsubh21<.f> a,limm,limm 0011011000111010F111111110AAAAAA. */ -+{ "dsubh21", 0x363A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh21<.f> 0,limm,limm 0011011000111010F111111110111110. */ -+{ "dsubh21", 0x363A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh21<.f><.cc> 0,limm,limm 0011011011111010F1111111100QQQQQ. */ -+{ "dsubh21", 0x36FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA. */ -+{ "dsubh22", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh22<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110. */ -+{ "dsubh22", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh22<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ. */ -+{ "dsubh22", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> a,b,c 00110bbb00111011FBBBCCCCCCAAAAAA. */ -+{ "dsubh22", 0x303B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh22<.f> 0,b,c 00110bbb00111011FBBBCCCCCC111110. */ -+{ "dsubh22", 0x303B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* dsubh22<.f><.cc> b,b,c 00110bbb11111011FBBBCCCCCC0QQQQQ. */ -+{ "dsubh22", 0x30FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA. */ -+{ "dsubh22", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh22<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110. */ -+{ "dsubh22", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh22<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ. */ -+{ "dsubh22", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> a,b,u6 00110bbb01111011FBBBuuuuuuAAAAAA. */ -+{ "dsubh22", 0x307B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh22<.f> 0,b,u6 00110bbb01111011FBBBuuuuuu111110. */ -+{ "dsubh22", 0x307B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh22<.f><.cc> b,b,u6 00110bbb11111011FBBBuuuuuu1QQQQQ. */ -+{ "dsubh22", 0x30FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS. */ -+{ "dsubh22", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh22<.f> b,b,s12 00110bbb10111011FBBBssssssSSSSSS. */ -+{ "dsubh22", 0x30BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh22<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA. */ -+{ "dsubh22", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh22<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA. */ -+{ "dsubh22", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh22<.f> 0,limm,c 0011011000010011F111CCCCCC111110. */ -+{ "dsubh22", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh22<.f> 0,b,limm 00110bbb00010011FBBB111110111110. */ -+{ "dsubh22", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh22<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ. */ -+{ "dsubh22", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh22<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ. */ -+{ "dsubh22", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> a,limm,c 0011011000111011F111CCCCCCAAAAAA. */ -+{ "dsubh22", 0x363B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh22<.f> a,b,limm 00110bbb00111011FBBB111110AAAAAA. */ -+{ "dsubh22", 0x303B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh22<.f> 0,limm,c 0011011000111011F111CCCCCC111110. */ -+{ "dsubh22", 0x363B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* dsubh22<.f> 0,b,limm 00110bbb00111011FBBB111110111110. */ -+{ "dsubh22", 0x303B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* dsubh22<.f><.cc> 0,limm,c 0011011011111011F111CCCCCC0QQQQQ. */ -+{ "dsubh22", 0x36FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* dsubh22<.f><.cc> b,b,limm 00110bbb11111011FBBB1111100QQQQQ. */ -+{ "dsubh22", 0x30FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA. */ -+{ "dsubh22", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh22<.f> 0,limm,u6 0011011001010011F111uuuuuu111110. */ -+{ "dsubh22", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh22<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ. */ -+{ "dsubh22", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> a,limm,u6 0011011001111011F111uuuuuuAAAAAA. */ -+{ "dsubh22", 0x367B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh22<.f> 0,limm,u6 0011011001111011F111uuuuuu111110. */ -+{ "dsubh22", 0x367B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* dsubh22<.f><.cc> 0,limm,u6 0011011011111011F111uuuuuu1QQQQQ. */ -+{ "dsubh22", 0x36FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS. */ -+{ "dsubh22", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh22<.f> 0,limm,s12 0011011010111011F111ssssssSSSSSS. */ -+{ "dsubh22", 0x36BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* dsubh22<.f> a,limm,limm 0011011000010011F111111110AAAAAA. */ -+{ "dsubh22", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh22<.f> 0,limm,limm 0011011000010011F111111110111110. */ -+{ "dsubh22", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh22<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ. */ -+{ "dsubh22", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsubh22<.f> a,limm,limm 0011011000111011F111111110AAAAAA. */ -+{ "dsubh22", 0x363B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh22<.f> 0,limm,limm 0011011000111011F111111110111110. */ -+{ "dsubh22", 0x363B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* dsubh22<.f><.cc> 0,limm,limm 0011011011111011F1111111100QQQQQ. */ -+{ "dsubh22", 0x36FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* dsync 00100010011011110001RRRRRR111111. */ -+{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* ei_s u10 010111uuuuuuuuuu. */ -+{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, EI, CD2, { OPERAND_UIMM10_6_S }, { 0 }}, -+ -+/* enter_s u6 110000UU111uuuu0. */ -+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { OPERAND_UIMM6_11_S }, { 0 }}, -+ -+/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */ -+{ "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> b,u6 00100bbb01101111DBBBuuuuuu001100. */ -+{ "ex", 0x206F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> b,limm 00100bbb00101111DBBB111110001100. */ -+{ "ex", 0x202F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> limm,c 0010011000101111D111CCCCCC001100. */ -+{ "ex", 0x262F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> limm,u6 0010011001101111D111uuuuuu001100. */ -+{ "ex", 0x266F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* ex<.di> limm,limm 0010011000101111D111111110001100. */ -+{ "ex", 0x262F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* extb<.f> b,c 00100bbb00101111FBBBCCCCCC000111. */ -+{ "extb", 0x202F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* extb<.f> 0,c 0010011000101111F111CCCCCC000111. */ -+{ "extb", 0x262F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* extb<.f> b,u6 00100bbb01101111FBBBuuuuuu000111. */ -+{ "extb", 0x206F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* extb<.f> 0,u6 0010011001101111F111uuuuuu000111. */ -+{ "extb", 0x266F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* extb<.f> b,limm 00100bbb00101111FBBB111110000111. */ -+{ "extb", 0x202F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* extb<.f> 0,limm 0010011000101111F111111110000111. */ -+{ "extb", 0x262F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* extb_s b,c 01111bbbccc01111. */ -+{ "extb_s", 0x0000780F, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* exth<.f> b,c 00100bbb00101111FBBBCCCCCC001000. */ -+{ "exth", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* exth<.f> 0,c 0010011000101111F111CCCCCC001000. */ -+{ "exth", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* exth<.f> b,u6 00100bbb01101111FBBBuuuuuu001000. */ -+{ "exth", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* exth<.f> 0,u6 0010011001101111F111uuuuuu001000. */ -+{ "exth", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* exth<.f> b,limm 00100bbb00101111FBBB111110001000. */ -+{ "exth", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* exth<.f> 0,limm 0010011000101111F111111110001000. */ -+{ "exth", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* exth_s b,c 01111bbbccc10000. */ -+{ "exth_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* extw<.f> b,c 00100bbb00101111FBBBCCCCCC001000. */ -+{ "extw", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* extw<.f> 0,c 0010011000101111F111CCCCCC001000. */ -+{ "extw", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* extw<.f> b,u6 00100bbb01101111FBBBuuuuuu001000. */ -+{ "extw", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* extw<.f> 0,u6 0010011001101111F111uuuuuu001000. */ -+{ "extw", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* extw<.f> b,limm 00100bbb00101111FBBB111110001000. */ -+{ "extw", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* extw<.f> 0,limm 0010011000101111F111111110001000. */ -+{ "extw", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* extw_s b,c 01111bbbccc10000. */ -+{ "extw_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* fadd<.f> a,b,c 00110bbb00000001FBBBCCCCCCAAAAAA. */ -+{ "fadd", 0x30010000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fadd<.f> 0,b,c 00110bbb00000001FBBBCCCCCC111110. */ -+{ "fadd", 0x3001003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fadd<.f><.cc> b,b,c 00110bbb11000001FBBBCCCCCC0QQQQQ. */ -+{ "fadd", 0x30C10000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fadd<.f> a,b,u6 00110bbb01000001FBBBuuuuuuAAAAAA. */ -+{ "fadd", 0x30410000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fadd<.f> 0,b,u6 00110bbb01000001FBBBuuuuuu111110. */ -+{ "fadd", 0x3041003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fadd<.f><.cc> b,b,u6 00110bbb11000001FBBBuuuuuu1QQQQQ. */ -+{ "fadd", 0x30C10020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fadd<.f> b,b,s12 00110bbb10000001FBBBssssssSSSSSS. */ -+{ "fadd", 0x30810000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fadd<.f> a,limm,c 0011011000000001F111CCCCCCAAAAAA. */ -+{ "fadd", 0x36017000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fadd<.f> a,b,limm 00110bbb00000001FBBB111110AAAAAA. */ -+{ "fadd", 0x30010F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fadd<.f> 0,limm,c 0011011000000001F111CCCCCC111110. */ -+{ "fadd", 0x3601703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fadd<.f> 0,b,limm 00110bbb00000001FBBB111110111110. */ -+{ "fadd", 0x30010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fadd<.f><.cc> 0,limm,c 0011011011000001F111CCCCCC0QQQQQ. */ -+{ "fadd", 0x36C17000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fadd<.f><.cc> b,b,limm 00110bbb11000001FBBB1111100QQQQQ. */ -+{ "fadd", 0x30C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* fadd<.f> a,limm,u6 0011011001000001F111uuuuuuAAAAAA. */ -+{ "fadd", 0x36417000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fadd<.f> 0,limm,u6 0011011001000001F111uuuuuu111110. */ -+{ "fadd", 0x3641703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fadd<.f><.cc> 0,limm,u6 0011011011000001F111uuuuuu1QQQQQ. */ -+{ "fadd", 0x36C17020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fadd<.f> 0,limm,s12 0011011010000001F111ssssssSSSSSS. */ -+{ "fadd", 0x36817000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fadd<.f> a,limm,limm 0011011000000001F111111110AAAAAA. */ -+{ "fadd", 0x36017F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fadd<.f> 0,limm,limm 0011011000000001F111111110111110. */ -+{ "fadd", 0x36017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fadd<.f><.cc> 0,limm,limm 0011011011000001F1111111100QQQQQ. */ -+{ "fadd", 0x36C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* fbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001011. */ -+{ "fbfdw", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* fbfdw<.f> 0,c 0010111000101111F111CCCCCC001011. */ -+{ "fbfdw", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001011. */ -+{ "fbfdw", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fbfdw<.f> 0,u6 0010111001101111F111uuuuuu001011. */ -+{ "fbfdw", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fbfdw<.f> b,limm 00101bbb00101111FBBB111110001011. */ -+{ "fbfdw", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* fbfdw<.f> 0,limm 0010111000101111F111111110001011. */ -+{ "fbfdw", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fcvt32 a,b,c 00110bbb000010000BBBCCCCCCAAAAAA. */ -+{ "fcvt32", 0x30080000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fcvt32 0,b,c 00110bbb000010000BBBCCCCCC111110. */ -+{ "fcvt32", 0x3008003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fcvt32<.cc> b,b,c 00110bbb110010000BBBCCCCCC0QQQQQ. */ -+{ "fcvt32", 0x30C80000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fcvt32 a,b,u6 00110bbb010010000BBBuuuuuuAAAAAA. */ -+{ "fcvt32", 0x30480000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt32 0,b,u6 00110bbb010010000BBBuuuuuu111110. */ -+{ "fcvt32", 0x3048003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt32<.cc> b,b,u6 00110bbb110010000BBBuuuuuu1QQQQQ. */ -+{ "fcvt32", 0x30C80020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fcvt32 b,b,s12 00110bbb100010000BBBssssssSSSSSS. */ -+{ "fcvt32", 0x30880000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fcvt32 a,limm,c 00110110000010000111CCCCCCAAAAAA. */ -+{ "fcvt32", 0x36087000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fcvt32 a,b,limm 00110bbb000010000BBB111110AAAAAA. */ -+{ "fcvt32", 0x30080F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fcvt32 0,limm,c 00110110000010000111CCCCCC111110. */ -+{ "fcvt32", 0x3608703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fcvt32 0,b,limm 00110bbb000010000BBB111110111110. */ -+{ "fcvt32", 0x30080FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fcvt32<.cc> b,b,limm 00110bbb110010000BBB1111100QQQQQ. */ -+{ "fcvt32", 0x30C80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fcvt32<.cc> 0,limm,c 00110110110010000111CCCCCC0QQQQQ. */ -+{ "fcvt32", 0x36C87000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fcvt32 a,limm,u6 00110110010010000111uuuuuuAAAAAA. */ -+{ "fcvt32", 0x36487000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt32 0,limm,u6 00110110010010000111uuuuuu111110. */ -+{ "fcvt32", 0x3648703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt32<.cc> 0,limm,u6 00110110110010000111uuuuuu1QQQQQ. */ -+{ "fcvt32", 0x36C87020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fcvt32 0,limm,s12 00110110100010000111ssssssSSSSSS. */ -+{ "fcvt32", 0x36887000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fcvt32 a,limm,limm 00110110000010000111111110AAAAAA. */ -+{ "fcvt32", 0x36087F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fcvt32 0,limm,limm 00110110000010000111111110111110. */ -+{ "fcvt32", 0x36087FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fcvt32<.cc> 0,limm,limm 001101101100100001111111100QQQQQ. */ -+{ "fcvt32", 0x36C87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fcvt32_64 a,b,c 00110bbb000010010BBBCCCCCCAAAAAA. */ -+{ "fcvt32_64", 0x30090000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fcvt32_64 0,b,c 00110bbb000010010BBBCCCCCC111110. */ -+{ "fcvt32_64", 0x3009003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fcvt32_64<.cc> b,b,c 00110bbb110010010BBBCCCCCC0QQQQQ. */ -+{ "fcvt32_64", 0x30C90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fcvt32_64 a,b,u6 00110bbb010010010BBBuuuuuuAAAAAA. */ -+{ "fcvt32_64", 0x30490000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt32_64 0,b,u6 00110bbb010010010BBBuuuuuu111110. */ -+{ "fcvt32_64", 0x3049003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt32_64<.cc> b,b,u6 00110bbb110010010BBBuuuuuu1QQQQQ. */ -+{ "fcvt32_64", 0x30C90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fcvt32_64 b,b,s12 00110bbb100010010BBBssssssSSSSSS. */ -+{ "fcvt32_64", 0x30890000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fcvt32_64 a,limm,c 00110110000010010111CCCCCCAAAAAA. */ -+{ "fcvt32_64", 0x36097000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fcvt32_64 a,b,limm 00110bbb000010010BBB111110AAAAAA. */ -+{ "fcvt32_64", 0x30090F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fcvt32_64 0,limm,c 00110110000010010111CCCCCC111110. */ -+{ "fcvt32_64", 0x3609703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fcvt32_64 0,b,limm 00110bbb000010010BBB111110111110. */ -+{ "fcvt32_64", 0x30090FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fcvt32_64<.cc> b,b,limm 00110bbb110010010BBB1111100QQQQQ. */ -+{ "fcvt32_64", 0x30C90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fcvt32_64<.cc> 0,limm,c 00110110110010010111CCCCCC0QQQQQ. */ -+{ "fcvt32_64", 0x36C97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fcvt32_64 a,limm,u6 00110110010010010111uuuuuuAAAAAA. */ -+{ "fcvt32_64", 0x36497000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt32_64 0,limm,u6 00110110010010010111uuuuuu111110. */ -+{ "fcvt32_64", 0x3649703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt32_64<.cc> 0,limm,u6 00110110110010010111uuuuuu1QQQQQ. */ -+{ "fcvt32_64", 0x36C97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fcvt32_64 0,limm,s12 00110110100010010111ssssssSSSSSS. */ -+{ "fcvt32_64", 0x36897000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fcvt32_64 a,limm,limm 00110110000010010111111110AAAAAA. */ -+{ "fcvt32_64", 0x36097F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fcvt32_64 0,limm,limm 00110110000010010111111110111110. */ -+{ "fcvt32_64", 0x36097FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fcvt32_64<.cc> 0,limm,limm 001101101100100101111111100QQQQQ. */ -+{ "fcvt32_64", 0x36C97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fcvt64 a,b,c 00110bbb001110000BBBCCCCCCAAAAAA. */ -+{ "fcvt64", 0x30380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fcvt64 0,b,c 00110bbb001110000BBBCCCCCC111110. */ -+{ "fcvt64", 0x3038003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fcvt64<.cc> b,b,c 00110bbb111110000BBBCCCCCC0QQQQQ. */ -+{ "fcvt64", 0x30F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fcvt64 a,b,u6 00110bbb011110000BBBuuuuuuAAAAAA. */ -+{ "fcvt64", 0x30780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt64 0,b,u6 00110bbb011110000BBBuuuuuu111110. */ -+{ "fcvt64", 0x3078003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt64<.cc> b,b,u6 00110bbb111110000BBBuuuuuu1QQQQQ. */ -+{ "fcvt64", 0x30F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fcvt64 b,b,s12 00110bbb101110000BBBssssssSSSSSS. */ -+{ "fcvt64", 0x30B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fcvt64 a,limm,c 00110110001110000111CCCCCCAAAAAA. */ -+{ "fcvt64", 0x36387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fcvt64 a,b,limm 00110bbb001110000BBB111110AAAAAA. */ -+{ "fcvt64", 0x30380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fcvt64 0,limm,c 00110110001110000111CCCCCC111110. */ -+{ "fcvt64", 0x3638703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fcvt64 0,b,limm 00110bbb001110000BBB111110111110. */ -+{ "fcvt64", 0x30380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fcvt64<.cc> b,b,limm 00110bbb111110000BBB1111100QQQQQ. */ -+{ "fcvt64", 0x30F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fcvt64<.cc> 0,limm,c 00110110111110000111CCCCCC0QQQQQ. */ -+{ "fcvt64", 0x36F87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fcvt64 a,limm,u6 00110110011110000111uuuuuuAAAAAA. */ -+{ "fcvt64", 0x36787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt64 0,limm,u6 00110110011110000111uuuuuu111110. */ -+{ "fcvt64", 0x3678703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt64<.cc> 0,limm,u6 00110110111110000111uuuuuu1QQQQQ. */ -+{ "fcvt64", 0x36F87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fcvt64 0,limm,s12 00110110101110000111ssssssSSSSSS. */ -+{ "fcvt64", 0x36B87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fcvt64 a,limm,limm 00110110001110000111111110AAAAAA. */ -+{ "fcvt64", 0x36387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fcvt64 0,limm,limm 00110110001110000111111110111110. */ -+{ "fcvt64", 0x36387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fcvt64<.cc> 0,limm,limm 001101101111100001111111100QQQQQ. */ -+{ "fcvt64", 0x36F87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fcvt64_32 a,b,c 00110bbb001110010BBBCCCCCCAAAAAA. */ -+{ "fcvt64_32", 0x30390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fcvt64_32 0,b,c 00110bbb001110010BBBCCCCCC111110. */ -+{ "fcvt64_32", 0x3039003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fcvt64_32<.cc> b,b,c 00110bbb111110010BBBCCCCCC0QQQQQ. */ -+{ "fcvt64_32", 0x30F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fcvt64_32 a,b,u6 00110bbb011110010BBBuuuuuuAAAAAA. */ -+{ "fcvt64_32", 0x30790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt64_32 0,b,u6 00110bbb011110010BBBuuuuuu111110. */ -+{ "fcvt64_32", 0x3079003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt64_32<.cc> b,b,u6 00110bbb111110010BBBuuuuuu1QQQQQ. */ -+{ "fcvt64_32", 0x30F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fcvt64_32 b,b,s12 00110bbb101110010BBBssssssSSSSSS. */ -+{ "fcvt64_32", 0x30B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fcvt64_32 a,limm,c 00110110001110010111CCCCCCAAAAAA. */ -+{ "fcvt64_32", 0x36397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fcvt64_32 a,b,limm 00110bbb001110010BBB111110AAAAAA. */ -+{ "fcvt64_32", 0x30390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fcvt64_32 0,limm,c 00110110001110010111CCCCCC111110. */ -+{ "fcvt64_32", 0x3639703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fcvt64_32 0,b,limm 00110bbb001110010BBB111110111110. */ -+{ "fcvt64_32", 0x30390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fcvt64_32<.cc> b,b,limm 00110bbb111110010BBB1111100QQQQQ. */ -+{ "fcvt64_32", 0x30F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fcvt64_32<.cc> 0,limm,c 00110110111110010111CCCCCC0QQQQQ. */ -+{ "fcvt64_32", 0x36F97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fcvt64_32 a,limm,u6 00110110011110010111uuuuuuAAAAAA. */ -+{ "fcvt64_32", 0x36797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt64_32 0,limm,u6 00110110011110010111uuuuuu111110. */ -+{ "fcvt64_32", 0x3679703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fcvt64_32<.cc> 0,limm,u6 00110110111110010111uuuuuu1QQQQQ. */ -+{ "fcvt64_32", 0x36F97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fcvt64_32 0,limm,s12 00110110101110010111ssssssSSSSSS. */ -+{ "fcvt64_32", 0x36B97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fcvt64_32 a,limm,limm 00110110001110010111111110AAAAAA. */ -+{ "fcvt64_32", 0x36397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fcvt64_32 0,limm,limm 00110110001110010111111110111110. */ -+{ "fcvt64_32", 0x36397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fcvt64_32<.cc> 0,limm,limm 001101101111100101111111100QQQQQ. */ -+{ "fcvt64_32", 0x36F97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fdadd a,b,c 00110bbb001100010BBBCCCCCCAAAAAA. */ -+{ "fdadd", 0x30310000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdadd 0,b,c 00110bbb001100010BBBCCCCCC111110. */ -+{ "fdadd", 0x3031003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdadd<.cc> b,b,c 00110bbb111100010BBBCCCCCC0QQQQQ. */ -+{ "fdadd", 0x30F10000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fdadd a,b,u6 00110bbb011100010BBBuuuuuuAAAAAA. */ -+{ "fdadd", 0x30710000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdadd 0,b,u6 00110bbb011100010BBBuuuuuu111110. */ -+{ "fdadd", 0x3071003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdadd<.cc> b,b,u6 00110bbb111100010BBBuuuuuu1QQQQQ. */ -+{ "fdadd", 0x30F10020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdadd b,b,s12 00110bbb101100010BBBssssssSSSSSS. */ -+{ "fdadd", 0x30B10000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdadd a,limm,c 00110110001100010111CCCCCCAAAAAA. */ -+{ "fdadd", 0x36317000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdadd a,b,limm 00110bbb001100010BBB111110AAAAAA. */ -+{ "fdadd", 0x30310F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdadd 0,limm,c 00110110001100010111CCCCCC111110. */ -+{ "fdadd", 0x3631703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdadd 0,b,limm 00110bbb001100010BBB111110111110. */ -+{ "fdadd", 0x30310FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdadd<.cc> b,b,limm 00110bbb111100010BBB1111100QQQQQ. */ -+{ "fdadd", 0x30F10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fdadd<.cc> 0,limm,c 00110110111100010111CCCCCC0QQQQQ. */ -+{ "fdadd", 0x36F17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fdadd a,limm,u6 00110110011100010111uuuuuuAAAAAA. */ -+{ "fdadd", 0x36717000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdadd 0,limm,u6 00110110011100010111uuuuuu111110. */ -+{ "fdadd", 0x3671703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdadd<.cc> 0,limm,u6 00110110111100010111uuuuuu1QQQQQ. */ -+{ "fdadd", 0x36F17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdadd 0,limm,s12 00110110101100010111ssssssSSSSSS. */ -+{ "fdadd", 0x36B17000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdadd a,limm,limm 00110110001100010111111110AAAAAA. */ -+{ "fdadd", 0x36317F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdadd 0,limm,limm 00110110001100010111111110111110. */ -+{ "fdadd", 0x36317FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdadd<.cc> 0,limm,limm 001101101111000101111111100QQQQQ. */ -+{ "fdadd", 0x36F17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fdcmp b,c 00110bbb001100111BBBCCCCCC000000. */ -+{ "fdcmp", 0x30338000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdcmp<.cc> b,c 00110bbb111100111BBBCCCCCC0QQQQQ. */ -+{ "fdcmp", 0x30F38000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* fdcmp b,u6 00110bbb011100111BBBuuuuuu000000. */ -+{ "fdcmp", 0x30738000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdcmp<.cc> b,u6 00110bbb111100111BBBuuuuuu1QQQQQ. */ -+{ "fdcmp", 0x30F38020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdcmp b,s12 00110bbb101100111BBBssssssSSSSSS. */ -+{ "fdcmp", 0x30B38000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdcmp limm,c 00110110001100111111CCCCCC000000. */ -+{ "fdcmp", 0x3633F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdcmp b,limm 00110bbb001100111BBB111110000000. */ -+{ "fdcmp", 0x30338F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdcmp<.cc> b,limm 00110bbb111100111BBB1111100QQQQQ. */ -+{ "fdcmp", 0x30F38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* fdcmp<.cc> limm,c 00110110111100111111CCCCCC0QQQQQ. */ -+{ "fdcmp", 0x36F3F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fdcmp limm,u6 00110110011100111111uuuuuu000000. */ -+{ "fdcmp", 0x3673F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdcmp<.cc> limm,u6 00110110111100111111uuuuuu1QQQQQ. */ -+{ "fdcmp", 0x36F3F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdcmp limm,s12 00110110101100111111ssssssSSSSSS. */ -+{ "fdcmp", 0x36B3F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdcmp limm,limm 00110110001100111111111110000000. */ -+{ "fdcmp", 0x3633FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdcmp<.cc> limm,limm 001101101111001111111111100QQQQQ. */ -+{ "fdcmp", 0x36F3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fdcmpf b,c 00110bbb001101001BBBCCCCCC000000. */ -+{ "fdcmpf", 0x30348000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdcmpf<.cc> b,c 00110bbb111101001BBBCCCCCC0QQQQQ. */ -+{ "fdcmpf", 0x30F48000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* fdcmpf b,u6 00110bbb011101001BBBuuuuuu000000. */ -+{ "fdcmpf", 0x30748000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdcmpf<.cc> b,u6 00110bbb111101001BBBuuuuuu1QQQQQ. */ -+{ "fdcmpf", 0x30F48020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdcmpf b,s12 00110bbb101101001BBBssssssSSSSSS. */ -+{ "fdcmpf", 0x30B48000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdcmpf limm,c 00110110001101001111CCCCCC000000. */ -+{ "fdcmpf", 0x3634F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdcmpf b,limm 00110bbb001101001BBB111110000000. */ -+{ "fdcmpf", 0x30348F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdcmpf<.cc> b,limm 00110bbb111101001BBB1111100QQQQQ. */ -+{ "fdcmpf", 0x30F48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* fdcmpf<.cc> limm,c 00110110111101001111CCCCCC0QQQQQ. */ -+{ "fdcmpf", 0x36F4F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fdcmpf limm,u6 00110110011101001111uuuuuu000000. */ -+{ "fdcmpf", 0x3674F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdcmpf<.cc> limm,u6 00110110111101001111uuuuuu1QQQQQ. */ -+{ "fdcmpf", 0x36F4F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdcmpf limm,s12 00110110101101001111ssssssSSSSSS. */ -+{ "fdcmpf", 0x36B4F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdcmpf limm,limm 00110110001101001111111110000000. */ -+{ "fdcmpf", 0x3634FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdcmpf<.cc> limm,limm 001101101111010011111111100QQQQQ. */ -+{ "fdcmpf", 0x36F4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fddiv a,b,c 00110bbb001101110BBBCCCCCCAAAAAA. */ -+{ "fddiv", 0x30370000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fddiv 0,b,c 00110bbb001101110BBBCCCCCC111110. */ -+{ "fddiv", 0x3037003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fddiv<.cc> b,b,c 00110bbb111101110BBBCCCCCC0QQQQQ. */ -+{ "fddiv", 0x30F70000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fddiv a,b,u6 00110bbb011101110BBBuuuuuuAAAAAA. */ -+{ "fddiv", 0x30770000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fddiv 0,b,u6 00110bbb011101110BBBuuuuuu111110. */ -+{ "fddiv", 0x3077003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fddiv<.cc> b,b,u6 00110bbb111101110BBBuuuuuu1QQQQQ. */ -+{ "fddiv", 0x30F70020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fddiv b,b,s12 00110bbb101101110BBBssssssSSSSSS. */ -+{ "fddiv", 0x30B70000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fddiv a,limm,c 00110110001101110111CCCCCCAAAAAA. */ -+{ "fddiv", 0x36377000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fddiv a,b,limm 00110bbb001101110BBB111110AAAAAA. */ -+{ "fddiv", 0x30370F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fddiv 0,limm,c 00110110001101110111CCCCCC111110. */ -+{ "fddiv", 0x3637703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fddiv 0,b,limm 00110bbb001101110BBB111110111110. */ -+{ "fddiv", 0x30370FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fddiv<.cc> b,b,limm 00110bbb111101110BBB1111100QQQQQ. */ -+{ "fddiv", 0x30F70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fddiv<.cc> 0,limm,c 00110110111101110111CCCCCC0QQQQQ. */ -+{ "fddiv", 0x36F77000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fddiv a,limm,u6 00110110011101110111uuuuuuAAAAAA. */ -+{ "fddiv", 0x36777000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fddiv 0,limm,u6 00110110011101110111uuuuuu111110. */ -+{ "fddiv", 0x3677703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fddiv<.cc> 0,limm,u6 00110110111101110111uuuuuu1QQQQQ. */ -+{ "fddiv", 0x36F77020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fddiv 0,limm,s12 00110110101101110111ssssssSSSSSS. */ -+{ "fddiv", 0x36B77000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fddiv a,limm,limm 00110110001101110111111110AAAAAA. */ -+{ "fddiv", 0x36377F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fddiv 0,limm,limm 00110110001101110111111110111110. */ -+{ "fddiv", 0x36377FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fddiv<.cc> 0,limm,limm 001101101111011101111111100QQQQQ. */ -+{ "fddiv", 0x36F77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fdmadd a,b,c 00110bbb001101010BBBCCCCCCAAAAAA. */ -+{ "fdmadd", 0x30350000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdmadd 0,b,c 00110bbb001101010BBBCCCCCC111110. */ -+{ "fdmadd", 0x3035003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdmadd<.cc> b,b,c 00110bbb111101010BBBCCCCCC0QQQQQ. */ -+{ "fdmadd", 0x30F50000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fdmadd a,b,u6 00110bbb011101010BBBuuuuuuAAAAAA. */ -+{ "fdmadd", 0x30750000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmadd 0,b,u6 00110bbb011101010BBBuuuuuu111110. */ -+{ "fdmadd", 0x3075003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmadd<.cc> b,b,u6 00110bbb111101010BBBuuuuuu1QQQQQ. */ -+{ "fdmadd", 0x30F50020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdmadd b,b,s12 00110bbb101101010BBBssssssSSSSSS. */ -+{ "fdmadd", 0x30B50000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdmadd a,limm,c 00110110001101010111CCCCCCAAAAAA. */ -+{ "fdmadd", 0x36357000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdmadd a,b,limm 00110bbb001101010BBB111110AAAAAA. */ -+{ "fdmadd", 0x30350F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdmadd 0,limm,c 00110110001101010111CCCCCC111110. */ -+{ "fdmadd", 0x3635703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdmadd 0,b,limm 00110bbb001101010BBB111110111110. */ -+{ "fdmadd", 0x30350FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdmadd<.cc> b,b,limm 00110bbb111101010BBB1111100QQQQQ. */ -+{ "fdmadd", 0x30F50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fdmadd<.cc> 0,limm,c 00110110111101010111CCCCCC0QQQQQ. */ -+{ "fdmadd", 0x36F57000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fdmadd a,limm,u6 00110110011101010111uuuuuuAAAAAA. */ -+{ "fdmadd", 0x36757000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmadd 0,limm,u6 00110110011101010111uuuuuu111110. */ -+{ "fdmadd", 0x3675703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmadd<.cc> 0,limm,u6 00110110111101010111uuuuuu1QQQQQ. */ -+{ "fdmadd", 0x36F57020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdmadd 0,limm,s12 00110110101101010111ssssssSSSSSS. */ -+{ "fdmadd", 0x36B57000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdmadd a,limm,limm 00110110001101010111111110AAAAAA. */ -+{ "fdmadd", 0x36357F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdmadd 0,limm,limm 00110110001101010111111110111110. */ -+{ "fdmadd", 0x36357FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdmadd<.cc> 0,limm,limm 001101101111010101111111100QQQQQ. */ -+{ "fdmadd", 0x36F57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fdmsub a,b,c 00110bbb001101100BBBCCCCCCAAAAAA. */ -+{ "fdmsub", 0x30360000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdmsub 0,b,c 00110bbb001101100BBBCCCCCC111110. */ -+{ "fdmsub", 0x3036003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdmsub<.cc> b,b,c 00110bbb111101100BBBCCCCCC0QQQQQ. */ -+{ "fdmsub", 0x30F60000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fdmsub a,b,u6 00110bbb011101100BBBuuuuuuAAAAAA. */ -+{ "fdmsub", 0x30760000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmsub 0,b,u6 00110bbb011101100BBBuuuuuu111110. */ -+{ "fdmsub", 0x3076003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmsub<.cc> b,b,u6 00110bbb111101100BBBuuuuuu1QQQQQ. */ -+{ "fdmsub", 0x30F60020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdmsub b,b,s12 00110bbb101101100BBBssssssSSSSSS. */ -+{ "fdmsub", 0x30B60000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdmsub a,limm,c 00110110001101100111CCCCCCAAAAAA. */ -+{ "fdmsub", 0x36367000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdmsub a,b,limm 00110bbb001101100BBB111110AAAAAA. */ -+{ "fdmsub", 0x30360F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdmsub 0,limm,c 00110110001101100111CCCCCC111110. */ -+{ "fdmsub", 0x3636703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdmsub 0,b,limm 00110bbb001101100BBB111110111110. */ -+{ "fdmsub", 0x30360FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdmsub<.cc> b,b,limm 00110bbb111101100BBB1111100QQQQQ. */ -+{ "fdmsub", 0x30F60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fdmsub<.cc> 0,limm,c 00110110111101100111CCCCCC0QQQQQ. */ -+{ "fdmsub", 0x36F67000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fdmsub a,limm,u6 00110110011101100111uuuuuuAAAAAA. */ -+{ "fdmsub", 0x36767000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmsub 0,limm,u6 00110110011101100111uuuuuu111110. */ -+{ "fdmsub", 0x3676703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmsub<.cc> 0,limm,u6 00110110111101100111uuuuuu1QQQQQ. */ -+{ "fdmsub", 0x36F67020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdmsub 0,limm,s12 00110110101101100111ssssssSSSSSS. */ -+{ "fdmsub", 0x36B67000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdmsub a,limm,limm 00110110001101100111111110AAAAAA. */ -+{ "fdmsub", 0x36367F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdmsub 0,limm,limm 00110110001101100111111110111110. */ -+{ "fdmsub", 0x36367FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdmsub<.cc> 0,limm,limm 001101101111011001111111100QQQQQ. */ -+{ "fdmsub", 0x36F67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fdmul a,b,c 00110bbb001100000BBBCCCCCCAAAAAA. */ -+{ "fdmul", 0x30300000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdmul 0,b,c 00110bbb001100000BBBCCCCCC111110. */ -+{ "fdmul", 0x3030003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdmul<.cc> b,b,c 00110bbb111100000BBBCCCCCC0QQQQQ. */ -+{ "fdmul", 0x30F00000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fdmul a,b,u6 00110bbb011100000BBBuuuuuuAAAAAA. */ -+{ "fdmul", 0x30700000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmul 0,b,u6 00110bbb011100000BBBuuuuuu111110. */ -+{ "fdmul", 0x3070003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmul<.cc> b,b,u6 00110bbb111100000BBBuuuuuu1QQQQQ. */ -+{ "fdmul", 0x30F00020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdmul b,b,s12 00110bbb101100000BBBssssssSSSSSS. */ -+{ "fdmul", 0x30B00000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdmul a,limm,c 00110110001100000111CCCCCCAAAAAA. */ -+{ "fdmul", 0x36307000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdmul a,b,limm 00110bbb001100000BBB111110AAAAAA. */ -+{ "fdmul", 0x30300F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdmul 0,limm,c 00110110001100000111CCCCCC111110. */ -+{ "fdmul", 0x3630703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdmul 0,b,limm 00110bbb001100000BBB111110111110. */ -+{ "fdmul", 0x30300FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdmul<.cc> b,b,limm 00110bbb111100000BBB1111100QQQQQ. */ -+{ "fdmul", 0x30F00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fdmul<.cc> 0,limm,c 00110110111100000111CCCCCC0QQQQQ. */ -+{ "fdmul", 0x36F07000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fdmul a,limm,u6 00110110011100000111uuuuuuAAAAAA. */ -+{ "fdmul", 0x36707000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmul 0,limm,u6 00110110011100000111uuuuuu111110. */ -+{ "fdmul", 0x3670703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdmul<.cc> 0,limm,u6 00110110111100000111uuuuuu1QQQQQ. */ -+{ "fdmul", 0x36F07020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdmul 0,limm,s12 00110110101100000111ssssssSSSSSS. */ -+{ "fdmul", 0x36B07000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdmul a,limm,limm 00110110001100000111111110AAAAAA. */ -+{ "fdmul", 0x36307F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdmul 0,limm,limm 00110110001100000111111110111110. */ -+{ "fdmul", 0x36307FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdmul<.cc> 0,limm,limm 001101101111000001111111100QQQQQ. */ -+{ "fdmul", 0x36F07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fdsqrt b,c 00110bbb001011110BBBCCCCCC000001. */ -+{ "fdsqrt", 0x302F0001, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdsqrt 0,c 00110110001011110111CCCCCC000001. */ -+{ "fdsqrt", 0x362F7001, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* fdsqrt b,u6 00110bbb011011110BBBuuuuuu000001. */ -+{ "fdsqrt", 0x306F0001, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdsqrt 0,u6 00110110011011110111uuuuuu000001. */ -+{ "fdsqrt", 0x366F7001, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdsqrt b,limm 00110bbb001011110BBB111110000001. */ -+{ "fdsqrt", 0x302F0F81, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdsqrt 0,limm 00110110001011110111111110000001. */ -+{ "fdsqrt", 0x362F7F81, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* fdsub a,b,c 00110bbb001100100BBBCCCCCCAAAAAA. */ -+{ "fdsub", 0x30320000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdsub 0,b,c 00110bbb001100100BBBCCCCCC111110. */ -+{ "fdsub", 0x3032003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fdsub<.cc> b,b,c 00110bbb111100100BBBCCCCCC0QQQQQ. */ -+{ "fdsub", 0x30F20000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fdsub a,b,u6 00110bbb011100100BBBuuuuuuAAAAAA. */ -+{ "fdsub", 0x30720000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdsub 0,b,u6 00110bbb011100100BBBuuuuuu111110. */ -+{ "fdsub", 0x3072003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdsub<.cc> b,b,u6 00110bbb111100100BBBuuuuuu1QQQQQ. */ -+{ "fdsub", 0x30F20020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdsub b,b,s12 00110bbb101100100BBBssssssSSSSSS. */ -+{ "fdsub", 0x30B20000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdsub a,limm,c 00110110001100100111CCCCCCAAAAAA. */ -+{ "fdsub", 0x36327000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdsub a,b,limm 00110bbb001100100BBB111110AAAAAA. */ -+{ "fdsub", 0x30320F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdsub 0,limm,c 00110110001100100111CCCCCC111110. */ -+{ "fdsub", 0x3632703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fdsub 0,b,limm 00110bbb001100100BBB111110111110. */ -+{ "fdsub", 0x30320FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fdsub<.cc> b,b,limm 00110bbb111100100BBB1111100QQQQQ. */ -+{ "fdsub", 0x30F20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fdsub<.cc> 0,limm,c 00110110111100100111CCCCCC0QQQQQ. */ -+{ "fdsub", 0x36F27000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fdsub a,limm,u6 00110110011100100111uuuuuuAAAAAA. */ -+{ "fdsub", 0x36727000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdsub 0,limm,u6 00110110011100100111uuuuuu111110. */ -+{ "fdsub", 0x3672703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fdsub<.cc> 0,limm,u6 00110110111100100111uuuuuu1QQQQQ. */ -+{ "fdsub", 0x36F27020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fdsub 0,limm,s12 00110110101100100111ssssssSSSSSS. */ -+{ "fdsub", 0x36B27000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fdsub a,limm,limm 00110110001100100111111110AAAAAA. */ -+{ "fdsub", 0x36327F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdsub 0,limm,limm 00110110001100100111111110111110. */ -+{ "fdsub", 0x36327FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fdsub<.cc> 0,limm,limm 001101101111001001111111100QQQQQ. */ -+{ "fdsub", 0x36F27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* ffs<.f> b,c 00101bbb00101111FBBBCCCCCC010010. */ -+{ "ffs", 0x282F0012, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ffs<.f> 0,c 0010111000101111F111CCCCCC010010. */ -+{ "ffs", 0x2E2F7012, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* ffs<.f> b,u6 00101bbb01101111FBBBuuuuuu010010. */ -+{ "ffs", 0x286F0012, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ffs<.f> 0,u6 0010111001101111F111uuuuuu010010. */ -+{ "ffs", 0x2E6F7012, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ffs<.f> b,limm 00101bbb00101111FBBB111110010010. */ -+{ "ffs", 0x282F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ffs<.f> 0,limm 0010111000101111F111111110010010. */ -+{ "ffs", 0x2E2F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* flag c 00100RRR001010010RRRCCCCCCRRRRRR. */ -+{ "flag", 0x20290000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* flag<.cc> c 00100RRR111010010RRRCCCCCC0QQQQQ. */ -+{ "flag", 0x20E90000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { C_CC }}, -+ -+/* flag u6 00100RRR011010010RRRuuuuuuRRRRRR. */ -+{ "flag", 0x20690000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* flag<.cc> u6 00100RRR111010010RRRuuuuuu1QQQQQ. */ -+{ "flag", 0x20E90020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* flag s12 00100RRR101010010RRRssssssSSSSSS. */ -+{ "flag", 0x20A90000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* flag limm 00100RRR001010010RRR111110RRRRRR. */ -+{ "flag", 0x20290F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* flag<.cc> limm 00100RRR111010010RRR1111100QQQQQ. */ -+{ "flag", 0x20E90F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { C_CC }}, -+ -+/* flagacc c 00101100001011111000CCCCCC111111. */ -+{ "flagacc", 0x2C2F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* flagacc u6 00101100011011111000uuuuuu111111. */ -+{ "flagacc", 0x2C6F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fls<.f> b,c 00101bbb00101111FBBBCCCCCC010011. */ -+{ "fls", 0x282F0013, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fls<.f> 0,c 0010111000101111F111CCCCCC010011. */ -+{ "fls", 0x2E2F7013, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* fls<.f> b,u6 00101bbb01101111FBBBuuuuuu010011. */ -+{ "fls", 0x286F0013, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fls<.f> 0,u6 0010111001101111F111uuuuuu010011. */ -+{ "fls", 0x2E6F7013, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fls<.f> b,limm 00101bbb00101111FBBB111110010011. */ -+{ "fls", 0x282F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fls<.f> 0,limm 0010111000101111F111111110010011. */ -+{ "fls", 0x2E2F7F93, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* fmul<.f> a,b,c 00110bbb00000000FBBBCCCCCCAAAAAA. */ -+{ "fmul", 0x30000000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmul<.f> 0,b,c 00110bbb00000000FBBBCCCCCC111110. */ -+{ "fmul", 0x3000003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fmul<.f><.cc> b,b,c 00110bbb11000000FBBBCCCCCC0QQQQQ. */ -+{ "fmul", 0x30C00000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fmul<.f> a,b,u6 00110bbb01000000FBBBuuuuuuAAAAAA. */ -+{ "fmul", 0x30400000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmul<.f> 0,b,u6 00110bbb01000000FBBBuuuuuu111110. */ -+{ "fmul", 0x3040003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmul<.f><.cc> b,b,u6 00110bbb11000000FBBBuuuuuu1QQQQQ. */ -+{ "fmul", 0x30C00020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fmul<.f> b,b,s12 00110bbb10000000FBBBssssssSSSSSS. */ -+{ "fmul", 0x30800000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fmul<.f> a,limm,c 0011011000000000F111CCCCCCAAAAAA. */ -+{ "fmul", 0x36007000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fmul<.f> a,b,limm 00110bbb00000000FBBB111110AAAAAA. */ -+{ "fmul", 0x30000F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmul<.f> 0,limm,c 0011011000000000F111CCCCCC111110. */ -+{ "fmul", 0x3600703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fmul<.f> 0,b,limm 00110bbb00000000FBBB111110111110. */ -+{ "fmul", 0x30000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fmul<.f><.cc> 0,limm,c 0011011011000000F111CCCCCC0QQQQQ. */ -+{ "fmul", 0x36C07000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fmul<.f><.cc> b,b,limm 00110bbb11000000FBBB1111100QQQQQ. */ -+{ "fmul", 0x30C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* fmul<.f> a,limm,u6 0011011001000000F111uuuuuuAAAAAA. */ -+{ "fmul", 0x36407000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmul<.f> 0,limm,u6 0011011001000000F111uuuuuu111110. */ -+{ "fmul", 0x3640703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fmul<.f><.cc> 0,limm,u6 0011011011000000F111uuuuuu1QQQQQ. */ -+{ "fmul", 0x36C07020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fmul<.f> 0,limm,s12 0011011010000000F111ssssssSSSSSS. */ -+{ "fmul", 0x36807000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fmul<.f> a,limm,limm 0011011000000000F111111110AAAAAA. */ -+{ "fmul", 0x36007F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fmul<.f> 0,limm,limm 0011011000000000F111111110111110. */ -+{ "fmul", 0x36007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fmul<.f><.cc> 0,limm,limm 0011011011000000F1111111100QQQQQ. */ -+{ "fmul", 0x36C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* fsadd a,b,c 00110bbb000000010BBBCCCCCCAAAAAA. */ -+{ "fsadd", 0x30010000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsadd 0,b,c 00110bbb000000010BBBCCCCCC111110. */ -+{ "fsadd", 0x3001003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsadd<.cc> b,b,c 00110bbb110000010BBBCCCCCC0QQQQQ. */ -+{ "fsadd", 0x30C10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fsadd a,b,u6 00110bbb010000010BBBuuuuuuAAAAAA. */ -+{ "fsadd", 0x30410000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsadd 0,b,u6 00110bbb010000010BBBuuuuuu111110. */ -+{ "fsadd", 0x3041003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsadd<.cc> b,b,u6 00110bbb110000010BBBuuuuuu1QQQQQ. */ -+{ "fsadd", 0x30C10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsadd b,b,s12 00110bbb100000010BBBssssssSSSSSS. */ -+{ "fsadd", 0x30810000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsadd a,limm,c 00110110000000010111CCCCCCAAAAAA. */ -+{ "fsadd", 0x36017000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsadd a,b,limm 00110bbb000000010BBB111110AAAAAA. */ -+{ "fsadd", 0x30010F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsadd 0,limm,c 00110110000000010111CCCCCC111110. */ -+{ "fsadd", 0x3601703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsadd 0,b,limm 00110bbb000000010BBB111110111110. */ -+{ "fsadd", 0x30010FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsadd<.cc> b,b,limm 00110bbb110000010BBB1111100QQQQQ. */ -+{ "fsadd", 0x30C10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fsadd<.cc> 0,limm,c 00110110110000010111CCCCCC0QQQQQ. */ -+{ "fsadd", 0x36C17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fsadd a,limm,u6 00110110010000010111uuuuuuAAAAAA. */ -+{ "fsadd", 0x36417000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsadd 0,limm,u6 00110110010000010111uuuuuu111110. */ -+{ "fsadd", 0x3641703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsadd<.cc> 0,limm,u6 00110110110000010111uuuuuu1QQQQQ. */ -+{ "fsadd", 0x36C17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsadd 0,limm,s12 00110110100000010111ssssssSSSSSS. */ -+{ "fsadd", 0x36817000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsadd a,limm,limm 00110110000000010111111110AAAAAA. */ -+{ "fsadd", 0x36017F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsadd 0,limm,limm 00110110000000010111111110111110. */ -+{ "fsadd", 0x36017FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsadd<.cc> 0,limm,limm 001101101100000101111111100QQQQQ. */ -+{ "fsadd", 0x36C17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fscmp b,c 00110bbb000000111BBBCCCCCC000000. */ -+{ "fscmp", 0x30038000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fscmp<.cc> b,c 00110bbb110000111BBBCCCCCC0QQQQQ. */ -+{ "fscmp", 0x30C38000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* fscmp b,u6 00110bbb010000111BBBuuuuuu000000. */ -+{ "fscmp", 0x30438000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fscmp<.cc> b,u6 00110bbb110000111BBBuuuuuu1QQQQQ. */ -+{ "fscmp", 0x30C38020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fscmp b,s12 00110bbb100000111BBBssssssSSSSSS. */ -+{ "fscmp", 0x30838000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fscmp limm,c 00110110000000111111CCCCCC000000. */ -+{ "fscmp", 0x3603F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fscmp b,limm 00110bbb000000111BBB111110000000. */ -+{ "fscmp", 0x30038F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fscmp<.cc> b,limm 00110bbb110000111BBB1111100QQQQQ. */ -+{ "fscmp", 0x30C38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* fscmp<.cc> limm,c 00110110110000111111CCCCCC0QQQQQ. */ -+{ "fscmp", 0x36C3F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fscmp limm,u6 00110110010000111111uuuuuu000000. */ -+{ "fscmp", 0x3643F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fscmp<.cc> limm,u6 00110110110000111111uuuuuu1QQQQQ. */ -+{ "fscmp", 0x36C3F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fscmp limm,s12 00110110100000111111ssssssSSSSSS. */ -+{ "fscmp", 0x3683F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fscmp limm,limm 00110110000000111111111110000000. */ -+{ "fscmp", 0x3603FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fscmp<.cc> limm,limm 001101101100001111111111100QQQQQ. */ -+{ "fscmp", 0x36C3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fscmpf b,c 00110bbb000001001BBBCCCCCC000000. */ -+{ "fscmpf", 0x30048000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fscmpf<.cc> b,c 00110bbb110001001BBBCCCCCC0QQQQQ. */ -+{ "fscmpf", 0x30C48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* fscmpf b,u6 00110bbb010001001BBBuuuuuu000000. */ -+{ "fscmpf", 0x30448000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fscmpf<.cc> b,u6 00110bbb110001001BBBuuuuuu1QQQQQ. */ -+{ "fscmpf", 0x30C48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fscmpf b,s12 00110bbb100001001BBBssssssSSSSSS. */ -+{ "fscmpf", 0x30848000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fscmpf limm,c 00110110000001001111CCCCCC000000. */ -+{ "fscmpf", 0x3604F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fscmpf b,limm 00110bbb000001001BBB111110000000. */ -+{ "fscmpf", 0x30048F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fscmpf<.cc> b,limm 00110bbb110001001BBB1111100QQQQQ. */ -+{ "fscmpf", 0x30C48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* fscmpf<.cc> limm,c 00110110110001001111CCCCCC0QQQQQ. */ -+{ "fscmpf", 0x36C4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fscmpf limm,u6 00110110010001001111uuuuuu000000. */ -+{ "fscmpf", 0x3644F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fscmpf<.cc> limm,u6 00110110110001001111uuuuuu1QQQQQ. */ -+{ "fscmpf", 0x36C4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fscmpf limm,s12 00110110100001001111ssssssSSSSSS. */ -+{ "fscmpf", 0x3684F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fscmpf limm,limm 00110110000001001111111110000000. */ -+{ "fscmpf", 0x3604FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fscmpf<.cc> limm,limm 001101101100010011111111100QQQQQ. */ -+{ "fscmpf", 0x36C4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fsdiv a,b,c 00110bbb000001110BBBCCCCCCAAAAAA. */ -+{ "fsdiv", 0x30070000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsdiv 0,b,c 00110bbb000001110BBBCCCCCC111110. */ -+{ "fsdiv", 0x3007003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsdiv<.cc> b,b,c 00110bbb110001110BBBCCCCCC0QQQQQ. */ -+{ "fsdiv", 0x30C70000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fsdiv a,b,u6 00110bbb010001110BBBuuuuuuAAAAAA. */ -+{ "fsdiv", 0x30470000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsdiv 0,b,u6 00110bbb010001110BBBuuuuuu111110. */ -+{ "fsdiv", 0x3047003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsdiv<.cc> b,b,u6 00110bbb110001110BBBuuuuuu1QQQQQ. */ -+{ "fsdiv", 0x30C70020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsdiv b,b,s12 00110bbb100001110BBBssssssSSSSSS. */ -+{ "fsdiv", 0x30870000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsdiv a,limm,c 00110110000001110111CCCCCCAAAAAA. */ -+{ "fsdiv", 0x36077000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsdiv a,b,limm 00110bbb000001110BBB111110AAAAAA. */ -+{ "fsdiv", 0x30070F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsdiv 0,limm,c 00110110000001110111CCCCCC111110. */ -+{ "fsdiv", 0x3607703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsdiv 0,b,limm 00110bbb000001110BBB111110111110. */ -+{ "fsdiv", 0x30070FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsdiv<.cc> b,b,limm 00110bbb110001110BBB1111100QQQQQ. */ -+{ "fsdiv", 0x30C70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fsdiv<.cc> 0,limm,c 00110110110001110111CCCCCC0QQQQQ. */ -+{ "fsdiv", 0x36C77000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fsdiv a,limm,u6 00110110010001110111uuuuuuAAAAAA. */ -+{ "fsdiv", 0x36477000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsdiv 0,limm,u6 00110110010001110111uuuuuu111110. */ -+{ "fsdiv", 0x3647703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsdiv<.cc> 0,limm,u6 00110110110001110111uuuuuu1QQQQQ. */ -+{ "fsdiv", 0x36C77020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsdiv 0,limm,s12 00110110100001110111ssssssSSSSSS. */ -+{ "fsdiv", 0x36877000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsdiv a,limm,limm 00110110000001110111111110AAAAAA. */ -+{ "fsdiv", 0x36077F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsdiv 0,limm,limm 00110110000001110111111110111110. */ -+{ "fsdiv", 0x36077FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsdiv<.cc> 0,limm,limm 001101101100011101111111100QQQQQ. */ -+{ "fsdiv", 0x36C77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fsmadd a,b,c 00110bbb000001010BBBCCCCCCAAAAAA. */ -+{ "fsmadd", 0x30050000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsmadd 0,b,c 00110bbb000001010BBBCCCCCC111110. */ -+{ "fsmadd", 0x3005003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsmadd<.cc> b,b,c 00110bbb110001010BBBCCCCCC0QQQQQ. */ -+{ "fsmadd", 0x30C50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fsmadd a,b,u6 00110bbb010001010BBBuuuuuuAAAAAA. */ -+{ "fsmadd", 0x30450000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmadd 0,b,u6 00110bbb010001010BBBuuuuuu111110. */ -+{ "fsmadd", 0x3045003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmadd<.cc> b,b,u6 00110bbb110001010BBBuuuuuu1QQQQQ. */ -+{ "fsmadd", 0x30C50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsmadd b,b,s12 00110bbb100001010BBBssssssSSSSSS. */ -+{ "fsmadd", 0x30850000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsmadd a,limm,c 00110110000001010111CCCCCCAAAAAA. */ -+{ "fsmadd", 0x36057000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsmadd a,b,limm 00110bbb000001010BBB111110AAAAAA. */ -+{ "fsmadd", 0x30050F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsmadd 0,limm,c 00110110000001010111CCCCCC111110. */ -+{ "fsmadd", 0x3605703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsmadd 0,b,limm 00110bbb000001010BBB111110111110. */ -+{ "fsmadd", 0x30050FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsmadd<.cc> b,b,limm 00110bbb110001010BBB1111100QQQQQ. */ -+{ "fsmadd", 0x30C50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fsmadd<.cc> 0,limm,c 00110110110001010111CCCCCC0QQQQQ. */ -+{ "fsmadd", 0x36C57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fsmadd a,limm,u6 00110110010001010111uuuuuuAAAAAA. */ -+{ "fsmadd", 0x36457000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmadd 0,limm,u6 00110110010001010111uuuuuu111110. */ -+{ "fsmadd", 0x3645703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmadd<.cc> 0,limm,u6 00110110110001010111uuuuuu1QQQQQ. */ -+{ "fsmadd", 0x36C57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsmadd 0,limm,s12 00110110100001010111ssssssSSSSSS. */ -+{ "fsmadd", 0x36857000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsmadd a,limm,limm 00110110000001010111111110AAAAAA. */ -+{ "fsmadd", 0x36057F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsmadd 0,limm,limm 00110110000001010111111110111110. */ -+{ "fsmadd", 0x36057FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsmadd<.cc> 0,limm,limm 001101101100010101111111100QQQQQ. */ -+{ "fsmadd", 0x36C57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fsmsub a,b,c 00110bbb000001100BBBCCCCCCAAAAAA. */ -+{ "fsmsub", 0x30060000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsmsub 0,b,c 00110bbb000001100BBBCCCCCC111110. */ -+{ "fsmsub", 0x3006003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsmsub<.cc> b,b,c 00110bbb110001100BBBCCCCCC0QQQQQ. */ -+{ "fsmsub", 0x30C60000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fsmsub a,b,u6 00110bbb010001100BBBuuuuuuAAAAAA. */ -+{ "fsmsub", 0x30460000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmsub 0,b,u6 00110bbb010001100BBBuuuuuu111110. */ -+{ "fsmsub", 0x3046003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmsub<.cc> b,b,u6 00110bbb110001100BBBuuuuuu1QQQQQ. */ -+{ "fsmsub", 0x30C60020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsmsub b,b,s12 00110bbb100001100BBBssssssSSSSSS. */ -+{ "fsmsub", 0x30860000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsmsub a,limm,c 00110110000001100111CCCCCCAAAAAA. */ -+{ "fsmsub", 0x36067000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsmsub a,b,limm 00110bbb000001100BBB111110AAAAAA. */ -+{ "fsmsub", 0x30060F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsmsub 0,limm,c 00110110000001100111CCCCCC111110. */ -+{ "fsmsub", 0x3606703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsmsub 0,b,limm 00110bbb000001100BBB111110111110. */ -+{ "fsmsub", 0x30060FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsmsub<.cc> b,b,limm 00110bbb110001100BBB1111100QQQQQ. */ -+{ "fsmsub", 0x30C60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fsmsub<.cc> 0,limm,c 00110110110001100111CCCCCC0QQQQQ. */ -+{ "fsmsub", 0x36C67000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fsmsub a,limm,u6 00110110010001100111uuuuuuAAAAAA. */ -+{ "fsmsub", 0x36467000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmsub 0,limm,u6 00110110010001100111uuuuuu111110. */ -+{ "fsmsub", 0x3646703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmsub<.cc> 0,limm,u6 00110110110001100111uuuuuu1QQQQQ. */ -+{ "fsmsub", 0x36C67020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsmsub 0,limm,s12 00110110100001100111ssssssSSSSSS. */ -+{ "fsmsub", 0x36867000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsmsub a,limm,limm 00110110000001100111111110AAAAAA. */ -+{ "fsmsub", 0x36067F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsmsub 0,limm,limm 00110110000001100111111110111110. */ -+{ "fsmsub", 0x36067FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsmsub<.cc> 0,limm,limm 001101101100011001111111100QQQQQ. */ -+{ "fsmsub", 0x36C67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fsmul a,b,c 00110bbb000000000BBBCCCCCCAAAAAA. */ -+{ "fsmul", 0x30000000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsmul 0,b,c 00110bbb000000000BBBCCCCCC111110. */ -+{ "fsmul", 0x3000003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fsmul<.cc> b,b,c 00110bbb110000000BBBCCCCCC0QQQQQ. */ -+{ "fsmul", 0x30C00000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fsmul a,b,u6 00110bbb010000000BBBuuuuuuAAAAAA. */ -+{ "fsmul", 0x30400000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmul 0,b,u6 00110bbb010000000BBBuuuuuu111110. */ -+{ "fsmul", 0x3040003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmul<.cc> b,b,u6 00110bbb110000000BBBuuuuuu1QQQQQ. */ -+{ "fsmul", 0x30C00020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsmul b,b,s12 00110bbb100000000BBBssssssSSSSSS. */ -+{ "fsmul", 0x30800000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsmul a,limm,c 00110110000000000111CCCCCCAAAAAA. */ -+{ "fsmul", 0x36007000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsmul a,b,limm 00110bbb000000000BBB111110AAAAAA. */ -+{ "fsmul", 0x30000F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsmul 0,limm,c 00110110000000000111CCCCCC111110. */ -+{ "fsmul", 0x3600703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fsmul 0,b,limm 00110bbb000000000BBB111110111110. */ -+{ "fsmul", 0x30000FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fsmul<.cc> b,b,limm 00110bbb110000000BBB1111100QQQQQ. */ -+{ "fsmul", 0x30C00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fsmul<.cc> 0,limm,c 00110110110000000111CCCCCC0QQQQQ. */ -+{ "fsmul", 0x36C07000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fsmul a,limm,u6 00110110010000000111uuuuuuAAAAAA. */ -+{ "fsmul", 0x36407000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmul 0,limm,u6 00110110010000000111uuuuuu111110. */ -+{ "fsmul", 0x3640703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fsmul<.cc> 0,limm,u6 00110110110000000111uuuuuu1QQQQQ. */ -+{ "fsmul", 0x36C07020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fsmul 0,limm,s12 00110110100000000111ssssssSSSSSS. */ -+{ "fsmul", 0x36807000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fsmul a,limm,limm 00110110000000000111111110AAAAAA. */ -+{ "fsmul", 0x36007F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsmul 0,limm,limm 00110110000000000111111110111110. */ -+{ "fsmul", 0x36007FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fsmul<.cc> 0,limm,limm 001101101100000001111111100QQQQQ. */ -+{ "fsmul", 0x36C07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fssqrt b,c 00110bbb001011110BBBCCCCCC000000. */ -+{ "fssqrt", 0x302F0000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fssqrt 0,c 00110110001011110111CCCCCC000000. */ -+{ "fssqrt", 0x362F7000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* fssqrt b,u6 00110bbb011011110BBBuuuuuu000000. */ -+{ "fssqrt", 0x306F0000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fssqrt 0,u6 00110110011011110111uuuuuu000000. */ -+{ "fssqrt", 0x366F7000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fssqrt b,limm 00110bbb001011110BBB111110000000. */ -+{ "fssqrt", 0x302F0F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fssqrt 0,limm 00110110001011110111111110000000. */ -+{ "fssqrt", 0x362F7F80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* fssub a,b,c 00110bbb000000100BBBCCCCCCAAAAAA. */ -+{ "fssub", 0x30020000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fssub 0,b,c 00110bbb000000100BBBCCCCCC111110. */ -+{ "fssub", 0x3002003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* fssub<.cc> b,b,c 00110bbb110000100BBBCCCCCC0QQQQQ. */ -+{ "fssub", 0x30C20000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* fssub a,b,u6 00110bbb010000100BBBuuuuuuAAAAAA. */ -+{ "fssub", 0x30420000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fssub 0,b,u6 00110bbb010000100BBBuuuuuu111110. */ -+{ "fssub", 0x3042003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fssub<.cc> b,b,u6 00110bbb110000100BBBuuuuuu1QQQQQ. */ -+{ "fssub", 0x30C20020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fssub b,b,s12 00110bbb100000100BBBssssssSSSSSS. */ -+{ "fssub", 0x30820000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fssub a,limm,c 00110110000000100111CCCCCCAAAAAA. */ -+{ "fssub", 0x36027000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fssub a,b,limm 00110bbb000000100BBB111110AAAAAA. */ -+{ "fssub", 0x30020F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fssub 0,limm,c 00110110000000100111CCCCCC111110. */ -+{ "fssub", 0x3602703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* fssub 0,b,limm 00110bbb000000100BBB111110111110. */ -+{ "fssub", 0x30020FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* fssub<.cc> b,b,limm 00110bbb110000100BBB1111100QQQQQ. */ -+{ "fssub", 0x30C20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* fssub<.cc> 0,limm,c 00110110110000100111CCCCCC0QQQQQ. */ -+{ "fssub", 0x36C27000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* fssub a,limm,u6 00110110010000100111uuuuuuAAAAAA. */ -+{ "fssub", 0x36427000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fssub 0,limm,u6 00110110010000100111uuuuuu111110. */ -+{ "fssub", 0x3642703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* fssub<.cc> 0,limm,u6 00110110110000100111uuuuuu1QQQQQ. */ -+{ "fssub", 0x36C27020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* fssub 0,limm,s12 00110110100000100111ssssssSSSSSS. */ -+{ "fssub", 0x36827000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* fssub a,limm,limm 00110110000000100111111110AAAAAA. */ -+{ "fssub", 0x36027F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fssub 0,limm,limm 00110110000000100111111110111110. */ -+{ "fssub", 0x36027FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* fssub<.cc> 0,limm,limm 001101101100001001111111100QQQQQ. */ -+{ "fssub", 0x36C27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* fsub<.f> a,b,c 00110bbb00000010FBBBCCCCCCAAAAAA. */ -+{ "fsub", 0x30020000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fsub<.f> 0,b,c 00110bbb00000010FBBBCCCCCC111110. */ -+{ "fsub", 0x3002003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fsub<.f><.cc> b,b,c 00110bbb11000010FBBBCCCCCC0QQQQQ. */ -+{ "fsub", 0x30C20000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fsub<.f> a,b,u6 00110bbb01000010FBBBuuuuuuAAAAAA. */ -+{ "fsub", 0x30420000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fsub<.f> 0,b,u6 00110bbb01000010FBBBuuuuuu111110. */ -+{ "fsub", 0x3042003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fsub<.f><.cc> b,b,u6 00110bbb11000010FBBBuuuuuu1QQQQQ. */ -+{ "fsub", 0x30C20020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fsub<.f> b,b,s12 00110bbb10000010FBBBssssssSSSSSS. */ -+{ "fsub", 0x30820000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fsub<.f> a,limm,c 0011011000000010F111CCCCCCAAAAAA. */ -+{ "fsub", 0x36027000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fsub<.f> a,b,limm 00110bbb00000010FBBB111110AAAAAA. */ -+{ "fsub", 0x30020F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fsub<.f> 0,limm,c 0011011000000010F111CCCCCC111110. */ -+{ "fsub", 0x3602703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fsub<.f> 0,b,limm 00110bbb00000010FBBB111110111110. */ -+{ "fsub", 0x30020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fsub<.f><.cc> 0,limm,c 0011011011000010F111CCCCCC0QQQQQ. */ -+{ "fsub", 0x36C27000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fsub<.f><.cc> b,b,limm 00110bbb11000010FBBB1111100QQQQQ. */ -+{ "fsub", 0x30C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* fsub<.f> a,limm,u6 0011011001000010F111uuuuuuAAAAAA. */ -+{ "fsub", 0x36427000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fsub<.f> 0,limm,u6 0011011001000010F111uuuuuu111110. */ -+{ "fsub", 0x3642703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fsub<.f><.cc> 0,limm,u6 0011011011000010F111uuuuuu1QQQQQ. */ -+{ "fsub", 0x36C27020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fsub<.f> 0,limm,s12 0011011010000010F111ssssssSSSSSS. */ -+{ "fsub", 0x36827000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fsub<.f> a,limm,limm 0011011000000010F111111110AAAAAA. */ -+{ "fsub", 0x36027F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fsub<.f> 0,limm,limm 0011011000000010F111111110111110. */ -+{ "fsub", 0x36027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* fsub<.f><.cc> 0,limm,limm 0011011011000010F1111111100QQQQQ. */ -+{ "fsub", 0x36C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* fxtr<.f> a,b,c 00110bbb00100110FBBBCCCCCCAAAAAA. */ -+{ "fxtr", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* fxtr<.f><.cc> b,b,c 00110bbb11100110FBBBCCCCCC0QQQQQ. */ -+{ "fxtr", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* fxtr<.f> a,b,u6 00110bbb01100110FBBBuuuuuuAAAAAA. */ -+{ "fxtr", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* fxtr<.f><.cc> b,b,u6 00110bbb11100110FBBBuuuuuu1QQQQQ. */ -+{ "fxtr", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* fxtr<.f> b,b,s12 00110bbb10100110FBBBssssssSSSSSS. */ -+{ "fxtr", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* fxtr<.f> a,limm,c 0011011000100110F111CCCCCCAAAAAA. */ -+{ "fxtr", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* fxtr<.f> a,b,limm 00110bbb00100110FBBB111110AAAAAA. */ -+{ "fxtr", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* fxtr<.f><.cc> b,b,limm 00110bbb11100110FBBB1111100QQQQQ. */ -+{ "fxtr", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* getacc b,c 00101bbb001011110BBBCCCCCC011000. */ -+{ "getacc", 0x282F0018, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* getacc 0,c 00101110001011110111CCCCCC011000. */ -+{ "getacc", 0x2E2F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* getacc b,u6 00101bbb011011110BBBuuuuuu011000. */ -+{ "getacc", 0x286F0018, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* getacc 0,u6 00101110011011110111uuuuuu011000. */ -+{ "getacc", 0x2E6F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* getacc b,limm 00101bbb001011110BBB111110011000. */ -+{ "getacc", 0x282F0F98, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* getacc 0,limm 00101110001011110111111110011000. */ -+{ "getacc", 0x2E2F7F98, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* iaddr<.f> a,b,c 00110bbb00100111FBBBCCCCCCAAAAAA. */ -+{ "iaddr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* iaddr<.f><.cc> b,b,c 00110bbb11100111FBBBCCCCCC0QQQQQ. */ -+{ "iaddr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* iaddr<.f> a,b,u6 00110bbb01100111FBBBuuuuuuAAAAAA. */ -+{ "iaddr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* iaddr<.f><.cc> b,b,u6 00110bbb11100111FBBBuuuuuu1QQQQQ. */ -+{ "iaddr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* iaddr<.f> b,b,s12 00110bbb10100111FBBBssssssSSSSSS. */ -+{ "iaddr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* iaddr<.f> a,limm,c 0011011000100111F111CCCCCCAAAAAA. */ -+{ "iaddr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* iaddr<.f> a,b,limm 00110bbb00100111FBBB111110AAAAAA. */ -+{ "iaddr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* iaddr<.f><.cc> b,b,limm 00110bbb11100111FBBB1111100QQQQQ. */ -+{ "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* j c 00100RRR001000000RRRCCCCCCRRRRRR. */ -+{ "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j OPERAND_BLINK 00100RRR001000000RRR011111RRRRRR. */ -+{ "j", 0x202007C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j.F OPERAND_ILINK1 00100RRR001000001RRR011101RRRRRR. */ -+{ "j", 0x20208740, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK1, OPERAND_BRAKETdup }, { C_FHARD }}, -+ -+/* j.F OPERAND_ILINK2 00100RRR001000001RRR011110RRRRRR. */ -+{ "j", 0x20208780, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK2, OPERAND_BRAKETdup }, { C_FHARD }}, -+ -+/* jcc c 00100RRR111000000RRRCCCCCC0QQQQQ. */ -+{ "j", 0x20E00000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* jcc OPERAND_BLINK 00100RRR111000000RRR0111110QQQQQ. */ -+{ "j", 0x20E007C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* j.Fcc OPERAND_ILINK1 00100RRR111000001RRR0111010QQQQQ. */ -+{ "j", 0x20E08740, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK1, OPERAND_BRAKETdup }, { C_FHARD, C_CC }}, -+ -+/* j.Fcc OPERAND_ILINK2 00100RRR111000001RRR0111100QQQQQ. */ -+{ "j", 0x20E08780, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK2, OPERAND_BRAKETdup }, { C_FHARD, C_CC }}, -+ -+/* j.D c 00100RRR001000010RRRCCCCCCRRRRRR. */ -+{ "j", 0x20210000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* j.D OPERAND_BLINK 00100RRR001000010RRR011111RRRRRR. */ -+{ "j", 0x202107C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* jcc.D c 00100RRR111000010RRRCCCCCC0QQQQQ. */ -+{ "j", 0x20E10000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, -+ -+/* jcc.D OPERAND_BLINK 00100RRR111000010RRR0111110QQQQQ. */ -+{ "j", 0x20E107C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, -+ -+/* j c 00100RRR00100000RRRRCCCCCCRRRRRR. */ -+{ "j", 0x20200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j OPERAND_BLINK 00100RRR00100000RRRR011111RRRRRR. */ -+{ "j", 0x202007C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* jcc c 00100RRR11100000RRRRCCCCCC0QQQQQ. */ -+{ "j", 0x20E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* jcc OPERAND_BLINK 00100RRR11100000RRRR0111110QQQQQ. */ -+{ "j", 0x20E007C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* j.D c 00100RRR00100001RRRRCCCCCCRRRRRR. */ -+{ "j", 0x20210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* j.D OPERAND_BLINK 00100RRR00100001RRRR011111RRRRRR. */ -+{ "j", 0x202107C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* jcc.D c 00100RRR11100001RRRRCCCCCC0QQQQQ. */ -+{ "j", 0x20E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, -+ -+/* jcc.D OPERAND_BLINK 00100RRR11100001RRRR0111110QQQQQ. */ -+{ "j", 0x20E107C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, -+ -+/* j s12 00100RRR101000000RRRssssssSSSSSS. */ -+{ "j", 0x20A00000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* j.D s12 00100RRR101000010RRRssssssSSSSSS. */ -+{ "j", 0x20A10000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, -+ -+/* j s12 00100RRR10100000RRRRssssssSSSSSS. */ -+{ "j", 0x20A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* j.D s12 00100RRR10100001RRRRssssssSSSSSS. */ -+{ "j", 0x20A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, -+ -+/* j u6 00100RRR011000000RRRuuuuuuRRRRRR. */ -+{ "j", 0x20600000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* jcc u6 00100RRR111000000RRRuuuuuu1QQQQQ. */ -+{ "j", 0x20E00020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* j.D u6 00100RRR011000010RRRuuuuuuRRRRRR. */ -+{ "j", 0x20610000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, -+ -+/* jcc.D u6 00100RRR111000010RRRuuuuuu1QQQQQ. */ -+{ "j", 0x20E10020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, -+ -+/* j u6 00100RRR01100000RRRRuuuuuuRRRRRR. */ -+{ "j", 0x20600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* jcc u6 00100RRR11100000RRRRuuuuuu1QQQQQ. */ -+{ "j", 0x20E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* j.D u6 00100RRR01100001RRRRuuuuuuRRRRRR. */ -+{ "j", 0x20610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, -+ -+/* jcc.D u6 00100RRR11100001RRRRuuuuuu1QQQQQ. */ -+{ "j", 0x20E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, -+ -+/* j limm 00100RRR001000000RRR111110RRRRRR. */ -+{ "j", 0x20200F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* jcc limm 00100RRR111000000RRR1111100QQQQQ. */ -+{ "j", 0x20E00F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { C_CC }}, -+ -+/* j limm 00100RRR00100000RRRR111110RRRRRR. */ -+{ "j", 0x20200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* jcc limm 00100RRR11100000RRRR1111100QQQQQ. */ -+{ "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { C_CC }}, -+ -+/* jeq_s OPERAND_BLINK 0111110011100000. */ -+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_EQ }}, -+ -+/* jeq_s OPERAND_BLINK 0111110011100000. */ -+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_EQ }}, -+ -+/* jl c 00100RRR001000100RRRCCCCCCRRRRRR. */ -+{ "jl", 0x20220000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* jlcc c 00100RRR111000100RRRCCCCCC0QQQQQ. */ -+{ "jl", 0x20E20000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* jl.D c 00100RRR001000110RRRCCCCCCRRRRRR. */ -+{ "jl", 0x20230000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* jlcc.D c 00100RRR111000110RRRCCCCCC0QQQQQ. */ -+{ "jl", 0x20E30000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, -+ -+/* jl c 00100RRR00100010RRRRCCCCCCRRRRRR. */ -+{ "jl", 0x20220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* jlcc c 00100RRR11100010RRRRCCCCCC0QQQQQ. */ -+{ "jl", 0x20E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* jl.D c 00100RRR00100011RRRRCCCCCCRRRRRR. */ -+{ "jl", 0x20230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* jlcc.D c 00100RRR11100011RRRRCCCCCC0QQQQQ. */ -+{ "jl", 0x20E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, -+ -+/* jl s12 00100RRR101000100RRRssssssSSSSSS. */ -+{ "jl", 0x20A20000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* jl.D s12 00100RRR101000110RRRssssssSSSSSS. */ -+{ "jl", 0x20A30000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, -+ -+/* jl s12 00100RRR10100010RRRRssssssSSSSSS. */ -+{ "jl", 0x20A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* jl.D s12 00100RRR10100011RRRRssssssSSSSSS. */ -+{ "jl", 0x20A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, -+ -+/* jl u6 00100RRR011000100RRRuuuuuuRRRRRR. */ -+{ "jl", 0x20620000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* jlcc u6 00100RRR111000100RRRuuuuuu1QQQQQ. */ -+{ "jl", 0x20E20020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* jl.D u6 00100RRR011000110RRRuuuuuuRRRRRR. */ -+{ "jl", 0x20630000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, -+ -+/* jlcc.D u6 00100RRR111000110RRRuuuuuu1QQQQQ. */ -+{ "jl", 0x20E30020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, -+ -+/* jl u6 00100RRR01100010RRRRuuuuuuRRRRRR. */ -+{ "jl", 0x20620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* jlcc u6 00100RRR11100010RRRRuuuuuu1QQQQQ. */ -+{ "jl", 0x20E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* jl.D u6 00100RRR01100011RRRRuuuuuuRRRRRR. */ -+{ "jl", 0x20630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, -+ -+/* jlcc.D u6 00100RRR11100011RRRRuuuuuu1QQQQQ. */ -+{ "jl", 0x20E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, -+ -+/* jl limm 00100RRR001000100RRR111110RRRRRR. */ -+{ "jl", 0x20220F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* jlcc limm 00100RRR111000100RRR1111100QQQQQ. */ -+{ "jl", 0x20E20F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { C_CC }}, -+ -+/* jl limm 00100RRR00100010RRRR111110RRRRRR. */ -+{ "jl", 0x20220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* jlcc limm 00100RRR11100010RRRR1111100QQQQQ. */ -+{ "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { C_CC }}, -+ -+/* jli_s u10 010110uuuuuuuuuu. */ -+{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JLI, CD1, { OPERAND_UIMM10_6_S }, { 0 }}, -+{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JLI, CD1, { OPERAND_UIMM10_6_S_JLIOFF }, { 0 }}, -+ -+/* jl_s b 01111bbb01000000. */ -+{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* jl_s.D b 01111bbb01100000. */ -+{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* jl_s b 01111bbb01000000. */ -+{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* jl_s.D b 01111bbb01100000. */ -+{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* jne_s OPERAND_BLINK 0111110111100000. */ -+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_NE }}, -+ -+/* jne_s OPERAND_BLINK 0111110111100000. */ -+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_NE }}, -+ -+/* j_s b 01111bbb00000000. */ -+{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j_s.D b 01111bbb00100000. */ -+{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* j_s OPERAND_BLINK 0111111011100000. */ -+{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j_s.D OPERAND_BLINK 0111111111100000. */ -+{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* j_s b 01111bbb00000000. */ -+{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j_s.D b 01111bbb00100000. */ -+{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* j_s OPERAND_BLINK 0111111011100000. */ -+{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* j_s.D OPERAND_BLINK 0111111111100000. */ -+{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_DHARD }}, -+ -+/* kflag c 00100RRR001010011RRRCCCCCCRRRRRR. */ -+{ "kflag", 0x20298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* kflag<.cc> c 00100RRR111010011RRRCCCCCC0QQQQQ. */ -+{ "kflag", 0x20E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { C_CC }}, -+ -+/* kflag u6 00100RRR011010011RRRuuuuuuRRRRRR. */ -+{ "kflag", 0x20698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* kflag<.cc> u6 00100RRR111010011RRRuuuuuu1QQQQQ. */ -+{ "kflag", 0x20E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* kflag s12 00100RRR101010011RRRssssssSSSSSS. */ -+{ "kflag", 0x20A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* kflag limm 00100RRR001010011RRR111110RRRRRR. */ -+{ "kflag", 0x20298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* kflag<.cc> limm 00100RRR111010011RRR1111100QQQQQ. */ -+{ "kflag", 0x20E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { C_CC }}, -+ -+/* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110. */ -+{ "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prefetch b 00010bbb000000000BBB0RR000111110. */ -+{ "prefetch", 0x1000003E, 0xF8FF89FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetch<.aa> b,s9 00010bbbssssssssSBBB0aa000111110. */ -+{ "prefetch", 0x1000003E, 0xF80009FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, -+ -+/* prefetch<.aa> b,limm 00100bbbaa1100000BBB111110111110. */ -+{ "prefetch", 0x20300FBE, 0xF83F8FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prefetch<.aa> limm,c 00100110aa1100000111CCCCCC111110. */ -+{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prefetch limm,c 00100110RR1100000111CCCCCC111110. */ -+{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetch limm 000101100000000001110RR000111110. */ -+{ "prefetch", 0x1600703E, 0xFFFFF9FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetch<.aa> limm,s9 00010110ssssssssS1110aa000111110. */ -+{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, -+ -+/* prefetch limm,s9 00010110ssssssssS1110RR000111110. */ -+{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetch<.aa> limm,limm 00100110aa1100000111111110111110. */ -+{ "prefetch", 0x26307FBE, 0xFF3FFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110. */ -+{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110. */ -+{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, -+ -+/* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110. */ -+{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prealloc limm,c 00100110RR1100010111CCCCCC111110. */ -+{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prealloc limm 000101100000000001110RR001111110. */ -+{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prealloc limm,s9 00010110ssssssssS1110RR001111110. */ -+{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetchl2<.aa> b,c 00100bbbaa1100100BBBCCCCCC111110. */ -+{ "prefetchl2", 0x2032003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_RC }, { C_AA8 }}, -+ -+/* prefetchl2 b 00010bbb000000000BBB0RR000111110. */ -+{ "prefetchl2", 0x1000003E, 0xF8FF89FF, 0, MEMORY, NONE, { OPERAND_RB }, { 0 }}, -+ -+/* prefetchl2<.aa> b,s9 00010bbbssssssssSBBB0aa010111110. */ -+{ "prefetchl2", 0x100000BE, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_SIMM9_8 }, { C_AA21 }}, -+ -+/* prefetchl2<.aa> b,limm 00100bbbaa1100100BBB111110111110. */ -+{ "prefetchl2", 0x20320FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_AA8 }}, -+ -+/* prefetchl2<.aa> limm,c 00100110aa1100000111CCCCCC111110. */ -+{ "prefetchl2", 0x2630703E, 0xFF3FF03F, 0, MEMORY, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_AA8 }}, -+ -+/* prefetchl2 limm,c 00100110RR1100100111CCCCCC111110. */ -+{ "prefetchl2", 0x2632703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* prefetchl2 limm 000101100000000001110RR010111110. */ -+{ "prefetchl2", 0x160070BE, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* prefetchl2<.aa> limm,s9 00010110ssssssssS1110aa000111110. */ -+{ "prefetchl2", 0x1600703E, 0xFF0079FF, 0, MEMORY, NONE, { OPERAND_LIMM, OPERAND_SIMM9_8 }, { C_AA21 }}, -+ -+/* prefetchl2 limm,s9 00010110ssssssssS1110RR010111110. */ -+{ "prefetchl2", 0x160070BE, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_SIMM9_8 }, { 0 }}, -+ -+/* prefetchl2<.aa> limm,limm 00100110aa1100000111111110111110. */ -+{ "prefetchl2", 0x26307FBE, 0xFF3FFFFF, 0, MEMORY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_AA8 }}, -+ -+/* prefetchw<.aa> b,c 00100bbbaa1100001BBBCCCCCC111110. */ -+{ "prefetchw", 0x2030803E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prefetchw<.aa> b,s9 00010bbbssssssssSBBB1aa000111110. */ -+{ "prefetchw", 0x1000083E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, -+ -+/* prefetchw<.aa> b,limm 00100bbbaa1100001BBB111110111110. */ -+{ "prefetchw", 0x20308FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }}, -+ -+/* prefetchw limm,c 00100110RR1100001111CCCCCC111110. */ -+{ "prefetchw", 0x2630F03E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetchw limm 000101100000000001111RR000111110. */ -+{ "prefetchw", 0x1600783E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* prefetchw limm,s9 00010110ssssssssS1111RR000111110. */ -+{ "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld<.di><.aa><.x> a,b 00010bbb000000000BBBDaaZZXAAAAAA. */ -+{ "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, -+ -+/* ld<.di><.aa><.x> a,b,c 00100bbbaa110ZZXDBBBCCCCCCAAAAAA. */ -+{ "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, -+ -+/* ld<.di><.aa><.x> 0,b 00010bbb000000000BBBDaaZZX111110. */ -+{ "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, -+ -+/* ld<.di><.aa><.x> 0,b,c 00100bbbaa110ZZXDBBBCCCCCC111110. */ -+{ "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, -+ -+/* ld<.di><.aa><.x> a,b,s9 00010bbbssssssssSBBBDaaZZXAAAAAA. */ -+{ "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, -+ -+/* ld<.di><.aa><.x> 0,b,s9 00010bbbssssssssSBBBDaaZZX111110. */ -+{ "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, -+ -+/* ld<.di><.x> a,limm 00010110000000000111DRRZZXAAAAAA. */ -+{ "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }}, -+ -+/* ld<.di><.aa><.x> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */ -+{ "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, -+ -+/* ld<.di><.aa><.x> a,limm,c 00100110aa110ZZXD111CCCCCCAAAAAA. */ -+{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, -+ -+/* ld<.di><.x> a,limm,c 00100110RR110ZZXD111CCCCCCAAAAAA. */ -+{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}, -+ -+/* ld<.di><.x> 0,limm 00010110000000000111DRRZZX111110. */ -+{ "ld", 0x1600703E, 0xFFFFF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }}, -+ -+/* ld<.di><.aa><.x> 0,b,limm 00100bbbaa110ZZXDBBB111110111110. */ -+{ "ld", 0x20300FBE, 0xF8380FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, -+ -+/* ld<.di><.aa><.x> 0,limm,c 00100110aa110ZZXD111CCCCCC111110. */ -+{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, -+ -+/* ld<.di><.x> 0,limm,c 00100110RR110ZZXD111CCCCCC111110. */ -+{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}, -+ -+/* ld<.di><.aa><.x> a,limm,s9 00010110ssssssssS111DaaZZXAAAAAA. */ -+{ "ld", 0x16007000, 0xFF007000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, -+ -+/* ld<.di><.aa><.x> 0,limm,s9 00010110ssssssssS111DaaZZX111110. */ -+{ "ld", 0x1600703E, 0xFF00703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, -+ -+/* ld<.di><.aa><.x> a,limm,limm 00100110aa110ZZXD111111110AAAAAA. */ -+{ "ld", 0x26307F80, 0xFF387FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, -+ -+/* ld<.di><.aa><.x> 0,limm,limm 00100110aa110ZZXD111111110111110. */ -+{ "ld", 0x26307FBE, 0xFF387FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, -+ -+/* ldb_s a,b,c 01100bbbccc01aaa. */ -+{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* ldb_s c,b,u5 10001bbbcccuuuuu. */ -+{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* ldb_s b,SP,u7 11000bbb001uuuuu. */ -+{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* ldb_s OPERAND_R0,GP,s9 1100101sssssssss. */ -+{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM9_7_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* ldd<.di><.aa> a,b 00010bbb000000000BBBDaa110AAAAAA. */ -+{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, -+ -+/* ldd<.di><.aa> a,b,c 00100bbbaa110110DBBBCCCCCCAAAAAA. */ -+{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, -+ -+/* ldd<.di><.aa> 0,b 00010bbb000000000BBBDaa110111110. */ -+{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, -+ -+/* ldd<.di><.aa> 0,b,c 00100bbbaa110110DBBBCCCCCC111110. */ -+{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, -+ -+/* ldd<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa110AAAAAA. */ -+{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, -+ -+/* ldd<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa110111110. */ -+{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, -+ -+/* ldd<.di> a,limm 00010110000000000111DRR110AAAAAA. */ -+{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI20, C_ZZ_D }}, -+ -+/* ldd<.di><.aa> a,b,limm 00100bbbaa110110DBBB111110AAAAAA. */ -+{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, -+ -+/* ldd<.di> a,limm,c 00100110RR110110D111CCCCCCAAAAAA. */ -+{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_ZZ_D }}, -+ -+/* ldd<.di> 0,limm 00010110000000000111DRR110111110. */ -+{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI20, C_ZZ_D }}, -+ -+/* ldd<.di><.aa> 0,b,limm 00100bbbaa110110DBBB111110111110. */ -+{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, -+ -+/* ldd<.di> 0,limm,c 00100110RR110110D111CCCCCC111110. */ -+{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_ZZ_D }}, -+ -+/* ldd<.di><.aa> a,limm,s9 00010110ssssssssS111Daa110AAAAAA. */ -+{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, -+ -+/* ldd<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa110111110. */ -+{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, -+ -+/* ldh_s a,b,c 01100bbbccc10aaa. */ -+{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* ldh_s c,b,u6 10010bbbcccuuuuu. */ -+{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* ldh_s.X c,b,u6 10011bbbcccuuuuu. */ -+{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_XHARD, C_ZZ_H }}, -+ -+/* ldh_s OPERAND_R0,GP,s10 1100110sssssssss. */ -+{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM10_A16_7_Sbis, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* ldi b,c 00100bbb00100110RBBBCCCCCCRRRRRR. */ -+{ "ldi", 0x20260000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ldi 0,c 0010011000100110R111CCCCCCRRRRRR. */ -+{ "ldi", 0x26267000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ldi b,u6 00100bbb01100110RBBBuuuuuu000000. */ -+{ "ldi", 0x20660000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ldi 0,u6 0010011001100110R111uuuuuu000000. */ -+{ "ldi", 0x26667000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ldi<.cc> b,u6 00100bbb11100110RBBBuuuuuu1QQQQQ. */ -+{ "ldi", 0x20E60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* ldi<.cc> 0,u6 0010011011100110R111uuuuuu1QQQQQ. */ -+{ "ldi", 0x26E67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, -+ -+/* ldi b,s12 00100bbb10100110RBBBssssssSSSSSS. */ -+{ "ldi", 0x20A60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ldi 0,s12 0010011010100110R111ssssssSSSSSS. */ -+{ "ldi", 0x26A67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ldi b,limm 00100bbb00100110RBBB111110RRRRRR. */ -+{ "ldi", 0x20260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ldi 0,limm 0010011000100110R111111110RRRRRR. */ -+{ "ldi", 0x26267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ldi_s b,u7 01010bbbUUUU1uuu. */ -+{ "ldi_s", 0x00005008, 0x0000F808, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_UIMM7_13_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ldm a,u6,b 00101bbb01001100RBBBRuuuuuAAAAAA. */ -+{ "ldm", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }}, -+ -+/* ldm 0,u6,b 00101bbb01001100RBBBRuuuuu111110. */ -+{ "ldm", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }}, -+ -+/* ldm a,u6,limm 0010111001001100R111RuuuuuAAAAAA. */ -+{ "ldm", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }}, -+ -+/* ldm 0,u6,limm 0010111001001100R111Ruuuuu111110. */ -+{ "ldm", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }}, -+ -+/* ldw_s a,b,c 01100bbbccc10aaa. */ -+{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* ldw_s c,b,u6 10010bbbcccuuuuu. */ -+{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* ldw_s.X c,b,u6 10011bbbcccuuuuu. */ -+{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_XHARD, C_ZZ_H }}, -+ -+/* ldw_s OPERAND_R0,GP,s10 1100110sssssssss. */ -+{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM10_A16_7_Sbis, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* ld_s a,b,c 01100bbbccc00aaa. */ -+{ "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s.AS a,b,c 01001bbbccc00aaa. */ -+{ "ld_s", 0x00004800, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_AS }}, -+ -+/* ld_s OPERAND_R0,h,u5 01000U00hhhuu1HH. */ -+{ "ld_s", 0x00004004, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_RH_S, OPERAND_UIMM5_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s OPERAND_R1,h,u5 01000U01hhhuu1HH. */ -+{ "ld_s", 0x00004104, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R1_S, OPERAND_BRAKET, OPERAND_RH_S, OPERAND_UIMM5_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s OPERAND_R2,h,u5 01000U10hhhuu1HH. */ -+{ "ld_s", 0x00004204, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R2_S, OPERAND_BRAKET, OPERAND_RH_S, OPERAND_UIMM5_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s OPERAND_R3,h,u5 01000U11hhhuu1HH. */ -+{ "ld_s", 0x00004304, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R3_S, OPERAND_BRAKET, OPERAND_RH_S, OPERAND_UIMM5_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s b,SP,u7 11000bbb000uuuuu. */ -+{ "ld_s", 0x0000C000, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s c,b,u7 10000bbbcccuuuuu. */ -+{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s b,PCL,u10 11010bbbuuuuuuuu. */ -+{ "ld_s", 0x0000D000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_PCL_S, OPERAND_UIMM10_A32_8_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s OPERAND_R0,GP,s11 1100100sssssssss. */ -+{ "ld_s", 0x0000C800, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* ld_s OPERAND_R1,GP,s11 01010SSSSSS00sss. */ -+{ "ld_s", 0x00005000, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R1_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_13_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* leave_s u7 11000UUU110uuuu0. */ -+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { OPERAND_UIMM7_11_S }, { 0 }}, -+ -+/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */ -+{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> 0,c 0010011000101111D111CCCCCC010000. */ -+{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000. */ -+{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> 0,u6 0010011001101111D111uuuuuu010000. */ -+{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> b,limm 00100bbb00101111DBBB111110010000. */ -+{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llock<.di> 0,limm 0010011000101111D111111110010000. */ -+{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llockd<.di> b,c 00100bbb00101111DBBBCCCCCC010010. */ -+{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llockd<.di> 0,c 0010011000101111D111CCCCCC010010. */ -+{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llockd<.di> b,u6 00100bbb01101111DBBBuuuuuu010010. */ -+{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llockd<.di> 0,u6 0010011001101111D111uuuuuu010010. */ -+{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llockd<.di> b,limm 00100bbb00101111DBBB111110010010. */ -+{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* llockd<.di> 0,limm 0010011000101111D111111110010010. */ -+{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* lp s13 00100RRR101010000RRRssssssSSSSSS. */ -+{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, NONE, { OPERAND_SIMM13_A16_20 }, { 0 }}, -+ -+/* lp s13 00100RRR10101000RRRRssssssSSSSSS. */ -+{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { OPERAND_SIMM13_A16_20 }, { 0 }}, -+ -+/* lp u7 00100RRR111010000RRRuuuuuu1QQQQQ. */ -+{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { C_CC }}, -+ -+/* lp u7 00100RRR011010000RRRuuuuuuRRRRRR. */ -+{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { 0 }}, -+ -+/* lp u7 00100RRR11101000RRRRuuuuuu1QQQQQ. */ -+{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { C_CC }}, -+ -+/* lp u7 00100RRR01101000RRRRuuuuuuRRRRRR. */ -+{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { 0 }}, -+ -+/* lr b,c 00100bbb001010100BBBCCCCCCRRRRRR. */ -+{ "lr", 0x202A0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,c 00100110001010100111CCCCCCRRRRRR. */ -+{ "lr", 0x262A7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,c 00100bbb00101010RBBBCCCCCCRRRRRR. */ -+{ "lr", 0x202A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,c 0010011000101010R111CCCCCCRRRRRR. */ -+{ "lr", 0x262A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,u6 00100bbb011010100BBBuuuuuu000000. */ -+{ "lr", 0x206A0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,u6 00100110011010100111uuuuuu000000. */ -+{ "lr", 0x266A7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,u6 00100bbb01101010RBBBuuuuuu000000. */ -+{ "lr", 0x206A0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,u6 0010011001101010R111uuuuuu000000. */ -+{ "lr", 0x266A7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,s12 00100bbb101010100BBBssssssSSSSSS. */ -+{ "lr", 0x20AA0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,s12 00100110101010100111ssssssSSSSSS. */ -+{ "lr", 0x26AA7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,s12 00100bbb10101010RBBBssssssSSSSSS. */ -+{ "lr", 0x20AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,s12 0010011010101010R111ssssssSSSSSS. */ -+{ "lr", 0x26AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,limm 00100bbb001010100BBB111110RRRRRR. */ -+{ "lr", 0x202A0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,limm 00100110001010100111111110RRRRRR. */ -+{ "lr", 0x262A7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr b,limm 00100bbb00101010RBBB111110RRRRRR. */ -+{ "lr", 0x202A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lr 0,limm 0010011000101010R111111110RRRRRR. */ -+{ "lr", 0x262A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* lsl16<.f> b,c 00101bbb00101111FBBBCCCCCC001010. */ -+{ "lsl16", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsl16<.f> 0,c 0010111000101111F111CCCCCC001010. */ -+{ "lsl16", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsl16<.f> b,u6 00101bbb01101111FBBBuuuuuu001010. */ -+{ "lsl16", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsl16<.f> 0,u6 0010111001101111F111uuuuuu001010. */ -+{ "lsl16", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsl16<.f> b,limm 00101bbb00101111FBBB111110001010. */ -+{ "lsl16", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsl16<.f> 0,limm 0010111000101111F111111110001010. */ -+{ "lsl16", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsl8<.f> b,c 00101bbb00101111FBBBCCCCCC001111. */ -+{ "lsl8", 0x282F000F, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsl8<.f> 0,c 0010111000101111F111CCCCCC001111. */ -+{ "lsl8", 0x2E2F700F, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsl8<.f> b,u6 00101bbb01101111FBBBuuuuuu001111. */ -+{ "lsl8", 0x286F000F, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsl8<.f> 0,u6 0010111001101111F111uuuuuu001111. */ -+{ "lsl8", 0x2E6F700F, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsl8<.f> b,limm 00101bbb00101111FBBB111110001111. */ -+{ "lsl8", 0x282F0F8F, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsl8<.f> 0,limm 0010111000101111F111111110001111. */ -+{ "lsl8", 0x2E2F7F8F, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f> b,c 00100bbb00101111FBBBCCCCCC000010. */ -+{ "lsr", 0x202F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> 0,c 0010011000101111F111CCCCCC000010. */ -+{ "lsr", 0x262F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> a,b,c 00101bbb00000001FBBBCCCCCCAAAAAA. */ -+{ "lsr", 0x28010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> 0,b,c 00101bbb00000001FBBBCCCCCC111110. */ -+{ "lsr", 0x2801003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f><.cc> b,b,c 00101bbb11000001FBBBCCCCCC0QQQQQ. */ -+{ "lsr", 0x28C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* lsr<.f> b,u6 00100bbb01101111FBBBuuuuuu000010. */ -+{ "lsr", 0x206F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f> 0,u6 0010011001101111F111uuuuuu000010. */ -+{ "lsr", 0x266F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f> a,b,u6 00101bbb01000001FBBBuuuuuuAAAAAA. */ -+{ "lsr", 0x28410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f> 0,b,u6 00101bbb01000001FBBBuuuuuu111110. */ -+{ "lsr", 0x2841003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f><.cc> b,b,u6 00101bbb11000001FBBBuuuuuu1QQQQQ. */ -+{ "lsr", 0x28C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* lsr<.f> b,b,s12 00101bbb10000001FBBBssssssSSSSSS. */ -+{ "lsr", 0x28810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* lsr<.f> b,limm 00100bbb00101111FBBB111110000010. */ -+{ "lsr", 0x202F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f> 0,limm 0010011000101111F111111110000010. */ -+{ "lsr", 0x262F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f> a,limm,c 0010111000000001F111CCCCCCAAAAAA. */ -+{ "lsr", 0x2E017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> a,b,limm 00101bbb00000001FBBB111110AAAAAA. */ -+{ "lsr", 0x28010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f> 0,limm,c 0010111000000001F111CCCCCC111110. */ -+{ "lsr", 0x2E01703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsr<.f> 0,b,limm 00101bbb00000001FBBB111110111110. */ -+{ "lsr", 0x28010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr<.f><.cc> b,b,limm 00101bbb11000001FBBB1111100QQQQQ. */ -+{ "lsr", 0x28C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* lsr<.f><.cc> 0,limm,c 0010111011000001F111CCCCCC0QQQQQ. */ -+{ "lsr", 0x2EC17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* lsr<.f> a,limm,u6 0010111001000001F111uuuuuuAAAAAA. */ -+{ "lsr", 0x2E417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f> 0,limm,u6 0010111001000001F111uuuuuu111110. */ -+{ "lsr", 0x2E41703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr<.f><.cc> 0,limm,u6 0010111011000001F111uuuuuu1QQQQQ. */ -+{ "lsr", 0x2EC17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* lsr<.f> 0,limm,s12 0010111010000001F111ssssssSSSSSS. */ -+{ "lsr", 0x2E817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* lsr<.f> a,limm,limm 0010111000000001F111111110AAAAAA. */ -+{ "lsr", 0x2E017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* lsr<.f> 0,limm,limm 0010111000000001F111111110111110. */ -+{ "lsr", 0x2E017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* lsr<.f><.cc> 0,limm,limm 0010111011000001F1111111100QQQQQ. */ -+{ "lsr", 0x2EC17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* lsr16<.f> b,c 00101bbb00101111FBBBCCCCCC001011. */ -+{ "lsr16", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr16<.f> 0,c 0010111000101111F111CCCCCC001011. */ -+{ "lsr16", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001011. */ -+{ "lsr16", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr16<.f> 0,u6 0010111001101111F111uuuuuu001011. */ -+{ "lsr16", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr16<.f> b,limm 00101bbb00101111FBBB111110001011. */ -+{ "lsr16", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr16<.f> 0,limm 0010111000101111F111111110001011. */ -+{ "lsr16", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr8<.f> b,c 00101bbb00101111FBBBCCCCCC001110. */ -+{ "lsr8", 0x282F000E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsr8<.f> 0,c 0010111000101111F111CCCCCC001110. */ -+{ "lsr8", 0x2E2F700E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* lsr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001110. */ -+{ "lsr8", 0x286F000E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr8<.f> 0,u6 0010111001101111F111uuuuuu001110. */ -+{ "lsr8", 0x2E6F700E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsr8<.f> b,limm 00101bbb00101111FBBB111110001110. */ -+{ "lsr8", 0x282F0F8E, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsr8<.f> 0,limm 0010111000101111F111111110001110. */ -+{ "lsr8", 0x2E2F7F8E, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* lsrdw<.f> a,b,c 00101bbb00100011FBBBCCCCCCAAAAAA. */ -+{ "lsrdw", 0x28230000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsrdw<.f> 0,b,c 00101bbb00100011FBBBCCCCCC111110. */ -+{ "lsrdw", 0x2823003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* lsrdw<.f><.cc> b,b,c 00101bbb11100011FBBBCCCCCC0QQQQQ. */ -+{ "lsrdw", 0x28E30000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* lsrdw<.f> a,b,u6 00101bbb01100011FBBBuuuuuuAAAAAA. */ -+{ "lsrdw", 0x28630000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrdw<.f> 0,b,u6 00101bbb01100011FBBBuuuuuu111110. */ -+{ "lsrdw", 0x2863003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrdw<.f><.cc> b,b,u6 00101bbb11100011FBBBuuuuuu1QQQQQ. */ -+{ "lsrdw", 0x28E30020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* lsrdw<.f> b,b,s12 00101bbb10100011FBBBssssssSSSSSS. */ -+{ "lsrdw", 0x28A30000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* lsrdw<.f> a,limm,c 0010111000100011F111CCCCCCAAAAAA. */ -+{ "lsrdw", 0x2E237000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsrdw<.f> a,b,limm 00101bbb00100011FBBB111110AAAAAA. */ -+{ "lsrdw", 0x28230F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsrdw<.f> 0,limm,c 0010111000100011F111CCCCCC111110. */ -+{ "lsrdw", 0x2E23703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* lsrdw<.f> 0,b,limm 00101bbb00100011FBBB111110111110. */ -+{ "lsrdw", 0x28230FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* lsrdw<.f><.cc> 0,limm,c 0010111011100011F111CCCCCC0QQQQQ. */ -+{ "lsrdw", 0x2EE37000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* lsrdw<.f><.cc> b,b,limm 00101bbb11100011FBBB1111100QQQQQ. */ -+{ "lsrdw", 0x28E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* lsrdw<.f> a,limm,u6 0010111001100011F111uuuuuuAAAAAA. */ -+{ "lsrdw", 0x2E637000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrdw<.f> 0,limm,u6 0010111001100011F111uuuuuu111110. */ -+{ "lsrdw", 0x2E63703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* lsrdw<.f><.cc> 0,limm,u6 0010111011100011F111uuuuuu1QQQQQ. */ -+{ "lsrdw", 0x2EE37020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* lsrdw<.f> 0,limm,s12 0010111010100011F111ssssssSSSSSS. */ -+{ "lsrdw", 0x2EA37000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* lsrdw<.f> a,limm,limm 0010111000100011F111111110AAAAAA. */ -+{ "lsrdw", 0x2E237F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* lsrdw<.f> 0,limm,limm 0010111000100011F111111110111110. */ -+{ "lsrdw", 0x2E237FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* lsrdw<.f><.cc> 0,limm,limm 0010111011100011F1111111100QQQQQ. */ -+{ "lsrdw", 0x2EE37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* lsr_s b,c 01111bbbccc11101. */ -+{ "lsr_s", 0x0000781D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* lsr_s b,b,c 01111bbbccc11001. */ -+{ "lsr_s", 0x00007819, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* lsr_s b,b,u5 10111bbb001uuuuu. */ -+{ "lsr_s", 0x0000B820, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* mac<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA. */ -+{ "mac", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mac<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110. */ -+{ "mac", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mac<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ. */ -+{ "mac", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mac<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA. */ -+{ "mac", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mac<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110. */ -+{ "mac", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mac<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ. */ -+{ "mac", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mac<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS. */ -+{ "mac", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mac<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA. */ -+{ "mac", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mac<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA. */ -+{ "mac", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mac<.f> 0,limm,c 0010111000001110F111CCCCCC111110. */ -+{ "mac", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mac<.f> 0,b,limm 00101bbb00001110FBBB111110111110. */ -+{ "mac", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mac<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ. */ -+{ "mac", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mac<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ. */ -+{ "mac", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mac<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA. */ -+{ "mac", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mac<.f> 0,limm,u6 0010111001001110F111uuuuuu111110. */ -+{ "mac", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mac<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ. */ -+{ "mac", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mac<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS. */ -+{ "mac", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mac<.f> a,limm,limm 0010111000001110F111111110AAAAAA. */ -+{ "mac", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mac<.f> 0,limm,limm 0010111000001110F111111110111110. */ -+{ "mac", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mac<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ. */ -+{ "mac", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macd<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA. */ -+{ "macd", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macd<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110. */ -+{ "macd", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macd<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ. */ -+{ "macd", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macd<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA. */ -+{ "macd", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macd<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110. */ -+{ "macd", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macd<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ. */ -+{ "macd", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macd<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS. */ -+{ "macd", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macd<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA. */ -+{ "macd", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macd<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA. */ -+{ "macd", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macd<.f> 0,limm,c 0010111000011010F111CCCCCC111110. */ -+{ "macd", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macd<.f> 0,b,limm 00101bbb00011010FBBB111110111110. */ -+{ "macd", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macd<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ. */ -+{ "macd", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macd<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ. */ -+{ "macd", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macd<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA. */ -+{ "macd", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macd<.f> 0,limm,u6 0010111001011010F111uuuuuu111110. */ -+{ "macd", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macd<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ. */ -+{ "macd", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macd<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS. */ -+{ "macd", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macd<.f> a,limm,limm 0010111000011010F111111110AAAAAA. */ -+{ "macd", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macd<.f> 0,limm,limm 0010111000011010F111111110111110. */ -+{ "macd", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macd<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ. */ -+{ "macd", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macdf<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA. */ -+{ "macdf", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdf<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110. */ -+{ "macdf", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdf<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ. */ -+{ "macdf", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdf<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA. */ -+{ "macdf", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdf<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110. */ -+{ "macdf", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdf<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ. */ -+{ "macdf", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdf<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS. */ -+{ "macdf", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdf<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA. */ -+{ "macdf", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdf<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA. */ -+{ "macdf", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdf<.f> 0,limm,c 0011011000010011F111CCCCCC111110. */ -+{ "macdf", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdf<.f> 0,b,limm 00110bbb00010011FBBB111110111110. */ -+{ "macdf", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdf<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ. */ -+{ "macdf", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macdf<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ. */ -+{ "macdf", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdf<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA. */ -+{ "macdf", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdf<.f> 0,limm,u6 0011011001010011F111uuuuuu111110. */ -+{ "macdf", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdf<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ. */ -+{ "macdf", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdf<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS. */ -+{ "macdf", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdf<.f> a,limm,limm 0011011000010011F111111110AAAAAA. */ -+{ "macdf", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdf<.f> 0,limm,limm 0011011000010011F111111110111110. */ -+{ "macdf", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdf<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ. */ -+{ "macdf", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macdu<.f> a,b,c 00101bbb00011011FBBBCCCCCCAAAAAA. */ -+{ "macdu", 0x281B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdu<.f> 0,b,c 00101bbb00011011FBBBCCCCCC111110. */ -+{ "macdu", 0x281B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdu<.f><.cc> b,b,c 00101bbb11011011FBBBCCCCCC0QQQQQ. */ -+{ "macdu", 0x28DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdu<.f> a,b,u6 00101bbb01011011FBBBuuuuuuAAAAAA. */ -+{ "macdu", 0x285B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdu<.f> 0,b,u6 00101bbb01011011FBBBuuuuuu111110. */ -+{ "macdu", 0x285B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdu<.f><.cc> b,b,u6 00101bbb11011011FBBBuuuuuu1QQQQQ. */ -+{ "macdu", 0x28DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdu<.f> b,b,s12 00101bbb10011011FBBBssssssSSSSSS. */ -+{ "macdu", 0x289B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdu<.f> a,limm,c 0010111000011011F111CCCCCCAAAAAA. */ -+{ "macdu", 0x2E1B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdu<.f> a,b,limm 00101bbb00011011FBBB111110AAAAAA. */ -+{ "macdu", 0x281B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdu<.f> 0,limm,c 0010111000011011F111CCCCCC111110. */ -+{ "macdu", 0x2E1B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdu<.f> 0,b,limm 00101bbb00011011FBBB111110111110. */ -+{ "macdu", 0x281B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdu<.f><.cc> b,b,limm 00101bbb11011011FBBB1111100QQQQQ. */ -+{ "macdu", 0x28DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macdu<.f><.cc> 0,limm,c 0010111011011011F111CCCCCC0QQQQQ. */ -+{ "macdu", 0x2EDB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdu<.f> a,limm,u6 0010111001011011F111uuuuuuAAAAAA. */ -+{ "macdu", 0x2E5B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdu<.f> 0,limm,u6 0010111001011011F111uuuuuu111110. */ -+{ "macdu", 0x2E5B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdu<.f><.cc> 0,limm,u6 0010111011011011F111uuuuuu1QQQQQ. */ -+{ "macdu", 0x2EDB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdu<.f> 0,limm,s12 0010111010011011F111ssssssSSSSSS. */ -+{ "macdu", 0x2E9B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdu<.f> a,limm,limm 0010111000011011F111111110AAAAAA. */ -+{ "macdu", 0x2E1B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdu<.f> 0,limm,limm 0010111000011011F111111110111110. */ -+{ "macdu", 0x2E1B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdu<.f><.cc> 0,limm,limm 0010111011011011F1111111100QQQQQ. */ -+{ "macdu", 0x2EDB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macdw<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */ -+{ "macdw", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdw<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110. */ -+{ "macdw", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macdw<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ. */ -+{ "macdw", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdw<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA. */ -+{ "macdw", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdw<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110. */ -+{ "macdw", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdw<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ. */ -+{ "macdw", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdw<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS. */ -+{ "macdw", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdw<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA. */ -+{ "macdw", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdw<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA. */ -+{ "macdw", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdw<.f> 0,limm,c 0010111000010000F111CCCCCC111110. */ -+{ "macdw", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macdw<.f> 0,b,limm 00101bbb00010000FBBB111110111110. */ -+{ "macdw", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macdw<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ. */ -+{ "macdw", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macdw<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ. */ -+{ "macdw", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macdw<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA. */ -+{ "macdw", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdw<.f> 0,limm,u6 0010111001010000F111uuuuuu111110. */ -+{ "macdw", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macdw<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ. */ -+{ "macdw", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macdw<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS. */ -+{ "macdw", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macdw<.f> a,limm,limm 0010111000010000F111111110AAAAAA. */ -+{ "macdw", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdw<.f> 0,limm,limm 0010111000010000F111111110111110. */ -+{ "macdw", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macdw<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ. */ -+{ "macdw", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macf<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA. */ -+{ "macf", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macf<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110. */ -+{ "macf", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macf<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ. */ -+{ "macf", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macf<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA. */ -+{ "macf", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macf<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110. */ -+{ "macf", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macf<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ. */ -+{ "macf", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macf<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS. */ -+{ "macf", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macf<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA. */ -+{ "macf", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macf<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA. */ -+{ "macf", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macf<.f> 0,limm,c 0011011000001100F111CCCCCC111110. */ -+{ "macf", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macf<.f> 0,b,limm 00110bbb00001100FBBB111110111110. */ -+{ "macf", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macf<.f><.cc> 0,limm,c 00110bbb11001100FBBB1111100QQQQQ. */ -+{ "macf", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macf<.f><.cc> b,b,limm 0011011011001100F111CCCCCC0QQQQQ. */ -+{ "macf", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macf<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA. */ -+{ "macf", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macf<.f> 0,limm,u6 0011011001001100F111uuuuuu111110. */ -+{ "macf", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macf<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ. */ -+{ "macf", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macf<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS. */ -+{ "macf", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macf<.f> a,limm,limm 0011011000001100F111111110AAAAAA. */ -+{ "macf", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macf<.f> 0,limm,limm 0011011000001100F111111110111110. */ -+{ "macf", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macf<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ. */ -+{ "macf", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macflw<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */ -+{ "macflw", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macflw<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110. */ -+{ "macflw", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macflw<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ. */ -+{ "macflw", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macflw<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA. */ -+{ "macflw", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macflw<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110. */ -+{ "macflw", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macflw<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ. */ -+{ "macflw", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macflw<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS. */ -+{ "macflw", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macflw<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA. */ -+{ "macflw", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macflw<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA. */ -+{ "macflw", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macflw<.f> 0,limm,c 0010111000110100F111CCCCCC111110. */ -+{ "macflw", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macflw<.f> 0,b,limm 00101bbb00110100FBBB111110111110. */ -+{ "macflw", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macflw<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ. */ -+{ "macflw", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macflw<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ. */ -+{ "macflw", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macflw<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA. */ -+{ "macflw", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macflw<.f> 0,limm,u6 0010111001110100F111uuuuuu111110. */ -+{ "macflw", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macflw<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ. */ -+{ "macflw", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macflw<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS. */ -+{ "macflw", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macflw<.f> a,limm,limm 0010111000110100F111111110AAAAAA. */ -+{ "macflw", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macflw<.f> 0,limm,limm 0010111000110100F111111110111110. */ -+{ "macflw", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macflw<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ. */ -+{ "macflw", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macfr<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA. */ -+{ "macfr", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macfr<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110. */ -+{ "macfr", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macfr<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ. */ -+{ "macfr", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macfr<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA. */ -+{ "macfr", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macfr<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110. */ -+{ "macfr", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macfr<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ. */ -+{ "macfr", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macfr<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS. */ -+{ "macfr", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macfr<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA. */ -+{ "macfr", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macfr<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA. */ -+{ "macfr", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macfr<.f> 0,limm,c 0011011000001101F111CCCCCC111110. */ -+{ "macfr", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macfr<.f> 0,b,limm 00110bbb00001101FBBB111110111110. */ -+{ "macfr", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macfr<.f><.cc> 0,limm,c 00110bbb11001101FBBB1111100QQQQQ. */ -+{ "macfr", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macfr<.f><.cc> b,b,limm 0011011011001101F111CCCCCC0QQQQQ. */ -+{ "macfr", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macfr<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA. */ -+{ "macfr", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macfr<.f> 0,limm,u6 0011011001001101F111uuuuuu111110. */ -+{ "macfr", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macfr<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ. */ -+{ "macfr", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macfr<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS. */ -+{ "macfr", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macfr<.f> a,limm,limm 0011011000001101F111111110AAAAAA. */ -+{ "macfr", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macfr<.f> 0,limm,limm 0011011000001101F111111110111110. */ -+{ "macfr", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macfr<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ. */ -+{ "macfr", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* machflw<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA. */ -+{ "machflw", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* machflw<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110. */ -+{ "machflw", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* machflw<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ. */ -+{ "machflw", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* machflw<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA. */ -+{ "machflw", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machflw<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110. */ -+{ "machflw", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machflw<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ. */ -+{ "machflw", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* machflw<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS. */ -+{ "machflw", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* machflw<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA. */ -+{ "machflw", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* machflw<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA. */ -+{ "machflw", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* machflw<.f> 0,limm,c 0010111000110111F111CCCCCC111110. */ -+{ "machflw", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* machflw<.f> 0,b,limm 00101bbb00110111FBBB111110111110. */ -+{ "machflw", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* machflw<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ. */ -+{ "machflw", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* machflw<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ. */ -+{ "machflw", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* machflw<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA. */ -+{ "machflw", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machflw<.f> 0,limm,u6 0010111001110111F111uuuuuu111110. */ -+{ "machflw", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machflw<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ. */ -+{ "machflw", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* machflw<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS. */ -+{ "machflw", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* machflw<.f> a,limm,limm 0010111000110111F111111110AAAAAA. */ -+{ "machflw", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* machflw<.f> 0,limm,limm 0010111000110111F111111110111110. */ -+{ "machflw", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* machflw<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ. */ -+{ "machflw", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* machlw<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA. */ -+{ "machlw", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* machlw<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110. */ -+{ "machlw", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* machlw<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ. */ -+{ "machlw", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* machlw<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA. */ -+{ "machlw", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machlw<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110. */ -+{ "machlw", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machlw<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ. */ -+{ "machlw", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* machlw<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS. */ -+{ "machlw", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* machlw<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA. */ -+{ "machlw", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* machlw<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA. */ -+{ "machlw", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* machlw<.f> 0,limm,c 0010111000110110F111CCCCCC111110. */ -+{ "machlw", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* machlw<.f> 0,b,limm 00101bbb00110110FBBB111110111110. */ -+{ "machlw", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* machlw<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ. */ -+{ "machlw", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* machlw<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ. */ -+{ "machlw", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* machlw<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA. */ -+{ "machlw", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machlw<.f> 0,limm,u6 0010111001110110F111uuuuuu111110. */ -+{ "machlw", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machlw<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ. */ -+{ "machlw", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* machlw<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS. */ -+{ "machlw", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* machlw<.f> a,limm,limm 0010111000110110F111111110AAAAAA. */ -+{ "machlw", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* machlw<.f> 0,limm,limm 0010111000110110F111111110111110. */ -+{ "machlw", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* machlw<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ. */ -+{ "machlw", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* machulw<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA. */ -+{ "machulw", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* machulw<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110. */ -+{ "machulw", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* machulw<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ. */ -+{ "machulw", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* machulw<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA. */ -+{ "machulw", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machulw<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110. */ -+{ "machulw", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machulw<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ. */ -+{ "machulw", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* machulw<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS. */ -+{ "machulw", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* machulw<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA. */ -+{ "machulw", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* machulw<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA. */ -+{ "machulw", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* machulw<.f> 0,limm,c 0010111000110101F111CCCCCC111110. */ -+{ "machulw", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* machulw<.f> 0,b,limm 00101bbb00110101FBBB111110111110. */ -+{ "machulw", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* machulw<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ. */ -+{ "machulw", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* machulw<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ. */ -+{ "machulw", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* machulw<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA. */ -+{ "machulw", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machulw<.f> 0,limm,u6 0010111001110101F111uuuuuu111110. */ -+{ "machulw", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* machulw<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ. */ -+{ "machulw", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* machulw<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS. */ -+{ "machulw", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* machulw<.f> a,limm,limm 0010111000110101F111111110AAAAAA. */ -+{ "machulw", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* machulw<.f> 0,limm,limm 0010111000110101F111111110111110. */ -+{ "machulw", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* machulw<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ. */ -+{ "machulw", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* maclw<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA. */ -+{ "maclw", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* maclw<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110. */ -+{ "maclw", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* maclw<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ. */ -+{ "maclw", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* maclw<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA. */ -+{ "maclw", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maclw<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110. */ -+{ "maclw", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maclw<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ. */ -+{ "maclw", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* maclw<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS. */ -+{ "maclw", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* maclw<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA. */ -+{ "maclw", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* maclw<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA. */ -+{ "maclw", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* maclw<.f> 0,limm,c 0010111000110011F111CCCCCC111110. */ -+{ "maclw", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* maclw<.f> 0,b,limm 00101bbb00110011FBBB111110111110. */ -+{ "maclw", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* maclw<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ. */ -+{ "maclw", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* maclw<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ. */ -+{ "maclw", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* maclw<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA. */ -+{ "maclw", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maclw<.f> 0,limm,u6 0010111001110011F111uuuuuu111110. */ -+{ "maclw", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maclw<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ. */ -+{ "maclw", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* maclw<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS. */ -+{ "maclw", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* maclw<.f> a,limm,limm 0010111000110011F111111110AAAAAA. */ -+{ "maclw", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* maclw<.f> 0,limm,limm 0010111000110011F111111110111110. */ -+{ "maclw", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* maclw<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ. */ -+{ "maclw", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macrdw<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA. */ -+{ "macrdw", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macrdw<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110. */ -+{ "macrdw", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macrdw<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ. */ -+{ "macrdw", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macrdw<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA. */ -+{ "macrdw", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macrdw<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110. */ -+{ "macrdw", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macrdw<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ. */ -+{ "macrdw", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macrdw<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS. */ -+{ "macrdw", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macrdw<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA. */ -+{ "macrdw", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macrdw<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA. */ -+{ "macrdw", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macrdw<.f> 0,limm,c 0010111000010010F111CCCCCC111110. */ -+{ "macrdw", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macrdw<.f> 0,b,limm 00101bbb00010010FBBB111110111110. */ -+{ "macrdw", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macrdw<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ. */ -+{ "macrdw", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macrdw<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ. */ -+{ "macrdw", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macrdw<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA. */ -+{ "macrdw", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macrdw<.f> 0,limm,u6 0010111001010010F111uuuuuu111110. */ -+{ "macrdw", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macrdw<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ. */ -+{ "macrdw", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macrdw<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS. */ -+{ "macrdw", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macrdw<.f> a,limm,limm 0010111000010010F111111110AAAAAA. */ -+{ "macrdw", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macrdw<.f> 0,limm,limm 0010111000010010F111111110111110. */ -+{ "macrdw", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macrdw<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ. */ -+{ "macrdw", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macrt<.f> a,b,c 00101bbb00011110FBBBCCCCCCAAAAAA. */ -+{ "macrt", 0x281E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macrt<.f> 0,b,c 00101bbb00011110FBBBCCCCCC111110. */ -+{ "macrt", 0x281E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macrt<.f><.cc> b,b,c 00101bbb11011110FBBBCCCCCC0QQQQQ. */ -+{ "macrt", 0x28DE0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macrt<.f> a,b,u6 00101bbb01011110FBBBuuuuuuAAAAAA. */ -+{ "macrt", 0x285E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macrt<.f> 0,b,u6 00101bbb01011110FBBBuuuuuu111110. */ -+{ "macrt", 0x285E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macrt<.f><.cc> b,b,u6 00101bbb11011110FBBBuuuuuu1QQQQQ. */ -+{ "macrt", 0x28DE0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macrt<.f> b,b,s12 00101bbb10011110FBBBssssssSSSSSS. */ -+{ "macrt", 0x289E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macrt<.f> a,limm,c 0010111000011110F111CCCCCCAAAAAA. */ -+{ "macrt", 0x2E1E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macrt<.f> a,b,limm 00101bbb00011110FBBB111110AAAAAA. */ -+{ "macrt", 0x281E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macrt<.f> 0,limm,c 0010111000011110F111CCCCCC111110. */ -+{ "macrt", 0x2E1E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macrt<.f> 0,b,limm 00101bbb00011110FBBB111110111110. */ -+{ "macrt", 0x281E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macrt<.f><.cc> 0,limm,c 0010111011011110F111CCCCCC0QQQQQ. */ -+{ "macrt", 0x2EDE7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macrt<.f><.cc> b,b,limm 00101bbb11011110FBBB1111100QQQQQ. */ -+{ "macrt", 0x28DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macrt<.f> a,limm,u6 0010111001011110F111uuuuuuAAAAAA. */ -+{ "macrt", 0x2E5E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macrt<.f> 0,limm,u6 0010111001011110F111uuuuuu111110. */ -+{ "macrt", 0x2E5E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macrt<.f><.cc> 0,limm,u6 0010111011011110F111uuuuuu1QQQQQ. */ -+{ "macrt", 0x2EDE7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macrt<.f> 0,limm,s12 0010111010011110F111ssssssSSSSSS. */ -+{ "macrt", 0x2E9E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macrt<.f> a,limm,limm 0010111000011110F111111110AAAAAA. */ -+{ "macrt", 0x2E1E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macrt<.f> 0,limm,limm 0010111000011110F111111110111110. */ -+{ "macrt", 0x2E1E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macrt<.f><.cc> 0,limm,limm 0010111011011110F1111111100QQQQQ. */ -+{ "macrt", 0x2EDE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mact<.f> a,b,c 00101bbb00011100FBBBCCCCCCAAAAAA. */ -+{ "mact", 0x281C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mact<.f> 0,b,c 00101bbb00011100FBBBCCCCCC111110. */ -+{ "mact", 0x281C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mact<.f><.cc> b,b,c 00101bbb11011100FBBBCCCCCC0QQQQQ. */ -+{ "mact", 0x28DC0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mact<.f> a,b,u6 00101bbb01011100FBBBuuuuuuAAAAAA. */ -+{ "mact", 0x285C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mact<.f> 0,b,u6 00101bbb01011100FBBBuuuuuu111110. */ -+{ "mact", 0x285C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mact<.f><.cc> b,b,u6 00101bbb11011100FBBBuuuuuu1QQQQQ. */ -+{ "mact", 0x28DC0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mact<.f> b,b,s12 00101bbb10011100FBBBssssssSSSSSS. */ -+{ "mact", 0x289C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mact<.f> a,limm,c 0010111000011100F111CCCCCCAAAAAA. */ -+{ "mact", 0x2E1C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mact<.f> a,b,limm 00101bbb00011100FBBB111110AAAAAA. */ -+{ "mact", 0x281C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mact<.f> 0,limm,c 0010111000011100F111CCCCCC111110. */ -+{ "mact", 0x2E1C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mact<.f> 0,b,limm 00101bbb00011100FBBB111110111110. */ -+{ "mact", 0x281C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mact<.f><.cc> 0,limm,c 0010111011011100F111CCCCCC0QQQQQ. */ -+{ "mact", 0x2EDC7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mact<.f><.cc> b,b,limm 00101bbb11011100FBBB1111100QQQQQ. */ -+{ "mact", 0x28DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mact<.f> a,limm,u6 0010111001011100F111uuuuuuAAAAAA. */ -+{ "mact", 0x2E5C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mact<.f> 0,limm,u6 0010111001011100F111uuuuuu111110. */ -+{ "mact", 0x2E5C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mact<.f><.cc> 0,limm,u6 0010111011011100F111uuuuuu1QQQQQ. */ -+{ "mact", 0x2EDC7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mact<.f> 0,limm,s12 0010111010011100F111ssssssSSSSSS. */ -+{ "mact", 0x2E9C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mact<.f> a,limm,limm 0010111000011100F111111110AAAAAA. */ -+{ "mact", 0x2E1C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mact<.f> 0,limm,limm 0010111000011100F111111110111110. */ -+{ "mact", 0x2E1C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mact<.f><.cc> 0,limm,limm 0010111011011100F1111111100QQQQQ. */ -+{ "mact", 0x2EDC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macu<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA. */ -+{ "macu", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macu<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110. */ -+{ "macu", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macu<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ. */ -+{ "macu", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macu<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA. */ -+{ "macu", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macu<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110. */ -+{ "macu", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macu<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ. */ -+{ "macu", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macu<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS. */ -+{ "macu", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macu<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA. */ -+{ "macu", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macu<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA. */ -+{ "macu", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macu<.f> 0,limm,c 0010111000001111F111CCCCCC111110. */ -+{ "macu", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macu<.f> 0,b,limm 00101bbb00001111FBBB111110111110. */ -+{ "macu", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macu<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ. */ -+{ "macu", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macu<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ. */ -+{ "macu", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macu<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA. */ -+{ "macu", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macu<.f> 0,limm,u6 0010111001001111F111uuuuuu111110. */ -+{ "macu", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macu<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ. */ -+{ "macu", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macu<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS. */ -+{ "macu", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macu<.f> a,limm,limm 0010111000001111F111111110AAAAAA. */ -+{ "macu", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macu<.f> 0,limm,limm 0010111000001111F111111110111110. */ -+{ "macu", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macu<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ. */ -+{ "macu", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macudw<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA. */ -+{ "macudw", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macudw<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110. */ -+{ "macudw", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macudw<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ. */ -+{ "macudw", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macudw<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA. */ -+{ "macudw", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macudw<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110. */ -+{ "macudw", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macudw<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ. */ -+{ "macudw", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macudw<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS. */ -+{ "macudw", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macudw<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA. */ -+{ "macudw", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macudw<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA. */ -+{ "macudw", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macudw<.f> 0,limm,c 0010111000010001F111CCCCCC111110. */ -+{ "macudw", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macudw<.f> 0,b,limm 00101bbb00010001FBBB111110111110. */ -+{ "macudw", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macudw<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ. */ -+{ "macudw", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macudw<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ. */ -+{ "macudw", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macudw<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA. */ -+{ "macudw", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macudw<.f> 0,limm,u6 0010111001010001F111uuuuuu111110. */ -+{ "macudw", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macudw<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ. */ -+{ "macudw", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macudw<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS. */ -+{ "macudw", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macudw<.f> a,limm,limm 0010111000010001F111111110AAAAAA. */ -+{ "macudw", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macudw<.f> 0,limm,limm 0010111000010001F111111110111110. */ -+{ "macudw", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macudw<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ. */ -+{ "macudw", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA. */ -+{ "macwhfm", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfm<.f> 0,b,c 00110bbb00100010FBBBCCCCCC111110. */ -+{ "macwhfm", 0x3022003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfl<.f> a,b,c 00110bbb00100110FBBBCCCCCCAAAAAA */ -+{ "macwhfl", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfl<.f> 0,b,c 00110bbb00100110FBBBCCCCCC111110 */ -+{ "macwhfl", 0x3026003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfl<.f><.cc> b,b,c 00110bbb11100110FBBBCCCCCC0QQQQQ */ -+{ "macwhfl", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> a,b,u6 00110bbb01100110FBBBuuuuuuAAAAAA */ -+{ "macwhfl", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfl<.f><.cc> b,b,u6 00110bbb11100110FBBBuuuuuu1QQQQQ */ -+{ "macwhfl", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> 0,b,u6 00110bbb01100110FBBBuuuuuu111110 */ -+{ "macwhfl", 0x3066003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfl<.f> b,b,s12 00110bbb10100110FBBBssssssSSSSSS */ -+{ "macwhfl", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfl<.f> 0,limm,c 0011011001100110F111CCCCCC111110 */ -+{ "macwhfl", 0x3666703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfl<.f> 0,b,limm 00110bbb00100110FBBB111110111110 */ -+{ "macwhfl", 0x30260FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfl<.f> a,b,limm 00110bbb00100110FBBB111110AAAAAA */ -+{ "macwhfl", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfl<.f><.cc> b,b,limm 0011011011100110F111CCCCCC0QQQQQ */ -+{ "macwhfl", 0x36E67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhfl<.f><.cc> 0,limm,c 00110bbb11100110FBBB1111100QQQQQ */ -+{ "macwhfl", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> a,limm,c 0011011000100110F111CCCCCCAAAAAA */ -+{ "macwhfl", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfl<.f><.cc> 0,limm,u6 0011011011100110F111uuuuuu1QQQQQ */ -+{ "macwhfl", 0x36E67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> 0,limm,u6 0011011001100110F111uuuuuu111110 */ -+{ "macwhfl", 0x3666703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfl<.f> a,limm,u6 0011011001100110F111uuuuuuAAAAAA */ -+{ "macwhfl", 0x36667000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfl<.f> 0,limm,s12 0011011010100110F111ssssssSSSSSS */ -+{ "macwhfl", 0x36A67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfl<.f><.cc> 0,limm,limm 0011011011100110F1111111100QQQQQ */ -+{ "macwhfl", 0x36E67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhfl<.f> 0,limm,limm 0011011000100110F111111110111110 */ -+{ "macwhfl", 0x36267FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfl<.f> a,limm,limm 0011011000100110F111111110AAAAAA */ -+{ "macwhfl", 0x36267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhflr<.f><.cc> b,b,c 00110bbb11100111FBBBCCCCCC0QQQQQ */ -+{ "macwhflr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> 0,b,c 00110bbb00100111FBBBCCCCCC111110 */ -+{ "macwhflr", 0x3027003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhflr<.f> a,b,c 00110bbb00100111FBBBCCCCCCAAAAAA */ -+{ "macwhflr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhflr<.f> 0,b,u6 00110bbb01100111FBBBuuuuuu111110 */ -+{ "macwhflr", 0x3067003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhflr<.f> a,b,u6 00110bbb01100111FBBBuuuuuuAAAAAA */ -+{ "macwhflr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhflr<.f><.cc> b,b,u6 00110bbb11100111FBBBuuuuuu1QQQQQ */ -+{ "macwhflr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> b,b,s12 00110bbb10100111FBBBssssssSSSSSS */ -+{ "macwhflr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhflr<.f> a,b,limm 00110bbb00100111FBBB111110AAAAAA */ -+{ "macwhflr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhflr<.f><.cc> 0,limm,c 00110bbb11100111FBBB1111100QQQQQ */ -+{ "macwhflr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhflr<.f><.cc> b,b,limm 0011011011100111F111CCCCCC0QQQQQ */ -+{ "macwhflr", 0x36E77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> 0,b,limm 00110bbb00100111FBBB111110111110 */ -+{ "macwhflr", 0x30270FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhflr<.f> 0,limm,c 0011011001100111F111CCCCCC111110 */ -+{ "macwhflr", 0x3667703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhflr<.f> a,limm,c 0011011000100111F111CCCCCCAAAAAA */ -+{ "macwhflr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhflr<.f><.cc> 0,limm,u6 0011011011100111F111uuuuuu1QQQQQ */ -+{ "macwhflr", 0x36E77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> 0,limm,u6 0011011001100111F111uuuuuu111110 */ -+{ "macwhflr", 0x3667703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhflr<.f> a,limm,u6 0011011001100111F111uuuuuuAAAAAA */ -+{ "macwhflr", 0x36677000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhflr<.f> 0,limm,s12 0011011010100111F111ssssssSSSSSS */ -+{ "macwhflr", 0x36A77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhflr<.f><.cc> 0,limm,limm 0011011011100111F1111111100QQQQQ */ -+{ "macwhflr", 0x36E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhflr<.f> a,limm,limm 0011011000100111F111111110AAAAAA */ -+{ "macwhflr", 0x36277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhflr<.f> 0,limm,limm 0011011000100111F111111110111110 */ -+{ "macwhflr", 0x36277FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfm<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ. */ -+{ "macwhfm", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA. */ -+{ "macwhfm", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfm<.f> 0,b,u6 00110bbb01100010FBBBuuuuuu111110. */ -+{ "macwhfm", 0x3062003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfm<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ. */ -+{ "macwhfm", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS. */ -+{ "macwhfm", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfm<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA. */ -+{ "macwhfm", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfm<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA. */ -+{ "macwhfm", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfm<.f> 0,limm,c 0011011001100010F111CCCCCC111110. */ -+{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfm<.f> 0,b,limm 00110bbb00100010FBBB111110111110. */ -+{ "macwhfm", 0x30220FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfm<.f><.cc> 0,limm,c 00110bbb11100010FBBB1111100QQQQQ. */ -+{ "macwhfm", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfm<.f><.cc> b,b,limm 0011011011100010F111CCCCCC0QQQQQ. */ -+{ "macwhfm", 0x36E27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> a,limm,u6 0011011001100010F111uuuuuuAAAAAA. */ -+{ "macwhfm", 0x36627000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfm<.f> 0,limm,u6 0011011001100010F111uuuuuu111110. */ -+{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfm<.f><.cc> 0,limm,u6 0011011011100010F111uuuuuu1QQQQQ. */ -+{ "macwhfm", 0x36E27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfm<.f> 0,limm,s12 0011011010100010F111ssssssSSSSSS. */ -+{ "macwhfm", 0x36A27000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfm<.f> a,limm,limm 0011011000100010F111111110AAAAAA. */ -+{ "macwhfm", 0x36227F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfm<.f> 0,limm,limm 0011011000100010F111111110111110. */ -+{ "macwhfm", 0x36227FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfm<.f><.cc> 0,limm,limm 0011011011100010F1111111100QQQQQ. */ -+{ "macwhfm", 0x36E27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA. */ -+{ "macwhfmr", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfmr<.f> 0,b,c 00110bbb00100011FBBBCCCCCC111110. */ -+{ "macwhfmr", 0x3023003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ. */ -+{ "macwhfmr", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA. */ -+{ "macwhfmr", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfmr<.f> 0,b,u6 00110bbb01100011FBBBuuuuuu111110. */ -+{ "macwhfmr", 0x3063003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ. */ -+{ "macwhfmr", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS. */ -+{ "macwhfmr", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfmr<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA. */ -+{ "macwhfmr", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfmr<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA. */ -+{ "macwhfmr", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfmr<.f> 0,limm,c 0011011001100011F111CCCCCC111110. */ -+{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhfmr<.f> 0,b,limm 00110bbb00100011FBBB111110111110. */ -+{ "macwhfmr", 0x30230FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> 0,limm,c 00110bbb11100011FBBB1111100QQQQQ. */ -+{ "macwhfmr", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f><.cc> b,b,limm 0011011011100011F111CCCCCC0QQQQQ. */ -+{ "macwhfmr", 0x36E37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> a,limm,u6 0011011001100011F111uuuuuuAAAAAA. */ -+{ "macwhfmr", 0x36637000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfmr<.f> 0,limm,u6 0011011001100011F111uuuuuu111110. */ -+{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> 0,limm,u6 0011011011100011F111uuuuuu1QQQQQ. */ -+{ "macwhfmr", 0x36E37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhfmr<.f> 0,limm,s12 0011011010100011F111ssssssSSSSSS. */ -+{ "macwhfmr", 0x36A37000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhfmr<.f> a,limm,limm 0011011000100011F111111110AAAAAA. */ -+{ "macwhfmr", 0x36237F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfmr<.f> 0,limm,limm 0011011000100011F111111110111110. */ -+{ "macwhfmr", 0x36237FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhfmr<.f><.cc> 0,limm,limm 0011011011100011F1111111100QQQQQ. */ -+{ "macwhfmr", 0x36E37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> a,b,c 00110bbb00101000FBBBCCCCCCAAAAAA */ -+{ "macwhkl", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhkl<.f> 0,b,c 00110bbb00101000FBBBCCCCCC111110 */ -+{ "macwhkl", 0x3028003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhkl<.f><.cc> b,b,c 00110bbb11101000FBBBCCCCCC0QQQQQ */ -+{ "macwhkl", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> 0,b,u6 00110bbb01101000FBBBuuuuuu111110 */ -+{ "macwhkl", 0x3068003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkl<.f> a,b,u6 00110bbb01101000FBBBuuuuuuAAAAAA */ -+{ "macwhkl", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkl<.f><.cc> b,b,u6 00110bbb11101000FBBBuuuuuu1QQQQQ */ -+{ "macwhkl", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> b,b,s12 00110bbb10101000FBBBssssssSSSSSS */ -+{ "macwhkl", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhkl<.f> a,b,limm 00110bbb00101000FBBB111110AAAAAA */ -+{ "macwhkl", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhkl<.f><.cc> 0,limm,c 00110bbb11101000FBBB1111100QQQQQ */ -+{ "macwhkl", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> 0,limm,c 0011011001101000F111CCCCCC111110 */ -+{ "macwhkl", 0x3668703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhkl<.f> 0,b,limm 00110bbb00101000FBBB111110111110 */ -+{ "macwhkl", 0x30280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhkl<.f> a,limm,c 0011011000101000F111CCCCCCAAAAAA */ -+{ "macwhkl", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhkl<.f><.cc> b,b,limm 0011011011101000F111CCCCCC0QQQQQ */ -+{ "macwhkl", 0x36E87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> 0,limm,u6 0011011001101000F111uuuuuu111110 */ -+{ "macwhkl", 0x3668703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkl<.f><.cc> 0,limm,u6 0011011011101000F111uuuuuu1QQQQQ */ -+{ "macwhkl", 0x36E87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> a,limm,u6 0011011001101000F111uuuuuuAAAAAA */ -+{ "macwhkl", 0x36687000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkl<.f> 0,limm,s12 0011011010101000F111ssssssSSSSSS */ -+{ "macwhkl", 0x36A87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhkl<.f><.cc> 0,limm,limm 0011011011101000F1111111100QQQQQ */ -+{ "macwhkl", 0x36E87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhkl<.f> 0,limm,limm 0011011000101000F111111110111110 */ -+{ "macwhkl", 0x36287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhkl<.f> a,limm,limm 0011011000101000F111111110AAAAAA */ -+{ "macwhkl", 0x36287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhkul<.f> a,b,c 00110bbb00101001FBBBCCCCCCAAAAAA */ -+{ "macwhkul", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhkul<.f> 0,b,c 00110bbb00101001FBBBCCCCCC111110 */ -+{ "macwhkul", 0x3029003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhkul<.f><.cc> b,b,c 00110bbb11101001FBBBCCCCCC0QQQQQ */ -+{ "macwhkul", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhkul<.f> a,b,u6 00110bbb01101001FBBBuuuuuuAAAAAA */ -+{ "macwhkul", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkul<.f> 0,b,u6 00110bbb01101001FBBBuuuuuu111110 */ -+{ "macwhkul", 0x3069003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkul<.f><.cc> b,b,u6 00110bbb11101001FBBBuuuuuu1QQQQQ */ -+{ "macwhkul", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhkul<.f> b,b,s12 00110bbb10101001FBBBssssssSSSSSS */ -+{ "macwhkul", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhkul<.f> a,b,limm 00110bbb00101001FBBB111110AAAAAA */ -+{ "macwhkul", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhkul<.f><.cc> 0,limm,c 00110bbb11101001FBBB1111100QQQQQ */ -+{ "macwhkul", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhkul<.f><.cc> b,b,limm 0011011011101001F111CCCCCC0QQQQQ */ -+{ "macwhkul", 0x36E97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhkul<.f> a,limm,c 0011011000101001F111CCCCCCAAAAAA */ -+{ "macwhkul", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhkul<.f> 0,limm,c 0011011001101001F111CCCCCC111110 */ -+{ "macwhkul", 0x3669703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhkul<.f> 0,b,limm 00110bbb00101001FBBB111110111110 */ -+{ "macwhkul", 0x30290FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhkul<.f> a,limm,u6 0011011001101001F111uuuuuuAAAAAA */ -+{ "macwhkul", 0x36697000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkul<.f><.cc> 0,limm,u6 0011011011101001F111uuuuuu1QQQQQ */ -+{ "macwhkul", 0x36E97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhkul<.f> 0,limm,u6 0011011001101001F111uuuuuu111110 */ -+{ "macwhkul", 0x3669703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhkul<.f> 0,limm,s12 0011011010101001F111ssssssSSSSSS */ -+{ "macwhkul", 0x36A97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhkul<.f> a,limm,limm 0011011000101001F111111110AAAAAA */ -+{ "macwhkul", 0x36297F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhkul<.f> 0,limm,limm 0011011000101001F111111110111110 */ -+{ "macwhkul", 0x36297FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhkul<.f><.cc> 0,limm,limm 0011011011101001F1111111100QQQQQ */ -+{ "macwhkul", 0x36E97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhl<.f> a,b,c 00110bbb00011101FBBBCCCCCCAAAAAA. */ -+{ "macwhl", 0x301D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhl<.f> 0,b,c 00110bbb00011101FBBBCCCCCC111110. */ -+{ "macwhl", 0x301D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhl<.f><.cc> b,b,c 00110bbb11011101FBBBCCCCCC0QQQQQ. */ -+{ "macwhl", 0x30DD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhl<.f> a,b,u6 00110bbb01011101FBBBuuuuuuAAAAAA. */ -+{ "macwhl", 0x305D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhl<.f> 0,b,u6 00110bbb01011101FBBBuuuuuu111110. */ -+{ "macwhl", 0x305D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhl<.f><.cc> b,b,u6 00110bbb11011101FBBBuuuuuu1QQQQQ. */ -+{ "macwhl", 0x30DD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhl<.f> b,b,s12 00110bbb10011101FBBBssssssSSSSSS. */ -+{ "macwhl", 0x309D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhl<.f> a,limm,c 0011011000011101F111CCCCCCAAAAAA. */ -+{ "macwhl", 0x361D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhl<.f> a,b,limm 00110bbb00011101FBBB111110AAAAAA. */ -+{ "macwhl", 0x301D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhl<.f> 0,limm,c 0011011000011101F111CCCCCC111110. */ -+{ "macwhl", 0x361D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhl<.f> 0,b,limm 00110bbb00011101FBBB111110111110. */ -+{ "macwhl", 0x301D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhl<.f><.cc> 0,limm,c 00110bbb11011101FBBB1111100QQQQQ. */ -+{ "macwhl", 0x30DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhl<.f><.cc> b,b,limm 0011011011011101F111CCCCCC0QQQQQ. */ -+{ "macwhl", 0x36DD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhl<.f> a,limm,u6 0011011001011101F111uuuuuuAAAAAA. */ -+{ "macwhl", 0x365D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhl<.f> 0,limm,u6 0011011001011101F111uuuuuu111110. */ -+{ "macwhl", 0x365D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhl<.f><.cc> 0,limm,u6 0011011011011101F111uuuuuu1QQQQQ. */ -+{ "macwhl", 0x36DD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhl<.f> 0,limm,s12 0011011010011101F111ssssssSSSSSS. */ -+{ "macwhl", 0x369D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhl<.f> a,limm,limm 0011011000011101F111111110AAAAAA. */ -+{ "macwhl", 0x361D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhl<.f> 0,limm,limm 0011011000011101F111111110111110. */ -+{ "macwhl", 0x361D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhl<.f><.cc> 0,limm,limm 0011011011011101F1111111100QQQQQ. */ -+{ "macwhl", 0x36DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* macwhul<.f> a,b,c 00110bbb00011111FBBBCCCCCCAAAAAA. */ -+{ "macwhul", 0x301F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhul<.f> 0,b,c 00110bbb00011111FBBBCCCCCC111110. */ -+{ "macwhul", 0x301F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* macwhul<.f><.cc> b,b,c 00110bbb11011111FBBBCCCCCC0QQQQQ. */ -+{ "macwhul", 0x30DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhul<.f> a,b,u6 00110bbb01011111FBBBuuuuuuAAAAAA. */ -+{ "macwhul", 0x305F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhul<.f> 0,b,u6 00110bbb01011111FBBBuuuuuu111110. */ -+{ "macwhul", 0x305F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhul<.f><.cc> b,b,u6 00110bbb11011111FBBBuuuuuu1QQQQQ. */ -+{ "macwhul", 0x30DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhul<.f> b,b,s12 00110bbb10011111FBBBssssssSSSSSS. */ -+{ "macwhul", 0x309F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhul<.f> a,limm,c 0011011000011111F111CCCCCCAAAAAA. */ -+{ "macwhul", 0x361F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhul<.f> a,b,limm 00110bbb00011111FBBB111110AAAAAA. */ -+{ "macwhul", 0x301F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhul<.f> 0,limm,c 0011011000011111F111CCCCCC111110. */ -+{ "macwhul", 0x361F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* macwhul<.f> 0,b,limm 00110bbb00011111FBBB111110111110. */ -+{ "macwhul", 0x301F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* macwhul<.f><.cc> 0,limm,c 00110bbb11011111FBBB1111100QQQQQ. */ -+{ "macwhul", 0x30DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* macwhul<.f><.cc> b,b,limm 0011011011011111F111CCCCCC0QQQQQ. */ -+{ "macwhul", 0x36DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* macwhul<.f> a,limm,u6 0011011001011111F111uuuuuuAAAAAA. */ -+{ "macwhul", 0x365F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhul<.f> 0,limm,u6 0011011001011111F111uuuuuu111110. */ -+{ "macwhul", 0x365F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* macwhul<.f><.cc> 0,limm,u6 0011011011011111F111uuuuuu1QQQQQ. */ -+{ "macwhul", 0x36DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* macwhul<.f> 0,limm,s12 0011011010011111F111ssssssSSSSSS. */ -+{ "macwhul", 0x369F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* macwhul<.f> a,limm,limm 0011011000011111F111111110AAAAAA. */ -+{ "macwhul", 0x361F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhul<.f> 0,limm,limm 0011011000011111F111111110111110. */ -+{ "macwhul", 0x361F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* macwhul<.f><.cc> 0,limm,limm 0011011011011111F1111111100QQQQQ. */ -+{ "macwhul", 0x36DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* max<.f> a,b,c 00100bbb00001000FBBBCCCCCCAAAAAA. */ -+{ "max", 0x20080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* max<.f> 0,b,c 00100bbb00001000FBBBCCCCCC111110. */ -+{ "max", 0x2008003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* max<.f><.cc> b,b,c 00100bbb11001000FBBBCCCCCC0QQQQQ. */ -+{ "max", 0x20C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* max<.f> a,b,u6 00100bbb01001000FBBBuuuuuuAAAAAA. */ -+{ "max", 0x20480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* max<.f> 0,b,u6 00100bbb01001000FBBBuuuuuu111110. */ -+{ "max", 0x2048003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* max<.f><.cc> b,b,u6 00100bbb11001000FBBBuuuuuu1QQQQQ. */ -+{ "max", 0x20C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* max<.f> b,b,s12 00100bbb10001000FBBBssssssSSSSSS. */ -+{ "max", 0x20880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* max<.f> a,limm,c 0010011000001000F111CCCCCCAAAAAA. */ -+{ "max", 0x26087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* max<.f> a,b,limm 00100bbb00001000FBBB111110AAAAAA. */ -+{ "max", 0x20080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* max<.f> 0,limm,c 0010011000001000F111CCCCCC111110. */ -+{ "max", 0x2608703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* max<.f> 0,b,limm 00100bbb00001000FBBB111110111110. */ -+{ "max", 0x20080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* max<.f><.cc> b,b,limm 00100bbb11001000FBBB1111100QQQQQ. */ -+{ "max", 0x20C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* max<.f><.cc> 0,limm,c 0010011011001000F111CCCCCC0QQQQQ. */ -+{ "max", 0x26C87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* max<.f> a,limm,u6 0010011001001000F111uuuuuuAAAAAA. */ -+{ "max", 0x26487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* max<.f> 0,limm,u6 0010011001001000F111uuuuuu111110. */ -+{ "max", 0x2648703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* max<.f><.cc> 0,limm,u6 0010011011001000F111uuuuuu1QQQQQ. */ -+{ "max", 0x26C87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* max<.f> 0,limm,s12 0010011010001000F111ssssssSSSSSS. */ -+{ "max", 0x26887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* max<.f> a,limm,limm 0010011000001000F111111110AAAAAA. */ -+{ "max", 0x26087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* max<.f> 0,limm,limm 0010011000001000F111111110111110. */ -+{ "max", 0x26087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* max<.f><.cc> 0,limm,limm 0010011011001000F1111111100QQQQQ. */ -+{ "max", 0x26C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* maxabssdw<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA. */ -+{ "maxabssdw", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* maxabssdw<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110. */ -+{ "maxabssdw", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* maxabssdw<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ. */ -+{ "maxabssdw", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* maxabssdw<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA. */ -+{ "maxabssdw", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxabssdw<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110. */ -+{ "maxabssdw", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxabssdw<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ. */ -+{ "maxabssdw", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* maxabssdw<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS. */ -+{ "maxabssdw", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* maxabssdw<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA. */ -+{ "maxabssdw", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* maxabssdw<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA. */ -+{ "maxabssdw", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* maxabssdw<.f> 0,limm,c 0010111000101011F111CCCCCC111110. */ -+{ "maxabssdw", 0x2E2B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* maxabssdw<.f> 0,b,limm 00101bbb00101011FBBB111110111110. */ -+{ "maxabssdw", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* maxabssdw<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ. */ -+{ "maxabssdw", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* maxabssdw<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ. */ -+{ "maxabssdw", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* maxabssdw<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA. */ -+{ "maxabssdw", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxabssdw<.f> 0,limm,u6 0010111001101011F111uuuuuu111110. */ -+{ "maxabssdw", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxabssdw<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ. */ -+{ "maxabssdw", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* maxabssdw<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS. */ -+{ "maxabssdw", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* maxabssdw<.f> a,limm,limm 0010111000101011F111111110AAAAAA. */ -+{ "maxabssdw", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* maxabssdw<.f> 0,limm,limm 0010111000101011F111111110111110. */ -+{ "maxabssdw", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* maxabssdw<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ. */ -+{ "maxabssdw", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* maxidl<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA. */ -+{ "maxidl", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* maxidl<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110. */ -+{ "maxidl", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* maxidl<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ. */ -+{ "maxidl", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* maxidl<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA. */ -+{ "maxidl", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxidl<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110. */ -+{ "maxidl", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxidl<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ. */ -+{ "maxidl", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* maxidl<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS. */ -+{ "maxidl", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* maxidl<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA. */ -+{ "maxidl", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* maxidl<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA. */ -+{ "maxidl", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* maxidl<.f> 0,limm,c 0010111000001111F111CCCCCC111110. */ -+{ "maxidl", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* maxidl<.f> 0,b,limm 00101bbb00001111FBBB111110111110. */ -+{ "maxidl", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* maxidl<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ. */ -+{ "maxidl", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* maxidl<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ. */ -+{ "maxidl", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* maxidl<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA. */ -+{ "maxidl", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxidl<.f> 0,limm,u6 0010111001001111F111uuuuuu111110. */ -+{ "maxidl", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* maxidl<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ. */ -+{ "maxidl", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* maxidl<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS. */ -+{ "maxidl", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* maxidl<.f> a,limm,limm 0010111000001111F111111110AAAAAA. */ -+{ "maxidl", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* maxidl<.f> 0,limm,limm 0010111000001111F111111110111110. */ -+{ "maxidl", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* maxidl<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ. */ -+{ "maxidl", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* min<.f> a,b,c 00100bbb00001001FBBBCCCCCCAAAAAA. */ -+{ "min", 0x20090000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* min<.f> 0,b,c 00100bbb00001001FBBBCCCCCC111110. */ -+{ "min", 0x2009003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* min<.f><.cc> b,b,c 00100bbb11001001FBBBCCCCCC0QQQQQ. */ -+{ "min", 0x20C90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* min<.f> a,b,u6 00100bbb01001001FBBBuuuuuuAAAAAA. */ -+{ "min", 0x20490000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* min<.f> 0,b,u6 00100bbb01001001FBBBuuuuuu111110. */ -+{ "min", 0x2049003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* min<.f><.cc> b,b,u6 00100bbb11001001FBBBuuuuuu1QQQQQ. */ -+{ "min", 0x20C90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* min<.f> b,b,s12 00100bbb10001001FBBBssssssSSSSSS. */ -+{ "min", 0x20890000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* min<.f> a,limm,c 0010011000001001F111CCCCCCAAAAAA. */ -+{ "min", 0x26097000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* min<.f> a,b,limm 00100bbb00001001FBBB111110AAAAAA. */ -+{ "min", 0x20090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* min<.f> 0,limm,c 0010011000001001F111CCCCCC111110. */ -+{ "min", 0x2609703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* min<.f> 0,b,limm 00100bbb00001001FBBB111110111110. */ -+{ "min", 0x20090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* min<.f><.cc> b,b,limm 00100bbb11001001FBBB1111100QQQQQ. */ -+{ "min", 0x20C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* min<.f><.cc> 0,limm,c 0010011011001001F111CCCCCC0QQQQQ. */ -+{ "min", 0x26C97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* min<.f> a,limm,u6 0010011001001001F111uuuuuuAAAAAA. */ -+{ "min", 0x26497000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* min<.f> 0,limm,u6 0010011001001001F111uuuuuu111110. */ -+{ "min", 0x2649703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* min<.f><.cc> 0,limm,u6 0010011011001001F111uuuuuu1QQQQQ. */ -+{ "min", 0x26C97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* min<.f> 0,limm,s12 0010011010001001F111ssssssSSSSSS. */ -+{ "min", 0x26897000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* min<.f> a,limm,limm 0010011000001001F111111110AAAAAA. */ -+{ "min", 0x26097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* min<.f> 0,limm,limm 0010011000001001F111111110111110. */ -+{ "min", 0x26097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* min<.f><.cc> 0,limm,limm 0010011011001001F1111111100QQQQQ. */ -+{ "min", 0x26C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* minidl<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */ -+{ "minidl", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* minidl<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */ -+{ "minidl", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* minidl<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */ -+{ "minidl", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* minidl<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */ -+{ "minidl", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minidl<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */ -+{ "minidl", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minidl<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */ -+{ "minidl", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* minidl<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */ -+{ "minidl", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* minidl<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */ -+{ "minidl", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* minidl<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */ -+{ "minidl", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* minidl<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */ -+{ "minidl", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* minidl<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */ -+{ "minidl", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* minidl<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */ -+{ "minidl", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* minidl<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */ -+{ "minidl", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* minidl<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */ -+{ "minidl", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minidl<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */ -+{ "minidl", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* minidl<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */ -+{ "minidl", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* minidl<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */ -+{ "minidl", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* minidl<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */ -+{ "minidl", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* minidl<.f> 0,limm,limm 0010111000001001F111111110111110. */ -+{ "minidl", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* minidl<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */ -+{ "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* nop 00100110010010100111000000000000. */ -+{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */ -+{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mov<.f> 0,c 0010011000001010F111CCCCCCRRRRRR. */ -+{ "mov", 0x260A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* mov<.f><.cc> b,c 00100bbb11001010FBBBCCCCCC0QQQQQ. */ -+{ "mov", 0x20CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mov<.f><.cc> 0,c 0010011011001010F111CCCCCC0QQQQQ. */ -+{ "mov", 0x26CA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mov<.f> b,u6 00100bbb01001010FBBBuuuuuuRRRRRR. */ -+{ "mov", 0x204A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mov<.f> 0,u6 0010011001001010F111uuuuuuRRRRRR. */ -+{ "mov", 0x264A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */ -+{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mov<.f><.cc> 0,u6 0010011011001010F111uuuuuu1QQQQQ. */ -+{ "mov", 0x26CA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */ -+{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mov<.f> 0,s12 0010011010001010F111ssssssSSSSSS. */ -+{ "mov", 0x268A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ -+{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mov<.f> 0,limm 0010011000001010F111111110RRRRRR. */ -+{ "mov", 0x260A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ -+{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mov<.f><.cc> 0,limm 0010011011001010F1111111100QQQQQ. */ -+{ "mov", 0x26CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mov_s b,h 01110bbbhhh01HHH. */ -+{ "mov_s", 0x00007008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_RB_S, OPERAND_R6H }, { 0 }}, -+ -+/* mov_s b,h 01110bbbhhh010HH. */ -+{ "mov_s", 0x00007008, 0x0000F81C, 0, MOVE, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { 0 }}, -+ -+/* mov_s h,b 01110bbbhhh11HHH. */ -+{ "mov_s", 0x00007018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_R6H, OPERAND_RB_S }, { 0 }}, -+ -+/* mov_s h,b 01110bbbhhh110HH. */ -+{ "mov_s", 0x00007018, 0x0000F81C, 0, MOVE, NONE, { OPERAND_RH_S, OPERAND_RB_S }, { 0 }}, -+ -+/* mov_s 0,b 01110bbb1101111H. */ -+{ "mov_s", 0x000070DE, 0x0000F8FE, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_ZA_S, OPERAND_RB_S }, { 0 }}, -+ -+/* mov_s 0,b 01110bbb11011011. */ -+{ "mov_s", 0x000070DB, 0x0000F8FF, 0, MOVE, NONE, { OPERAND_ZA_S, OPERAND_RB_S }, { 0 }}, -+ -+/* mov_s g,h 01000ggghhhGG0HH. */ -+{ "mov_s", 0x00004000, 0x0000F804, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_G_S, OPERAND_RH_S }, { 0 }}, -+ -+/* mov_s 0,h 01000110hhh110HH. */ -+{ "mov_s", 0x00004618, 0x0000FF1C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA_S, OPERAND_RH_S }, { 0 }}, -+ -+/* mov_s h,s3 01110ssshhh011HH. */ -+{ "mov_s", 0x0000700C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* mov_s 0,s3 01110sss11001111. */ -+{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA_S, OPERAND_SIMM3_5_S }, { 0 }}, -+ -+/* mov_s b,u8 11011bbbuuuuuuuu. */ -+{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB_S, OPERAND_UIMM8_8_S }, { 0 }}, -+ -+/* mov_s b,limm 01110bbb11001111. */ -+{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* mov_s b,limm 01110bbb11001011. */ -+{ "mov_s", 0x000070CB, 0x0000F8FF, 0, MOVE, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* mov_s g,limm 01000ggg110GG011. */ -+{ "mov_s", 0x000040C3, 0x0000F8E7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_G_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* mov_s 0,limm 0100011011011011. */ -+{ "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA_S, OPERAND_LIMM_S }, { 0 }}, -+ -+/* mov_s.ne b,h 01110bbbhhh111HH. */ -+{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { C_NE, C_CC_NE }}, -+ -+/* mov_s.ne b,limm 01110bbb11011111. */ -+{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { C_NE, C_CC_NE }}, -+ -+/* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA. */ -+{ "mpy", 0x201A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpy<.f> 0,b,c 00100bbb00011010FBBBCCCCCC111110. */ -+{ "mpy", 0x201A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpy<.f><.cc> b,b,c 00100bbb11011010FBBBCCCCCC0QQQQQ. */ -+{ "mpy", 0x20DA0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */ -+{ "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpy<.f> 0,b,u6 00100bbb01011010FBBBuuuuuu111110. */ -+{ "mpy", 0x205A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpy<.f><.cc> b,b,u6 00100bbb11011010FBBBuuuuuu1QQQQQ. */ -+{ "mpy", 0x20DA0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpy<.f> b,b,s12 00100bbb10011010FBBBssssssSSSSSS. */ -+{ "mpy", 0x209A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpy<.f> a,limm,c 0010011000011010F111CCCCCCAAAAAA. */ -+{ "mpy", 0x261A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ -+{ "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpy<.f> 0,limm,c 0010011000011010F111CCCCCC111110. */ -+{ "mpy", 0x261A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpy<.f> 0,b,limm 00100bbb00011010FBBB111110111110. */ -+{ "mpy", 0x201A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpy<.f><.cc> b,b,limm 00100bbb11011010FBBB1111100QQQQQ. */ -+{ "mpy", 0x20DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpy<.f><.cc> 0,limm,c 0010011011011010F111CCCCCC0QQQQQ. */ -+{ "mpy", 0x26DA7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpy<.f> a,limm,u6 0010011001011010F111uuuuuuAAAAAA. */ -+{ "mpy", 0x265A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpy<.f> 0,limm,u6 0010011001011010F111uuuuuu111110. */ -+{ "mpy", 0x265A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpy<.f><.cc> 0,limm,u6 0010011011011010F111uuuuuu1QQQQQ. */ -+{ "mpy", 0x26DA7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpy<.f> 0,limm,s12 0010011010011010F111ssssssSSSSSS. */ -+{ "mpy", 0x269A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpy<.f> a,limm,limm 0010011000011010F111111110AAAAAA. */ -+{ "mpy", 0x261A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpy<.f> 0,limm,limm 0010011000011010F111111110111110. */ -+{ "mpy", 0x261A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpy<.f><.cc> 0,limm,limm 0010011011011010F1111111100QQQQQ. */ -+{ "mpy", 0x26DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyd<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA. */ -+{ "mpyd", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyd<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110. */ -+{ "mpyd", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyd<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ. */ -+{ "mpyd", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyd<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA. */ -+{ "mpyd", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyd<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110. */ -+{ "mpyd", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyd<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ. */ -+{ "mpyd", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyd<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS. */ -+{ "mpyd", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyd<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA. */ -+{ "mpyd", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyd<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA. */ -+{ "mpyd", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyd<.f> 0,limm,c 0010111000011000F111CCCCCC111110. */ -+{ "mpyd", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyd<.f> 0,b,limm 00101bbb00011000FBBB111110111110. */ -+{ "mpyd", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyd<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ. */ -+{ "mpyd", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyd<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ. */ -+{ "mpyd", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyd<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA. */ -+{ "mpyd", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyd<.f> 0,limm,u6 0010111001011000F111uuuuuu111110. */ -+{ "mpyd", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyd<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ. */ -+{ "mpyd", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyd<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS. */ -+{ "mpyd", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyd<.f> a,limm,limm 0010111000011000F111111110AAAAAA. */ -+{ "mpyd", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyd<.f> 0,limm,limm 0010111000011000F111111110111110. */ -+{ "mpyd", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyd<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ. */ -+{ "mpyd", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpydf<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA. */ -+{ "mpydf", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpydf<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110. */ -+{ "mpydf", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpydf<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ. */ -+{ "mpydf", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpydf<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA. */ -+{ "mpydf", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydf<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110. */ -+{ "mpydf", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydf<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ. */ -+{ "mpydf", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpydf<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS. */ -+{ "mpydf", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpydf<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA. */ -+{ "mpydf", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpydf<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA. */ -+{ "mpydf", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpydf<.f> 0,limm,c 0011011000010010F111CCCCCC111110. */ -+{ "mpydf", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpydf<.f> 0,b,limm 00110bbb00010010FBBB111110111110. */ -+{ "mpydf", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpydf<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ. */ -+{ "mpydf", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpydf<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ. */ -+{ "mpydf", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpydf<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA. */ -+{ "mpydf", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydf<.f> 0,limm,u6 0011011001010010F111uuuuuu111110. */ -+{ "mpydf", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydf<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ. */ -+{ "mpydf", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpydf<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS. */ -+{ "mpydf", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpydf<.f> a,limm,limm 0011011000010010F111111110AAAAAA. */ -+{ "mpydf", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpydf<.f> 0,limm,limm 0011011000010010F111111110111110. */ -+{ "mpydf", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpydf<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ. */ -+{ "mpydf", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpydu<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA. */ -+{ "mpydu", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpydu<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110. */ -+{ "mpydu", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpydu<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ. */ -+{ "mpydu", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpydu<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA. */ -+{ "mpydu", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydu<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110. */ -+{ "mpydu", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydu<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ. */ -+{ "mpydu", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpydu<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS. */ -+{ "mpydu", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpydu<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA. */ -+{ "mpydu", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpydu<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA. */ -+{ "mpydu", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpydu<.f> 0,limm,c 0010111000011001F111CCCCCC111110. */ -+{ "mpydu", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpydu<.f> 0,b,limm 00101bbb00011001FBBB111110111110. */ -+{ "mpydu", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpydu<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ. */ -+{ "mpydu", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpydu<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ. */ -+{ "mpydu", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpydu<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA. */ -+{ "mpydu", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydu<.f> 0,limm,u6 0010111001011001F111uuuuuu111110. */ -+{ "mpydu", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpydu<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ. */ -+{ "mpydu", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpydu<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS. */ -+{ "mpydu", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpydu<.f> a,limm,limm 0010111000011001F111111110AAAAAA. */ -+{ "mpydu", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpydu<.f> 0,limm,limm 0010111000011001F111111110111110. */ -+{ "mpydu", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpydu<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ. */ -+{ "mpydu", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyf<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA. */ -+{ "mpyf", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyf<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110. */ -+{ "mpyf", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyf<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ. */ -+{ "mpyf", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyf<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA. */ -+{ "mpyf", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyf<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110. */ -+{ "mpyf", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyf<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ. */ -+{ "mpyf", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyf<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS. */ -+{ "mpyf", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyf<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA. */ -+{ "mpyf", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyf<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA. */ -+{ "mpyf", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyf<.f> 0,limm,c 0011011000001010F111CCCCCC111110. */ -+{ "mpyf", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyf<.f> 0,b,limm 00110bbb00001010FBBB111110111110. */ -+{ "mpyf", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyf<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ. */ -+{ "mpyf", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyf<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ. */ -+{ "mpyf", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyf<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA. */ -+{ "mpyf", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyf<.f> 0,limm,u6 0011011001001010F111uuuuuu111110. */ -+{ "mpyf", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyf<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ. */ -+{ "mpyf", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyf<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS. */ -+{ "mpyf", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyf<.f> a,limm,limm 0011011000001010F111111110AAAAAA. */ -+{ "mpyf", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyf<.f> 0,limm,limm 0011011000001010F111111110111110. */ -+{ "mpyf", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyf<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ. */ -+{ "mpyf", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA. */ -+{ "mpyfr", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyfr<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110. */ -+{ "mpyfr", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyfr<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ. */ -+{ "mpyfr", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA. */ -+{ "mpyfr", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyfr<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110. */ -+{ "mpyfr", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyfr<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ. */ -+{ "mpyfr", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS. */ -+{ "mpyfr", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyfr<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA. */ -+{ "mpyfr", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyfr<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA. */ -+{ "mpyfr", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyfr<.f> 0,limm,c 0011011000001011F111CCCCCC111110. */ -+{ "mpyfr", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyfr<.f> 0,b,limm 00110bbb00001011FBBB111110111110. */ -+{ "mpyfr", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyfr<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ. */ -+{ "mpyfr", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyfr<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ. */ -+{ "mpyfr", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA. */ -+{ "mpyfr", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyfr<.f> 0,limm,u6 0011011001001011F111uuuuuu111110. */ -+{ "mpyfr", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyfr<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ. */ -+{ "mpyfr", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyfr<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS. */ -+{ "mpyfr", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyfr<.f> a,limm,limm 0011011000001011F111111110AAAAAA. */ -+{ "mpyfr", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyfr<.f> 0,limm,limm 0011011000001011F111111110111110. */ -+{ "mpyfr", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyfr<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ. */ -+{ "mpyfr", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyh<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA. */ -+{ "mpyh", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyh<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110. */ -+{ "mpyh", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyh<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ. */ -+{ "mpyh", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyh<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA. */ -+{ "mpyh", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyh<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110. */ -+{ "mpyh", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyh<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ. */ -+{ "mpyh", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyh<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS. */ -+{ "mpyh", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyh<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA. */ -+{ "mpyh", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyh<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA. */ -+{ "mpyh", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyh<.f> 0,limm,c 0010011000011011F111CCCCCC111110. */ -+{ "mpyh", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyh<.f> 0,b,limm 00100bbb00011011FBBB111110111110. */ -+{ "mpyh", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyh<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ. */ -+{ "mpyh", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyh<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ. */ -+{ "mpyh", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyh<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA. */ -+{ "mpyh", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyh<.f> 0,limm,u6 0010011001011011F111uuuuuu111110. */ -+{ "mpyh", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyh<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ. */ -+{ "mpyh", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyh<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS. */ -+{ "mpyh", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyh<.f> a,limm,limm 0010011000011011F111111110AAAAAA. */ -+{ "mpyh", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyh<.f> 0,limm,limm 0010011000011011F111111110111110. */ -+{ "mpyh", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyh<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ. */ -+{ "mpyh", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyhu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA. */ -+{ "mpyhu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyhu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110. */ -+{ "mpyhu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyhu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ. */ -+{ "mpyhu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyhu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA. */ -+{ "mpyhu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyhu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110. */ -+{ "mpyhu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyhu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ. */ -+{ "mpyhu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyhu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS. */ -+{ "mpyhu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyhu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA. */ -+{ "mpyhu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyhu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA. */ -+{ "mpyhu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyhu<.f> 0,limm,c 0010011000011100F111CCCCCC111110. */ -+{ "mpyhu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyhu<.f> 0,b,limm 00100bbb00011100FBBB111110111110. */ -+{ "mpyhu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyhu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ. */ -+{ "mpyhu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyhu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ. */ -+{ "mpyhu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyhu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA. */ -+{ "mpyhu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyhu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110. */ -+{ "mpyhu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyhu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ. */ -+{ "mpyhu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyhu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS. */ -+{ "mpyhu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyhu<.f> a,limm,limm 0010011000011100F111111110AAAAAA. */ -+{ "mpyhu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyhu<.f> 0,limm,limm 0010011000011100F111111110111110. */ -+{ "mpyhu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyhu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ. */ -+{ "mpyhu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpym<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA. */ -+{ "mpym", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpym<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110. */ -+{ "mpym", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpym<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ. */ -+{ "mpym", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpym<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA. */ -+{ "mpym", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpym<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110. */ -+{ "mpym", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpym<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ. */ -+{ "mpym", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpym<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS. */ -+{ "mpym", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpym<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA. */ -+{ "mpym", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpym<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA. */ -+{ "mpym", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpym<.f> 0,limm,c 0010011000011011F111CCCCCC111110. */ -+{ "mpym", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpym<.f> 0,b,limm 00100bbb00011011FBBB111110111110. */ -+{ "mpym", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpym<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ. */ -+{ "mpym", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpym<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ. */ -+{ "mpym", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpym<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA. */ -+{ "mpym", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpym<.f> 0,limm,u6 0010011001011011F111uuuuuu111110. */ -+{ "mpym", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpym<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ. */ -+{ "mpym", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpym<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS. */ -+{ "mpym", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpym<.f> a,limm,limm 0010011000011011F111111110AAAAAA. */ -+{ "mpym", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpym<.f> 0,limm,limm 0010011000011011F111111110111110. */ -+{ "mpym", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpym<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ. */ -+{ "mpym", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpymu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA. */ -+{ "mpymu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpymu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110. */ -+{ "mpymu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpymu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ. */ -+{ "mpymu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpymu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA. */ -+{ "mpymu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpymu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110. */ -+{ "mpymu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpymu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ. */ -+{ "mpymu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpymu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS. */ -+{ "mpymu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpymu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA. */ -+{ "mpymu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpymu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA. */ -+{ "mpymu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpymu<.f> 0,limm,c 0010011000011100F111CCCCCC111110. */ -+{ "mpymu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpymu<.f> 0,b,limm 00100bbb00011100FBBB111110111110. */ -+{ "mpymu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpymu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ. */ -+{ "mpymu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpymu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ. */ -+{ "mpymu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpymu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA. */ -+{ "mpymu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpymu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110. */ -+{ "mpymu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpymu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ. */ -+{ "mpymu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpymu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS. */ -+{ "mpymu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpymu<.f> a,limm,limm 0010011000011100F111111110AAAAAA. */ -+{ "mpymu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpymu<.f> 0,limm,limm 0010011000011100F111111110111110. */ -+{ "mpymu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpymu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ. */ -+{ "mpymu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyqb<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ. */ -+{ "mpyqb", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyqb<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA. */ -+{ "mpyqb", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyqb<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ. */ -+{ "mpyqb", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyqb<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS. */ -+{ "mpyqb", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyqb<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA. */ -+{ "mpyqb", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyqb<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA. */ -+{ "mpyqb", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyqb<.f><.cc> b,b,limm 00110bbb11100101FBBB1111100QQQQQ. */ -+{ "mpyqb", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyu<.f> a,b,c 00100bbb00011101FBBBCCCCCCAAAAAA. */ -+{ "mpyu", 0x201D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyu<.f> 0,b,c 00100bbb00011101FBBBCCCCCC111110. */ -+{ "mpyu", 0x201D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyu<.f><.cc> b,b,c 00100bbb11011101FBBBCCCCCC0QQQQQ. */ -+{ "mpyu", 0x20DD0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyu<.f> a,b,u6 00100bbb01011101FBBBuuuuuuAAAAAA. */ -+{ "mpyu", 0x205D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyu<.f> 0,b,u6 00100bbb01011101FBBBuuuuuu111110. */ -+{ "mpyu", 0x205D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyu<.f><.cc> b,b,u6 00100bbb11011101FBBBuuuuuu1QQQQQ. */ -+{ "mpyu", 0x20DD0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyu<.f> b,b,s12 00100bbb10011101FBBBssssssSSSSSS. */ -+{ "mpyu", 0x209D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyu<.f> a,limm,c 0010011000011101F111CCCCCCAAAAAA. */ -+{ "mpyu", 0x261D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyu<.f> a,b,limm 00100bbb00011101FBBB111110AAAAAA. */ -+{ "mpyu", 0x201D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyu<.f> 0,limm,c 0010011000011101F111CCCCCC111110. */ -+{ "mpyu", 0x261D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyu<.f> 0,b,limm 00100bbb00011101FBBB111110111110. */ -+{ "mpyu", 0x201D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyu<.f><.cc> b,b,limm 00100bbb11011101FBBB1111100QQQQQ. */ -+{ "mpyu", 0x20DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyu<.f><.cc> 0,limm,c 0010011011011101F111CCCCCC0QQQQQ. */ -+{ "mpyu", 0x26DD7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyu<.f> a,limm,u6 0010011001011101F111uuuuuuAAAAAA. */ -+{ "mpyu", 0x265D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyu<.f> 0,limm,u6 0010011001011101F111uuuuuu111110. */ -+{ "mpyu", 0x265D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyu<.f><.cc> 0,limm,u6 0010011011011101F111uuuuuu1QQQQQ. */ -+{ "mpyu", 0x26DD7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyu<.f> 0,limm,s12 0010011010011101F111ssssssSSSSSS. */ -+{ "mpyu", 0x269D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyu<.f> a,limm,limm 0010011000011101F111111110AAAAAA. */ -+{ "mpyu", 0x261D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyu<.f> 0,limm,limm 0010011000011101F111111110111110. */ -+{ "mpyu", 0x261D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyu<.f><.cc> 0,limm,limm 0010011011011101F1111111100QQQQQ. */ -+{ "mpyu", 0x26DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA. */ -+{ "mpyuw", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110. */ -+{ "mpyuw", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ. */ -+{ "mpyuw", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,b,c 00100bbb00011111FBBBCCCCCCAAAAAA. */ -+{ "mpyuw", 0x201F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f> 0,b,c 00100bbb00011111FBBBCCCCCC111110. */ -+{ "mpyuw", 0x201F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f><.cc> b,b,c 00100bbb11011111FBBBCCCCCC0QQQQQ. */ -+{ "mpyuw", 0x20DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA. */ -+{ "mpyuw", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110. */ -+{ "mpyuw", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ. */ -+{ "mpyuw", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,b,u6 00100bbb01011111FBBBuuuuuuAAAAAA. */ -+{ "mpyuw", 0x205F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f> 0,b,u6 00100bbb01011111FBBBuuuuuu111110. */ -+{ "mpyuw", 0x205F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f><.cc> b,b,u6 00100bbb11011111FBBBuuuuuu1QQQQQ. */ -+{ "mpyuw", 0x20DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS. */ -+{ "mpyuw", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyuw<.f> b,b,s12 00100bbb10011111FBBBssssssSSSSSS. */ -+{ "mpyuw", 0x209F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyuw<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA. */ -+{ "mpyuw", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA. */ -+{ "mpyuw", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,c 0010011000111111F111CCCCCC111110. */ -+{ "mpyuw", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f> 0,b,limm 00100bbb00111111FBBB111110111110. */ -+{ "mpyuw", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyuw<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ. */ -+{ "mpyuw", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyuw<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ. */ -+{ "mpyuw", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,limm,c 0010011000011111F111CCCCCCAAAAAA. */ -+{ "mpyuw", 0x261F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f> a,b,limm 00100bbb00011111FBBB111110AAAAAA. */ -+{ "mpyuw", 0x201F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,c 0010011000011111F111CCCCCC111110. */ -+{ "mpyuw", 0x261F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyuw<.f> 0,b,limm 00100bbb00011111FBBB111110111110. */ -+{ "mpyuw", 0x201F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyuw<.f><.cc> b,b,limm 00100bbb11011111FBBB1111100QQQQQ. */ -+{ "mpyuw", 0x20DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyuw<.f><.cc> 0,limm,c 0010011011011111F111CCCCCC0QQQQQ. */ -+{ "mpyuw", 0x26DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA. */ -+{ "mpyuw", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,u6 0010011001111111F111uuuuuu111110. */ -+{ "mpyuw", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ. */ -+{ "mpyuw", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,limm,u6 0010011001011111F111uuuuuuAAAAAA. */ -+{ "mpyuw", 0x265F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,u6 0010011001011111F111uuuuuu111110. */ -+{ "mpyuw", 0x265F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyuw<.f><.cc> 0,limm,u6 0010011011011111F111uuuuuu1QQQQQ. */ -+{ "mpyuw", 0x26DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS. */ -+{ "mpyuw", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,s12 0010011010011111F111ssssssSSSSSS. */ -+{ "mpyuw", 0x269F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyuw<.f> a,limm,limm 0010011000111111F111111110AAAAAA. */ -+{ "mpyuw", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,limm 0010011000111111F111111110111110. */ -+{ "mpyuw", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyuw<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ. */ -+{ "mpyuw", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyuw<.f> a,limm,limm 0010011000011111F111111110AAAAAA. */ -+{ "mpyuw", 0x261F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyuw<.f> 0,limm,limm 0010011000011111F111111110111110. */ -+{ "mpyuw", 0x261F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyuw<.f><.cc> 0,limm,limm 0010011011011111F1111111100QQQQQ. */ -+{ "mpyuw", 0x26DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyuw_s b,b,c 01111bbbccc01010. */ -+{ "mpyuw_s", 0x0000780A, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* mpyw<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */ -+{ "mpyw", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110. */ -+{ "mpyw", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ. */ -+{ "mpyw", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyw<.f> a,b,c 00100bbb00011110FBBBCCCCCCAAAAAA. */ -+{ "mpyw", 0x201E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f> 0,b,c 00100bbb00011110FBBBCCCCCC111110. */ -+{ "mpyw", 0x201E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f><.cc> b,b,c 00100bbb11011110FBBBCCCCCC0QQQQQ. */ -+{ "mpyw", 0x20DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyw<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA. */ -+{ "mpyw", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110. */ -+{ "mpyw", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ. */ -+{ "mpyw", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyw<.f> a,b,u6 00100bbb01011110FBBBuuuuuuAAAAAA. */ -+{ "mpyw", 0x205E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f> 0,b,u6 00100bbb01011110FBBBuuuuuu111110. */ -+{ "mpyw", 0x205E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f><.cc> b,b,u6 00100bbb11011110FBBBuuuuuu1QQQQQ. */ -+{ "mpyw", 0x20DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyw<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS. */ -+{ "mpyw", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyw<.f> b,b,s12 00100bbb10011110FBBBssssssSSSSSS. */ -+{ "mpyw", 0x209E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyw<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA. */ -+{ "mpyw", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA. */ -+{ "mpyw", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,c 0010011000111110F111CCCCCC111110. */ -+{ "mpyw", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f> 0,b,limm 00100bbb00111110FBBB111110111110. */ -+{ "mpyw", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyw<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ. */ -+{ "mpyw", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyw<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ. */ -+{ "mpyw", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyw<.f> a,limm,c 0010011000011110F111CCCCCCAAAAAA. */ -+{ "mpyw", 0x261E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f> a,b,limm 00100bbb00011110FBBB111110AAAAAA. */ -+{ "mpyw", 0x201E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,c 0010011000011110F111CCCCCC111110. */ -+{ "mpyw", 0x261E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpyw<.f> 0,b,limm 00100bbb00011110FBBB111110111110. */ -+{ "mpyw", 0x201E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpyw<.f><.cc> b,b,limm 00100bbb11011110FBBB1111100QQQQQ. */ -+{ "mpyw", 0x20DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpyw<.f><.cc> 0,limm,c 0010011011011110F111CCCCCC0QQQQQ. */ -+{ "mpyw", 0x26DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpyw<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA. */ -+{ "mpyw", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,u6 0010011001111110F111uuuuuu111110. */ -+{ "mpyw", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ. */ -+{ "mpyw", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyw<.f> a,limm,u6 0010011001011110F111uuuuuuAAAAAA. */ -+{ "mpyw", 0x265E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,u6 0010011001011110F111uuuuuu111110. */ -+{ "mpyw", 0x265E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpyw<.f><.cc> 0,limm,u6 0010011011011110F111uuuuuu1QQQQQ. */ -+{ "mpyw", 0x26DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpyw<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS. */ -+{ "mpyw", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,s12 0010011010011110F111ssssssSSSSSS. */ -+{ "mpyw", 0x269E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpyw<.f> a,limm,limm 0010011000111110F111111110AAAAAA. */ -+{ "mpyw", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,limm 0010011000111110F111111110111110. */ -+{ "mpyw", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyw<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ. */ -+{ "mpyw", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyw<.f> a,limm,limm 0010011000011110F111111110AAAAAA. */ -+{ "mpyw", 0x261E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyw<.f> 0,limm,limm 0010011000011110F111111110111110. */ -+{ "mpyw", 0x261E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpyw<.f><.cc> 0,limm,limm 0010011011011110F1111111100QQQQQ. */ -+{ "mpyw", 0x26DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA. */ -+{ "mpywhfl", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfl<.f> 0,b,c 00110bbb00100100FBBBCCCCCC111110. */ -+{ "mpywhfl", 0x3024003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ. */ -+{ "mpywhfl", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA. */ -+{ "mpywhfl", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfl<.f> 0,b,u6 00110bbb01100100FBBBuuuuuu111110. */ -+{ "mpywhfl", 0x3064003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ. */ -+{ "mpywhfl", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS. */ -+{ "mpywhfl", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfl<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA. */ -+{ "mpywhfl", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfl<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA. */ -+{ "mpywhfl", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfl<.f> 0,limm,c 0011011001100100F111CCCCCC111110. */ -+{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfl<.f> 0,b,limm 00110bbb00100100FBBB111110111110. */ -+{ "mpywhfl", 0x30240FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> 0,limm,c 00110bbb11100100FBBB1111100QQQQQ. */ -+{ "mpywhfl", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f><.cc> b,b,limm 0011011011100100F111CCCCCC0QQQQQ. */ -+{ "mpywhfl", 0x36E47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> a,limm,u6 0011011001100100F111uuuuuuAAAAAA. */ -+{ "mpywhfl", 0x36647000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfl<.f> 0,limm,u6 0011011001100100F111uuuuuu111110. */ -+{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> 0,limm,u6 0011011011100100F111uuuuuu1QQQQQ. */ -+{ "mpywhfl", 0x36E47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfl<.f> 0,limm,s12 0011011010100100F111ssssssSSSSSS. */ -+{ "mpywhfl", 0x36A47000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfl<.f> a,limm,limm 0011011000100100F111111110AAAAAA. */ -+{ "mpywhfl", 0x36247F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfl<.f> 0,limm,limm 0011011000100100F111111110111110. */ -+{ "mpywhfl", 0x36247FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfl<.f><.cc> 0,limm,limm 0011011011100100F1111111100QQQQQ. */ -+{ "mpywhfl", 0x36E47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> a,b,c 00110bbb00100101FBBBCCCCCCAAAAAA. */ -+{ "mpywhflr", 0x30250000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhflr<.f> 0,b,c 00110bbb00100101FBBBCCCCCC111110. */ -+{ "mpywhflr", 0x3025003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ. */ -+{ "mpywhflr", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA. */ -+{ "mpywhflr", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhflr<.f> 0,b,u6 00110bbb01100101FBBBuuuuuu111110. */ -+{ "mpywhflr", 0x3065003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ. */ -+{ "mpywhflr", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS. */ -+{ "mpywhflr", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhflr<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA. */ -+{ "mpywhflr", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhflr<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA. */ -+{ "mpywhflr", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhflr<.f> 0,limm,c 0011011001100101F111CCCCCC111110. */ -+{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhflr<.f> 0,b,limm 00110bbb00100101FBBB111110111110. */ -+{ "mpywhflr", 0x30250FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> 0,limm,c 00110bbb11100101FBBB1111100QQQQQ. */ -+{ "mpywhflr", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f><.cc> b,b,limm 0011011011100101F111CCCCCC0QQQQQ. */ -+{ "mpywhflr", 0x36E57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> a,limm,u6 0011011001100101F111uuuuuuAAAAAA. */ -+{ "mpywhflr", 0x36657000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhflr<.f> 0,limm,u6 0011011001100101F111uuuuuu111110. */ -+{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> 0,limm,u6 0011011011100101F111uuuuuu1QQQQQ. */ -+{ "mpywhflr", 0x36E57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhflr<.f> 0,limm,s12 0011011010100101F111ssssssSSSSSS. */ -+{ "mpywhflr", 0x36A57000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhflr<.f> a,limm,limm 0011011000100101F111111110AAAAAA. */ -+{ "mpywhflr", 0x36257F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhflr<.f> 0,limm,limm 0011011000100101F111111110111110. */ -+{ "mpywhflr", 0x36257FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhflr<.f><.cc> 0,limm,limm 0011011011100101F1111111100QQQQQ. */ -+{ "mpywhflr", 0x36E57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA. */ -+{ "mpywhfm", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfm<.f> 0,b,c 00110bbb00100000FBBBCCCCCC111110. */ -+{ "mpywhfm", 0x3020003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ. */ -+{ "mpywhfm", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA. */ -+{ "mpywhfm", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfm<.f> 0,b,u6 00110bbb01100000FBBBuuuuuu111110. */ -+{ "mpywhfm", 0x3060003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ. */ -+{ "mpywhfm", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS. */ -+{ "mpywhfm", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfm<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA. */ -+{ "mpywhfm", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfm<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA. */ -+{ "mpywhfm", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfm<.f> 0,limm,c 0011011001100000F111CCCCCC111110. */ -+{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfm<.f> 0,b,limm 00110bbb00100000FBBB111110111110. */ -+{ "mpywhfm", 0x30200FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> 0,limm,c 00110bbb11100000FBBB1111100QQQQQ. */ -+{ "mpywhfm", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f><.cc> b,b,limm 0011011011100000F111CCCCCC0QQQQQ. */ -+{ "mpywhfm", 0x36E07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> a,limm,u6 0011011001100000F111uuuuuuAAAAAA. */ -+{ "mpywhfm", 0x36607000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfm<.f> 0,limm,u6 0011011001100000F111uuuuuu111110. */ -+{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> 0,limm,u6 0011011011100000F111uuuuuu1QQQQQ. */ -+{ "mpywhfm", 0x36E07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfm<.f> 0,limm,s12 0011011010100000F111ssssssSSSSSS. */ -+{ "mpywhfm", 0x36A07000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfm<.f> a,limm,limm 0011011000100000F111111110AAAAAA. */ -+{ "mpywhfm", 0x36207F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfm<.f> 0,limm,limm 0011011000100000F111111110111110. */ -+{ "mpywhfm", 0x36207FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfm<.f><.cc> 0,limm,limm 0011011011100000F1111111100QQQQQ. */ -+{ "mpywhfm", 0x36E07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */ -+{ "mpywhfmr", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,b,c 00110bbb00100001FBBBCCCCCC111110. */ -+{ "mpywhfmr", 0x3021003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ. */ -+{ "mpywhfmr", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA. */ -+{ "mpywhfmr", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,b,u6 00110bbb01100001FBBBuuuuuu111110. */ -+{ "mpywhfmr", 0x3061003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> b,b,u6 00110bbb11100001FBBBuuuuuu1QQQQQ. */ -+{ "mpywhfmr", 0x30E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS. */ -+{ "mpywhfmr", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfmr<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA. */ -+{ "mpywhfmr", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfmr<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA. */ -+{ "mpywhfmr", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,limm,c 0011011001100001F111CCCCCC111110. */ -+{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,b,limm 00110bbb00100001FBBB111110111110. */ -+{ "mpywhfmr", 0x30210FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> 0,limm,c 00110bbb11100001FBBB1111100QQQQQ. */ -+{ "mpywhfmr", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f><.cc> b,b,limm 0011011011100001F111CCCCCC0QQQQQ. */ -+{ "mpywhfmr", 0x36E17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> a,limm,u6 0011011001100001F111uuuuuuAAAAAA. */ -+{ "mpywhfmr", 0x36617000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,limm,u6 0011011001100001F111uuuuuu111110. */ -+{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> 0,limm,u6 0011011011100001F111uuuuuu1QQQQQ. */ -+{ "mpywhfmr", 0x36E17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhfmr<.f> 0,limm,s12 0011011010100001F111ssssssSSSSSS. */ -+{ "mpywhfmr", 0x36A17000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhfmr<.f> a,limm,limm 0011011000100001F111111110AAAAAA. */ -+{ "mpywhfmr", 0x36217F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfmr<.f> 0,limm,limm 0011011000100001F111111110111110. */ -+{ "mpywhfmr", 0x36217FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhfmr<.f><.cc> 0,limm,limm 0011011011100001F1111111100QQQQQ. */ -+{ "mpywhfmr", 0x36E17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f><.cc> b,b,c 00110bbb11101010FBBBCCCCCC0QQQQQ */ -+{ "mpywhkl", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> 0,b,c 00110bbb00101010FBBBCCCCCC111110 */ -+{ "mpywhkl", 0x302A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkl<.f> a,b,c 00110bbb00101010FBBBCCCCCCAAAAAA */ -+{ "mpywhkl", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkl<.f> a,b,u6 00110bbb01101010FBBBuuuuuuAAAAAA */ -+{ "mpywhkl", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkl<.f><.cc> b,b,u6 00110bbb11101010FBBBuuuuuu1QQQQQ */ -+{ "mpywhkl", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> 0,b,u6 00110bbb01101010FBBBuuuuuu111110 */ -+{ "mpywhkl", 0x306A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkl<.f> b,b,s12 00110bbb10101010FBBBssssssSSSSSS */ -+{ "mpywhkl", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhkl<.f> a,b,limm 00110bbb00101010FBBB111110AAAAAA */ -+{ "mpywhkl", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhkl<.f><.cc> 0,limm,c 00110bbb11101010FBBB1111100QQQQQ */ -+{ "mpywhkl", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f><.cc> b,b,limm 0011011011101010F111CCCCCC0QQQQQ */ -+{ "mpywhkl", 0x36EA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> 0,limm,c 0011011001101010F111CCCCCC111110 */ -+{ "mpywhkl", 0x366A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkl<.f> a,limm,c 0011011000101010F111CCCCCCAAAAAA */ -+{ "mpywhkl", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkl<.f> 0,b,limm 00110bbb00101010FBBB111110111110 */ -+{ "mpywhkl", 0x302A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhkl<.f> 0,limm,u6 0011011001101010F111uuuuuu111110 */ -+{ "mpywhkl", 0x366A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkl<.f><.cc> 0,limm,u6 0011011011101010F111uuuuuu1QQQQQ */ -+{ "mpywhkl", 0x36EA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> a,limm,u6 0011011001101010F111uuuuuuAAAAAA */ -+{ "mpywhkl", 0x366A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkl<.f> 0,limm,s12 0011011010101010F111ssssssSSSSSS */ -+{ "mpywhkl", 0x36AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhkl<.f> 0,limm,limm 0011011000101010F111111110111110 */ -+{ "mpywhkl", 0x362A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhkl<.f><.cc> 0,limm,limm 0011011011101010F1111111100QQQQQ */ -+{ "mpywhkl", 0x36EA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhkl<.f> a,limm,limm 0011011000101010F111111110AAAAAA */ -+{ "mpywhkl", 0x362A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhkul<.f> 0,b,c 00110bbb00101011FBBBCCCCCC111110 */ -+{ "mpywhkul", 0x302B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkul<.f> a,b,c 00110bbb00101011FBBBCCCCCCAAAAAA */ -+{ "mpywhkul", 0x302B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> b,b,c 00110bbb11101011FBBBCCCCCC0QQQQQ */ -+{ "mpywhkul", 0x30EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f><.cc> b,b,u6 00110bbb11101011FBBBuuuuuu1QQQQQ */ -+{ "mpywhkul", 0x30EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> 0,b,u6 00110bbb01101011FBBBuuuuuu111110 */ -+{ "mpywhkul", 0x306B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkul<.f> a,b,u6 00110bbb01101011FBBBuuuuuuAAAAAA */ -+{ "mpywhkul", 0x306B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkul<.f> b,b,s12 00110bbb10101011FBBBssssssSSSSSS */ -+{ "mpywhkul", 0x30AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhkul<.f> a,b,limm 00110bbb00101011FBBB111110AAAAAA */ -+{ "mpywhkul", 0x302B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> b,b,limm 0011011011101011F111CCCCCC0QQQQQ */ -+{ "mpywhkul", 0x36EB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> 0,b,limm 00110bbb00101011FBBB111110111110 */ -+{ "mpywhkul", 0x302B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> 0,limm,c 00110bbb11101011FBBB1111100QQQQQ */ -+{ "mpywhkul", 0x30EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> 0,limm,c 0011011001101011F111CCCCCC111110 */ -+{ "mpywhkul", 0x366B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkul<.f> a,limm,c 0011011000101011F111CCCCCCAAAAAA */ -+{ "mpywhkul", 0x362B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhkul<.f> 0,limm,u6 0011011001101011F111uuuuuu111110 */ -+{ "mpywhkul", 0x366B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkul<.f> a,limm,u6 0011011001101011F111uuuuuuAAAAAA */ -+{ "mpywhkul", 0x366B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> 0,limm,u6 0011011011101011F111uuuuuu1QQQQQ */ -+{ "mpywhkul", 0x36EB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> 0,limm,s12 0011011010101011F111ssssssSSSSSS */ -+{ "mpywhkul", 0x36AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhkul<.f> 0,limm,limm 0011011000101011F111111110111110 */ -+{ "mpywhkul", 0x362B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhkul<.f><.cc> 0,limm,limm 0011011011101011F1111111100QQQQQ */ -+{ "mpywhkul", 0x36EB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhkul<.f> a,limm,limm 0011011000101011F111111110AAAAAA */ -+{ "mpywhkul", 0x362B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhl<.f> a,b,c 00110bbb00011100FBBBCCCCCCAAAAAA. */ -+{ "mpywhl", 0x301C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhl<.f> 0,b,c 00110bbb00011100FBBBCCCCCC111110. */ -+{ "mpywhl", 0x301C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhl<.f><.cc> b,b,c 00110bbb11011100FBBBCCCCCC0QQQQQ. */ -+{ "mpywhl", 0x30DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhl<.f> a,b,u6 00110bbb01011100FBBBuuuuuuAAAAAA. */ -+{ "mpywhl", 0x305C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhl<.f> 0,b,u6 00110bbb01011100FBBBuuuuuu111110. */ -+{ "mpywhl", 0x305C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhl<.f><.cc> b,b,u6 00110bbb11011100FBBBuuuuuu1QQQQQ. */ -+{ "mpywhl", 0x30DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhl<.f> b,b,s12 00110bbb10011100FBBBssssssSSSSSS. */ -+{ "mpywhl", 0x309C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhl<.f> a,limm,c 0011011000011100F111CCCCCCAAAAAA. */ -+{ "mpywhl", 0x361C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhl<.f> a,b,limm 00110bbb00011100FBBB111110AAAAAA. */ -+{ "mpywhl", 0x301C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhl<.f> 0,limm,c 0011011000011100F111CCCCCC111110. */ -+{ "mpywhl", 0x361C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhl<.f> 0,b,limm 00110bbb00011100FBBB111110111110. */ -+{ "mpywhl", 0x301C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhl<.f><.cc> 0,limm,c 00110bbb11011100FBBB1111100QQQQQ. */ -+{ "mpywhl", 0x30DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhl<.f><.cc> b,b,limm 0011011011011100F111CCCCCC0QQQQQ. */ -+{ "mpywhl", 0x36DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhl<.f> a,limm,u6 0011011001011100F111uuuuuuAAAAAA. */ -+{ "mpywhl", 0x365C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhl<.f> 0,limm,u6 0011011001011100F111uuuuuu111110. */ -+{ "mpywhl", 0x365C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhl<.f><.cc> 0,limm,u6 0011011011011100F111uuuuuu1QQQQQ. */ -+{ "mpywhl", 0x36DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhl<.f> 0,limm,s12 0011011010011100F111ssssssSSSSSS. */ -+{ "mpywhl", 0x369C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhl<.f> a,limm,limm 0011011000011100F111111110AAAAAA. */ -+{ "mpywhl", 0x361C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhl<.f> 0,limm,limm 0011011000011100F111111110111110. */ -+{ "mpywhl", 0x361C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhl<.f><.cc> 0,limm,limm 0011011011011100F1111111100QQQQQ. */ -+{ "mpywhl", 0x36DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> a,b,c 00110bbb00011110FBBBCCCCCCAAAAAA. */ -+{ "mpywhul", 0x301E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhul<.f> 0,b,c 00110bbb00011110FBBBCCCCCC111110. */ -+{ "mpywhul", 0x301E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mpywhul<.f><.cc> b,b,c 00110bbb11011110FBBBCCCCCC0QQQQQ. */ -+{ "mpywhul", 0x30DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> a,b,u6 00110bbb01011110FBBBuuuuuuAAAAAA. */ -+{ "mpywhul", 0x305E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhul<.f> 0,b,u6 00110bbb01011110FBBBuuuuuu111110. */ -+{ "mpywhul", 0x305E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhul<.f><.cc> b,b,u6 00110bbb11011110FBBBuuuuuu1QQQQQ. */ -+{ "mpywhul", 0x30DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> b,b,s12 00110bbb10011110FBBBssssssSSSSSS. */ -+{ "mpywhul", 0x309E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhul<.f> a,limm,c 0011011000011110F111CCCCCCAAAAAA. */ -+{ "mpywhul", 0x361E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhul<.f> a,b,limm 00110bbb00011110FBBB111110AAAAAA. */ -+{ "mpywhul", 0x301E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhul<.f> 0,limm,c 0011011000011110F111CCCCCC111110. */ -+{ "mpywhul", 0x361E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mpywhul<.f> 0,b,limm 00110bbb00011110FBBB111110111110. */ -+{ "mpywhul", 0x301E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mpywhul<.f><.cc> 0,limm,c 00110bbb11011110FBBB1111100QQQQQ. */ -+{ "mpywhul", 0x30DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mpywhul<.f><.cc> b,b,limm 0011011011011110F111CCCCCC0QQQQQ. */ -+{ "mpywhul", 0x36DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> a,limm,u6 0011011001011110F111uuuuuuAAAAAA. */ -+{ "mpywhul", 0x365E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhul<.f> 0,limm,u6 0011011001011110F111uuuuuu111110. */ -+{ "mpywhul", 0x365E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mpywhul<.f><.cc> 0,limm,u6 0011011011011110F111uuuuuu1QQQQQ. */ -+{ "mpywhul", 0x36DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mpywhul<.f> 0,limm,s12 0011011010011110F111ssssssSSSSSS. */ -+{ "mpywhul", 0x369E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mpywhul<.f> a,limm,limm 0011011000011110F111111110AAAAAA. */ -+{ "mpywhul", 0x361E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhul<.f> 0,limm,limm 0011011000011110F111111110111110. */ -+{ "mpywhul", 0x361E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mpywhul<.f><.cc> 0,limm,limm 0011011011011110F1111111100QQQQQ. */ -+{ "mpywhul", 0x36DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mpyw_s b,b,c 01111bbbccc01001. */ -+{ "mpyw_s", 0x00007809, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* mpy_s b,b,c 01111bbbccc01100. */ -+{ "mpy_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* msubdf<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA. */ -+{ "msubdf", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubdf<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110. */ -+{ "msubdf", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubdf<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ. */ -+{ "msubdf", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubdf<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA. */ -+{ "msubdf", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdf<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110. */ -+{ "msubdf", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdf<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ. */ -+{ "msubdf", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubdf<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS. */ -+{ "msubdf", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubdf<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA. */ -+{ "msubdf", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubdf<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA. */ -+{ "msubdf", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubdf<.f> 0,limm,c 0011011000010101F111CCCCCC111110. */ -+{ "msubdf", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubdf<.f> 0,b,limm 00110bbb00010101FBBB111110111110. */ -+{ "msubdf", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubdf<.f><.cc> 0,limm,c 00110bbb11010101FBBB1111100QQQQQ. */ -+{ "msubdf", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubdf<.f><.cc> b,b,limm 0011011011010101F111CCCCCC0QQQQQ. */ -+{ "msubdf", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubdf<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA. */ -+{ "msubdf", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdf<.f> 0,limm,u6 0011011001010101F111uuuuuu111110. */ -+{ "msubdf", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdf<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ. */ -+{ "msubdf", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubdf<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS. */ -+{ "msubdf", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubdf<.f> a,limm,limm 0011011000010101F111111110AAAAAA. */ -+{ "msubdf", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubdf<.f> 0,limm,limm 0011011000010101F111111110111110. */ -+{ "msubdf", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubdf<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ. */ -+{ "msubdf", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubdw<.f> a,b,c 00101bbb00010100FBBBCCCCCCAAAAAA. */ -+{ "msubdw", 0x28140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubdw<.f> 0,b,c 00101bbb00010100FBBBCCCCCC111110. */ -+{ "msubdw", 0x2814003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubdw<.f><.cc> b,b,c 00101bbb11010100FBBBCCCCCC0QQQQQ. */ -+{ "msubdw", 0x28D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubdw<.f> a,b,u6 00101bbb01010100FBBBuuuuuuAAAAAA. */ -+{ "msubdw", 0x28540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdw<.f> 0,b,u6 00101bbb01010100FBBBuuuuuu111110. */ -+{ "msubdw", 0x2854003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdw<.f><.cc> b,b,u6 00101bbb11010100FBBBuuuuuu1QQQQQ. */ -+{ "msubdw", 0x28D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubdw<.f> b,b,s12 00101bbb10010100FBBBssssssSSSSSS. */ -+{ "msubdw", 0x28940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubdw<.f> a,limm,c 0010111000010100F111CCCCCCAAAAAA. */ -+{ "msubdw", 0x2E147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubdw<.f> a,b,limm 00101bbb00010100FBBB111110AAAAAA. */ -+{ "msubdw", 0x28140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubdw<.f> 0,limm,c 0010111000010100F111CCCCCC111110. */ -+{ "msubdw", 0x2E14703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubdw<.f> 0,b,limm 00101bbb00010100FBBB111110111110. */ -+{ "msubdw", 0x28140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubdw<.f><.cc> 0,limm,c 0010111011010100F111CCCCCC0QQQQQ. */ -+{ "msubdw", 0x2ED47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubdw<.f><.cc> b,b,limm 00101bbb11010100FBBB1111100QQQQQ. */ -+{ "msubdw", 0x28D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubdw<.f> a,limm,u6 0010111001010100F111uuuuuuAAAAAA. */ -+{ "msubdw", 0x2E547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdw<.f> 0,limm,u6 0010111001010100F111uuuuuu111110. */ -+{ "msubdw", 0x2E54703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubdw<.f><.cc> 0,limm,u6 0010111011010100F111uuuuuu1QQQQQ. */ -+{ "msubdw", 0x2ED47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubdw<.f> 0,limm,s12 0010111010010100F111ssssssSSSSSS. */ -+{ "msubdw", 0x2E947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubdw<.f> a,limm,limm 0010111000010100F111111110AAAAAA. */ -+{ "msubdw", 0x2E147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubdw<.f> 0,limm,limm 0010111000010100F111111110111110. */ -+{ "msubdw", 0x2E147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubdw<.f><.cc> 0,limm,limm 0010111011010100F1111111100QQQQQ. */ -+{ "msubdw", 0x2ED47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubf<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA. */ -+{ "msubf", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubf<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110. */ -+{ "msubf", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubf<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ. */ -+{ "msubf", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubf<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA. */ -+{ "msubf", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubf<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110. */ -+{ "msubf", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubf<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ. */ -+{ "msubf", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubf<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS. */ -+{ "msubf", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubf<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA. */ -+{ "msubf", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubf<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA. */ -+{ "msubf", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubf<.f> 0,limm,c 0011011000001110F111CCCCCC111110. */ -+{ "msubf", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubf<.f> 0,b,limm 00110bbb00001110FBBB111110111110. */ -+{ "msubf", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubf<.f><.cc> 0,limm,c 00110bbb11001110FBBB1111100QQQQQ. */ -+{ "msubf", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubf<.f><.cc> b,b,limm 0011011011001110F111CCCCCC0QQQQQ. */ -+{ "msubf", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubf<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA. */ -+{ "msubf", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubf<.f> 0,limm,u6 0011011001001110F111uuuuuu111110. */ -+{ "msubf", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubf<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ. */ -+{ "msubf", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubf<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS. */ -+{ "msubf", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubf<.f> a,limm,limm 0011011000001110F111111110AAAAAA. */ -+{ "msubf", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubf<.f> 0,limm,limm 0011011000001110F111111110111110. */ -+{ "msubf", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubf<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ. */ -+{ "msubf", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubfr<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA. */ -+{ "msubfr", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubfr<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110. */ -+{ "msubfr", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubfr<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ. */ -+{ "msubfr", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubfr<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA. */ -+{ "msubfr", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubfr<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110. */ -+{ "msubfr", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubfr<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ. */ -+{ "msubfr", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubfr<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS. */ -+{ "msubfr", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubfr<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA. */ -+{ "msubfr", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubfr<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA. */ -+{ "msubfr", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubfr<.f> 0,limm,c 0011011000001111F111CCCCCC111110. */ -+{ "msubfr", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubfr<.f> 0,b,limm 00110bbb00001111FBBB111110111110. */ -+{ "msubfr", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubfr<.f><.cc> 0,limm,c 00110bbb11001111FBBB1111100QQQQQ. */ -+{ "msubfr", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubfr<.f><.cc> b,b,limm 0011011011001111F111CCCCCC0QQQQQ. */ -+{ "msubfr", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubfr<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA. */ -+{ "msubfr", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubfr<.f> 0,limm,u6 0011011001001111F111uuuuuu111110. */ -+{ "msubfr", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubfr<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ. */ -+{ "msubfr", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubfr<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS. */ -+{ "msubfr", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubfr<.f> a,limm,limm 0011011000001111F111111110AAAAAA. */ -+{ "msubfr", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubfr<.f> 0,limm,limm 0011011000001111F111111110111110. */ -+{ "msubfr", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubfr<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ. */ -+{ "msubfr", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubt<.f> a,b,c 00101bbb00100000FBBBCCCCCCAAAAAA. */ -+{ "msubt", 0x28200000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubt<.f> 0,b,c 00101bbb00100000FBBBCCCCCC111110. */ -+{ "msubt", 0x2820003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubt<.f><.cc> b,b,c 00101bbb11100000FBBBCCCCCC0QQQQQ. */ -+{ "msubt", 0x28E00000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubt<.f> a,b,u6 00101bbb01100000FBBBuuuuuuAAAAAA. */ -+{ "msubt", 0x28600000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubt<.f> 0,b,u6 00101bbb01100000FBBBuuuuuu111110. */ -+{ "msubt", 0x2860003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubt<.f><.cc> b,b,u6 00101bbb11100000FBBBuuuuuu1QQQQQ. */ -+{ "msubt", 0x28E00020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubt<.f> b,b,s12 00101bbb10100000FBBBssssssSSSSSS. */ -+{ "msubt", 0x28A00000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubt<.f> a,limm,c 0010111000100000F111CCCCCCAAAAAA. */ -+{ "msubt", 0x2E207000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubt<.f> a,b,limm 00101bbb00100000FBBB111110AAAAAA. */ -+{ "msubt", 0x28200F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubt<.f> 0,limm,c 0010111000100000F111CCCCCC111110. */ -+{ "msubt", 0x2E20703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubt<.f> 0,b,limm 00101bbb00100000FBBB111110111110. */ -+{ "msubt", 0x28200FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubt<.f><.cc> 0,limm,c 0010111011100000F111CCCCCC0QQQQQ. */ -+{ "msubt", 0x2EE07000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubt<.f><.cc> b,b,limm 00101bbb11100000FBBB1111100QQQQQ. */ -+{ "msubt", 0x28E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubt<.f> a,limm,u6 0010111001100000F111uuuuuuAAAAAA. */ -+{ "msubt", 0x2E607000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubt<.f> 0,limm,u6 0010111001100000F111uuuuuu111110. */ -+{ "msubt", 0x2E60703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubt<.f><.cc> 0,limm,u6 0010111011100000F111uuuuuu1QQQQQ. */ -+{ "msubt", 0x2EE07020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubt<.f> 0,limm,s12 0010111010100000F111ssssssSSSSSS. */ -+{ "msubt", 0x2EA07000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubt<.f> a,limm,limm 0010111000100000F111111110AAAAAA. */ -+{ "msubt", 0x2E207F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubt<.f> 0,limm,limm 0010111000100000F111111110111110. */ -+{ "msubt", 0x2E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubt<.f><.cc> 0,limm,limm 0010111011100000F1111111100QQQQQ. */ -+{ "msubt", 0x2EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f><.cc> b,b,c 00110bbb11010100FBBBCCCCCC0QQQQQ */ -+{ "msubwhfl", 0x30D40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> 0,b,c 00110bbb00010100FBBBCCCCCC111110 */ -+{ "msubwhfl", 0x3014003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfl<.f> a,b,u6 00110bbb01010100FBBBuuuuuuAAAAAA */ -+{ "msubwhfl", 0x30540000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> b,b,u6 00110bbb11010100FBBBuuuuuu1QQQQQ */ -+{ "msubwhfl", 0x30D40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> 0,b,u6 00110bbb01010100FBBBuuuuuu111110 */ -+{ "msubwhfl", 0x3054003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfl<.f> b,b,s12 00110bbb10010100FBBBssssssSSSSSS */ -+{ "msubwhfl", 0x30940000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfl<.f> a,limm,c 0011011000010100F111CCCCCCAAAAAA */ -+{ "msubwhfl", 0x36147000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> 0,limm,c 00110bbb11010100FBBB1111100QQQQQ */ -+{ "msubwhfl", 0x30D40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> a,b,limm 00110bbb00010100FBBB111110AAAAAA */ -+{ "msubwhfl", 0x30140F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfl<.f> 0,limm,c 0011011000010100F111CCCCCC111110 */ -+{ "msubwhfl", 0x3614703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> b,b,limm 0011011011010100F111CCCCCC0QQQQQ */ -+{ "msubwhfl", 0x36D47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> 0,b,limm 00110bbb00010100FBBB111110111110 */ -+{ "msubwhfl", 0x30140FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfl<.f> 0,limm,u6 0011011001010100F111uuuuuu111110 */ -+{ "msubwhfl", 0x3654703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfl<.f> a,limm,u6 0011011001010100F111uuuuuuAAAAAA */ -+{ "msubwhfl", 0x36547000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> 0,limm,u6 0011011011010100F111uuuuuu1QQQQQ */ -+{ "msubwhfl", 0x36D47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfl<.f> 0,limm,s12 0011011010010100F111ssssssSSSSSS */ -+{ "msubwhfl", 0x36947000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfl<.f> 0,limm,limm 0011011000010100F111111110111110 */ -+{ "msubwhfl", 0x36147FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfl<.f> a,limm,limm 0011011000010100F111111110AAAAAA */ -+{ "msubwhfl", 0x36147F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfl<.f><.cc> 0,limm,limm 0011011011010100F1111111100QQQQQ */ -+{ "msubwhfl", 0x36D47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> 0,b,c 00110bbb00011010FBBBCCCCCC111110 */ -+{ "msubwhflr", 0x301A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> b,b,c 00110bbb11011010FBBBCCCCCC0QQQQQ */ -+{ "msubwhflr", 0x30DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> a,b,c 00110bbb00011010FBBBCCCCCCAAAAAA */ -+{ "msubwhflr", 0x301A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhflr<.f> a,b,u6 00110bbb01011010FBBBuuuuuuAAAAAA */ -+{ "msubwhflr", 0x305A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> b,b,u6 00110bbb11011010FBBBuuuuuu1QQQQQ */ -+{ "msubwhflr", 0x30DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> 0,b,u6 00110bbb01011010FBBBuuuuuu111110 */ -+{ "msubwhflr", 0x305A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhflr<.f> b,b,s12 00110bbb10011010FBBBssssssSSSSSS */ -+{ "msubwhflr", 0x309A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> b,b,limm 0011011011011010F111CCCCCC0QQQQQ */ -+{ "msubwhflr", 0x36DA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f><.cc> 0,limm,c 00110bbb11011010FBBB1111100QQQQQ */ -+{ "msubwhflr", 0x30DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> a,b,limm 00110bbb00011010FBBB111110AAAAAA */ -+{ "msubwhflr", 0x301A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhflr<.f> 0,b,limm 00110bbb00011010FBBB111110111110 */ -+{ "msubwhflr", 0x301A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhflr<.f> 0,limm,c 0011011000011010F111CCCCCC111110 */ -+{ "msubwhflr", 0x361A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhflr<.f> a,limm,c 0011011000011010F111CCCCCCAAAAAA */ -+{ "msubwhflr", 0x361A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> 0,limm,u6 0011011011011010F111uuuuuu1QQQQQ */ -+{ "msubwhflr", 0x36DA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> 0,limm,u6 0011011001011010F111uuuuuu111110 */ -+{ "msubwhflr", 0x365A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhflr<.f> a,limm,u6 0011011001011010F111uuuuuuAAAAAA */ -+{ "msubwhflr", 0x365A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhflr<.f> 0,limm,s12 0011011010011010F111ssssssSSSSSS */ -+{ "msubwhflr", 0x369A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhflr<.f><.cc> 0,limm,limm 0011011011011010F1111111100QQQQQ */ -+{ "msubwhflr", 0x36DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubwhflr<.f> a,limm,limm 0011011000011010F111111110AAAAAA */ -+{ "msubwhflr", 0x361A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhflr<.f> 0,limm,limm 0011011000011010F111111110111110 */ -+{ "msubwhflr", 0x361A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfm<.f> 0,b,c 00110bbb00101100FBBBCCCCCC111110 */ -+{ "msubwhfm", 0x302C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> b,b,c 00110bbb11101100FBBBCCCCCC0QQQQQ */ -+{ "msubwhfm", 0x30EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> a,b,c 00110bbb00101100FBBBCCCCCCAAAAAA */ -+{ "msubwhfm", 0x302C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> b,b,u6 00110bbb11101100FBBBuuuuuu1QQQQQ */ -+{ "msubwhfm", 0x30EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> a,b,u6 00110bbb01101100FBBBuuuuuuAAAAAA */ -+{ "msubwhfm", 0x306C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfm<.f> 0,b,u6 00110bbb01101100FBBBuuuuuu111110 */ -+{ "msubwhfm", 0x306C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfm<.f> b,b,s12 00110bbb10101100FBBBssssssSSSSSS */ -+{ "msubwhfm", 0x30AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfm<.f> 0,limm,c 0011011001101100F111CCCCCC111110 */ -+{ "msubwhfm", 0x366C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> 0,limm,c 00110bbb11101100FBBB1111100QQQQQ */ -+{ "msubwhfm", 0x30EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> a,limm,c 0011011000101100F111CCCCCCAAAAAA */ -+{ "msubwhfm", 0x362C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> b,b,limm 0011011011101100F111CCCCCC0QQQQQ */ -+{ "msubwhfm", 0x36EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> a,b,limm 00110bbb00101100FBBB111110AAAAAA */ -+{ "msubwhfm", 0x302C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfm<.f> 0,b,limm 00110bbb00101100FBBB111110111110 */ -+{ "msubwhfm", 0x302C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfm<.f> 0,limm,u6 0011011001101100F111uuuuuu111110 */ -+{ "msubwhfm", 0x366C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfm<.f> a,limm,u6 0011011001101100F111uuuuuuAAAAAA */ -+{ "msubwhfm", 0x366C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> 0,limm,u6 0011011011101100F111uuuuuu1QQQQQ */ -+{ "msubwhfm", 0x36EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfm<.f> 0,limm,s12 0011011010101100F111ssssssSSSSSS */ -+{ "msubwhfm", 0x36AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfm<.f> 0,limm,limm 0011011000101100F111111110111110 */ -+{ "msubwhfm", 0x362C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfm<.f> a,limm,limm 0011011000101100F111111110AAAAAA */ -+{ "msubwhfm", 0x362C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfm<.f><.cc> 0,limm,limm 0011011011101100F1111111100QQQQQ */ -+{ "msubwhfm", 0x36EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> a,b,c 00110bbb00101101FBBBCCCCCCAAAAAA */ -+{ "msubwhfmr", 0x302D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,b,c 00110bbb00101101FBBBCCCCCC111110 */ -+{ "msubwhfmr", 0x302D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> b,b,c 00110bbb11101101FBBBCCCCCC0QQQQQ */ -+{ "msubwhfmr", 0x30ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> a,b,u6 00110bbb01101101FBBBuuuuuuAAAAAA */ -+{ "msubwhfmr", 0x306D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> b,b,u6 00110bbb11101101FBBBuuuuuu1QQQQQ */ -+{ "msubwhfmr", 0x30ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> 0,b,u6 00110bbb01101101FBBBuuuuuu111110 */ -+{ "msubwhfmr", 0x306D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfmr<.f> b,b,s12 00110bbb10101101FBBBssssssSSSSSS */ -+{ "msubwhfmr", 0x30AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfmr<.f> a,limm,c 0011011000101101F111CCCCCCAAAAAA */ -+{ "msubwhfmr", 0x362D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,b,limm 00110bbb00101101FBBB111110111110 */ -+{ "msubwhfmr", 0x302D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfmr<.f> a,b,limm 00110bbb00101101FBBB111110AAAAAA */ -+{ "msubwhfmr", 0x302D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> b,b,limm 0011011011101101F111CCCCCC0QQQQQ */ -+{ "msubwhfmr", 0x36ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f><.cc> 0,limm,c 00110bbb11101101FBBB1111100QQQQQ */ -+{ "msubwhfmr", 0x30ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> 0,limm,c 0011011001101101F111CCCCCC111110 */ -+{ "msubwhfmr", 0x366D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> 0,limm,u6 0011011011101101F111uuuuuu1QQQQQ */ -+{ "msubwhfmr", 0x36ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> a,limm,u6 0011011001101101F111uuuuuuAAAAAA */ -+{ "msubwhfmr", 0x366D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,limm,u6 0011011001101101F111uuuuuu111110 */ -+{ "msubwhfmr", 0x366D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* msubwhfmr<.f> 0,limm,s12 0011011010101101F111ssssssSSSSSS */ -+{ "msubwhfmr", 0x36AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* msubwhfmr<.f><.cc> 0,limm,limm 0011011011101101F1111111100QQQQQ */ -+{ "msubwhfmr", 0x36ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* msubwhfmr<.f> 0,limm,limm 0011011000101101F111111110111110 */ -+{ "msubwhfmr", 0x362D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* msubwhfmr<.f> a,limm,limm 0011011000101101F111111110AAAAAA */ -+{ "msubwhfmr", 0x362D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110. */ -+{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ. */ -+{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110. */ -+{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ. */ -+{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS. */ -+{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mul64 0,limm,c 00101110000001000111CCCCCC111110. */ -+{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mul64 0,b,limm 00101bbb000001000BBB111110111110. */ -+{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ. */ -+{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ. */ -+{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* mul64 0,limm,u6 00101110010001000111uuuuuu111110. */ -+{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ. */ -+{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS. */ -+{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mul64 0,limm,limm 00101110000001000111111110111110. */ -+{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ. */ -+{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110. */ -+{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ. */ -+{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110. */ -+{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ. */ -+{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS. */ -+{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mul64 0,limm,c 00101110000001000111CCCCCC111110. */ -+{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mul64 0,b,limm 00101bbb000001000BBB111110111110. */ -+{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ. */ -+{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ. */ -+{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* mul64 0,limm,u6 00101110010001000111uuuuuu111110. */ -+{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ. */ -+{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS. */ -+{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mul64 0,limm,limm 00101110000001000111111110111110. */ -+{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ. */ -+{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* mul64_s 0,b,c 01111bbbccc01100. */ -+{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* mul64_s 0,b,c 01111bbbccc01100. */ -+{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* muldw<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA. */ -+{ "muldw", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* muldw<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110. */ -+{ "muldw", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* muldw<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ. */ -+{ "muldw", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* muldw<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA. */ -+{ "muldw", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* muldw<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110. */ -+{ "muldw", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* muldw<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ. */ -+{ "muldw", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* muldw<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS. */ -+{ "muldw", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* muldw<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA. */ -+{ "muldw", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* muldw<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA. */ -+{ "muldw", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* muldw<.f> 0,limm,c 0010111000001100F111CCCCCC111110. */ -+{ "muldw", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* muldw<.f> 0,b,limm 00101bbb00001100FBBB111110111110. */ -+{ "muldw", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* muldw<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ. */ -+{ "muldw", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* muldw<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ. */ -+{ "muldw", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* muldw<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA. */ -+{ "muldw", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* muldw<.f> 0,limm,u6 0010111001001100F111uuuuuu111110. */ -+{ "muldw", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* muldw<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ. */ -+{ "muldw", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* muldw<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS. */ -+{ "muldw", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* muldw<.f> a,limm,limm 0010111000001100F111111110AAAAAA. */ -+{ "muldw", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* muldw<.f> 0,limm,limm 0010111000001100F111111110111110. */ -+{ "muldw", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* muldw<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ. */ -+{ "muldw", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mulflw<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA. */ -+{ "mulflw", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulflw<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110. */ -+{ "mulflw", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulflw<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ. */ -+{ "mulflw", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulflw<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA. */ -+{ "mulflw", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulflw<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110. */ -+{ "mulflw", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulflw<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ. */ -+{ "mulflw", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulflw<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS. */ -+{ "mulflw", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulflw<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA. */ -+{ "mulflw", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulflw<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA. */ -+{ "mulflw", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulflw<.f> 0,limm,c 0010111000110010F111CCCCCC111110. */ -+{ "mulflw", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulflw<.f> 0,b,limm 00101bbb00110010FBBB111110111110. */ -+{ "mulflw", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulflw<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ. */ -+{ "mulflw", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulflw<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ. */ -+{ "mulflw", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mulflw<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA. */ -+{ "mulflw", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulflw<.f> 0,limm,u6 0010111001110010F111uuuuuu111110. */ -+{ "mulflw", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulflw<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ. */ -+{ "mulflw", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulflw<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS. */ -+{ "mulflw", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulflw<.f> a,limm,limm 0010111000110010F111111110AAAAAA. */ -+{ "mulflw", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulflw<.f> 0,limm,limm 0010111000110010F111111110111110. */ -+{ "mulflw", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulflw<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ. */ -+{ "mulflw", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mulhflw<.f> a,b,c 00101bbb00111001FBBBCCCCCCAAAAAA. */ -+{ "mulhflw", 0x28390000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulhflw<.f> 0,b,c 00101bbb00111001FBBBCCCCCC111110. */ -+{ "mulhflw", 0x2839003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulhflw<.f><.cc> b,b,c 00101bbb11111001FBBBCCCCCC0QQQQQ. */ -+{ "mulhflw", 0x28F90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulhflw<.f> a,b,u6 00101bbb01111001FBBBuuuuuuAAAAAA. */ -+{ "mulhflw", 0x28790000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulhflw<.f> 0,b,u6 00101bbb01111001FBBBuuuuuu111110. */ -+{ "mulhflw", 0x2879003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulhflw<.f><.cc> b,b,u6 00101bbb11111001FBBBuuuuuu1QQQQQ. */ -+{ "mulhflw", 0x28F90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulhflw<.f> b,b,s12 00101bbb10111001FBBBssssssSSSSSS. */ -+{ "mulhflw", 0x28B90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulhflw<.f> a,limm,c 0010111000111001F111CCCCCCAAAAAA. */ -+{ "mulhflw", 0x2E397000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulhflw<.f> a,b,limm 00101bbb00111001FBBB111110AAAAAA. */ -+{ "mulhflw", 0x28390F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulhflw<.f> 0,limm,c 0010111000111001F111CCCCCC111110. */ -+{ "mulhflw", 0x2E39703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulhflw<.f> 0,b,limm 00101bbb00111001FBBB111110111110. */ -+{ "mulhflw", 0x28390FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulhflw<.f><.cc> 0,limm,c 0010111011111001F111CCCCCC0QQQQQ. */ -+{ "mulhflw", 0x2EF97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulhflw<.f><.cc> b,b,limm 00101bbb11111001FBBB1111100QQQQQ. */ -+{ "mulhflw", 0x28F90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mulhflw<.f> a,limm,u6 0010111001111001F111uuuuuuAAAAAA. */ -+{ "mulhflw", 0x2E797000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulhflw<.f> 0,limm,u6 0010111001111001F111uuuuuu111110. */ -+{ "mulhflw", 0x2E79703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulhflw<.f><.cc> 0,limm,u6 0010111011111001F111uuuuuu1QQQQQ. */ -+{ "mulhflw", 0x2EF97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulhflw<.f> 0,limm,s12 0010111010111001F111ssssssSSSSSS. */ -+{ "mulhflw", 0x2EB97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulhflw<.f> a,limm,limm 0010111000111001F111111110AAAAAA. */ -+{ "mulhflw", 0x2E397F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulhflw<.f> 0,limm,limm 0010111000111001F111111110111110. */ -+{ "mulhflw", 0x2E397FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulhflw<.f><.cc> 0,limm,limm 0010111011111001F1111111100QQQQQ. */ -+{ "mulhflw", 0x2EF97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mulhlw<.f> a,b,c 00101bbb00111000FBBBCCCCCCAAAAAA. */ -+{ "mulhlw", 0x28380000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulhlw<.f> 0,b,c 00101bbb00111000FBBBCCCCCC111110. */ -+{ "mulhlw", 0x2838003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulhlw<.f><.cc> b,b,c 00101bbb11111000FBBBCCCCCC0QQQQQ. */ -+{ "mulhlw", 0x28F80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulhlw<.f> a,b,u6 00101bbb01111000FBBBuuuuuuAAAAAA. */ -+{ "mulhlw", 0x28780000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulhlw<.f> 0,b,u6 00101bbb01111000FBBBuuuuuu111110. */ -+{ "mulhlw", 0x2878003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulhlw<.f><.cc> b,b,u6 00101bbb11111000FBBBuuuuuu1QQQQQ. */ -+{ "mulhlw", 0x28F80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulhlw<.f> b,b,s12 00101bbb10111000FBBBssssssSSSSSS. */ -+{ "mulhlw", 0x28B80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulhlw<.f> a,limm,c 0010111000111000F111CCCCCCAAAAAA. */ -+{ "mulhlw", 0x2E387000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulhlw<.f> a,b,limm 00101bbb00111000FBBB111110AAAAAA. */ -+{ "mulhlw", 0x28380F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulhlw<.f> 0,limm,c 0010111000111000F111CCCCCC111110. */ -+{ "mulhlw", 0x2E38703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulhlw<.f> 0,b,limm 00101bbb00111000FBBB111110111110. */ -+{ "mulhlw", 0x28380FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulhlw<.f><.cc> 0,limm,c 0010111011111000F111CCCCCC0QQQQQ. */ -+{ "mulhlw", 0x2EF87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulhlw<.f><.cc> b,b,limm 00101bbb11111000FBBB1111100QQQQQ. */ -+{ "mulhlw", 0x28F80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mulhlw<.f> a,limm,u6 0010111001111000F111uuuuuuAAAAAA. */ -+{ "mulhlw", 0x2E787000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulhlw<.f> 0,limm,u6 0010111001111000F111uuuuuu111110. */ -+{ "mulhlw", 0x2E78703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulhlw<.f><.cc> 0,limm,u6 0010111011111000F111uuuuuu1QQQQQ. */ -+{ "mulhlw", 0x2EF87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulhlw<.f> 0,limm,s12 0010111010111000F111ssssssSSSSSS. */ -+{ "mulhlw", 0x2EB87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulhlw<.f> a,limm,limm 0010111000111000F111111110AAAAAA. */ -+{ "mulhlw", 0x2E387F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulhlw<.f> 0,limm,limm 0010111000111000F111111110111110. */ -+{ "mulhlw", 0x2E387FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulhlw<.f><.cc> 0,limm,limm 0010111011111000F1111111100QQQQQ. */ -+{ "mulhlw", 0x2EF87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mullw<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA. */ -+{ "mullw", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mullw<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110. */ -+{ "mullw", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mullw<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ. */ -+{ "mullw", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mullw<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA. */ -+{ "mullw", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mullw<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110. */ -+{ "mullw", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mullw<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ. */ -+{ "mullw", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mullw<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS. */ -+{ "mullw", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mullw<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA. */ -+{ "mullw", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mullw<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA. */ -+{ "mullw", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mullw<.f> 0,limm,c 0010111000110001F111CCCCCC111110. */ -+{ "mullw", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mullw<.f> 0,b,limm 00101bbb00110001FBBB111110111110. */ -+{ "mullw", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mullw<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ. */ -+{ "mullw", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mullw<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ. */ -+{ "mullw", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mullw<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA. */ -+{ "mullw", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mullw<.f> 0,limm,u6 0010111001110001F111uuuuuu111110. */ -+{ "mullw", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mullw<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ. */ -+{ "mullw", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mullw<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS. */ -+{ "mullw", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mullw<.f> a,limm,limm 0010111000110001F111111110AAAAAA. */ -+{ "mullw", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mullw<.f> 0,limm,limm 0010111000110001F111111110111110. */ -+{ "mullw", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mullw<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ. */ -+{ "mullw", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mulrdw<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA. */ -+{ "mulrdw", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulrdw<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110. */ -+{ "mulrdw", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulrdw<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ. */ -+{ "mulrdw", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulrdw<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA. */ -+{ "mulrdw", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulrdw<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110. */ -+{ "mulrdw", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulrdw<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ. */ -+{ "mulrdw", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulrdw<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS. */ -+{ "mulrdw", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulrdw<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA. */ -+{ "mulrdw", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulrdw<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA. */ -+{ "mulrdw", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulrdw<.f> 0,limm,c 0010111000001110F111CCCCCC111110. */ -+{ "mulrdw", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulrdw<.f> 0,b,limm 00101bbb00001110FBBB111110111110. */ -+{ "mulrdw", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulrdw<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ. */ -+{ "mulrdw", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulrdw<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ. */ -+{ "mulrdw", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mulrdw<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA. */ -+{ "mulrdw", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulrdw<.f> 0,limm,u6 0010111001001110F111uuuuuu111110. */ -+{ "mulrdw", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulrdw<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ. */ -+{ "mulrdw", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulrdw<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS. */ -+{ "mulrdw", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulrdw<.f> a,limm,limm 0010111000001110F111111110AAAAAA. */ -+{ "mulrdw", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulrdw<.f> 0,limm,limm 0010111000001110F111111110111110. */ -+{ "mulrdw", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulrdw<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ. */ -+{ "mulrdw", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mulrt<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA. */ -+{ "mulrt", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulrt<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110. */ -+{ "mulrt", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulrt<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ. */ -+{ "mulrt", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulrt<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA. */ -+{ "mulrt", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulrt<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110. */ -+{ "mulrt", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulrt<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ. */ -+{ "mulrt", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulrt<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS. */ -+{ "mulrt", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulrt<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA. */ -+{ "mulrt", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulrt<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA. */ -+{ "mulrt", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulrt<.f> 0,limm,c 0010111000011010F111CCCCCC111110. */ -+{ "mulrt", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulrt<.f> 0,b,limm 00101bbb00011010FBBB111110111110. */ -+{ "mulrt", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulrt<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ. */ -+{ "mulrt", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulrt<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ. */ -+{ "mulrt", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mulrt<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA. */ -+{ "mulrt", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulrt<.f> 0,limm,u6 0010111001011010F111uuuuuu111110. */ -+{ "mulrt", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulrt<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ. */ -+{ "mulrt", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulrt<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS. */ -+{ "mulrt", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulrt<.f> a,limm,limm 0010111000011010F111111110AAAAAA. */ -+{ "mulrt", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulrt<.f> 0,limm,limm 0010111000011010F111111110111110. */ -+{ "mulrt", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulrt<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ. */ -+{ "mulrt", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mult<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA. */ -+{ "mult", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mult<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110. */ -+{ "mult", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mult<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ. */ -+{ "mult", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mult<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA. */ -+{ "mult", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mult<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110. */ -+{ "mult", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mult<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ. */ -+{ "mult", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mult<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS. */ -+{ "mult", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mult<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA. */ -+{ "mult", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mult<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA. */ -+{ "mult", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mult<.f> 0,limm,c 0010111000011000F111CCCCCC111110. */ -+{ "mult", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mult<.f> 0,b,limm 00101bbb00011000FBBB111110111110. */ -+{ "mult", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mult<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ. */ -+{ "mult", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mult<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ. */ -+{ "mult", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mult<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA. */ -+{ "mult", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mult<.f> 0,limm,u6 0010111001011000F111uuuuuu111110. */ -+{ "mult", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mult<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ. */ -+{ "mult", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mult<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS. */ -+{ "mult", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mult<.f> a,limm,limm 0010111000011000F111111110AAAAAA. */ -+{ "mult", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mult<.f> 0,limm,limm 0010111000011000F111111110111110. */ -+{ "mult", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mult<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ. */ -+{ "mult", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110. */ -+{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ. */ -+{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110. */ -+{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ. */ -+{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS. */ -+{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mulu64 0,limm,c 00101110000001010111CCCCCC111110. */ -+{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mulu64 0,b,limm 00101bbb000001010BBB111110111110. */ -+{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ. */ -+{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ. */ -+{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* mulu64 0,limm,u6 00101110010001010111uuuuuu111110. */ -+{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ. */ -+{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS. */ -+{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mulu64 0,limm,limm 00101110000001010111111110111110. */ -+{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ. */ -+{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110. */ -+{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ. */ -+{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110. */ -+{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ. */ -+{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS. */ -+{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mulu64 0,limm,c 00101110000001010111CCCCCC111110. */ -+{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* mulu64 0,b,limm 00101bbb000001010BBB111110111110. */ -+{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ. */ -+{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ. */ -+{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* mulu64 0,limm,u6 00101110010001010111uuuuuu111110. */ -+{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ. */ -+{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS. */ -+{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* mulu64 0,limm,limm 00101110000001010111111110111110. */ -+{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ. */ -+{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* muludw<.f> a,b,c 00101bbb00001101FBBBCCCCCCAAAAAA. */ -+{ "muludw", 0x280D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* muludw<.f> 0,b,c 00101bbb00001101FBBBCCCCCC111110. */ -+{ "muludw", 0x280D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* muludw<.f><.cc> b,b,c 00101bbb11001101FBBBCCCCCC0QQQQQ. */ -+{ "muludw", 0x28CD0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* muludw<.f> a,b,u6 00101bbb01001101FBBBuuuuuuAAAAAA. */ -+{ "muludw", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* muludw<.f> 0,b,u6 00101bbb01001101FBBBuuuuuu111110. */ -+{ "muludw", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* muludw<.f><.cc> b,b,u6 00101bbb11001101FBBBuuuuuu1QQQQQ. */ -+{ "muludw", 0x28CD0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* muludw<.f> b,b,s12 00101bbb10001101FBBBssssssSSSSSS. */ -+{ "muludw", 0x288D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* muludw<.f> a,limm,c 0010111000001101F111CCCCCCAAAAAA. */ -+{ "muludw", 0x2E0D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* muludw<.f> a,b,limm 00101bbb00001101FBBB111110AAAAAA. */ -+{ "muludw", 0x280D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* muludw<.f> 0,limm,c 0010111000001101F111CCCCCC111110. */ -+{ "muludw", 0x2E0D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* muludw<.f> 0,b,limm 00101bbb00001101FBBB111110111110. */ -+{ "muludw", 0x280D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* muludw<.f><.cc> 0,limm,c 0010111011001101F111CCCCCC0QQQQQ. */ -+{ "muludw", 0x2ECD7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* muludw<.f><.cc> b,b,limm 00101bbb11001101FBBB1111100QQQQQ. */ -+{ "muludw", 0x28CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* muludw<.f> a,limm,u6 0010111001001101F111uuuuuuAAAAAA. */ -+{ "muludw", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* muludw<.f> 0,limm,u6 0010111001001101F111uuuuuu111110. */ -+{ "muludw", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* muludw<.f><.cc> 0,limm,u6 0010111011001101F111uuuuuu1QQQQQ. */ -+{ "muludw", 0x2ECD7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* muludw<.f> 0,limm,s12 0010111010001101F111ssssssSSSSSS. */ -+{ "muludw", 0x2E8D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* muludw<.f> a,limm,limm 0010111000001101F111111110AAAAAA. */ -+{ "muludw", 0x2E0D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* muludw<.f> 0,limm,limm 0010111000001101F111111110111110. */ -+{ "muludw", 0x2E0D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* muludw<.f><.cc> 0,limm,limm 0010111011001101F1111111100QQQQQ. */ -+{ "muludw", 0x2ECD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mululw<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA. */ -+{ "mululw", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mululw<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110. */ -+{ "mululw", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mululw<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ. */ -+{ "mululw", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mululw<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA. */ -+{ "mululw", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mululw<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110. */ -+{ "mululw", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mululw<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ. */ -+{ "mululw", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mululw<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS. */ -+{ "mululw", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mululw<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA. */ -+{ "mululw", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mululw<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA. */ -+{ "mululw", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mululw<.f> 0,limm,c 0010111000110000F111CCCCCC111110. */ -+{ "mululw", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mululw<.f> 0,b,limm 00101bbb00110000FBBB111110111110. */ -+{ "mululw", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mululw<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ. */ -+{ "mululw", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mululw<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ. */ -+{ "mululw", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mululw<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA. */ -+{ "mululw", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mululw<.f> 0,limm,u6 0010111001110000F111uuuuuu111110. */ -+{ "mululw", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mululw<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ. */ -+{ "mululw", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mululw<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS. */ -+{ "mululw", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mululw<.f> a,limm,limm 0010111000110000F111111110AAAAAA. */ -+{ "mululw", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mululw<.f> 0,limm,limm 0010111000110000F111111110111110. */ -+{ "mululw", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mululw<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ. */ -+{ "mululw", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* mulut<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA. */ -+{ "mulut", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulut<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110. */ -+{ "mulut", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* mulut<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ. */ -+{ "mulut", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulut<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA. */ -+{ "mulut", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulut<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110. */ -+{ "mulut", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulut<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ. */ -+{ "mulut", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulut<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS. */ -+{ "mulut", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulut<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA. */ -+{ "mulut", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulut<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA. */ -+{ "mulut", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulut<.f> 0,limm,c 0010111000011001F111CCCCCC111110. */ -+{ "mulut", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* mulut<.f> 0,b,limm 00101bbb00011001FBBB111110111110. */ -+{ "mulut", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* mulut<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ. */ -+{ "mulut", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* mulut<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ. */ -+{ "mulut", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* mulut<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA. */ -+{ "mulut", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulut<.f> 0,limm,u6 0010111001011001F111uuuuuu111110. */ -+{ "mulut", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* mulut<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ. */ -+{ "mulut", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* mulut<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS. */ -+{ "mulut", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* mulut<.f> a,limm,limm 0010111000011001F111111110AAAAAA. */ -+{ "mulut", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulut<.f> 0,limm,limm 0010111000011001F111111110111110. */ -+{ "mulut", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* mulut<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ. */ -+{ "mulut", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* neg<.f> a,b 00100bbb01001110FBBB000000AAAAAA. */ -+{ "neg", 0x204E0000, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB }, { C_F }}, -+ -+/* neg<.f> 0,b 00100bbb01001110FBBB000000111110. */ -+{ "neg", 0x204E0000, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB }, { C_F }}, -+ -+/* neg<.f><.cc> b,b 00100bbb11001110FBBB0000001QQQQQ. */ -+{ "neg", 0x20CE0020, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup }, { C_F, C_CC }}, -+ -+/* neg<.f> a,limm 0010011001001110F111000000AAAAAA. */ -+{ "neg", 0x264E7000, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM }, { C_F }}, -+ -+/* neg<.f><.cc> 0,limm 0010011011001110F1110000001QQQQQ. */ -+{ "neg", 0x26CE7020, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* negs<.f> b,c 00101bbb00101111FBBBCCCCCC000111. */ -+{ "negs", 0x282F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* negs<.f> 0,c 0010111000101111F111CCCCCC000111. */ -+{ "negs", 0x2E2F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* negs<.f> b,u6 00101bbb01101111FBBBuuuuuu000111. */ -+{ "negs", 0x286F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negs<.f> 0,u6 0010111001101111F111uuuuuu000111. */ -+{ "negs", 0x2E6F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negs<.f> b,limm 00101bbb00101111FBBB111110000111. */ -+{ "negs", 0x282F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* negs<.f> 0,limm 0010111000101111F111111110000111. */ -+{ "negs", 0x2E2F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* negsh<.f> b,c 00101bbb00101111FBBBCCCCCC000110. */ -+{ "negsh", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* negsh<.f> 0,c 0010111000101111F111CCCCCC000110. */ -+{ "negsh", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* negsh<.f> b,u6 00101bbb01101111FBBBuuuuuu000110. */ -+{ "negsh", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negsh<.f> 0,u6 0010111001101111F111uuuuuu000110. */ -+{ "negsh", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negsh<.f> b,limm 00101bbb00101111FBBB111110000110. */ -+{ "negsh", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* negsh<.f> 0,limm 0010111000101111F111111110000110. */ -+{ "negsh", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* negsw<.f> b,c 00101bbb00101111FBBBCCCCCC000110. */ -+{ "negsw", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* negsw<.f> 0,c 0010111000101111F111CCCCCC000110. */ -+{ "negsw", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* negsw<.f> b,u6 00101bbb01101111FBBBuuuuuu000110. */ -+{ "negsw", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negsw<.f> 0,u6 0010111001101111F111uuuuuu000110. */ -+{ "negsw", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* negsw<.f> b,limm 00101bbb00101111FBBB111110000110. */ -+{ "negsw", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* negsw<.f> 0,limm 0010111000101111F111111110000110. */ -+{ "negsw", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* neg_s b,c 01111bbbccc10011. */ -+{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* nop_s 0111100011100000. */ -+{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001. */ -+{ "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* norm<.f> 0,c 0010111000101111F111CCCCCC000001. */ -+{ "norm", 0x2E2F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* norm<.f> b,u6 00101bbb01101111FBBBuuuuuu000001. */ -+{ "norm", 0x286F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* norm<.f> 0,u6 0010111001101111F111uuuuuu000001. */ -+{ "norm", 0x2E6F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* norm<.f> b,limm 00101bbb00101111FBBB111110000001. */ -+{ "norm", 0x282F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* norm<.f> 0,limm 0010111000101111F111111110000001. */ -+{ "norm", 0x2E2F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* normacc b,c 00101bbb001011110BBBCCCCCC011001. */ -+{ "normacc", 0x282F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* normacc 0,c 00101110001011110111CCCCCC011001. */ -+{ "normacc", 0x2E2F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* normacc b,u6 00101bbb011011110BBBuuuuuu011001. */ -+{ "normacc", 0x286F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* normacc 0,u6 00101110011011110111uuuuuu011001. */ -+{ "normacc", 0x2E6F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* normacc b,limm 00101bbb001011110BBB111110011001. */ -+{ "normacc", 0x282F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* normacc 0,limm 00101110001011110111111110011001. */ -+{ "normacc", 0x2E2F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* normh<.f> b,c 00101bbb00101111FBBBCCCCCC001000. */ -+{ "normh", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* normh<.f> 0,c 0010111000101111F111CCCCCC001000. */ -+{ "normh", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* normh<.f> b,u6 00101bbb01101111FBBBuuuuuu001000. */ -+{ "normh", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* normh<.f> 0,u6 0010111001101111F111uuuuuu001000. */ -+{ "normh", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* normh<.f> b,limm 00101bbb00101111FBBB111110001000. */ -+{ "normh", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* normh<.f> 0,limm 0010111000101111F111111110001000. */ -+{ "normh", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* normw<.f> b,c 00101bbb00101111FBBBCCCCCC001000. */ -+{ "normw", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* normw<.f> 0,c 0010111000101111F111CCCCCC001000. */ -+{ "normw", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* normw<.f> b,u6 00101bbb01101111FBBBuuuuuu001000. */ -+{ "normw", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* normw<.f> 0,u6 0010111001101111F111uuuuuu001000. */ -+{ "normw", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* normw<.f> b,limm 00101bbb00101111FBBB111110001000. */ -+{ "normw", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* normw<.f> 0,limm 0010111000101111F111111110001000. */ -+{ "normw", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* not<.f> b,c 00100bbb00101111FBBBCCCCCC001010. */ -+{ "not", 0x202F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* not<.f> 0,c 0010011000101111F111CCCCCC001010. */ -+{ "not", 0x262F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* not<.f> b,u6 00100bbb01101111FBBBuuuuuu001010. */ -+{ "not", 0x206F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* not<.f> 0,u6 0010011001101111F111uuuuuu001010. */ -+{ "not", 0x266F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* not<.f> b,limm 00100bbb00101111FBBB111110001010. */ -+{ "not", 0x202F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* not<.f> 0,limm 0010011000101111F111111110001010. */ -+{ "not", 0x262F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* not_s b,c 01111bbbccc10010. */ -+{ "not_s", 0x00007812, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* or<.f> a,b,c 00100bbb00000101FBBBCCCCCCAAAAAA. */ -+{ "or", 0x20050000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* or<.f> 0,b,c 00100bbb00000101FBBBCCCCCC111110. */ -+{ "or", 0x2005003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* or<.f><.cc> b,b,c 00100bbb11000101FBBBCCCCCC0QQQQQ. */ -+{ "or", 0x20C50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* or<.f> a,b,u6 00100bbb01000101FBBBuuuuuuAAAAAA. */ -+{ "or", 0x20450000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* or<.f> 0,b,u6 00100bbb01000101FBBBuuuuuu111110. */ -+{ "or", 0x2045003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* or<.f><.cc> b,b,u6 00100bbb11000101FBBBuuuuuu1QQQQQ. */ -+{ "or", 0x20C50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* or<.f> b,b,s12 00100bbb10000101FBBBssssssSSSSSS. */ -+{ "or", 0x20850000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* or<.f> a,limm,c 0010011000000101F111CCCCCCAAAAAA. */ -+{ "or", 0x26057000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* or<.f> a,b,limm 00100bbb00000101FBBB111110AAAAAA. */ -+{ "or", 0x20050F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* or<.f> 0,limm,c 0010011000000101F111CCCCCC111110. */ -+{ "or", 0x2605703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* or<.f> 0,b,limm 00100bbb00000101FBBB111110111110. */ -+{ "or", 0x20050FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* or<.f><.cc> b,b,limm 00100bbb11000101FBBB1111100QQQQQ. */ -+{ "or", 0x20C50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* or<.f><.cc> 0,limm,c 0010011011000101F111CCCCCC0QQQQQ. */ -+{ "or", 0x26C57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* or<.f> a,limm,u6 0010011001000101F111uuuuuuAAAAAA. */ -+{ "or", 0x26457000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* or<.f> 0,limm,u6 0010011001000101F111uuuuuu111110. */ -+{ "or", 0x2645703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* or<.f><.cc> 0,limm,u6 0010011011000101F111uuuuuu1QQQQQ. */ -+{ "or", 0x26C57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* or<.f> 0,limm,s12 0010011010000101F111ssssssSSSSSS. */ -+{ "or", 0x26857000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* or<.f> a,limm,limm 0010011000000101F111111110AAAAAA. */ -+{ "or", 0x26057F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* or<.f> 0,limm,limm 0010011000000101F111111110111110. */ -+{ "or", 0x26057FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* or<.f><.cc> 0,limm,limm 0010011011000101F1111111100QQQQQ. */ -+{ "or", 0x26C57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* or_s b,b,c 01111bbbccc00101. */ -+{ "or_s", 0x00007805, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* pkqb<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA. */ -+{ "pkqb", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* pkqb<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ. */ -+{ "pkqb", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* pkqb<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA. */ -+{ "pkqb", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* pkqb<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ. */ -+{ "pkqb", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* pkqb<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS. */ -+{ "pkqb", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* pkqb<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA. */ -+{ "pkqb", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* pkqb<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA. */ -+{ "pkqb", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* pkqb<.f><.cc> b,b,limm 00110bbb11100000FBBB1111100QQQQQ. */ -+{ "pkqb", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* pop_s b 11000bbb11000001. */ -+{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, NONE, { OPERAND_RB_S }, { C_AA_AB }}, -+ -+/* pop_s OPERAND_BLINK 11000RRR11010001. */ -+{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, NONE, { OPERAND_BLINK_S }, { C_AA_AB }}, -+ -+/* push_s b 11000bbb11100001. */ -+{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, NONE, { OPERAND_RB_S }, { C_AA_AW }}, -+ -+/* push_s blink 11000RRR11110001. */ -+{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, NONE, { OPERAND_BLINK_S }, { C_AA_AW }}, -+ -+/* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */ -+{ "qmach", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmach<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110. */ -+{ "qmach", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmach<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ. */ -+{ "qmach", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmach<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA. */ -+{ "qmach", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmach<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110. */ -+{ "qmach", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmach<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ. */ -+{ "qmach", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmach<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS. */ -+{ "qmach", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmach<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA. */ -+{ "qmach", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmach<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA. */ -+{ "qmach", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmach<.f> 0,limm,c 0010111000110100F111CCCCCC111110. */ -+{ "qmach", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmach<.f> 0,b,limm 00101bbb00110100FBBB111110111110. */ -+{ "qmach", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmach<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ. */ -+{ "qmach", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmach<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ. */ -+{ "qmach", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmach<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA. */ -+{ "qmach", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmach<.f> 0,limm,u6 0010111001110100F111uuuuuu111110. */ -+{ "qmach", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmach<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ. */ -+{ "qmach", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmach<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS. */ -+{ "qmach", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmach<.f> a,limm,limm 0010111000110100F111111110AAAAAA. */ -+{ "qmach", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmach<.f> 0,limm,limm 0010111000110100F111111110111110. */ -+{ "qmach", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmach<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ. */ -+{ "qmach", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmachf<.f> 0,b,c 00110bbb00110101FBBBCCCCCC111110 */ -+{ "qmachf", 0x3035003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmachf<.f> a,b,c 00110bbb00110101FBBBCCCCCCAAAAAA */ -+{ "qmachf", 0x30350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmachf<.f><.cc> b,b,c 00110bbb11110101FBBBCCCCCC0QQQQQ */ -+{ "qmachf", 0x30F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmachf<.f> 0,b,u6 00110bbb01110101FBBBuuuuuu111110 */ -+{ "qmachf", 0x3075003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachf<.f> a,b,u6 00110bbb01110101FBBBuuuuuuAAAAAA */ -+{ "qmachf", 0x30750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachf<.f><.cc> b,b,u6 00110bbb11110101FBBBuuuuuu1QQQQQ */ -+{ "qmachf", 0x30F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmachf<.f> b,b,s12 00110bbb10110101FBBBssssssSSSSSS */ -+{ "qmachf", 0x30B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmachf<.f> 0,b,limm 00110bbb00110101FBBB111110111110 */ -+{ "qmachf", 0x30350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmachf<.f><.cc> b,b,limm 00110bbb11110101FBBB1111100QQQQQ */ -+{ "qmachf", 0x30F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmachf<.f> a,limm,c 0011011000110101F111CCCCCCAAAAAA */ -+{ "qmachf", 0x36357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmachf<.f><.cc> 0,limm,c 0011011011110101F111CCCCCC0QQQQQ */ -+{ "qmachf", 0x36F57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmachf<.f> 0,limm,c 0011011000110101F111CCCCCC111110 */ -+{ "qmachf", 0x3635703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmachf<.f> a,b,limm 00110bbb00110101FBBB111110AAAAAA */ -+{ "qmachf", 0x30350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmachf<.f><.cc> 0,limm,u6 0011011011110101F111uuuuuu1QQQQQ */ -+{ "qmachf", 0x36F57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmachf<.f> a,limm,u6 0011011001110101F111uuuuuuAAAAAA */ -+{ "qmachf", 0x36757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachf<.f> 0,limm,u6 0011011001110101F111uuuuuu111110 */ -+{ "qmachf", 0x3675703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachf<.f> 0,limm,s12 0011011010110101F111ssssssSSSSSS */ -+{ "qmachf", 0x36B57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmachf<.f> a,limm,limm 0011011000110101F111111110AAAAAA */ -+{ "qmachf", 0x36357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmachf<.f><.cc> 0,limm,limm 0011011011110101F1111111100QQQQQ */ -+{ "qmachf", 0x36F57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmachf<.f> 0,limm,limm 0011011000110101F111111110111110 */ -+{ "qmachf", 0x36357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmachu<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA. */ -+{ "qmachu", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmachu<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110. */ -+{ "qmachu", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmachu<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ. */ -+{ "qmachu", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmachu<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA. */ -+{ "qmachu", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachu<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110. */ -+{ "qmachu", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachu<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ. */ -+{ "qmachu", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmachu<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS. */ -+{ "qmachu", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmachu<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA. */ -+{ "qmachu", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmachu<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA. */ -+{ "qmachu", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmachu<.f> 0,limm,c 0010111000110101F111CCCCCC111110. */ -+{ "qmachu", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmachu<.f> 0,b,limm 00101bbb00110101FBBB111110111110. */ -+{ "qmachu", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmachu<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ. */ -+{ "qmachu", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmachu<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ. */ -+{ "qmachu", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmachu<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA. */ -+{ "qmachu", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachu<.f> 0,limm,u6 0010111001110101F111uuuuuu111110. */ -+{ "qmachu", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmachu<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ. */ -+{ "qmachu", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmachu<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS. */ -+{ "qmachu", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmachu<.f> a,limm,limm 0010111000110101F111111110AAAAAA. */ -+{ "qmachu", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmachu<.f> 0,limm,limm 0010111000110101F111111110111110. */ -+{ "qmachu", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmachu<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ. */ -+{ "qmachu", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA. */ -+{ "qmpyh", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyh<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110. */ -+{ "qmpyh", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyh<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ. */ -+{ "qmpyh", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA. */ -+{ "qmpyh", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyh<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110. */ -+{ "qmpyh", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyh<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ. */ -+{ "qmpyh", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS. */ -+{ "qmpyh", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyh<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA. */ -+{ "qmpyh", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyh<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA. */ -+{ "qmpyh", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyh<.f> 0,limm,c 0010111000110000F111CCCCCC111110. */ -+{ "qmpyh", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyh<.f> 0,b,limm 00101bbb00110000FBBB111110111110. */ -+{ "qmpyh", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyh<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ. */ -+{ "qmpyh", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmpyh<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ. */ -+{ "qmpyh", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA. */ -+{ "qmpyh", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyh<.f> 0,limm,u6 0010111001110000F111uuuuuu111110. */ -+{ "qmpyh", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyh<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ. */ -+{ "qmpyh", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS. */ -+{ "qmpyh", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyh<.f> a,limm,limm 0010111000110000F111111110AAAAAA. */ -+{ "qmpyh", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyh<.f> 0,limm,limm 0010111000110000F111111110111110. */ -+{ "qmpyh", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyh<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ. */ -+{ "qmpyh", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmpyh<.f> a,limm,limm 0010111000110000F111111110AAAAAA */ -+{ "qmpyh", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> b,b,c 00110bbb11110001FBBBCCCCCC0QQQQQ */ -+{ "qmpyhf", 0x30F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> a,b,c 00110bbb00110001FBBBCCCCCCAAAAAA */ -+{ "qmpyhf", 0x30310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhf<.f> 0,b,c 00110bbb00110001FBBBCCCCCC111110 */ -+{ "qmpyhf", 0x3031003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> b,b,u6 00110bbb11110001FBBBuuuuuu1QQQQQ */ -+{ "qmpyhf", 0x30F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> a,b,u6 00110bbb01110001FBBBuuuuuuAAAAAA */ -+{ "qmpyhf", 0x30710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhf<.f> 0,b,u6 00110bbb01110001FBBBuuuuuu111110 */ -+{ "qmpyhf", 0x3071003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhf<.f> b,b,s12 00110bbb10110001FBBBssssssSSSSSS */ -+{ "qmpyhf", 0x30B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyhf<.f> 0,limm,c 0011011000110001F111CCCCCC111110 */ -+{ "qmpyhf", 0x3631703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhf<.f> a,b,limm 00110bbb00110001FBBB111110AAAAAA */ -+{ "qmpyhf", 0x30310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyhf<.f> a,limm,c 0011011000110001F111CCCCCCAAAAAA */ -+{ "qmpyhf", 0x36317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhf<.f> 0,b,limm 00110bbb00110001FBBB111110111110 */ -+{ "qmpyhf", 0x30310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> b,b,limm 00110bbb11110001FBBB1111100QQQQQ */ -+{ "qmpyhf", 0x30F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f><.cc> 0,limm,c 0011011011110001F111CCCCCC0QQQQQ */ -+{ "qmpyhf", 0x36F17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> a,limm,u6 0011011001110001F111uuuuuuAAAAAA */ -+{ "qmpyhf", 0x36717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhf<.f> 0,limm,u6 0011011001110001F111uuuuuu111110 */ -+{ "qmpyhf", 0x3671703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> 0,limm,u6 0011011011110001F111uuuuuu1QQQQQ */ -+{ "qmpyhf", 0x36F17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> 0,limm,s12 0011011010110001F111ssssssSSSSSS */ -+{ "qmpyhf", 0x36B17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyhf<.f><.cc> 0,limm,limm 0011011011110001F1111111100QQQQQ */ -+{ "qmpyhf", 0x36F17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* qmpyhf<.f> a,limm,limm 0011011000110001F111111110AAAAAA */ -+{ "qmpyhf", 0x36317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyhf<.f> 0,limm,limm 0011011000110001F111111110111110 */ -+{ "qmpyhf", 0x36317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyhu<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA. */ -+{ "qmpyhu", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhu<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110. */ -+{ "qmpyhu", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ. */ -+{ "qmpyhu", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA. */ -+{ "qmpyhu", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhu<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110. */ -+{ "qmpyhu", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ. */ -+{ "qmpyhu", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS. */ -+{ "qmpyhu", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyhu<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA. */ -+{ "qmpyhu", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhu<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA. */ -+{ "qmpyhu", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyhu<.f> 0,limm,c 0010111000110001F111CCCCCC111110. */ -+{ "qmpyhu", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* qmpyhu<.f> 0,b,limm 00101bbb00110001FBBB111110111110. */ -+{ "qmpyhu", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ. */ -+{ "qmpyhu", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ. */ -+{ "qmpyhu", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA. */ -+{ "qmpyhu", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhu<.f> 0,limm,u6 0010111001110001F111uuuuuu111110. */ -+{ "qmpyhu", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ. */ -+{ "qmpyhu", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* qmpyhu<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS. */ -+{ "qmpyhu", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* qmpyhu<.f> a,limm,limm 0010111000110001F111111110AAAAAA. */ -+{ "qmpyhu", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyhu<.f> 0,limm,limm 0010111000110001F111111110111110. */ -+{ "qmpyhu", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* qmpyhu<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ. */ -+{ "qmpyhu", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* rcmp b,c 00100bbb000011011BBBCCCCCCRRRRRR. */ -+{ "rcmp", 0x200D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* rcmp b,c 00100bbb000011011BBBCCCCCC000000. */ -+{ "rcmp", 0x200D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* rcmp<.cc> b,c 00100bbb110011011BBBCCCCCC0QQQQQ. */ -+{ "rcmp", 0x20CD8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* rcmp b,u6 00100bbb010011011BBBuuuuuuRRRRRR. */ -+{ "rcmp", 0x204D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rcmp b,u6 00100bbb010011011BBBuuuuuu000000. */ -+{ "rcmp", 0x204D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rcmp<.cc> b,u6 00100bbb110011011BBBuuuuuu1QQQQQ. */ -+{ "rcmp", 0x20CD8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* rcmp b,s12 00100bbb100011011BBBssssssSSSSSS. */ -+{ "rcmp", 0x208D8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* rcmp limm,c 00100110000011011111CCCCCCRRRRRR. */ -+{ "rcmp", 0x260DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* rcmp b,limm 00100bbb000011011BBB111110RRRRRR. */ -+{ "rcmp", 0x200D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* rcmp limm,c 00100110000011011111CCCCCC000000. */ -+{ "rcmp", 0x260DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* rcmp b,limm 00100bbb000011011BBB111110000000. */ -+{ "rcmp", 0x200D8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* rcmp<.cc> limm,c 00100110110011011111CCCCCC0QQQQQ. */ -+{ "rcmp", 0x26CDF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* rcmp<.cc> b,limm 00100bbb110011011BBB1111100QQQQQ. */ -+{ "rcmp", 0x20CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* rcmp limm,u6 00100110010011011111uuuuuuRRRRRR. */ -+{ "rcmp", 0x264DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rcmp limm,u6 00100110010011011111uuuuuu000000. */ -+{ "rcmp", 0x264DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rcmp<.cc> limm,u6 00100110110011011111uuuuuu1QQQQQ. */ -+{ "rcmp", 0x26CDF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* rcmp limm,s12 00100110100011011111ssssssSSSSSS. */ -+{ "rcmp", 0x268DF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* rcmp limm,limm 00100110000011011111111110RRRRRR. */ -+{ "rcmp", 0x260DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* rcmp limm,limm 00100110000011011111111110000000. */ -+{ "rcmp", 0x260DFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* rcmp<.cc> limm,limm 001001101100110111111111100QQQQQ. */ -+{ "rcmp", 0x26CDFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */ -+{ "rem", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */ -+{ "rem", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */ -+{ "rem", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rem<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */ -+{ "rem", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */ -+{ "rem", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */ -+{ "rem", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rem<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */ -+{ "rem", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rem<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */ -+{ "rem", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */ -+{ "rem", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rem<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */ -+{ "rem", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rem<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */ -+{ "rem", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rem<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */ -+{ "rem", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* rem<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */ -+{ "rem", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rem<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */ -+{ "rem", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */ -+{ "rem", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rem<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */ -+{ "rem", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rem<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */ -+{ "rem", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rem<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */ -+{ "rem", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rem<.f> 0,limm,limm 0010111000001000F111111110111110. */ -+{ "rem", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rem<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */ -+{ "rem", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* remu<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */ -+{ "remu", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */ -+{ "remu", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */ -+{ "remu", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* remu<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */ -+{ "remu", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */ -+{ "remu", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */ -+{ "remu", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* remu<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */ -+{ "remu", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* remu<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */ -+{ "remu", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */ -+{ "remu", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* remu<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */ -+{ "remu", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* remu<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */ -+{ "remu", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* remu<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */ -+{ "remu", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* remu<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */ -+{ "remu", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* remu<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */ -+{ "remu", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */ -+{ "remu", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* remu<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */ -+{ "remu", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* remu<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */ -+{ "remu", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* remu<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */ -+{ "remu", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* remu<.f> 0,limm,limm 0010111000001001F111111110111110. */ -+{ "remu", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* remu<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */ -+{ "remu", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* rlc<.f> b,c 00100bbb00101111FBBBCCCCCC001011. */ -+{ "rlc", 0x202F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rlc<.f> 0,c 0010011000101111F111CCCCCC001011. */ -+{ "rlc", 0x262F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rlc<.f> b,u6 00100bbb01101111FBBBuuuuuu001011. */ -+{ "rlc", 0x206F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rlc<.f> 0,u6 0010011001101111F111uuuuuu001011. */ -+{ "rlc", 0x266F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rlc<.f> b,limm 00100bbb00101111FBBB111110001011. */ -+{ "rlc", 0x202F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rlc<.f> 0,limm 0010011000101111F111111110001011. */ -+{ "rlc", 0x262F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rnd16<.f> b,c 00101bbb00101111FBBBCCCCCC000011. */ -+{ "rnd16", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rnd16<.f> 0,c 0010111000101111F111CCCCCC000011. */ -+{ "rnd16", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rnd16<.f> b,u6 00101bbb01101111FBBBuuuuuu000011. */ -+{ "rnd16", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rnd16<.f> 0,u6 0010111001101111F111uuuuuu000011. */ -+{ "rnd16", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rnd16<.f> b,limm 00101bbb00101111FBBB111110000011. */ -+{ "rnd16", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rnd16<.f> 0,limm 0010111000101111F111111110000011. */ -+{ "rnd16", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rndh<.f> b,c 00101bbb00101111FBBBCCCCCC000011. */ -+{ "rndh", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* rndh<.f> 0,c 0010111000101111F111CCCCCC000011. */ -+{ "rndh", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rndh<.f> b,u6 00101bbb01101111FBBBuuuuuu000011. */ -+{ "rndh", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rndh<.f> 0,u6 0010111001101111F111uuuuuu000011. */ -+{ "rndh", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rndh<.f> b,limm 00101bbb00101111FBBB111110000011. */ -+{ "rndh", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* rndh<.f> 0,limm 0010111000101111F111111110000011. */ -+{ "rndh", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rol<.f> b,c 00100bbb00101111FBBBCCCCCC001101. */ -+{ "rol", 0x202F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rol<.f> 0,c 0010011000101111F111CCCCCC001101. */ -+{ "rol", 0x262F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rol<.f> b,u6 00100bbb01101111FBBBuuuuuu001101. */ -+{ "rol", 0x206F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rol<.f> 0,u6 0010011001101111F111uuuuuu001101. */ -+{ "rol", 0x266F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rol<.f> b,limm 00100bbb00101111FBBB111110001101. */ -+{ "rol", 0x202F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rol<.f> 0,limm 0010011000101111F111111110001101. */ -+{ "rol", 0x262F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rol8<.f> b,c 00101bbb00101111FBBBCCCCCC010000. */ -+{ "rol8", 0x282F0010, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rol8<.f> 0,c 0010111000101111F111CCCCCC010000. */ -+{ "rol8", 0x2E2F7010, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rol8<.f> b,u6 00101bbb01101111FBBBuuuuuu010000. */ -+{ "rol8", 0x286F0010, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rol8<.f> 0,u6 0010111001101111F111uuuuuu010000. */ -+{ "rol8", 0x2E6F7010, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rol8<.f> b,limm 00101bbb00101111FBBB111110010000. */ -+{ "rol8", 0x282F0F90, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rol8<.f> 0,limm 0010111000101111F111111110010000. */ -+{ "rol8", 0x2E2F7F90, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f> b,c 00100bbb00101111FBBBCCCCCC000011. */ -+{ "ror", 0x202F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> 0,c 0010011000101111F111CCCCCC000011. */ -+{ "ror", 0x262F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> a,b,c 00101bbb00000011FBBBCCCCCCAAAAAA. */ -+{ "ror", 0x28030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> 0,b,c 00101bbb00000011FBBBCCCCCC111110. */ -+{ "ror", 0x2803003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f><.cc> b,b,c 00101bbb11000011FBBBCCCCCC0QQQQQ. */ -+{ "ror", 0x28C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* ror<.f> b,u6 00100bbb01101111FBBBuuuuuu000011. */ -+{ "ror", 0x206F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f> 0,u6 0010011001101111F111uuuuuu000011. */ -+{ "ror", 0x266F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f> a,b,u6 00101bbb01000011FBBBuuuuuuAAAAAA. */ -+{ "ror", 0x28430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f> 0,b,u6 00101bbb01000011FBBBuuuuuu111110. */ -+{ "ror", 0x2843003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f><.cc> b,b,u6 00101bbb11000011FBBBuuuuuu1QQQQQ. */ -+{ "ror", 0x28C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* ror<.f> b,b,s12 00101bbb10000011FBBBssssssSSSSSS. */ -+{ "ror", 0x28830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* ror<.f> b,limm 00100bbb00101111FBBB111110000011. */ -+{ "ror", 0x202F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f> 0,limm 0010011000101111F111111110000011. */ -+{ "ror", 0x262F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f> a,limm,c 0010111000000011F111CCCCCCAAAAAA. */ -+{ "ror", 0x2E037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> a,b,limm 00101bbb00000011FBBB111110AAAAAA. */ -+{ "ror", 0x28030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f> 0,limm,c 0010111000000011F111CCCCCC111110. */ -+{ "ror", 0x2E03703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* ror<.f> 0,b,limm 00101bbb00000011FBBB111110111110. */ -+{ "ror", 0x28030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ror<.f><.cc> b,b,limm 00101bbb11000011FBBB1111100QQQQQ. */ -+{ "ror", 0x28C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* ror<.f><.cc> 0,limm,c 0010111011000011F111CCCCCC0QQQQQ. */ -+{ "ror", 0x2EC37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* ror<.f> a,limm,u6 0010111001000011F111uuuuuuAAAAAA. */ -+{ "ror", 0x2E437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f> 0,limm,u6 0010111001000011F111uuuuuu111110. */ -+{ "ror", 0x2E43703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror<.f><.cc> 0,limm,u6 0010111011000011F111uuuuuu1QQQQQ. */ -+{ "ror", 0x2EC37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* ror<.f> 0,limm,s12 0010111010000011F111ssssssSSSSSS. */ -+{ "ror", 0x2E837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* ror<.f> a,limm,limm 0010111000000011F111111110AAAAAA. */ -+{ "ror", 0x2E037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* ror<.f> 0,limm,limm 0010111000000011F111111110111110. */ -+{ "ror", 0x2E037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* ror<.f><.cc> 0,limm,limm 0010111011000011F1111111100QQQQQ. */ -+{ "ror", 0x2EC37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* ror8<.f> b,c 00101bbb00101111FBBBCCCCCC010001. */ -+{ "ror8", 0x282F0011, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* ror8<.f> 0,c 0010111000101111F111CCCCCC010001. */ -+{ "ror8", 0x2E2F7011, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* ror8<.f> b,u6 00101bbb01101111FBBBuuuuuu010001. */ -+{ "ror8", 0x286F0011, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror8<.f> 0,u6 0010111001101111F111uuuuuu010001. */ -+{ "ror8", 0x2E6F7011, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* ror8<.f> b,limm 00101bbb00101111FBBB111110010001. */ -+{ "ror8", 0x282F0F91, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* ror8<.f> 0,limm 0010111000101111F111111110010001. */ -+{ "ror8", 0x2E2F7F91, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rrc<.f> b,c 00100bbb00101111FBBBCCCCCC000100. */ -+{ "rrc", 0x202F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rrc<.f> 0,c 0010011000101111F111CCCCCC000100. */ -+{ "rrc", 0x262F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* rrc<.f> b,u6 00100bbb01101111FBBBuuuuuu000100. */ -+{ "rrc", 0x206F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rrc<.f> 0,u6 0010011001101111F111uuuuuu000100. */ -+{ "rrc", 0x266F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rrc<.f> b,limm 00100bbb00101111FBBB111110000100. */ -+{ "rrc", 0x202F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rrc<.f> 0,limm 0010011000101111F111111110000100. */ -+{ "rrc", 0x262F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* rsub<.f> a,b,c 00100bbb00001110FBBBCCCCCCAAAAAA. */ -+{ "rsub", 0x200E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rsub<.f> 0,b,c 00100bbb00001110FBBBCCCCCC111110. */ -+{ "rsub", 0x200E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* rsub<.f><.cc> b,b,c 00100bbb11001110FBBBCCCCCC0QQQQQ. */ -+{ "rsub", 0x20CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rsub<.f> a,b,u6 00100bbb01001110FBBBuuuuuuAAAAAA. */ -+{ "rsub", 0x204E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsub<.f> 0,b,u6 00100bbb01001110FBBBuuuuuu111110. */ -+{ "rsub", 0x204E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsub<.f><.cc> b,b,u6 00100bbb11001110FBBBuuuuuu1QQQQQ. */ -+{ "rsub", 0x20CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rsub<.f> b,b,s12 00100bbb10001110FBBBssssssSSSSSS. */ -+{ "rsub", 0x208E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rsub<.f> a,limm,c 0010011000001110F111CCCCCCAAAAAA. */ -+{ "rsub", 0x260E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rsub<.f> a,b,limm 00100bbb00001110FBBB111110AAAAAA. */ -+{ "rsub", 0x200E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rsub<.f> 0,limm,c 0010011000001110F111CCCCCC111110. */ -+{ "rsub", 0x260E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* rsub<.f> 0,b,limm 00100bbb00001110FBBB111110111110. */ -+{ "rsub", 0x200E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* rsub<.f><.cc> b,b,limm 00100bbb11001110FBBB1111100QQQQQ. */ -+{ "rsub", 0x20CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* rsub<.f><.cc> 0,limm,c 0010011011001110F111CCCCCC0QQQQQ. */ -+{ "rsub", 0x26CE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* rsub<.f> a,limm,u6 0010011001001110F111uuuuuuAAAAAA. */ -+{ "rsub", 0x264E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsub<.f> 0,limm,u6 0010011001001110F111uuuuuu111110. */ -+{ "rsub", 0x264E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* rsub<.f><.cc> 0,limm,u6 0010011011001110F111uuuuuu1QQQQQ. */ -+{ "rsub", 0x26CE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* rsub<.f> 0,limm,s12 0010011010001110F111ssssssSSSSSS. */ -+{ "rsub", 0x268E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* rsub<.f> a,limm,limm 0010011000001110F111111110AAAAAA. */ -+{ "rsub", 0x260E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rsub<.f> 0,limm,limm 0010011000001110F111111110111110. */ -+{ "rsub", 0x260E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* rsub<.f><.cc> 0,limm,limm 0010011011001110F1111111100QQQQQ. */ -+{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* rtie 00100100011011110000000000111111. */ -+{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* rtsc b,0 00110bbb01101111RBBB000000011010. */ -+{ "rtsc", 0x306F001A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_ZB }, { 0 }}, -+ -+/* rtsc 0,0 0011011001101111R111000000011010. */ -+{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_ZB }, { 0 }}, -+ -+/* rtsc b,c 00110bbb00101111RBBBCCCCCC011010. */ -+{ "rtsc", 0x302F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* rtsc 0,c 0011011000101111R111CCCCCC011010. */ -+{ "rtsc", 0x362F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* rtsc b,u6 00110bbb01101111RBBBuuuuuu011010. */ -+{ "rtsc", 0x306F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rtsc 0,u6 0011011001101111R111uuuuuu011010. */ -+{ "rtsc", 0x366F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* rtsc b,limm 00110bbb00101111RBBB111110011010. */ -+{ "rtsc", 0x302F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* rtsc 0,limm 0011011000101111R111111110011010. */ -+{ "rtsc", 0x362F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* rtsc 0011011001101111R111000000011010. */ -+{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* sat16<.f> b,c 00101bbb00101111FBBBCCCCCC000010. */ -+{ "sat16", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sat16<.f> 0,c 0010111000101111F111CCCCCC000010. */ -+{ "sat16", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sat16<.f> b,u6 00101bbb01101111FBBBuuuuuu000010. */ -+{ "sat16", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sat16<.f> 0,u6 0010111001101111F111uuuuuu000010. */ -+{ "sat16", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sat16<.f> b,limm 00101bbb00101111FBBB111110000010. */ -+{ "sat16", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sat16<.f> 0,limm 0010111000101111F111111110000010. */ -+{ "sat16", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* satf<.f> b,c 00101bbb00101111FBBBCCCCCC011010 */ -+{ "satf", 0x282F001A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+/* satf<.f> 0,c 0010111000101111F111CCCCCC011010 */ -+{ "satf", 0x2E2F701A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* satf<.f> b,u6 00101bbb01101111FBBBuuuuuu011010 */ -+{ "satf", 0x286F001A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* satf<.f> 0,u6 0010111001101111F111uuuuuu011010 */ -+{ "satf", 0x2E6F701A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* satf<.f> 0,limm 0010111000101111F111111110011010 */ -+{ "satf", 0x2E2F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* satf<.f> b,limm 00101bbb00101111FBBB111110011010 */ -+{ "satf", 0x282F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sath<.f> b,c 00101bbb00101111FBBBCCCCCC000010. */ -+{ "sath", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* sath<.f> 0,c 0010111000101111F111CCCCCC000010. */ -+{ "sath", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sath<.f> b,u6 00101bbb01101111FBBBuuuuuu000010. */ -+{ "sath", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sath<.f> 0,u6 0010111001101111F111uuuuuu000010. */ -+{ "sath", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sath<.f> b,limm 00101bbb00101111FBBB111110000010. */ -+{ "sath", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* sath<.f> 0,limm 0010111000101111F111111110000010. */ -+{ "sath", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sbc<.f> a,b,c 00100bbb00000011FBBBCCCCCCAAAAAA. */ -+{ "sbc", 0x20030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbc<.f> 0,b,c 00100bbb00000011FBBBCCCCCC111110. */ -+{ "sbc", 0x2003003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbc<.f><.cc> b,b,c 00100bbb11000011FBBBCCCCCC0QQQQQ. */ -+{ "sbc", 0x20C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbc<.f> a,b,u6 00100bbb01000011FBBBuuuuuuAAAAAA. */ -+{ "sbc", 0x20430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbc<.f> 0,b,u6 00100bbb01000011FBBBuuuuuu111110. */ -+{ "sbc", 0x2043003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbc<.f><.cc> b,b,u6 00100bbb11000011FBBBuuuuuu1QQQQQ. */ -+{ "sbc", 0x20C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbc<.f> b,b,s12 00100bbb10000011FBBBssssssSSSSSS. */ -+{ "sbc", 0x20830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbc<.f> a,limm,c 0010011000000011F111CCCCCCAAAAAA. */ -+{ "sbc", 0x26037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbc<.f> a,b,limm 00100bbb00000011FBBB111110AAAAAA. */ -+{ "sbc", 0x20030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbc<.f> 0,limm,c 0010011000000011F111CCCCCC111110. */ -+{ "sbc", 0x2603703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbc<.f> 0,b,limm 00100bbb00000011FBBB111110111110. */ -+{ "sbc", 0x20030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbc<.f><.cc> b,b,limm 00100bbb11000011FBBB1111100QQQQQ. */ -+{ "sbc", 0x20C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sbc<.f><.cc> 0,limm,c 0010011011000011F111CCCCCC0QQQQQ. */ -+{ "sbc", 0x26C37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbc<.f> a,limm,u6 0010011001000011F111uuuuuuAAAAAA. */ -+{ "sbc", 0x26437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbc<.f> 0,limm,u6 0010011001000011F111uuuuuu111110. */ -+{ "sbc", 0x2643703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbc<.f><.cc> 0,limm,u6 0010011011000011F111uuuuuu1QQQQQ. */ -+{ "sbc", 0x26C37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbc<.f> 0,limm,s12 0010011010000011F111ssssssSSSSSS. */ -+{ "sbc", 0x26837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbc<.f> a,limm,limm 0010011000000011F111111110AAAAAA. */ -+{ "sbc", 0x26037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sbc<.f> 0,limm,limm 0010011000000011F111111110111110. */ -+{ "sbc", 0x26037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sbc<.f><.cc> 0,limm,limm 0010011011000011F1111111100QQQQQ. */ -+{ "sbc", 0x26C37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sbcs<.f><.cc> b,b,c 00101bbb11100111FBBBCCCCCC0QQQQQ */ -+{ "sbcs", 0x28E70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbcs<.f> 0,b,c 00101bbb00100111FBBBCCCCCC111110 */ -+{ "sbcs", 0x2827003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbcs<.f> a,b,c 00101bbb00100111FBBBCCCCCCAAAAAA */ -+{ "sbcs", 0x28270000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sbcs<.f><.cc> b,b,u6 00101bbb11100111FBBBuuuuuu1QQQQQ */ -+{ "sbcs", 0x28E70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbcs<.f> a,b,u6 00101bbb01100111FBBBuuuuuuAAAAAA */ -+{ "sbcs", 0x28670000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcs<.f> 0,b,u6 00101bbb01100111FBBBuuuuuu111110 */ -+{ "sbcs", 0x2867003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcs<.f> b,b,s12 00101bbb10100111FBBBssssssSSSSSS */ -+{ "sbcs", 0x28A70000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbcs<.f><.cc> 0,limm,c 0010111011100111F111CCCCCC0QQQQQ */ -+{ "sbcs", 0x2EE77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sbcs<.f> a,b,limm 00101bbb00100111FBBB111110AAAAAA */ -+{ "sbcs", 0x28270F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbcs<.f> 0,b,limm 00101bbb00100111FBBB111110111110 */ -+{ "sbcs", 0x28270FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sbcs<.f><.cc> b,b,limm 00101bbb11100111FBBB1111100QQQQQ */ -+{ "sbcs", 0x28E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sbcs<.f> a,limm,c 0010111000100111F111CCCCCCAAAAAA */ -+{ "sbcs", 0x2E277000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbcs<.f> 0,limm,c 0010111001100111F111CCCCCC111110 */ -+{ "sbcs", 0x2E67703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sbcs<.f><.cc> 0,limm,u6 0010111011100111F111uuuuuu1QQQQQ */ -+{ "sbcs", 0x2EE77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sbcs<.f> 0,limm,u6 0010111001100111F111uuuuuu111110 */ -+{ "sbcs", 0x2E67703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcs<.f> a,limm,u6 0010111001100111F111uuuuuuAAAAAA */ -+{ "sbcs", 0x2E677000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sbcs<.f> 0,limm,s12 0010111010100111F111ssssssSSSSSS */ -+{ "sbcs", 0x2EA77000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sbcs<.f><.cc> 0,limm,limm 0010111011100111F1111111100QQQQQ */ -+{ "sbcs", 0x2EE77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sbcs<.f> a,limm,limm 0010111000100111F111111110AAAAAA */ -+{ "sbcs", 0x2E277F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sbcs<.f> 0,limm,limm 0010111000100111F111111110111110 */ -+{ "sbcs", 0x2E277FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001. */ -+{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001. */ -+{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scond<.di> b,limm 00100bbb00101111DBBB111110010001. */ -+{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scond<.di> limm,c 0010011000101111D111CCCCCC010001. */ -+{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scond<.di> limm,u6 0010011001101111D111uuuuuu010001. */ -+{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scond<.di> limm,limm 0010011000101111D111111110010001. */ -+{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011. */ -+{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011. */ -+{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* scondd<.di> b,limm 00100bbb00101111DBBB111110010011. */ -+{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, -+ -+/* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA. */ -+{ "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* setacc 0,b,c 00101bbb000011011BBBCCCCCC111110. */ -+{ "setacc", 0x280D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* setacc<.cc> b,b,c 00101bbb110011011BBBCCCCCC0QQQQQ. */ -+{ "setacc", 0x28CD8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* setacc a,b,u6 00101bbb010011011BBBuuuuuuAAAAAA. */ -+{ "setacc", 0x284D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* setacc 0,b,u6 00101bbb010011011BBBuuuuuu111110. */ -+{ "setacc", 0x284D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* setacc<.cc> b,b,u6 00101bbb110011011BBBuuuuuu1QQQQQ. */ -+{ "setacc", 0x28CD8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* setacc b,b,s12 00101bbb100011011BBBssssssSSSSSS. */ -+{ "setacc", 0x288D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* setacc a,limm,c 00101110000011011111CCCCCCAAAAAA. */ -+{ "setacc", 0x2E0DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* setacc a,b,limm 00101bbb000011011BBB111110AAAAAA. */ -+{ "setacc", 0x280D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* setacc 0,limm,c 00101110000011011111CCCCCC111110. */ -+{ "setacc", 0x2E0DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* setacc 0,b,limm 00101bbb000011011BBB111110111110. */ -+{ "setacc", 0x280D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* setacc<.cc> b,b,limm 00101bbb110011011BBB1111100QQQQQ. */ -+{ "setacc", 0x28CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* setacc<.cc> 0,limm,c 00101110110011011111CCCCCC0QQQQQ. */ -+{ "setacc", 0x2ECDF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* setacc a,limm,u6 00101110010011011111uuuuuuAAAAAA. */ -+{ "setacc", 0x2E4DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* setacc 0,limm,u6 00101110010011011111uuuuuu111110. */ -+{ "setacc", 0x2E4DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* setacc<.cc> 0,limm,u6 00101110110011011111uuuuuu1QQQQQ. */ -+{ "setacc", 0x2ECDF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* setacc 0,limm,s12 00101110100011011111ssssssSSSSSS. */ -+{ "setacc", 0x2E8DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* setacc a,limm,limm 00101110000011011111111110AAAAAA. */ -+{ "setacc", 0x2E0DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* setacc 0,limm,limm 00101110000011011111111110111110. */ -+{ "setacc", 0x2E0DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* setacc<.cc> 0,limm,limm 001011101100110111111111100QQQQQ. */ -+{ "setacc", 0x2ECDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* seteq<.f> a,b,c 00100bbb00111000FBBBCCCCCCAAAAAA. */ -+{ "seteq", 0x20380000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seteq<.f> 0,b,c 00100bbb00111000FBBBCCCCCC111110. */ -+{ "seteq", 0x2038003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seteq<.f><.cc> b,b,c 00100bbb11111000FBBBCCCCCC0QQQQQ. */ -+{ "seteq", 0x20F80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seteq<.f> a,b,u6 00100bbb01111000FBBBuuuuuuAAAAAA. */ -+{ "seteq", 0x20780000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteq<.f> 0,b,u6 00100bbb01111000FBBBuuuuuu111110. */ -+{ "seteq", 0x2078003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteq<.f><.cc> b,b,u6 00100bbb11111000FBBBuuuuuu1QQQQQ. */ -+{ "seteq", 0x20F80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seteq<.f> b,b,s12 00100bbb10111000FBBBssssssSSSSSS. */ -+{ "seteq", 0x20B80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seteq<.f> a,limm,c 0010011000111000F111CCCCCCAAAAAA. */ -+{ "seteq", 0x26387000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seteq<.f> a,b,limm 00100bbb00111000FBBB111110AAAAAA. */ -+{ "seteq", 0x20380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seteq<.f> 0,limm,c 0010011000111000F111CCCCCC111110. */ -+{ "seteq", 0x2638703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seteq<.f> 0,b,limm 00100bbb00111000FBBB111110111110. */ -+{ "seteq", 0x20380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seteq<.f><.cc> b,b,limm 00100bbb11111000FBBB1111100QQQQQ. */ -+{ "seteq", 0x20F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* seteq<.f><.cc> 0,limm,c 0010011011111000F111CCCCCC0QQQQQ. */ -+{ "seteq", 0x26F87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seteq<.f> a,limm,u6 0010011001111000F111uuuuuuAAAAAA. */ -+{ "seteq", 0x26787000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteq<.f> 0,limm,u6 0010011001111000F111uuuuuu111110. */ -+{ "seteq", 0x2678703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seteq<.f><.cc> 0,limm,u6 0010011011111000F111uuuuuu1QQQQQ. */ -+{ "seteq", 0x26F87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seteq<.f> 0,limm,s12 0010011010111000F111ssssssSSSSSS. */ -+{ "seteq", 0x26B87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seteq<.f> a,limm,limm 0010011000111000F111111110AAAAAA. */ -+{ "seteq", 0x26387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seteq<.f> 0,limm,limm 0010011000111000F111111110111110. */ -+{ "seteq", 0x26387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seteq<.f><.cc> 0,limm,limm 0010011011111000F1111111100QQQQQ. */ -+{ "seteq", 0x26F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setge<.f> a,b,c 00100bbb00111011FBBBCCCCCCAAAAAA. */ -+{ "setge", 0x203B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setge<.f> 0,b,c 00100bbb00111011FBBBCCCCCC111110. */ -+{ "setge", 0x203B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setge<.f><.cc> b,b,c 00100bbb11111011FBBBCCCCCC0QQQQQ. */ -+{ "setge", 0x20FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setge<.f> a,b,u6 00100bbb01111011FBBBuuuuuuAAAAAA. */ -+{ "setge", 0x207B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setge<.f> 0,b,u6 00100bbb01111011FBBBuuuuuu111110. */ -+{ "setge", 0x207B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setge<.f><.cc> b,b,u6 00100bbb11111011FBBBuuuuuu1QQQQQ. */ -+{ "setge", 0x20FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setge<.f> b,b,s12 00100bbb10111011FBBBssssssSSSSSS. */ -+{ "setge", 0x20BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setge<.f> a,limm,c 0010011000111011F111CCCCCCAAAAAA. */ -+{ "setge", 0x263B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setge<.f> a,b,limm 00100bbb00111011FBBB111110AAAAAA. */ -+{ "setge", 0x203B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setge<.f> 0,limm,c 0010011000111011F111CCCCCC111110. */ -+{ "setge", 0x263B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setge<.f> 0,b,limm 00100bbb00111011FBBB111110111110. */ -+{ "setge", 0x203B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setge<.f><.cc> b,b,limm 00100bbb11111011FBBB1111100QQQQQ. */ -+{ "setge", 0x20FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setge<.f><.cc> 0,limm,c 0010011011111011F111CCCCCC0QQQQQ. */ -+{ "setge", 0x26FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setge<.f> a,limm,u6 0010011001111011F111uuuuuuAAAAAA. */ -+{ "setge", 0x267B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setge<.f> 0,limm,u6 0010011001111011F111uuuuuu111110. */ -+{ "setge", 0x267B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setge<.f><.cc> 0,limm,u6 0010011011111011F111uuuuuu1QQQQQ. */ -+{ "setge", 0x26FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setge<.f> 0,limm,s12 0010011010111011F111ssssssSSSSSS. */ -+{ "setge", 0x26BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setge<.f> a,limm,limm 0010011000111011F111111110AAAAAA. */ -+{ "setge", 0x263B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setge<.f> 0,limm,limm 0010011000111011F111111110111110. */ -+{ "setge", 0x263B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setge<.f><.cc> 0,limm,limm 0010011011111011F1111111100QQQQQ. */ -+{ "setge", 0x26FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setgt<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA. */ -+{ "setgt", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setgt<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110. */ -+{ "setgt", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setgt<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ. */ -+{ "setgt", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgt<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA. */ -+{ "setgt", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgt<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110. */ -+{ "setgt", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgt<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ. */ -+{ "setgt", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgt<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS. */ -+{ "setgt", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgt<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA. */ -+{ "setgt", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgt<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA. */ -+{ "setgt", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setgt<.f> 0,limm,c 0010011000111111F111CCCCCC111110. */ -+{ "setgt", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setgt<.f> 0,b,limm 00100bbb00111111FBBB111110111110. */ -+{ "setgt", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setgt<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ. */ -+{ "setgt", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setgt<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ. */ -+{ "setgt", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setgt<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA. */ -+{ "setgt", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgt<.f> 0,limm,u6 0010011001111111F111uuuuuu111110. */ -+{ "setgt", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setgt<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ. */ -+{ "setgt", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setgt<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS. */ -+{ "setgt", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setgt<.f> a,limm,limm 0010011000111111F111111110AAAAAA. */ -+{ "setgt", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setgt<.f> 0,limm,limm 0010011000111111F111111110111110. */ -+{ "setgt", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setgt<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ. */ -+{ "setgt", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* seths<.f> a,b,c 00100bbb00111101FBBBCCCCCCAAAAAA. */ -+{ "seths", 0x203D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seths<.f> 0,b,c 00100bbb00111101FBBBCCCCCC111110. */ -+{ "seths", 0x203D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* seths<.f><.cc> b,b,c 00100bbb11111101FBBBCCCCCC0QQQQQ. */ -+{ "seths", 0x20FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seths<.f> a,b,u6 00100bbb01111101FBBBuuuuuuAAAAAA. */ -+{ "seths", 0x207D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seths<.f> 0,b,u6 00100bbb01111101FBBBuuuuuu111110. */ -+{ "seths", 0x207D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seths<.f><.cc> b,b,u6 00100bbb11111101FBBBuuuuuu1QQQQQ. */ -+{ "seths", 0x20FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seths<.f> b,b,s12 00100bbb10111101FBBBssssssSSSSSS. */ -+{ "seths", 0x20BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seths<.f> a,limm,c 0010011000111101F111CCCCCCAAAAAA. */ -+{ "seths", 0x263D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seths<.f> a,b,limm 00100bbb00111101FBBB111110AAAAAA. */ -+{ "seths", 0x203D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seths<.f> 0,limm,c 0010011000111101F111CCCCCC111110. */ -+{ "seths", 0x263D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* seths<.f> 0,b,limm 00100bbb00111101FBBB111110111110. */ -+{ "seths", 0x203D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* seths<.f><.cc> b,b,limm 00100bbb11111101FBBB1111100QQQQQ. */ -+{ "seths", 0x20FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* seths<.f><.cc> 0,limm,c 0010011011111101F111CCCCCC0QQQQQ. */ -+{ "seths", 0x26FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* seths<.f> a,limm,u6 0010011001111101F111uuuuuuAAAAAA. */ -+{ "seths", 0x267D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seths<.f> 0,limm,u6 0010011001111101F111uuuuuu111110. */ -+{ "seths", 0x267D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* seths<.f><.cc> 0,limm,u6 0010011011111101F111uuuuuu1QQQQQ. */ -+{ "seths", 0x26FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* seths<.f> 0,limm,s12 0010011010111101F111ssssssSSSSSS. */ -+{ "seths", 0x26BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* seths<.f> a,limm,limm 0010011000111101F111111110AAAAAA. */ -+{ "seths", 0x263D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seths<.f> 0,limm,limm 0010011000111101F111111110111110. */ -+{ "seths", 0x263D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* seths<.f><.cc> 0,limm,limm 0010011011111101F1111111100QQQQQ. */ -+{ "seths", 0x26FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* seti c 00100110001011110000CCCCCC111111. */ -+{ "seti", 0x262F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* seti u6 00100110011011110000uuuuuu111111. */ -+{ "seti", 0x266F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* seti limm 00100110001011110000111110111111. */ -+{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* seti 00100110011011110000uuuuuu111111. */ -+{ "seti", 0x266F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */ -+{ "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setle<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110. */ -+{ "setle", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setle<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ. */ -+{ "setle", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setle<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA. */ -+{ "setle", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setle<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110. */ -+{ "setle", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setle<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ. */ -+{ "setle", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setle<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS. */ -+{ "setle", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setle<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA. */ -+{ "setle", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setle<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA. */ -+{ "setle", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setle<.f> 0,limm,c 0010011000111110F111CCCCCC111110. */ -+{ "setle", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setle<.f> 0,b,limm 00100bbb00111110FBBB111110111110. */ -+{ "setle", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setle<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ. */ -+{ "setle", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setle<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ. */ -+{ "setle", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setle<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA. */ -+{ "setle", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setle<.f> 0,limm,u6 0010011001111110F111uuuuuu111110. */ -+{ "setle", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setle<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ. */ -+{ "setle", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setle<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS. */ -+{ "setle", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setle<.f> a,limm,limm 0010011000111110F111111110AAAAAA. */ -+{ "setle", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setle<.f> 0,limm,limm 0010011000111110F111111110111110. */ -+{ "setle", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setle<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ. */ -+{ "setle", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setlo<.f> a,b,c 00100bbb00111100FBBBCCCCCCAAAAAA. */ -+{ "setlo", 0x203C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlo<.f> 0,b,c 00100bbb00111100FBBBCCCCCC111110. */ -+{ "setlo", 0x203C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlo<.f><.cc> b,b,c 00100bbb11111100FBBBCCCCCC0QQQQQ. */ -+{ "setlo", 0x20FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlo<.f> a,b,u6 00100bbb01111100FBBBuuuuuuAAAAAA. */ -+{ "setlo", 0x207C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlo<.f> 0,b,u6 00100bbb01111100FBBBuuuuuu111110. */ -+{ "setlo", 0x207C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlo<.f><.cc> b,b,u6 00100bbb11111100FBBBuuuuuu1QQQQQ. */ -+{ "setlo", 0x20FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlo<.f> b,b,s12 00100bbb10111100FBBBssssssSSSSSS. */ -+{ "setlo", 0x20BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlo<.f> a,limm,c 0010011000111100F111CCCCCCAAAAAA. */ -+{ "setlo", 0x263C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlo<.f> a,b,limm 00100bbb00111100FBBB111110AAAAAA. */ -+{ "setlo", 0x203C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlo<.f> 0,limm,c 0010011000111100F111CCCCCC111110. */ -+{ "setlo", 0x263C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlo<.f> 0,b,limm 00100bbb00111100FBBB111110111110. */ -+{ "setlo", 0x203C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlo<.f><.cc> b,b,limm 00100bbb11111100FBBB1111100QQQQQ. */ -+{ "setlo", 0x20FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setlo<.f><.cc> 0,limm,c 0010011011111100F111CCCCCC0QQQQQ. */ -+{ "setlo", 0x26FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlo<.f> a,limm,u6 0010011001111100F111uuuuuuAAAAAA. */ -+{ "setlo", 0x267C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlo<.f> 0,limm,u6 0010011001111100F111uuuuuu111110. */ -+{ "setlo", 0x267C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlo<.f><.cc> 0,limm,u6 0010011011111100F111uuuuuu1QQQQQ. */ -+{ "setlo", 0x26FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlo<.f> 0,limm,s12 0010011010111100F111ssssssSSSSSS. */ -+{ "setlo", 0x26BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlo<.f> a,limm,limm 0010011000111100F111111110AAAAAA. */ -+{ "setlo", 0x263C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlo<.f> 0,limm,limm 0010011000111100F111111110111110. */ -+{ "setlo", 0x263C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlo<.f><.cc> 0,limm,limm 0010011011111100F1111111100QQQQQ. */ -+{ "setlo", 0x26FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setlt<.f> a,b,c 00100bbb00111010FBBBCCCCCCAAAAAA. */ -+{ "setlt", 0x203A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlt<.f> 0,b,c 00100bbb00111010FBBBCCCCCC111110. */ -+{ "setlt", 0x203A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setlt<.f><.cc> b,b,c 00100bbb11111010FBBBCCCCCC0QQQQQ. */ -+{ "setlt", 0x20FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlt<.f> a,b,u6 00100bbb01111010FBBBuuuuuuAAAAAA. */ -+{ "setlt", 0x207A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlt<.f> 0,b,u6 00100bbb01111010FBBBuuuuuu111110. */ -+{ "setlt", 0x207A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlt<.f><.cc> b,b,u6 00100bbb11111010FBBBuuuuuu1QQQQQ. */ -+{ "setlt", 0x20FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlt<.f> b,b,s12 00100bbb10111010FBBBssssssSSSSSS. */ -+{ "setlt", 0x20BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlt<.f> a,limm,c 0010011000111010F111CCCCCCAAAAAA. */ -+{ "setlt", 0x263A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlt<.f> a,b,limm 00100bbb00111010FBBB111110AAAAAA. */ -+{ "setlt", 0x203A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlt<.f> 0,limm,c 0010011000111010F111CCCCCC111110. */ -+{ "setlt", 0x263A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setlt<.f> 0,b,limm 00100bbb00111010FBBB111110111110. */ -+{ "setlt", 0x203A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setlt<.f><.cc> b,b,limm 00100bbb11111010FBBB1111100QQQQQ. */ -+{ "setlt", 0x20FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setlt<.f><.cc> 0,limm,c 0010011011111010F111CCCCCC0QQQQQ. */ -+{ "setlt", 0x26FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setlt<.f> a,limm,u6 0010011001111010F111uuuuuuAAAAAA. */ -+{ "setlt", 0x267A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlt<.f> 0,limm,u6 0010011001111010F111uuuuuu111110. */ -+{ "setlt", 0x267A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setlt<.f><.cc> 0,limm,u6 0010011011111010F111uuuuuu1QQQQQ. */ -+{ "setlt", 0x26FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setlt<.f> 0,limm,s12 0010011010111010F111ssssssSSSSSS. */ -+{ "setlt", 0x26BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setlt<.f> a,limm,limm 0010011000111010F111111110AAAAAA. */ -+{ "setlt", 0x263A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlt<.f> 0,limm,limm 0010011000111010F111111110111110. */ -+{ "setlt", 0x263A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setlt<.f><.cc> 0,limm,limm 0010011011111010F1111111100QQQQQ. */ -+{ "setlt", 0x26FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setne<.f> a,b,c 00100bbb00111001FBBBCCCCCCAAAAAA. */ -+{ "setne", 0x20390000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setne<.f> 0,b,c 00100bbb00111001FBBBCCCCCC111110. */ -+{ "setne", 0x2039003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setne<.f><.cc> b,b,c 00100bbb11111001FBBBCCCCCC0QQQQQ. */ -+{ "setne", 0x20F90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setne<.f> a,b,u6 00100bbb01111001FBBBuuuuuuAAAAAA. */ -+{ "setne", 0x20790000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setne<.f> 0,b,u6 00100bbb01111001FBBBuuuuuu111110. */ -+{ "setne", 0x2079003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setne<.f><.cc> b,b,u6 00100bbb11111001FBBBuuuuuu1QQQQQ. */ -+{ "setne", 0x20F90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setne<.f> b,b,s12 00100bbb10111001FBBBssssssSSSSSS. */ -+{ "setne", 0x20B90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setne<.f> a,limm,c 0010011000111001F111CCCCCCAAAAAA. */ -+{ "setne", 0x26397000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setne<.f> a,b,limm 00100bbb00111001FBBB111110AAAAAA. */ -+{ "setne", 0x20390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setne<.f> 0,limm,c 0010011000111001F111CCCCCC111110. */ -+{ "setne", 0x2639703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setne<.f> 0,b,limm 00100bbb00111001FBBB111110111110. */ -+{ "setne", 0x20390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setne<.f><.cc> b,b,limm 00100bbb11111001FBBB1111100QQQQQ. */ -+{ "setne", 0x20F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setne<.f><.cc> 0,limm,c 0010011011111001F111CCCCCC0QQQQQ. */ -+{ "setne", 0x26F97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setne<.f> a,limm,u6 0010011001111001F111uuuuuuAAAAAA. */ -+{ "setne", 0x26797000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setne<.f> 0,limm,u6 0010011001111001F111uuuuuu111110. */ -+{ "setne", 0x2679703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setne<.f><.cc> 0,limm,u6 0010011011111001F111uuuuuu1QQQQQ. */ -+{ "setne", 0x26F97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setne<.f> 0,limm,s12 0010011010111001F111ssssssSSSSSS. */ -+{ "setne", 0x26B97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setne<.f> a,limm,limm 0010011000111001F111111110AAAAAA. */ -+{ "setne", 0x26397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setne<.f> 0,limm,limm 0010011000111001F111111110111110. */ -+{ "setne", 0x26397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setne<.f><.cc> 0,limm,limm 0010011011111001F1111111100QQQQQ. */ -+{ "setne", 0x26F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* setcc<.f> a,b,c 00100bbb00iiiiiiFBBBCCCCCCAAAAAA. */ -+{ "setcc", 0x20000000, 0xF8C00000, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setcc<.f> 0,b,c 00100bbb00iiiiiiFBBBCCCCCC111110. */ -+{ "setcc", 0x2000003E, 0xF8C0003F, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* setcc<.f><.cc> b,b,c 00100bbb11iiiiiiFBBBCCCCCC0QQQQQ. */ -+{ "setcc", 0x20C00000, 0xF8C00020, 0, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setcc<.f> a,b,u6 00100bbb01iiiiiiFBBBuuuuuuAAAAAA. */ -+{ "setcc", 0x20400000, 0xF8C00000, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setcc<.f> 0,b,u6 00100bbb01iiiiiiFBBBuuuuuu111110. */ -+{ "setcc", 0x2040003E, 0xF8C0003F, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setcc<.f><.cc> b,b,u6 00100bbb11iiiiiiFBBBuuuuuu1QQQQQ. */ -+{ "setcc", 0x20C00020, 0xF8C00020, 0, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setcc<.f> b,b,s12 00100bbb10iiiiiiFBBBssssssSSSSSS. */ -+{ "setcc", 0x20800000, 0xF8C00000, 0, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setcc<.f> a,limm,c 0010011000iiiiiiF111CCCCCCAAAAAA. */ -+{ "setcc", 0x26007000, 0xFFC07000, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setcc<.f> a,b,limm 00100bbb00iiiiiiFBBB111110AAAAAA. */ -+{ "setcc", 0x20000F80, 0xF8C00FC0, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setcc<.f> 0,limm,c 0010011000iiiiiiF111CCCCCC111110. */ -+{ "setcc", 0x2600703E, 0xFFC0703F, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* setcc<.f> 0,b,limm 00100bbb00iiiiiiFBBB111110111110. */ -+{ "setcc", 0x20000FBE, 0xF8C00FFF, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* setcc<.f><.cc> b,b,limm 00100bbb11iiiiiiFBBB1111100QQQQQ. */ -+{ "setcc", 0x20C00F80, 0xF8C00FE0, 0, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* setcc<.f><.cc> 0,limm,c 0010011011iiiiiiF111CCCCCC0QQQQQ. */ -+{ "setcc", 0x26C07000, 0xFFC07020, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* setcc<.f> a,limm,u6 0010011001iiiiiiF111uuuuuuAAAAAA. */ -+{ "setcc", 0x26407000, 0xFFC07000, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setcc<.f> 0,limm,u6 0010011001iiiiiiF111uuuuuu111110. */ -+{ "setcc", 0x2640703E, 0xFFC0703F, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* setcc<.f><.cc> 0,limm,u6 0010011011iiiiiiF111uuuuuu1QQQQQ. */ -+{ "setcc", 0x26C07020, 0xFFC07020, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* setcc<.f> 0,limm,s12 0010011010iiiiiiF111ssssssSSSSSS. */ -+{ "setcc", 0x26807000, 0xFFC07000, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* setcc<.f> a,limm,limm 0010011000iiiiiiF111111110AAAAAA. */ -+{ "setcc", 0x26007F80, 0xFFC07FC0, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setcc<.f> 0,limm,limm 0010011000iiiiiiF111111110111110. */ -+{ "setcc", 0x26007FBE, 0xFFC07FFF, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* setcc<.f><.cc> 0,limm,limm 0010011011iiiiiiF1111111100QQQQQ. */ -+{ "setcc", 0x26C07F80, 0xFFC07FE0, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sexb<.f> b,c 00100bbb00101111FBBBCCCCCC000101. */ -+{ "sexb", 0x202F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sexb<.f> 0,c 0010011000101111F111CCCCCC000101. */ -+{ "sexb", 0x262F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sexb<.f> b,u6 00100bbb01101111FBBBuuuuuu000101. */ -+{ "sexb", 0x206F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexb<.f> 0,u6 0010011001101111F111uuuuuu000101. */ -+{ "sexb", 0x266F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexb<.f> b,limm 00100bbb00101111FBBB111110000101. */ -+{ "sexb", 0x202F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sexb<.f> 0,limm 0010011000101111F111111110000101. */ -+{ "sexb", 0x262F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sexb_s b,c 01111bbbccc01101. */ -+{ "sexb_s", 0x0000780D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* sexh<.f> b,c 00100bbb00101111FBBBCCCCCC000110. */ -+{ "sexh", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sexh<.f> 0,c 0010011000101111F111CCCCCC000110. */ -+{ "sexh", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sexh<.f> b,u6 00100bbb01101111FBBBuuuuuu000110. */ -+{ "sexh", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexh<.f> 0,u6 0010011001101111F111uuuuuu000110. */ -+{ "sexh", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexh<.f> b,limm 00100bbb00101111FBBB111110000110. */ -+{ "sexh", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sexh<.f> 0,limm 0010011000101111F111111110000110. */ -+{ "sexh", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sexh_s b,c 01111bbbccc01110. */ -+{ "sexh_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* sexw<.f> b,c 00100bbb00101111FBBBCCCCCC000110. */ -+{ "sexw", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sexw<.f> 0,c 0010011000101111F111CCCCCC000110. */ -+{ "sexw", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sexw<.f> b,u6 00100bbb01101111FBBBuuuuuu000110. */ -+{ "sexw", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexw<.f> 0,u6 0010011001101111F111uuuuuu000110. */ -+{ "sexw", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sexw<.f> b,limm 00100bbb00101111FBBB111110000110. */ -+{ "sexw", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sexw<.f> 0,limm 0010011000101111F111111110000110. */ -+{ "sexw", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sexw_s b,c 01111bbbccc01110. */ -+{ "sexw_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* sflag c 00110000001011110000CCCCCC111111 */ -+{ "sflag", 0x302F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, CONTROL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* sflag u6 00110000011011110000uuuuuu111111 */ -+{ "sflag", 0x306F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* sflag limm 00110000001011110000111110111111 */ -+{ "sflag", 0x302F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* sfxtr<.f> a,b,c 00110bbb00101001FBBBCCCCCCAAAAAA. */ -+{ "sfxtr", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sfxtr<.f><.cc> b,b,c 00110bbb11101001FBBBCCCCCC0QQQQQ. */ -+{ "sfxtr", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sfxtr<.f> a,b,u6 00110bbb01101001FBBBuuuuuuAAAAAA. */ -+{ "sfxtr", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sfxtr<.f><.cc> b,b,u6 00110bbb11101001FBBBuuuuuu1QQQQQ. */ -+{ "sfxtr", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sfxtr<.f> b,b,s12 00110bbb10101001FBBBssssssSSSSSS. */ -+{ "sfxtr", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sfxtr<.f> a,limm,c 0011011000101001F111CCCCCCAAAAAA. */ -+{ "sfxtr", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sfxtr<.f> a,b,limm 00110bbb00101001FBBB111110AAAAAA. */ -+{ "sfxtr", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sfxtr<.f><.cc> b,b,limm 00110bbb11101001FBBB1111100QQQQQ. */ -+{ "sfxtr", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sjli u12 00101RRR101000001RRRuuuuuuUUUUUU. */ -+{ "sjli", 0x28A08000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, SJLI, CD1, { OPERAND_UIMM12_20 }, { 0 }}, -+ -+/* sleep c 00100001001011110000CCCCCC111111. */ -+{ "sleep", 0x212F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* sleep u6 00100001011011110000uuuuuu111111. */ -+{ "sleep", 0x216F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* sleep limm 00100001001011110000111110111111. */ -+{ "sleep", 0x212F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_LIMM }, { 0 }}, -+ -+/* sleep 00100001011011110000uuuuuu111111. */ -+{ "sleep", 0x216F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* sqrt<.f> b,c 00101bbb00101111FBBBCCCCCC110000 */ -+{ "sqrt", 0x282F0030, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sqrt<.f> b,u6 00101bbb01101111FBBBuuuuuu110000 */ -+{ "sqrt", 0x286F0030, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sqrt<.f> 0,u6 0010111001101111F111uuuuuu110000 */ -+{ "sqrt", 0x2E6F7030, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sqrt<.f> 0,limm 0010111000101111F111111110110000 */ -+{ "sqrt", 0x2E2F7FB0, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sqrt<.f> b,limm 00101bbb00101111FBBB111110110000 */ -+{ "sqrt", 0x282F0FB0, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sqrtacc c 00101010001011110000CCCCCC111111. */ -+{ "sqrtacc", 0x2A2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* sqrtacc u6 00101010011011110000uuuuuu111111. */ -+{ "sqrtacc", 0x2A6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* sqrtf<.f> 0,c 0010111000101111F111CCCCCC110001 */ -+{ "sqrtf", 0x2E2F7031, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* sqrtf<.f> b,c 00101bbb00101111FBBBCCCCCC110001 */ -+{ "sqrtf", 0x282F0031, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sqrtf<.f> b,u6 00101bbb01101111FBBBuuuuuu110001 */ -+{ "sqrtf", 0x286F0031, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sqrtf<.f> 0,u6 0010111001101111F111uuuuuu110001 */ -+{ "sqrtf", 0x2E6F7031, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sqrtf<.f> b,limm 00101bbb00101111FBBB111110110001 */ -+{ "sqrtf", 0x282F0FB1, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sqrtf<.f> 0,limm 0010111000101111F111111110110001 */ -+{ "sqrtf", 0x2E2F7FB1, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* sr b,c 00100bbb001010110BBBCCCCCCRRRRRR. */ -+{ "sr", 0x202B0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,c 00100bbb00101011RBBBCCCCCCRRRRRR. */ -+{ "sr", 0x202B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,u6 00100bbb011010110BBBuuuuuu000000. */ -+{ "sr", 0x206B0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,u6 00100bbb01101011RBBBuuuuuu000000. */ -+{ "sr", 0x206B0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,s12 00100bbb101010110BBBssssssSSSSSS. */ -+{ "sr", 0x20AB0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,s12 00100bbb10101011RBBBssssssSSSSSS. */ -+{ "sr", 0x20AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,c 00100110001010110111CCCCCCRRRRRR. */ -+{ "sr", 0x262B7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,limm 00100bbb001010110BBB111110RRRRRR. */ -+{ "sr", 0x202B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,c 0010011000101011R111CCCCCCRRRRRR. */ -+{ "sr", 0x262B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr b,limm 00100bbb00101011RBBB111110RRRRRR. */ -+{ "sr", 0x202B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,u6 00100110011010110111uuuuuu000000. */ -+{ "sr", 0x266B7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,u6 0010011001101011R111uuuuuu000000. */ -+{ "sr", 0x266B7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,s12 00100110101010110111ssssssSSSSSS. */ -+{ "sr", 0x26AB7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,s12 0010011010101011R111ssssssSSSSSS. */ -+{ "sr", 0x26AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,limm 00100110001010110111111110RRRRRR. */ -+{ "sr", 0x262B7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sr limm,limm 0010011000101011R111111110RRRRRR. */ -+{ "sr", 0x262B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* st<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaaZZR. */ -+{ "st", 0x18000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaaZZ0. */ -+{ "st", 0x18000000, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaaZZ1. */ -+{ "st", 0x18000001, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZR. */ -+{ "st", 0x18000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZ0. */ -+{ "st", 0x18000000, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaaZZ1. */ -+{ "st", 0x18000001, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di> c,limm 00011110000000000111CCCCCCDRRZZR. */ -+{ "st", 0x1E007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }}, -+ -+/* st<.di> c,limm 00011110000000000111CCCCCCDRRZZ0. */ -+{ "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }}, -+ -+/* st<.di> w6,limm 00011110000000000111wwwwwwDRRZZ1. */ -+{ "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }}, -+ -+/* st<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110DaaZZR. */ -+{ "st", 0x18000F80, 0xF8000FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110DaaZZ0. */ -+{ "st", 0x18000F80, 0xF8000FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaaZZ1. */ -+{ "st", 0x1E007001, 0xFF007001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> limm,limm,s9 00011110ssssssssS111111110DaaZZR. */ -+{ "st", 0x1E007F80, 0xFF007FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* st<.di><.aa> limm,limm,s9 00011110ssssssssS111111110DaaZZ0. */ -+{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, -+ -+/* stb_s c,b,u5 10101bbbcccuuuuu. */ -+{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* stb_s b,SP,u7 11000bbb011uuuuu. */ -+{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, -+ -+/* std<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaa110. */ -+{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, -+ -+/* std<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaa111. */ -+{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, -+ -+/* std<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaa110. */ -+{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, -+ -+/* std<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaa111. */ -+{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, -+ -+/* std<.di> c,limm 00011110000000000111CCCCCCDRR110. */ -+{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI26, C_ZZ_D }}, -+ -+/* std<.di> w6,limm 00011110000000000111wwwwwwDRR111. */ -+{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI26, C_ZZ_D }}, -+ -+/* std<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110Daa110. */ -+{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, -+ -+/* std<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaa111. */ -+{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, -+ -+/* std<.di><.aa> limm,limm,s9 00011110ssssssssS111111110Daa110. */ -+{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, -+ -+/* sth_s c,b,u6 10110bbbcccuuuuu. */ -+{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* stm a,u6,b 00101bbb01001101RBBBRuuuuuAAAAAA. */ -+{ "stm", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }}, -+ -+/* stm 0,u6,b 00101bbb01001101RBBBRuuuuu111110. */ -+{ "stm", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }}, -+ -+/* stm a,u6,limm 0010111001001101R111RuuuuuAAAAAA. */ -+{ "stm", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }}, -+ -+/* stm 0,u6,limm 0010111001001101R111Ruuuuu111110. */ -+{ "stm", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }}, -+ -+/* stw_s c,b,u6 10110bbbcccuuuuu. */ -+{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, -+ -+/* st_s b,SP,u7 11000bbb010uuuuu. */ -+{ "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* st_s c,b,u7 10100bbbcccuuuuu. */ -+{ "st_s", 0x0000A000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* st_s OPERAND_R0,GP,s11 01010SSSSSS10sss. */ -+{ "st_s", 0x00005010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, CD2, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_13_S, OPERAND_BRAKETdup }, { 0 }}, -+ -+/* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA. */ -+{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110. */ -+{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ. */ -+{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */ -+{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110. */ -+{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ. */ -+{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS. */ -+{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA. */ -+{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ -+{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110. */ -+{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110. */ -+{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ. */ -+{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ. */ -+{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA. */ -+{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110. */ -+{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ. */ -+{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS. */ -+{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA. */ -+{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub<.f> 0,limm,limm 0010011000000010F111111110111110. */ -+{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ. */ -+{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA. */ -+{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110. */ -+{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ. */ -+{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA. */ -+{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110. */ -+{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ. */ -+{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS. */ -+{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA. */ -+{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA. */ -+{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110. */ -+{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110. */ -+{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ. */ -+{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ. */ -+{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA. */ -+{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110. */ -+{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ. */ -+{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS. */ -+{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA. */ -+{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub1<.f> 0,limm,limm 0010011000010111F111111110111110. */ -+{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ. */ -+{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA. */ -+{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110. */ -+{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ. */ -+{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA. */ -+{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110. */ -+{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ. */ -+{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS. */ -+{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA. */ -+{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA. */ -+{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110. */ -+{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110. */ -+{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ. */ -+{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ. */ -+{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA. */ -+{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110. */ -+{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ. */ -+{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS. */ -+{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA. */ -+{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub2<.f> 0,limm,limm 0010011000011000F111111110111110. */ -+{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ. */ -+{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA. */ -+{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110. */ -+{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ. */ -+{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA. */ -+{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110. */ -+{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ. */ -+{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS. */ -+{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA. */ -+{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA. */ -+{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110. */ -+{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110. */ -+{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ. */ -+{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ. */ -+{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA. */ -+{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110. */ -+{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ. */ -+{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS. */ -+{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA. */ -+{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub3<.f> 0,limm,limm 0010011000011001F111111110111110. */ -+{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ. */ -+{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* subs<.f> a,b,c 00101bbb00000111FBBBCCCCCCAAAAAA. */ -+{ "subs", 0x28070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f> 0,b,c 00101bbb00000111FBBBCCCCCC111110. */ -+{ "subs", 0x2807003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f><.cc> b,b,c 00101bbb11000111FBBBCCCCCC0QQQQQ. */ -+{ "subs", 0x28C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* subs<.f> a,b,u6 00101bbb01000111FBBBuuuuuuAAAAAA. */ -+{ "subs", 0x28470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subs<.f> 0,b,u6 00101bbb01000111FBBBuuuuuu111110. */ -+{ "subs", 0x2847003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subs<.f><.cc> b,b,u6 00101bbb11000111FBBBuuuuuu1QQQQQ. */ -+{ "subs", 0x28C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* subs<.f> b,b,s12 00101bbb10000111FBBBssssssSSSSSS. */ -+{ "subs", 0x28870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */ -+{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f> a,b,limm 00101bbb00000111FBBB111110AAAAAA. */ -+{ "subs", 0x28070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* subs<.f> 0,limm,c 0010111000000111F111CCCCCC111110. */ -+{ "subs", 0x2E07703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f> 0,b,limm 00101bbb00000111FBBB111110111110. */ -+{ "subs", 0x28070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */ -+{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subs<.f><.cc> b,b,limm 00101bbb11000111FBBB1111100QQQQQ. */ -+{ "subs", 0x28C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* subs<.f><.cc> 0,limm,c 0010111011000111F111CCCCCC0QQQQQ. */ -+{ "subs", 0x2EC77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* subs<.f> a,limm,u6 0010111001000111F111uuuuuuAAAAAA. */ -+{ "subs", 0x2E477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subs<.f> 0,limm,u6 0010111001000111F111uuuuuu111110. */ -+{ "subs", 0x2E47703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subs<.f><.cc> 0,limm,u6 0010111011000111F111uuuuuu1QQQQQ. */ -+{ "subs", 0x2EC77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* subs<.f> 0,limm,s12 0010111010000111F111ssssssSSSSSS. */ -+{ "subs", 0x2E877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* subs<.f> a,limm,limm 0010111000000111F111111110AAAAAA. */ -+{ "subs", 0x2E077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* subs<.f> 0,limm,limm 0010111000000111F111111110111110. */ -+{ "subs", 0x2E077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* subs<.f><.cc> 0,limm,limm 0010111011000111F1111111100QQQQQ. */ -+{ "subs", 0x2EC77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* subsdw<.f> a,b,c 00101bbb00101001FBBBCCCCCCAAAAAA. */ -+{ "subsdw", 0x28290000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* subsdw<.f> 0,b,c 00101bbb00101001FBBBCCCCCC111110. */ -+{ "subsdw", 0x2829003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* subsdw<.f><.cc> b,b,c 00101bbb11101001FBBBCCCCCC0QQQQQ. */ -+{ "subsdw", 0x28E90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* subsdw<.f> a,b,u6 00101bbb01101001FBBBuuuuuuAAAAAA. */ -+{ "subsdw", 0x28690000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subsdw<.f> 0,b,u6 00101bbb01101001FBBBuuuuuu111110. */ -+{ "subsdw", 0x2869003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subsdw<.f><.cc> b,b,u6 00101bbb11101001FBBBuuuuuu1QQQQQ. */ -+{ "subsdw", 0x28E90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* subsdw<.f> b,b,s12 00101bbb10101001FBBBssssssSSSSSS. */ -+{ "subsdw", 0x28A90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* subsdw<.f> a,limm,c 0010111000101001F111CCCCCCAAAAAA. */ -+{ "subsdw", 0x2E297000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subsdw<.f> a,b,limm 00101bbb00101001FBBB111110AAAAAA. */ -+{ "subsdw", 0x28290F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* subsdw<.f> 0,limm,c 0010111000101001F111CCCCCC111110. */ -+{ "subsdw", 0x2E29703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* subsdw<.f> 0,b,limm 00101bbb00101001FBBB111110111110. */ -+{ "subsdw", 0x28290FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* subsdw<.f><.cc> b,b,limm 00101bbb11101001FBBB1111100QQQQQ. */ -+{ "subsdw", 0x28E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* subsdw<.f><.cc> 0,limm,c 0010111011101001F111CCCCCC0QQQQQ. */ -+{ "subsdw", 0x2EE97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* subsdw<.f> a,limm,u6 0010111001101001F111uuuuuuAAAAAA. */ -+{ "subsdw", 0x2E697000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subsdw<.f> 0,limm,u6 0010111001101001F111uuuuuu111110. */ -+{ "subsdw", 0x2E69703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* subsdw<.f><.cc> 0,limm,u6 0010111011101001F111uuuuuu1QQQQQ. */ -+{ "subsdw", 0x2EE97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* subsdw<.f> 0,limm,s12 0010111010101001F111ssssssSSSSSS. */ -+{ "subsdw", 0x2EA97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* subsdw<.f> a,limm,limm 0010111000101001F111111110AAAAAA. */ -+{ "subsdw", 0x2E297F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* subsdw<.f> 0,limm,limm 0010111000101001F111111110111110. */ -+{ "subsdw", 0x2E297FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* subsdw<.f><.cc> 0,limm,limm 0010111011101001F1111111100QQQQQ. */ -+{ "subsdw", 0x2EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* sub_s b,b,c 01111bbbccc00010. */ -+{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* sub_s a,b,c 01001bbbccc10aaa. */ -+{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, CD2, { OPERAND_RA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* sub_s c,b,u3 01101bbbccc01uuu. */ -+{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, -+ -+/* sub_s b,b,u5 10111bbb011uuuuu. */ -+{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, -+ -+/* sub_s SP,SP,u7 11000001101uuuuu. */ -+{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM7_A32_11_S }, { 0 }}, -+ -+/* sub_s.ne b,b,b 01111bbb11000000. */ -+{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RB_Sdup }, { C_NE, C_CC_NE }}, -+ -+/* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000. */ -+{ "swap", 0x282F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* swap<.f> 0,c 0010111000101111F111CCCCCC000000. */ -+{ "swap", 0x2E2F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* swap<.f> b,u6 00101bbb01101111FBBBuuuuuu000000. */ -+{ "swap", 0x286F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swap<.f> 0,u6 0010111001101111F111uuuuuu000000. */ -+{ "swap", 0x2E6F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swap<.f> b,limm 00101bbb00101111FBBB111110000000. */ -+{ "swap", 0x282F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* swap<.f> 0,limm 0010111000101111F111111110000000. */ -+{ "swap", 0x2E2F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* swape<.f> b,c 00101bbb00101111FBBBCCCCCC001001. */ -+{ "swape", 0x282F0009, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* swape<.f> 0,c 0010111000101111F111CCCCCC001001. */ -+{ "swape", 0x2E2F7009, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* swape<.f> b,u6 00101bbb01101111FBBBuuuuuu001001. */ -+{ "swape", 0x286F0009, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swape<.f> 0,u6 0010111001101111F111uuuuuu001001. */ -+{ "swape", 0x2E6F7009, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* swape<.f> b,limm 00101bbb00101111FBBB111110001001. */ -+{ "swape", 0x282F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* swape<.f> 0,limm 0010111000101111F111111110001001. */ -+{ "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* swi 00100010011011110000000000111111. */ -+{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* swi_s 0111101011100000. */ -+{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* swi_s u6 01111uuuuuu11111. */ -+{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_5_S }, { 0 }}, -+ -+/* sync 00100011011011110000000000111111. */ -+{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, -+ -+/* trap0 00100010011011110000000000111111. */ -+{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* trap_s u6 01111uuuuuu11110. */ -+{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_5_S }, { 0 }}, -+ -+/* tst b,c 00100bbb000010111BBBCCCCCCRRRRRR. */ -+{ "tst", 0x200B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* tst b,c 00100bbb000010111BBBCCCCCC000000. */ -+{ "tst", 0x200B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* tst<.cc> b,c 00100bbb110010111BBBCCCCCC0QQQQQ. */ -+{ "tst", 0x20CB8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, -+ -+/* tst b,u6 00100bbb010010111BBBuuuuuuRRRRRR. */ -+{ "tst", 0x204B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* tst b,u6 00100bbb010010111BBBuuuuuu000000. */ -+{ "tst", 0x204B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* tst<.cc> b,u6 00100bbb110010111BBBuuuuuu1QQQQQ. */ -+{ "tst", 0x20CB8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* tst b,s12 00100bbb100010111BBBssssssSSSSSS. */ -+{ "tst", 0x208B8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* tst limm,c 00100110000010111111CCCCCCRRRRRR. */ -+{ "tst", 0x260BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* tst b,limm 00100bbb000010111BBB111110RRRRRR. */ -+{ "tst", 0x200B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* tst limm,c 00100110000010111111CCCCCC000000. */ -+{ "tst", 0x260BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* tst b,limm 00100bbb000010111BBB111110000000. */ -+{ "tst", 0x200B8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* tst<.cc> b,limm 00100bbb110010111BBB1111100QQQQQ. */ -+{ "tst", 0x20CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, -+ -+/* tst<.cc> limm,c 00100110110010111111CCCCCC0QQQQQ. */ -+{ "tst", 0x26CBF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* tst limm,u6 00100110010010111111uuuuuuRRRRRR. */ -+{ "tst", 0x264BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* tst limm,u6 00100110010010111111uuuuuu000000. */ -+{ "tst", 0x264BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* tst<.cc> limm,u6 00100110110010111111uuuuuu1QQQQQ. */ -+{ "tst", 0x26CBF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* tst limm,s12 00100110100010111111ssssssSSSSSS. */ -+{ "tst", 0x268BF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* tst limm,limm 00100110000010111111111110RRRRRR. */ -+{ "tst", 0x260BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* tst limm,limm 00100110000010111111111110000000. */ -+{ "tst", 0x260BFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* tst<.cc> limm,limm 001001101100101111111111100QQQQQ. */ -+{ "tst", 0x26CBFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* tst_s b,c 01111bbbccc01011. */ -+{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, -+ -+/* unimp_s 0111100111100000. */ -+{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, -+ -+/* upkqb<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */ -+{ "upkqb", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* upkqb<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ. */ -+{ "upkqb", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* upkqb<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA. */ -+{ "upkqb", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* upkqb<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS. */ -+{ "upkqb", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* upkqb<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA. */ -+{ "upkqb", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* upkqb<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA. */ -+{ "upkqb", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* upkqb<.f><.cc> b,b,limm 00110bbb11100001FBBB1111100QQQQQ. */ -+{ "upkqb", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* vabs2h b,c 00101bbb001011110BBBCCCCCC101000. */ -+{ "vabs2h", 0x282F0028, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vabs2h 0,c 00101110001011110111CCCCCC101000. */ -+{ "vabs2h", 0x2E2F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vabs2h b,u6 00101bbb011011110BBBuuuuuu101000. */ -+{ "vabs2h", 0x286F0028, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vabs2h 0,u6 00101110011011110111uuuuuu101000. */ -+{ "vabs2h", 0x2E6F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vabs2h b,limm 00101bbb001011110BBB111110101000. */ -+{ "vabs2h", 0x282F0FA8, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vabs2h 0,limm 00101110001011110111111110101000. */ -+{ "vabs2h", 0x2E2F7FA8, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vabss2h b,c 00101bbb001011110BBBCCCCCC101001. */ -+{ "vabss2h", 0x282F0029, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vabss2h 0,c 00101110001011110111CCCCCC101001. */ -+{ "vabss2h", 0x2E2F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vabss2h b,u6 00101bbb011011110BBBuuuuuu101001. */ -+{ "vabss2h", 0x286F0029, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vabss2h 0,u6 00101110011011110111uuuuuu101001. */ -+{ "vabss2h", 0x2E6F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vabss2h b,limm 00101bbb001011110BBB111110101001. */ -+{ "vabss2h", 0x282F0FA9, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vabss2h 0,limm 00101110001011110111111110101001. */ -+{ "vabss2h", 0x2E2F7FA9, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA. */ -+{ "vadd2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd2 0,b,c 00101bbb001111000BBBCCCCCC111110. */ -+{ "vadd2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ. */ -+{ "vadd2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadd2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA. */ -+{ "vadd2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2 0,b,u6 00101bbb011111000BBBuuuuuu111110. */ -+{ "vadd2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ. */ -+{ "vadd2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd2 b,b,s12 00101bbb101111000BBBssssssSSSSSS. */ -+{ "vadd2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd2 a,limm,c 00101110001111000111CCCCCCAAAAAA. */ -+{ "vadd2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd2 a,b,limm 00101bbb001111000BBB111110AAAAAA. */ -+{ "vadd2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2 0,limm,c 00101110001111000111CCCCCC111110. */ -+{ "vadd2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd2 0,b,limm 00101bbb001111000BBB111110111110. */ -+{ "vadd2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ. */ -+{ "vadd2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadd2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ. */ -+{ "vadd2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadd2 a,limm,u6 00101110011111000111uuuuuuAAAAAA. */ -+{ "vadd2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2 0,limm,u6 00101110011111000111uuuuuu111110. */ -+{ "vadd2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ. */ -+{ "vadd2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd2 0,limm,s12 00101110101111000111ssssssSSSSSS. */ -+{ "vadd2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd2 a,limm,limm 00101110001111000111111110AAAAAA. */ -+{ "vadd2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd2 0,limm,limm 00101110001111000111111110111110. */ -+{ "vadd2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ. */ -+{ "vadd2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadd2h a,b,c 00101bbb000101000BBBCCCCCCAAAAAA. */ -+{ "vadd2h", 0x28140000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd2h 0,b,c 00101bbb000101000BBBCCCCCC111110. */ -+{ "vadd2h", 0x2814003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd2h<.cc> b,b,c 00101bbb110101000BBBCCCCCC0QQQQQ. */ -+{ "vadd2h", 0x28D40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadd2h a,b,u6 00101bbb010101000BBBuuuuuuAAAAAA. */ -+{ "vadd2h", 0x28540000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2h 0,b,u6 00101bbb010101000BBBuuuuuu111110. */ -+{ "vadd2h", 0x2854003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2h<.cc> b,b,u6 00101bbb110101000BBBuuuuuu1QQQQQ. */ -+{ "vadd2h", 0x28D40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd2h b,b,s12 00101bbb100101000BBBssssssSSSSSS. */ -+{ "vadd2h", 0x28940000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd2h a,limm,c 00101110000101000111CCCCCCAAAAAA. */ -+{ "vadd2h", 0x2E147000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd2h a,b,limm 00101bbb000101000BBB111110AAAAAA. */ -+{ "vadd2h", 0x28140F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2h 0,limm,c 00101110000101000111CCCCCC111110. */ -+{ "vadd2h", 0x2E14703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd2h 0,b,limm 00101bbb000101000BBB111110111110. */ -+{ "vadd2h", 0x28140FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd2h<.cc> b,b,limm 00101bbb110101000BBB1111100QQQQQ. */ -+{ "vadd2h", 0x28D40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadd2h<.cc> 0,limm,c 00101110110101000111CCCCCC0QQQQQ. */ -+{ "vadd2h", 0x2ED47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadd2h a,limm,u6 00101110010101000111uuuuuuAAAAAA. */ -+{ "vadd2h", 0x2E547000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2h 0,limm,u6 00101110010101000111uuuuuu111110. */ -+{ "vadd2h", 0x2E54703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd2h<.cc> 0,limm,u6 00101110110101000111uuuuuu1QQQQQ. */ -+{ "vadd2h", 0x2ED47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd2h 0,limm,s12 00101110100101000111ssssssSSSSSS. */ -+{ "vadd2h", 0x2E947000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd2h a,limm,limm 00101110000101000111111110AAAAAA. */ -+{ "vadd2h", 0x2E147F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd2h 0,limm,limm 00101110000101000111111110111110. */ -+{ "vadd2h", 0x2E147FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd2h<.cc> 0,limm,limm 001011101101010001111111100QQQQQ. */ -+{ "vadd2h", 0x2ED47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadd4b a,b,c 00101bbb001001000BBBCCCCCCAAAAAA. */ -+{ "vadd4b", 0x28240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd4b 0,b,c 00101bbb001001000BBBCCCCCC111110. */ -+{ "vadd4b", 0x2824003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd4b<.cc> b,b,c 00101bbb111001000BBBCCCCCC0QQQQQ. */ -+{ "vadd4b", 0x28E40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadd4b a,b,u6 00101bbb011001000BBBuuuuuuAAAAAA. */ -+{ "vadd4b", 0x28640000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4b 0,b,u6 00101bbb011001000BBBuuuuuu111110. */ -+{ "vadd4b", 0x2864003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4b<.cc> b,b,u6 00101bbb111001000BBBuuuuuu1QQQQQ. */ -+{ "vadd4b", 0x28E40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd4b b,b,s12 00101bbb101001000BBBssssssSSSSSS. */ -+{ "vadd4b", 0x28A40000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd4b a,limm,c 00101110001001000111CCCCCCAAAAAA. */ -+{ "vadd4b", 0x2E247000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd4b a,b,limm 00101bbb001001000BBB111110AAAAAA. */ -+{ "vadd4b", 0x28240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd4b 0,limm,c 00101110011001000111CCCCCC111110. */ -+{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd4b 0,b,limm 00101bbb001001000BBB111110111110. */ -+{ "vadd4b", 0x28240FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd4b<.cc> b,b,limm 00101bbb111001000BBB1111100QQQQQ. */ -+{ "vadd4b", 0x28E40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadd4b<.cc> 0,limm,c 00101110111001000111CCCCCC0QQQQQ. */ -+{ "vadd4b", 0x2EE47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadd4b a,limm,u6 00101110011001000111uuuuuuAAAAAA. */ -+{ "vadd4b", 0x2E647000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4b 0,limm,u6 00101110011001000111uuuuuu111110. */ -+{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4b<.cc> 0,limm,u6 00101110111001000111uuuuuu1QQQQQ. */ -+{ "vadd4b", 0x2EE47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd4b 0,limm,s12 00101110101001000111ssssssSSSSSS. */ -+{ "vadd4b", 0x2EA47000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd4b a,limm,limm 00101110001001000111111110AAAAAA. */ -+{ "vadd4b", 0x2E247F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd4b 0,limm,limm 00101110001001000111111110111110. */ -+{ "vadd4b", 0x2E247FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd4b<.cc> 0,limm,limm 001011101110010001111111100QQQQQ. */ -+{ "vadd4b", 0x2EE47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadd4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA. */ -+{ "vadd4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd4h 0,b,c 00101bbb001110000BBBCCCCCC111110. */ -+{ "vadd4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadd4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ. */ -+{ "vadd4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadd4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA. */ -+{ "vadd4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4h 0,b,u6 00101bbb011110000BBBuuuuuu111110. */ -+{ "vadd4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ. */ -+{ "vadd4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd4h b,b,s12 00101bbb101110000BBBssssssSSSSSS. */ -+{ "vadd4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd4h a,limm,c 00101110001110000111CCCCCCAAAAAA. */ -+{ "vadd4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd4h a,b,limm 00101bbb001110000BBB111110AAAAAA. */ -+{ "vadd4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd4h 0,limm,c 00101110001110000111CCCCCC111110. */ -+{ "vadd4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadd4h 0,b,limm 00101bbb001110000BBB111110111110. */ -+{ "vadd4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadd4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ. */ -+{ "vadd4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadd4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ. */ -+{ "vadd4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadd4h a,limm,u6 00101110011110000111uuuuuuAAAAAA. */ -+{ "vadd4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4h 0,limm,u6 00101110011110000111uuuuuu111110. */ -+{ "vadd4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadd4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ. */ -+{ "vadd4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadd4h 0,limm,s12 00101110101110000111ssssssSSSSSS. */ -+{ "vadd4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadd4h a,limm,limm 00101110001110000111111110AAAAAA. */ -+{ "vadd4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd4h 0,limm,limm 00101110001110000111111110111110. */ -+{ "vadd4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadd4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ. */ -+{ "vadd4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadds2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ */ -+{ "vadds2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadds2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA */ -+{ "vadds2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds2 0,b,c 00101bbb001111000BBBCCCCCC111110 */ -+{ "vadds2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ */ -+{ "vadds2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA */ -+{ "vadds2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2 0,b,u6 00101bbb011111000BBBuuuuuu111110 */ -+{ "vadds2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2 b,b,s12 00101bbb101111000BBBssssssSSSSSS */ -+{ "vadds2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds2 a,b,limm 00101bbb001111000BBB111110AAAAAA */ -+{ "vadds2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ */ -+{ "vadds2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadds2 0,b,limm 00101bbb001111000BBB111110111110 */ -+{ "vadds2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ */ -+{ "vadds2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadds2 a,limm,c 00101110001111000111CCCCCCAAAAAA */ -+{ "vadds2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds2 0,limm,c 00101110001111000111CCCCCC111110 */ -+{ "vadds2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ */ -+{ "vadds2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds2 0,limm,u6 00101110011111000111uuuuuu111110 */ -+{ "vadds2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2 a,limm,u6 00101110011111000111uuuuuuAAAAAA */ -+{ "vadds2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2 0,limm,s12 00101110101111000111ssssssSSSSSS */ -+{ "vadds2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds2 0,limm,limm 00101110001111000111111110111110 */ -+{ "vadds2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds2 a,limm,limm 00101110001111000111111110AAAAAA */ -+{ "vadds2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ */ -+{ "vadds2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadds2h a,b,c 00101bbb000101001BBBCCCCCCAAAAAA. */ -+{ "vadds2h", 0x28148000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds2h 0,b,c 00101bbb000101001BBBCCCCCC111110. */ -+{ "vadds2h", 0x2814803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds2h<.cc> b,b,c 00101bbb110101001BBBCCCCCC0QQQQQ. */ -+{ "vadds2h", 0x28D48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadds2h a,b,u6 00101bbb010101001BBBuuuuuuAAAAAA. */ -+{ "vadds2h", 0x28548000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2h 0,b,u6 00101bbb010101001BBBuuuuuu111110. */ -+{ "vadds2h", 0x2854803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2h<.cc> b,b,u6 00101bbb110101001BBBuuuuuu1QQQQQ. */ -+{ "vadds2h", 0x28D48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds2h b,b,s12 00101bbb100101001BBBssssssSSSSSS. */ -+{ "vadds2h", 0x28948000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds2h a,limm,c 00101110000101001111CCCCCCAAAAAA. */ -+{ "vadds2h", 0x2E14F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds2h a,b,limm 00101bbb000101001BBB111110AAAAAA. */ -+{ "vadds2h", 0x28148F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds2h 0,limm,c 00101110000101001111CCCCCC111110. */ -+{ "vadds2h", 0x2E14F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds2h 0,b,limm 00101bbb000101001BBB111110111110. */ -+{ "vadds2h", 0x28148FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds2h<.cc> b,b,limm 00101bbb110101001BBB1111100QQQQQ. */ -+{ "vadds2h", 0x28D48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadds2h<.cc> 0,limm,c 00101110110101001111CCCCCC0QQQQQ. */ -+{ "vadds2h", 0x2ED4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadds2h a,limm,u6 00101110010101001111uuuuuuAAAAAA. */ -+{ "vadds2h", 0x2E54F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2h 0,limm,u6 00101110010101001111uuuuuu111110. */ -+{ "vadds2h", 0x2E54F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds2h<.cc> 0,limm,u6 00101110110101001111uuuuuu1QQQQQ. */ -+{ "vadds2h", 0x2ED4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds2h 0,limm,s12 00101110100101001111ssssssSSSSSS. */ -+{ "vadds2h", 0x2E94F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds2h a,limm,limm 00101110000101001111111110AAAAAA. */ -+{ "vadds2h", 0x2E14FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds2h 0,limm,limm 00101110000101001111111110111110. */ -+{ "vadds2h", 0x2E14FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds2h<.cc> 0,limm,limm 001011101101010011111111100QQQQQ. */ -+{ "vadds2h", 0x2ED4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadds4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA */ -+{ "vadds4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds4h 0,b,c 00101bbb001110000BBBCCCCCC111110 */ -+{ "vadds4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vadds4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ */ -+{ "vadds4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vadds4h 0,b,u6 00101bbb011110000BBBuuuuuu111110 */ -+{ "vadds4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ */ -+{ "vadds4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA */ -+{ "vadds4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds4h b,b,s12 00101bbb101110000BBBssssssSSSSSS */ -+{ "vadds4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ */ -+{ "vadds4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vadds4h a,b,limm 00101bbb001110000BBB111110AAAAAA */ -+{ "vadds4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ */ -+{ "vadds4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vadds4h a,limm,c 00101110001110000111CCCCCCAAAAAA */ -+{ "vadds4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds4h 0,b,limm 00101bbb001110000BBB111110111110 */ -+{ "vadds4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vadds4h 0,limm,c 00101110001110000111CCCCCC111110 */ -+{ "vadds4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vadds4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ */ -+{ "vadds4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vadds4h a,limm,u6 00101110011110000111uuuuuuAAAAAA */ -+{ "vadds4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds4h 0,limm,u6 00101110011110000111uuuuuu111110 */ -+{ "vadds4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vadds4h 0,limm,s12 00101110101110000111ssssssSSSSSS */ -+{ "vadds4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vadds4h a,limm,limm 00101110001110000111111110AAAAAA */ -+{ "vadds4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vadds4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ */ -+{ "vadds4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vadds4h 0,limm,limm 00101110001110000111111110111110 */ -+{ "vadds4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub a,b,c 00101bbb001111100BBBCCCCCCAAAAAA. */ -+{ "vaddsub", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub 0,b,c 00101bbb001111100BBBCCCCCC111110. */ -+{ "vaddsub", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ. */ -+{ "vaddsub", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA. */ -+{ "vaddsub", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub 0,b,u6 00101bbb011111100BBBuuuuuu111110. */ -+{ "vaddsub", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ. */ -+{ "vaddsub", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub b,b,s12 00101bbb101111100BBBssssssSSSSSS. */ -+{ "vaddsub", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub a,limm,c 00101110001111100111CCCCCCAAAAAA. */ -+{ "vaddsub", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub a,b,limm 00101bbb001111100BBB111110AAAAAA. */ -+{ "vaddsub", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub 0,limm,c 00101110001111100111CCCCCC111110. */ -+{ "vaddsub", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub 0,b,limm 00101bbb001111100BBB111110111110. */ -+{ "vaddsub", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ. */ -+{ "vaddsub", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsub<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ. */ -+{ "vaddsub", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub a,limm,u6 00101110011111100111uuuuuuAAAAAA. */ -+{ "vaddsub", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub 0,limm,u6 00101110011111100111uuuuuu111110. */ -+{ "vaddsub", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ. */ -+{ "vaddsub", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub 0,limm,s12 00101110101111100111ssssssSSSSSS. */ -+{ "vaddsub", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub a,limm,limm 00101110001111100111111110AAAAAA. */ -+{ "vaddsub", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub 0,limm,limm 00101110001111100111111110111110. */ -+{ "vaddsub", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub<.cc> 0,limm,limm 001011101111111001111111100QQQQQ. */ -+{ "vaddsub", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsub2h a,b,c 00101bbb000101100BBBCCCCCCAAAAAA. */ -+{ "vaddsub2h", 0x28160000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub2h 0,b,c 00101bbb000101100BBBCCCCCC111110. */ -+{ "vaddsub2h", 0x2816003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub2h<.cc> b,b,c 00101bbb110101100BBBCCCCCC0QQQQQ. */ -+{ "vaddsub2h", 0x28D60000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub2h a,b,u6 00101bbb010101100BBBuuuuuuAAAAAA. */ -+{ "vaddsub2h", 0x28560000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub2h 0,b,u6 00101bbb010101100BBBuuuuuu111110. */ -+{ "vaddsub2h", 0x2856003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub2h<.cc> b,b,u6 00101bbb110101100BBBuuuuuu1QQQQQ. */ -+{ "vaddsub2h", 0x28D60020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub2h b,b,s12 00101bbb100101100BBBssssssSSSSSS. */ -+{ "vaddsub2h", 0x28960000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub2h a,limm,c 00101110000101100111CCCCCCAAAAAA. */ -+{ "vaddsub2h", 0x2E167000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub2h a,b,limm 00101bbb000101100BBB111110AAAAAA. */ -+{ "vaddsub2h", 0x28160F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub2h 0,limm,c 00101110000101100111CCCCCC111110. */ -+{ "vaddsub2h", 0x2E16703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub2h 0,b,limm 00101bbb000101100BBB111110111110. */ -+{ "vaddsub2h", 0x28160FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub2h<.cc> b,b,limm 00101bbb110101100BBB1111100QQQQQ. */ -+{ "vaddsub2h", 0x28D60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsub2h<.cc> 0,limm,c 00101110110101100111CCCCCC0QQQQQ. */ -+{ "vaddsub2h", 0x2ED67000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub2h a,limm,u6 00101110010101100111uuuuuuAAAAAA. */ -+{ "vaddsub2h", 0x2E567000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub2h 0,limm,u6 00101110010101100111uuuuuu111110. */ -+{ "vaddsub2h", 0x2E56703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub2h<.cc> 0,limm,u6 00101110110101100111uuuuuu1QQQQQ. */ -+{ "vaddsub2h", 0x2ED67020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub2h 0,limm,s12 00101110100101100111ssssssSSSSSS. */ -+{ "vaddsub2h", 0x2E967000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub2h a,limm,limm 00101110000101100111111110AAAAAA. */ -+{ "vaddsub2h", 0x2E167F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub2h 0,limm,limm 00101110000101100111111110111110. */ -+{ "vaddsub2h", 0x2E167FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub2h<.cc> 0,limm,limm 001011101101011001111111100QQQQQ. */ -+{ "vaddsub2h", 0x2ED67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsub4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA. */ -+{ "vaddsub4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub4h 0,b,c 00101bbb001110100BBBCCCCCC111110. */ -+{ "vaddsub4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ. */ -+{ "vaddsub4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA. */ -+{ "vaddsub4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub4h 0,b,u6 00101bbb011110100BBBuuuuuu111110. */ -+{ "vaddsub4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ. */ -+{ "vaddsub4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub4h b,b,s12 00101bbb101110100BBBssssssSSSSSS. */ -+{ "vaddsub4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub4h a,limm,c 00101110001110100111CCCCCCAAAAAA. */ -+{ "vaddsub4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub4h a,b,limm 00101bbb001110100BBB111110AAAAAA. */ -+{ "vaddsub4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub4h 0,limm,c 00101110001110100111CCCCCC111110. */ -+{ "vaddsub4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsub4h 0,b,limm 00101bbb001110100BBB111110111110. */ -+{ "vaddsub4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsub4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ. */ -+{ "vaddsub4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsub4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ. */ -+{ "vaddsub4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsub4h a,limm,u6 00101110011110100111uuuuuuAAAAAA. */ -+{ "vaddsub4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub4h 0,limm,u6 00101110011110100111uuuuuu111110. */ -+{ "vaddsub4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsub4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ. */ -+{ "vaddsub4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsub4h 0,limm,s12 00101110101110100111ssssssSSSSSS. */ -+{ "vaddsub4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsub4h a,limm,limm 00101110001110100111111110AAAAAA. */ -+{ "vaddsub4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub4h 0,limm,limm 00101110001110100111111110111110. */ -+{ "vaddsub4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsub4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ. */ -+{ "vaddsub4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsubs a,b,c 00101bbb001111100BBBCCCCCCAAAAAA */ -+{ "vaddsubs", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ */ -+{ "vaddsubs", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs 0,b,c 00101bbb001111100BBBCCCCCC111110 */ -+{ "vaddsubs", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA */ -+{ "vaddsubs", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs 0,b,u6 00101bbb011111100BBBuuuuuu111110 */ -+{ "vaddsubs", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ */ -+{ "vaddsubs", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs b,b,s12 00101bbb101111100BBBssssssSSSSSS */ -+{ "vaddsubs", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs a,limm,c 00101110001111100111CCCCCCAAAAAA */ -+{ "vaddsubs", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs a,b,limm 00101bbb001111100BBB111110AAAAAA */ -+{ "vaddsubs", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ */ -+{ "vaddsubs", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs 0,limm,c 00101110001111100111CCCCCC111110 */ -+{ "vaddsubs", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ */ -+{ "vaddsubs", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsubs 0,b,limm 00101bbb001111100BBB111110111110 */ -+{ "vaddsubs", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs a,limm,u6 00101110011111100111uuuuuuAAAAAA */ -+{ "vaddsubs", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs 0,limm,u6 00101110011111100111uuuuuu111110 */ -+{ "vaddsubs", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ */ -+{ "vaddsubs", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs 0,limm,s12 00101110101111100111ssssssSSSSSS */ -+{ "vaddsubs", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs 0,limm,limm 00101110001111100111111110111110 */ -+{ "vaddsubs", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs<.cc> 0,limm,limm 001011101111111001111111100QQQQQ */ -+{ "vaddsubs", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsubs a,limm,limm 00101110001111100111111110AAAAAA */ -+{ "vaddsubs", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs2h a,b,c 00101bbb000101101BBBCCCCCCAAAAAA. */ -+{ "vaddsubs2h", 0x28168000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs2h 0,b,c 00101bbb000101101BBBCCCCCC111110. */ -+{ "vaddsubs2h", 0x2816803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs2h<.cc> b,b,c 00101bbb110101101BBBCCCCCC0QQQQQ. */ -+{ "vaddsubs2h", 0x28D68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs2h a,b,u6 00101bbb010101101BBBuuuuuuAAAAAA. */ -+{ "vaddsubs2h", 0x28568000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs2h 0,b,u6 00101bbb010101101BBBuuuuuu111110. */ -+{ "vaddsubs2h", 0x2856803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs2h<.cc> b,b,u6 00101bbb110101101BBBuuuuuu1QQQQQ. */ -+{ "vaddsubs2h", 0x28D68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs2h b,b,s12 00101bbb100101101BBBssssssSSSSSS. */ -+{ "vaddsubs2h", 0x28968000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs2h a,limm,c 00101110000101101111CCCCCCAAAAAA. */ -+{ "vaddsubs2h", 0x2E16F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs2h a,b,limm 00101bbb000101101BBB111110AAAAAA. */ -+{ "vaddsubs2h", 0x28168F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs2h 0,limm,c 00101110000101101111CCCCCC111110. */ -+{ "vaddsubs2h", 0x2E16F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs2h 0,b,limm 00101bbb000101101BBB111110111110. */ -+{ "vaddsubs2h", 0x28168FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs2h<.cc> b,b,limm 00101bbb110101101BBB1111100QQQQQ. */ -+{ "vaddsubs2h", 0x28D68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsubs2h<.cc> 0,limm,c 00101110110101101111CCCCCC0QQQQQ. */ -+{ "vaddsubs2h", 0x2ED6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs2h a,limm,u6 00101110010101101111uuuuuuAAAAAA. */ -+{ "vaddsubs2h", 0x2E56F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs2h 0,limm,u6 00101110010101101111uuuuuu111110. */ -+{ "vaddsubs2h", 0x2E56F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs2h<.cc> 0,limm,u6 00101110110101101111uuuuuu1QQQQQ. */ -+{ "vaddsubs2h", 0x2ED6F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs2h 0,limm,s12 00101110100101101111ssssssSSSSSS. */ -+{ "vaddsubs2h", 0x2E96F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs2h a,limm,limm 00101110000101101111111110AAAAAA. */ -+{ "vaddsubs2h", 0x2E16FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs2h 0,limm,limm 00101110000101101111111110111110. */ -+{ "vaddsubs2h", 0x2E16FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs2h<.cc> 0,limm,limm 001011101101011011111111100QQQQQ. */ -+{ "vaddsubs2h", 0x2ED6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsubs4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA */ -+{ "vaddsubs4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs4h 0,b,c 00101bbb001110100BBBCCCCCC111110 */ -+{ "vaddsubs4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ */ -+{ "vaddsubs4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA */ -+{ "vaddsubs4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ */ -+{ "vaddsubs4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs4h 0,b,u6 00101bbb011110100BBBuuuuuu111110 */ -+{ "vaddsubs4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs4h b,b,s12 00101bbb101110100BBBssssssSSSSSS */ -+{ "vaddsubs4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs4h a,limm,c 00101110001110100111CCCCCCAAAAAA */ -+{ "vaddsubs4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ */ -+{ "vaddsubs4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vaddsubs4h a,b,limm 00101bbb001110100BBB111110AAAAAA */ -+{ "vaddsubs4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ */ -+{ "vaddsubs4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vaddsubs4h 0,b,limm 00101bbb001110100BBB111110111110 */ -+{ "vaddsubs4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vaddsubs4h 0,limm,c 00101110001110100111CCCCCC111110 */ -+{ "vaddsubs4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vaddsubs4h 0,limm,u6 00101110011110100111uuuuuu111110 */ -+{ "vaddsubs4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs4h a,limm,u6 00101110011110100111uuuuuuAAAAAA */ -+{ "vaddsubs4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vaddsubs4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ */ -+{ "vaddsubs4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vaddsubs4h 0,limm,s12 00101110101110100111ssssssSSSSSS */ -+{ "vaddsubs4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vaddsubs4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ */ -+{ "vaddsubs4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vaddsubs4h 0,limm,limm 00101110001110100111111110111110 */ -+{ "vaddsubs4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vaddsubs4h a,limm,limm 00101110001110100111111110AAAAAA */ -+{ "vaddsubs4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* valgn2h a,b,c 00101bbb000011010BBBCCCCCCAAAAAA. */ -+{ "valgn2h", 0x280D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* valgn2h 0,b,c 00101bbb000011010BBBCCCCCC111110. */ -+{ "valgn2h", 0x280D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* valgn2h<.cc> b,b,c 00101bbb110011010BBBCCCCCC0QQQQQ. */ -+{ "valgn2h", 0x28CD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* valgn2h a,b,u6 00101bbb010011010BBBuuuuuuAAAAAA. */ -+{ "valgn2h", 0x284D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* valgn2h 0,b,u6 00101bbb010011010BBBuuuuuu111110. */ -+{ "valgn2h", 0x284D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* valgn2h<.cc> b,b,u6 00101bbb110011010BBBuuuuuu1QQQQQ. */ -+{ "valgn2h", 0x28CD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* valgn2h b,b,s12 00101bbb100011010BBBssssssSSSSSS. */ -+{ "valgn2h", 0x288D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* valgn2h a,limm,c 00101110000011010111CCCCCCAAAAAA. */ -+{ "valgn2h", 0x2E0D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* valgn2h a,b,limm 00101bbb000011010BBB111110AAAAAA. */ -+{ "valgn2h", 0x280D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* valgn2h 0,limm,c 00101110000011010111CCCCCC111110. */ -+{ "valgn2h", 0x2E0D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* valgn2h 0,b,limm 00101bbb000011010BBB111110111110. */ -+{ "valgn2h", 0x280D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* valgn2h<.cc> b,b,limm 00101bbb110011010BBB1111100QQQQQ. */ -+{ "valgn2h", 0x28CD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* valgn2h<.cc> 0,limm,c 00101110110011010111CCCCCC0QQQQQ. */ -+{ "valgn2h", 0x2ECD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* valgn2h a,limm,u6 00101110010011010111uuuuuuAAAAAA. */ -+{ "valgn2h", 0x2E4D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* valgn2h 0,limm,u6 00101110010011010111uuuuuu111110. */ -+{ "valgn2h", 0x2E4D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* valgn2h<.cc> 0,limm,u6 00101110110011010111uuuuuu1QQQQQ. */ -+{ "valgn2h", 0x2ECD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* valgn2h 0,limm,s12 00101110100011010111ssssssSSSSSS. */ -+{ "valgn2h", 0x2E8D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* valgn2h a,limm,limm 00101110000011010111111110AAAAAA. */ -+{ "valgn2h", 0x2E0D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* valgn2h 0,limm,limm 00101110000011010111111110111110. */ -+{ "valgn2h", 0x2E0D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* valgn2h<.cc> 0,limm,limm 001011101100110101111111100QQQQQ. */ -+{ "valgn2h", 0x2ECD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasl2h a,b,c 00101bbb001000010BBBCCCCCCAAAAAA. */ -+{ "vasl2h", 0x28210000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasl2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */ -+{ "vasl2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasl2h<.cc> b,b,c 00101bbb111000010BBBCCCCCC0QQQQQ. */ -+{ "vasl2h", 0x28E10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasl2h a,b,u6 00101bbb011000010BBBuuuuuuAAAAAA. */ -+{ "vasl2h", 0x28610000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasl2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */ -+{ "vasl2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasl2h<.cc> b,b,u6 00101bbb111000010BBBuuuuuu1QQQQQ. */ -+{ "vasl2h", 0x28E10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasl2h b,b,s12 00101bbb101000010BBBssssssSSSSSS. */ -+{ "vasl2h", 0x28A10000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasl2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */ -+{ "vasl2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasl2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */ -+{ "vasl2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasl2h 0,limm,c 00101110011000010111CCCCCC111110. */ -+{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasl2h 0,b,limm 00101bbb001000010BBB111110111110. */ -+{ "vasl2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasl2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */ -+{ "vasl2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasl2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */ -+{ "vasl2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasl2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */ -+{ "vasl2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasl2h 0,limm,u6 00101110011000010111uuuuuu111110. */ -+{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasl2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */ -+{ "vasl2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasl2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */ -+{ "vasl2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasl2h a,limm,limm 00101110001000010111111110AAAAAA. */ -+{ "vasl2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasl2h 0,limm,limm 00101110001000010111111110111110. */ -+{ "vasl2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasl2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */ -+{ "vasl2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasls2h a,b,c 00101bbb001000011BBBCCCCCCAAAAAA. */ -+{ "vasls2h", 0x28218000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasls2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */ -+{ "vasls2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasls2h<.cc> b,b,c 00101bbb111000011BBBCCCCCC0QQQQQ. */ -+{ "vasls2h", 0x28E18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasls2h a,b,u6 00101bbb011000011BBBuuuuuuAAAAAA. */ -+{ "vasls2h", 0x28618000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasls2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */ -+{ "vasls2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasls2h<.cc> b,b,u6 00101bbb111000011BBBuuuuuu1QQQQQ. */ -+{ "vasls2h", 0x28E18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasls2h b,b,s12 00101bbb101000011BBBssssssSSSSSS. */ -+{ "vasls2h", 0x28A18000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasls2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */ -+{ "vasls2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasls2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */ -+{ "vasls2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasls2h 0,limm,c 00101110011000010111CCCCCC111110. */ -+{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasls2h 0,b,limm 00101bbb001000010BBB111110111110. */ -+{ "vasls2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasls2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */ -+{ "vasls2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasls2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */ -+{ "vasls2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasls2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */ -+{ "vasls2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasls2h 0,limm,u6 00101110011000010111uuuuuu111110. */ -+{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasls2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */ -+{ "vasls2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasls2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */ -+{ "vasls2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasls2h a,limm,limm 00101110001000010111111110AAAAAA. */ -+{ "vasls2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasls2h 0,limm,limm 00101110001000010111111110111110. */ -+{ "vasls2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasls2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */ -+{ "vasls2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasr2h a,b,c 00101bbb001000100BBBCCCCCCAAAAAA. */ -+{ "vasr2h", 0x28220000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasr2h 0,b,c 00101bbb001000100BBBCCCCCC111110. */ -+{ "vasr2h", 0x2822003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasr2h<.cc> b,b,c 00101bbb111000100BBBCCCCCC0QQQQQ. */ -+{ "vasr2h", 0x28E20000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasr2h a,b,u6 00101bbb011000100BBBuuuuuuAAAAAA. */ -+{ "vasr2h", 0x28620000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasr2h 0,b,u6 00101bbb011000100BBBuuuuuu111110. */ -+{ "vasr2h", 0x2862003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasr2h<.cc> b,b,u6 00101bbb111000100BBBuuuuuu1QQQQQ. */ -+{ "vasr2h", 0x28E20020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasr2h b,b,s12 00101bbb101000100BBBssssssSSSSSS. */ -+{ "vasr2h", 0x28A20000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasr2h a,limm,c 00101110001000100111CCCCCCAAAAAA. */ -+{ "vasr2h", 0x2E227000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasr2h a,b,limm 00101bbb001000100BBB111110AAAAAA. */ -+{ "vasr2h", 0x28220F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasr2h 0,limm,c 00101110011000100111CCCCCC111110. */ -+{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasr2h 0,b,limm 00101bbb001000100BBB111110111110. */ -+{ "vasr2h", 0x28220FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasr2h<.cc> b,b,limm 00101bbb111000100BBB1111100QQQQQ. */ -+{ "vasr2h", 0x28E20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasr2h<.cc> 0,limm,c 00101110111000100111CCCCCC0QQQQQ. */ -+{ "vasr2h", 0x2EE27000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasr2h a,limm,u6 00101110011000100111uuuuuuAAAAAA. */ -+{ "vasr2h", 0x2E627000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasr2h 0,limm,u6 00101110011000100111uuuuuu111110. */ -+{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasr2h<.cc> 0,limm,u6 00101110111000100111uuuuuu1QQQQQ. */ -+{ "vasr2h", 0x2EE27020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasr2h 0,limm,s12 00101110101000100111ssssssSSSSSS. */ -+{ "vasr2h", 0x2EA27000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasr2h a,limm,limm 00101110001000100111111110AAAAAA. */ -+{ "vasr2h", 0x2E227F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasr2h 0,limm,limm 00101110001000100111111110111110. */ -+{ "vasr2h", 0x2E227FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasr2h<.cc> 0,limm,limm 001011101110001001111111100QQQQQ. */ -+{ "vasr2h", 0x2EE27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasrs2h a,b,c 00101bbb001000101BBBCCCCCCAAAAAA. */ -+{ "vasrs2h", 0x28228000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasrs2h 0,b,c 00101bbb001000101BBBCCCCCC111110. */ -+{ "vasrs2h", 0x2822803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasrs2h<.cc> b,b,c 00101bbb111000101BBBCCCCCC0QQQQQ. */ -+{ "vasrs2h", 0x28E28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasrs2h a,b,u6 00101bbb011000101BBBuuuuuuAAAAAA. */ -+{ "vasrs2h", 0x28628000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrs2h 0,b,u6 00101bbb011000101BBBuuuuuu111110. */ -+{ "vasrs2h", 0x2862803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrs2h<.cc> b,b,u6 00101bbb111000101BBBuuuuuu1QQQQQ. */ -+{ "vasrs2h", 0x28E28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasrs2h b,b,s12 00101bbb101000101BBBssssssSSSSSS. */ -+{ "vasrs2h", 0x28A28000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasrs2h a,limm,c 00101110001000101111CCCCCCAAAAAA. */ -+{ "vasrs2h", 0x2E22F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasrs2h a,b,limm 00101bbb001000101BBB111110AAAAAA. */ -+{ "vasrs2h", 0x28228F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasrs2h 0,limm,c 00101110011000101111CCCCCC111110. */ -+{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasrs2h 0,b,limm 00101bbb001000101BBB111110111110. */ -+{ "vasrs2h", 0x28228FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasrs2h<.cc> b,b,limm 00101bbb111000101BBB1111100QQQQQ. */ -+{ "vasrs2h", 0x28E28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasrs2h<.cc> 0,limm,c 00101110111000101111CCCCCC0QQQQQ. */ -+{ "vasrs2h", 0x2EE2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasrs2h a,limm,u6 00101110011000101111uuuuuuAAAAAA. */ -+{ "vasrs2h", 0x2E62F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrs2h 0,limm,u6 00101110011000101111uuuuuu111110. */ -+{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrs2h<.cc> 0,limm,u6 00101110111000101111uuuuuu1QQQQQ. */ -+{ "vasrs2h", 0x2EE2F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasrs2h 0,limm,s12 00101110101000101111ssssssSSSSSS. */ -+{ "vasrs2h", 0x2EA2F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasrs2h a,limm,limm 00101110001000101111111110AAAAAA. */ -+{ "vasrs2h", 0x2E22FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasrs2h 0,limm,limm 00101110001000101111111110111110. */ -+{ "vasrs2h", 0x2E22FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasrs2h<.cc> 0,limm,limm 001011101110001011111111100QQQQQ. */ -+{ "vasrs2h", 0x2EE2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vasrsr2h a,b,c 00101bbb001000111BBBCCCCCCAAAAAA. */ -+{ "vasrsr2h", 0x28238000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasrsr2h 0,b,c 00101bbb001000111BBBCCCCCC111110. */ -+{ "vasrsr2h", 0x2823803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vasrsr2h<.cc> b,b,c 00101bbb111000111BBBCCCCCC0QQQQQ. */ -+{ "vasrsr2h", 0x28E38000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vasrsr2h a,b,u6 00101bbb011000111BBBuuuuuuAAAAAA. */ -+{ "vasrsr2h", 0x28638000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrsr2h 0,b,u6 00101bbb011000111BBBuuuuuu111110. */ -+{ "vasrsr2h", 0x2863803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrsr2h<.cc> b,b,u6 00101bbb111000111BBBuuuuuu1QQQQQ. */ -+{ "vasrsr2h", 0x28E38020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasrsr2h b,b,s12 00101bbb101000111BBBssssssSSSSSS. */ -+{ "vasrsr2h", 0x28A38000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasrsr2h a,limm,c 00101110001000111111CCCCCCAAAAAA. */ -+{ "vasrsr2h", 0x2E23F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasrsr2h a,b,limm 00101bbb001000111BBB111110AAAAAA. */ -+{ "vasrsr2h", 0x28238F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasrsr2h 0,limm,c 00101110011000111111CCCCCC111110. */ -+{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vasrsr2h 0,b,limm 00101bbb001000111BBB111110111110. */ -+{ "vasrsr2h", 0x28238FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vasrsr2h<.cc> b,b,limm 00101bbb111000111BBB1111100QQQQQ. */ -+{ "vasrsr2h", 0x28E38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vasrsr2h<.cc> 0,limm,c 00101110111000111111CCCCCC0QQQQQ. */ -+{ "vasrsr2h", 0x2EE3F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vasrsr2h a,limm,u6 00101110011000111111uuuuuuAAAAAA. */ -+{ "vasrsr2h", 0x2E63F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrsr2h 0,limm,u6 00101110011000111111uuuuuu111110. */ -+{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vasrsr2h<.cc> 0,limm,u6 00101110111000111111uuuuuu1QQQQQ. */ -+{ "vasrsr2h", 0x2EE3F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vasrsr2h 0,limm,s12 00101110101000111111ssssssSSSSSS. */ -+{ "vasrsr2h", 0x2EA3F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vasrsr2h a,limm,limm 00101110001000111111111110AAAAAA. */ -+{ "vasrsr2h", 0x2E23FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasrsr2h 0,limm,limm 00101110001000111111111110111110. */ -+{ "vasrsr2h", 0x2E23FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vasrsr2h<.cc> 0,limm,limm 001011101110001111111111100QQQQQ. */ -+{ "vasrsr2h", 0x2EE3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001010. */ -+{ "vbfdw", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, -+ -+/* vbfdw<.f> 0,c 0010111000101111F111CCCCCC001010. */ -+{ "vbfdw", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, -+ -+/* vbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001010. */ -+{ "vbfdw", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* vbfdw<.f> 0,u6 0010111001101111F111uuuuuu001010. */ -+{ "vbfdw", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* vbfdw<.f> b,limm 00101bbb00101111FBBB111110001010. */ -+{ "vbfdw", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, -+ -+/* vbfdw<.f> 0,limm 0010111000101111F111111110001010. */ -+{ "vbfdw", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, -+ -+/* vext2bhl b,c 00101bbb001011110BBBCCCCCC100100. */ -+{ "vext2bhl", 0x282F0024, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhl 0,c 00101110001011110111CCCCCC100100. */ -+{ "vext2bhl", 0x2E2F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhl b,u6 00101bbb011011110BBBuuuuuu100100. */ -+{ "vext2bhl", 0x286F0024, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhl 0,u6 00101110011011110111uuuuuu100100. */ -+{ "vext2bhl", 0x2E6F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhl b,limm 00101bbb001011110BBB111110100100. */ -+{ "vext2bhl", 0x282F0FA4, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhl 0,limm 00101110001011110111111110100100. */ -+{ "vext2bhl", 0x2E2F7FA4, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhlf 0,c 00101110001011110111CCCCCC100000 */ -+{ "vext2bhlf", 0x2E2F7020, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhlf b,c 00101bbb001011110BBBCCCCCC100000 */ -+{ "vext2bhlf", 0x282F0020, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhlf b,u6 00101bbb011011110BBBuuuuuu100000 */ -+{ "vext2bhlf", 0x286F0020, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhlf 0,u6 00101110011011110111uuuuuu100000 */ -+{ "vext2bhlf", 0x2E6F7020, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhlf b,limm 00101bbb001011110BBB111110100000 */ -+{ "vext2bhlf", 0x282F0FA0, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhlf 0,limm 00101110001011110111111110100000 */ -+{ "vext2bhlf", 0x2E2F7FA0, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhm b,c 00101bbb001011110BBBCCCCCC100101. */ -+{ "vext2bhm", 0x282F0025, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhm 0,c 00101110001011110111CCCCCC100101. */ -+{ "vext2bhm", 0x2E2F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhm b,u6 00101bbb011011110BBBuuuuuu100101. */ -+{ "vext2bhm", 0x286F0025, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhm 0,u6 00101110011011110111uuuuuu100101. */ -+{ "vext2bhm", 0x2E6F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhm b,limm 00101bbb001011110BBB111110100101. */ -+{ "vext2bhm", 0x282F0FA5, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhm 0,limm 00101110001011110111111110100101. */ -+{ "vext2bhm", 0x2E2F7FA5, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhmf b,c 00101bbb001011110BBBCCCCCC100001 */ -+{ "vext2bhmf", 0x282F0021, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhmf 0,c 00101110001011110111CCCCCC100001 */ -+{ "vext2bhmf", 0x2E2F7021, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vext2bhmf b,u6 00101bbb011011110BBBuuuuuu100001 */ -+{ "vext2bhmf", 0x286F0021, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhmf 0,u6 00101110011011110111uuuuuu100001 */ -+{ "vext2bhmf", 0x2E6F7021, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vext2bhmf 0,limm 00101110001011110111111110100001 */ -+{ "vext2bhmf", 0x2E2F7FA1, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vext2bhmf b,limm 00101bbb001011110BBB111110100001 */ -+{ "vext2bhmf", 0x282F0FA1, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vlsr2h a,b,c 00101bbb001000110BBBCCCCCCAAAAAA. */ -+{ "vlsr2h", 0x28230000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vlsr2h 0,b,c 00101bbb001000110BBBCCCCCC111110. */ -+{ "vlsr2h", 0x2823003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vlsr2h<.cc> b,b,c 00101bbb111000110BBBCCCCCC0QQQQQ. */ -+{ "vlsr2h", 0x28E30000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vlsr2h a,b,u6 00101bbb011000110BBBuuuuuuAAAAAA. */ -+{ "vlsr2h", 0x28630000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vlsr2h 0,b,u6 00101bbb011000110BBBuuuuuu111110. */ -+{ "vlsr2h", 0x2863003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vlsr2h<.cc> b,b,u6 00101bbb111000110BBBuuuuuu1QQQQQ. */ -+{ "vlsr2h", 0x28E30020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vlsr2h b,b,s12 00101bbb101000110BBBssssssSSSSSS. */ -+{ "vlsr2h", 0x28A30000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vlsr2h a,limm,c 00101110001000110111CCCCCCAAAAAA. */ -+{ "vlsr2h", 0x2E237000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vlsr2h a,b,limm 00101bbb001000110BBB111110AAAAAA. */ -+{ "vlsr2h", 0x28230F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vlsr2h 0,limm,c 00101110011000110111CCCCCC111110. */ -+{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vlsr2h 0,b,limm 00101bbb001000110BBB111110111110. */ -+{ "vlsr2h", 0x28230FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vlsr2h<.cc> b,b,limm 00101bbb111000110BBB1111100QQQQQ. */ -+{ "vlsr2h", 0x28E30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vlsr2h<.cc> 0,limm,c 00101110111000110111CCCCCC0QQQQQ. */ -+{ "vlsr2h", 0x2EE37000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vlsr2h a,limm,u6 00101110011000110111uuuuuuAAAAAA. */ -+{ "vlsr2h", 0x2E637000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vlsr2h 0,limm,u6 00101110011000110111uuuuuu111110. */ -+{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vlsr2h<.cc> 0,limm,u6 00101110111000110111uuuuuu1QQQQQ. */ -+{ "vlsr2h", 0x2EE37020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vlsr2h 0,limm,s12 00101110101000110111ssssssSSSSSS. */ -+{ "vlsr2h", 0x2EA37000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vlsr2h a,limm,limm 00101110001000110111111110AAAAAA. */ -+{ "vlsr2h", 0x2E237F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vlsr2h 0,limm,limm 00101110001000110111111110111110. */ -+{ "vlsr2h", 0x2E237FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vlsr2h<.cc> 0,limm,limm 001011101110001101111111100QQQQQ. */ -+{ "vlsr2h", 0x2EE37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2h a,b,c 00101bbb000111100BBBCCCCCCAAAAAA. */ -+{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2h 0,b,c 00101bbb000111100BBBCCCCCC111110. */ -+{ "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2h<.cc> b,b,c 00101bbb110111100BBBCCCCCC0QQQQQ. */ -+{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2h a,b,u6 00101bbb010111100BBBuuuuuuAAAAAA. */ -+{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2h 0,b,u6 00101bbb010111100BBBuuuuuu111110. */ -+{ "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2h<.cc> b,b,u6 00101bbb110111100BBBuuuuuu1QQQQQ. */ -+{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2h b,b,s12 00101bbb100111100BBBssssssSSSSSS. */ -+{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2h a,limm,c 00101110000111100111CCCCCCAAAAAA. */ -+{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2h a,b,limm 00101bbb000111100BBB111110AAAAAA. */ -+{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2h 0,limm,c 00101110000111100111CCCCCC111110. */ -+{ "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2h 0,b,limm 00101bbb000111100BBB111110111110. */ -+{ "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2h<.cc> b,b,limm 00101bbb110111100BBB1111100QQQQQ. */ -+{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2h<.cc> 0,limm,c 00101110110111100111CCCCCC0QQQQQ. */ -+{ "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2h a,limm,u6 00101110010111100111uuuuuuAAAAAA. */ -+{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2h 0,limm,u6 00101110010111100111uuuuuu111110. */ -+{ "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2h<.cc> 0,limm,u6 00101110110111100111uuuuuu1QQQQQ. */ -+{ "vmac2h", 0x2EDE7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2h 0,limm,s12 00101110100111100111ssssssSSSSSS. */ -+{ "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2h a,limm,limm 00101110000111100111111110AAAAAA. */ -+{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2h 0,limm,limm 00101110000111100111111110111110. */ -+{ "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2h<.cc> 0,limm,limm 001011101101111001111111100QQQQQ. */ -+{ "vmac2h", 0x2EDE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2hf a,b,c 00101bbb000111101BBBCCCCCCAAAAAA. */ -+{ "vmac2hf", 0x281E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hf 0,b,c 00101bbb000111101BBBCCCCCC111110. */ -+{ "vmac2hf", 0x281E803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hf<.cc> b,b,c 00101bbb110111101BBBCCCCCC0QQQQQ. */ -+{ "vmac2hf", 0x28DE8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hf a,b,u6 00101bbb010111101BBBuuuuuuAAAAAA. */ -+{ "vmac2hf", 0x285E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hf 0,b,u6 00101bbb010111101BBBuuuuuu111110. */ -+{ "vmac2hf", 0x285E803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hf<.cc> b,b,u6 00101bbb110111101BBBuuuuuu1QQQQQ. */ -+{ "vmac2hf", 0x28DE8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hf b,b,s12 00101bbb100111101BBBssssssSSSSSS. */ -+{ "vmac2hf", 0x289E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hf a,limm,c 00101110000111101111CCCCCCAAAAAA. */ -+{ "vmac2hf", 0x2E1EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hf a,b,limm 00101bbb000111101BBB111110AAAAAA. */ -+{ "vmac2hf", 0x281E8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hf 0,limm,c 00101110000111101111CCCCCC111110. */ -+{ "vmac2hf", 0x2E1EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hf 0,b,limm 00101bbb000111101BBB111110111110. */ -+{ "vmac2hf", 0x281E8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hf<.cc> b,b,limm 00101bbb110111101BBB1111100QQQQQ. */ -+{ "vmac2hf", 0x28DE8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2hf<.cc> 0,limm,c 00101110110111101111CCCCCC0QQQQQ. */ -+{ "vmac2hf", 0x2EDEF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hf a,limm,u6 00101110010111101111uuuuuuAAAAAA. */ -+{ "vmac2hf", 0x2E5EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hf 0,limm,u6 00101110010111101111uuuuuu111110. */ -+{ "vmac2hf", 0x2E5EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hf<.cc> 0,limm,u6 00101110110111101111uuuuuu1QQQQQ. */ -+{ "vmac2hf", 0x2EDEF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hf 0,limm,s12 00101110100111101111ssssssSSSSSS. */ -+{ "vmac2hf", 0x2E9EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hf a,limm,limm 00101110000111101111111110AAAAAA. */ -+{ "vmac2hf", 0x2E1EFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hf 0,limm,limm 00101110000111101111111110111110. */ -+{ "vmac2hf", 0x2E1EFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hf<.cc> 0,limm,limm 001011101101111011111111100QQQQQ. */ -+{ "vmac2hf", 0x2EDEFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2hfr a,b,c 00101bbb000111111BBBCCCCCCAAAAAA. */ -+{ "vmac2hfr", 0x281F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hfr 0,b,c 00101bbb000111111BBBCCCCCC111110. */ -+{ "vmac2hfr", 0x281F803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hfr<.cc> b,b,c 00101bbb110111111BBBCCCCCC0QQQQQ. */ -+{ "vmac2hfr", 0x28DF8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hfr a,b,u6 00101bbb010111111BBBuuuuuuAAAAAA. */ -+{ "vmac2hfr", 0x285F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hfr 0,b,u6 00101bbb010111111BBBuuuuuu111110. */ -+{ "vmac2hfr", 0x285F803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hfr<.cc> b,b,u6 00101bbb110111111BBBuuuuuu1QQQQQ. */ -+{ "vmac2hfr", 0x28DF8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hfr b,b,s12 00101bbb100111111BBBssssssSSSSSS. */ -+{ "vmac2hfr", 0x289F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hfr a,limm,c 00101110000111111111CCCCCCAAAAAA. */ -+{ "vmac2hfr", 0x2E1FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hfr a,b,limm 00101bbb000111111BBB111110AAAAAA. */ -+{ "vmac2hfr", 0x281F8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hfr 0,limm,c 00101110000111111111CCCCCC111110. */ -+{ "vmac2hfr", 0x2E1FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hfr 0,b,limm 00101bbb000111111BBB111110111110. */ -+{ "vmac2hfr", 0x281F8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hfr<.cc> b,b,limm 00101bbb110111111BBB1111100QQQQQ. */ -+{ "vmac2hfr", 0x28DF8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2hfr<.cc> 0,limm,c 00101110110111111111CCCCCC0QQQQQ. */ -+{ "vmac2hfr", 0x2EDFF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hfr a,limm,u6 00101110010111111111uuuuuuAAAAAA. */ -+{ "vmac2hfr", 0x2E5FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hfr 0,limm,u6 00101110010111111111uuuuuu111110. */ -+{ "vmac2hfr", 0x2E5FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hfr<.cc> 0,limm,u6 00101110110111111111uuuuuu1QQQQQ. */ -+{ "vmac2hfr", 0x2EDFF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hfr 0,limm,s12 00101110100111111111ssssssSSSSSS. */ -+{ "vmac2hfr", 0x2E9FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hfr a,limm,limm 00101110000111111111111110AAAAAA. */ -+{ "vmac2hfr", 0x2E1FFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hfr 0,limm,limm 00101110000111111111111110111110. */ -+{ "vmac2hfr", 0x2E1FFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hfr<.cc> 0,limm,limm 001011101101111111111111100QQQQQ. */ -+{ "vmac2hfr", 0x2EDFFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2hnfr a,b,c 00110bbb000100010BBBCCCCCCAAAAAA. */ -+{ "vmac2hnfr", 0x30110000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hnfr 0,b,c 00110bbb000100010BBBCCCCCC111110. */ -+{ "vmac2hnfr", 0x3011003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hnfr<.cc> b,b,c 00110bbb110100010BBBCCCCCC0QQQQQ. */ -+{ "vmac2hnfr", 0x30D10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hnfr a,b,u6 00110bbb010100010BBBuuuuuuAAAAAA. */ -+{ "vmac2hnfr", 0x30510000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hnfr 0,b,u6 00110bbb010100010BBBuuuuuu111110. */ -+{ "vmac2hnfr", 0x3051003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hnfr<.cc> b,b,u6 00110bbb110100010BBBuuuuuu1QQQQQ. */ -+{ "vmac2hnfr", 0x30D10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hnfr b,b,s12 00110bbb100100010BBBssssssSSSSSS. */ -+{ "vmac2hnfr", 0x30910000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hnfr a,limm,c 00110110000100010111CCCCCCAAAAAA. */ -+{ "vmac2hnfr", 0x36117000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hnfr a,b,limm 00110bbb000100010BBB111110AAAAAA. */ -+{ "vmac2hnfr", 0x30110F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hnfr 0,limm,c 00110110000100010111CCCCCC111110. */ -+{ "vmac2hnfr", 0x3611703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hnfr 0,b,limm 00110bbb000100010BBB111110111110. */ -+{ "vmac2hnfr", 0x30110FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hnfr<.cc> b,b,limm 00110bbb110100010BBB1111100QQQQQ. */ -+{ "vmac2hnfr", 0x30D10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2hnfr<.cc> 0,limm,c 00110110110100010111CCCCCC0QQQQQ. */ -+{ "vmac2hnfr", 0x36D17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hnfr a,limm,u6 00110110010100010111uuuuuuAAAAAA. */ -+{ "vmac2hnfr", 0x36517000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hnfr 0,limm,u6 00110110010100010111uuuuuu111110. */ -+{ "vmac2hnfr", 0x3651703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hnfr<.cc> 0,limm,u6 00110110110100010111uuuuuu1QQQQQ. */ -+{ "vmac2hnfr", 0x36D17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hnfr 0,limm,s12 00110110100100010111ssssssSSSSSS. */ -+{ "vmac2hnfr", 0x36917000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hnfr a,limm,limm 00110110000100010111111110AAAAAA. */ -+{ "vmac2hnfr", 0x36117F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hnfr 0,limm,limm 00110110000100010111111110111110. */ -+{ "vmac2hnfr", 0x36117FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hnfr<.cc> 0,limm,limm 001101101101000101111111100QQQQQ. */ -+{ "vmac2hnfr", 0x36D17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmac2hu a,b,c 00101bbb000111110BBBCCCCCCAAAAAA. */ -+{ "vmac2hu", 0x281F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hu 0,b,c 00101bbb000111110BBBCCCCCC111110. */ -+{ "vmac2hu", 0x281F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hu<.cc> b,b,c 00101bbb110111110BBBCCCCCC0QQQQQ. */ -+{ "vmac2hu", 0x28DF0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hu a,b,u6 00101bbb010111110BBBuuuuuuAAAAAA. */ -+{ "vmac2hu", 0x285F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hu 0,b,u6 00101bbb010111110BBBuuuuuu111110. */ -+{ "vmac2hu", 0x285F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hu<.cc> b,b,u6 00101bbb110111110BBBuuuuuu1QQQQQ. */ -+{ "vmac2hu", 0x28DF0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hu b,b,s12 00101bbb100111110BBBssssssSSSSSS. */ -+{ "vmac2hu", 0x289F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hu a,limm,c 00101110000111110111CCCCCCAAAAAA. */ -+{ "vmac2hu", 0x2E1F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hu a,b,limm 00101bbb000111110BBB111110AAAAAA. */ -+{ "vmac2hu", 0x281F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hu 0,limm,c 00101110000111110111CCCCCC111110. */ -+{ "vmac2hu", 0x2E1F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmac2hu 0,b,limm 00101bbb000111110BBB111110111110. */ -+{ "vmac2hu", 0x281F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmac2hu<.cc> b,b,limm 00101bbb110111110BBB1111100QQQQQ. */ -+{ "vmac2hu", 0x28DF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmac2hu<.cc> 0,limm,c 00101110110111110111CCCCCC0QQQQQ. */ -+{ "vmac2hu", 0x2EDF7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmac2hu a,limm,u6 00101110010111110111uuuuuuAAAAAA. */ -+{ "vmac2hu", 0x2E5F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hu 0,limm,u6 00101110010111110111uuuuuu111110. */ -+{ "vmac2hu", 0x2E5F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmac2hu<.cc> 0,limm,u6 00101110110111110111uuuuuu1QQQQQ. */ -+{ "vmac2hu", 0x2EDF7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmac2hu 0,limm,s12 00101110100111110111ssssssSSSSSS. */ -+{ "vmac2hu", 0x2E9F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmac2hu a,limm,limm 00101110000111110111111110AAAAAA. */ -+{ "vmac2hu", 0x2E1F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hu 0,limm,limm 00101110000111110111111110111110. */ -+{ "vmac2hu", 0x2E1F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmac2hu<.cc> 0,limm,limm 001011101101111101111111100QQQQQ. */ -+{ "vmac2hu", 0x2EDF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmax2h a,b,c 00101bbb001001001BBBCCCCCCAAAAAA. */ -+{ "vmax2h", 0x28248000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmax2h 0,b,c 00101bbb001001001BBBCCCCCC111110. */ -+{ "vmax2h", 0x2824803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmax2h<.cc> b,b,c 00101bbb111001001BBBCCCCCC0QQQQQ. */ -+{ "vmax2h", 0x28E48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmax2h a,b,u6 00101bbb011001001BBBuuuuuuAAAAAA. */ -+{ "vmax2h", 0x28648000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmax2h 0,b,u6 00101bbb011001001BBBuuuuuu111110. */ -+{ "vmax2h", 0x2864803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmax2h<.cc> b,b,u6 00101bbb111001001BBBuuuuuu1QQQQQ. */ -+{ "vmax2h", 0x28E48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmax2h b,b,s12 00101bbb101001001BBBssssssSSSSSS. */ -+{ "vmax2h", 0x28A48000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmax2h a,limm,c 00101110001001001111CCCCCCAAAAAA. */ -+{ "vmax2h", 0x2E24F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmax2h a,b,limm 00101bbb001001001BBB111110AAAAAA. */ -+{ "vmax2h", 0x28248F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmax2h 0,limm,c 00101110011001001111CCCCCC111110. */ -+{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmax2h 0,b,limm 00101bbb001001001BBB111110111110. */ -+{ "vmax2h", 0x28248FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmax2h<.cc> b,b,limm 00101bbb111001001BBB1111100QQQQQ. */ -+{ "vmax2h", 0x28E48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmax2h<.cc> 0,limm,c 00101110111001001111CCCCCC0QQQQQ. */ -+{ "vmax2h", 0x2EE4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmax2h a,limm,u6 00101110011001001111uuuuuuAAAAAA. */ -+{ "vmax2h", 0x2E64F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmax2h 0,limm,u6 00101110011001001111uuuuuu111110. */ -+{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmax2h<.cc> 0,limm,u6 00101110111001001111uuuuuu1QQQQQ. */ -+{ "vmax2h", 0x2EE4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmax2h 0,limm,s12 00101110101001001111ssssssSSSSSS. */ -+{ "vmax2h", 0x2EA4F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmax2h a,limm,limm 00101110001001001111111110AAAAAA. */ -+{ "vmax2h", 0x2E24FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmax2h 0,limm,limm 00101110001001001111111110111110. */ -+{ "vmax2h", 0x2E24FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmax2h<.cc> 0,limm,limm 001011101110010011111111100QQQQQ. */ -+{ "vmax2h", 0x2EE4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmin2h a,b,c 00101bbb001001011BBBCCCCCCAAAAAA. */ -+{ "vmin2h", 0x28258000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmin2h 0,b,c 00101bbb001001011BBBCCCCCC111110. */ -+{ "vmin2h", 0x2825803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmin2h<.cc> b,b,c 00101bbb111001011BBBCCCCCC0QQQQQ. */ -+{ "vmin2h", 0x28E58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmin2h a,b,u6 00101bbb011001011BBBuuuuuuAAAAAA. */ -+{ "vmin2h", 0x28658000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmin2h 0,b,u6 00101bbb011001011BBBuuuuuu111110. */ -+{ "vmin2h", 0x2865803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmin2h<.cc> b,b,u6 00101bbb111001011BBBuuuuuu1QQQQQ. */ -+{ "vmin2h", 0x28E58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmin2h b,b,s12 00101bbb101001011BBBssssssSSSSSS. */ -+{ "vmin2h", 0x28A58000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmin2h a,limm,c 00101110001001011111CCCCCCAAAAAA. */ -+{ "vmin2h", 0x2E25F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmin2h a,b,limm 00101bbb001001011BBB111110AAAAAA. */ -+{ "vmin2h", 0x28258F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmin2h 0,limm,c 00101110011001011111CCCCCC111110. */ -+{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmin2h 0,b,limm 00101bbb001001011BBB111110111110. */ -+{ "vmin2h", 0x28258FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmin2h<.cc> b,b,limm 00101bbb111001011BBB1111100QQQQQ. */ -+{ "vmin2h", 0x28E58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmin2h<.cc> 0,limm,c 00101110111001011111CCCCCC0QQQQQ. */ -+{ "vmin2h", 0x2EE5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmin2h a,limm,u6 00101110011001011111uuuuuuAAAAAA. */ -+{ "vmin2h", 0x2E65F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmin2h 0,limm,u6 00101110011001011111uuuuuu111110. */ -+{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmin2h<.cc> 0,limm,u6 00101110111001011111uuuuuu1QQQQQ. */ -+{ "vmin2h", 0x2EE5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmin2h 0,limm,s12 00101110101001011111ssssssSSSSSS. */ -+{ "vmin2h", 0x2EA5F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmin2h a,limm,limm 00101110001001011111111110AAAAAA. */ -+{ "vmin2h", 0x2E25FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmin2h 0,limm,limm 00101110001001011111111110111110. */ -+{ "vmin2h", 0x2E25FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmin2h<.cc> 0,limm,limm 001011101110010111111111100QQQQQ. */ -+{ "vmin2h", 0x2EE5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */ -+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */ -+{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */ -+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */ -+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */ -+{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */ -+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */ -+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */ -+{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */ -+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */ -+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */ -+{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */ -+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */ -+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */ -+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */ -+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */ -+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */ -+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */ -+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */ -+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */ -+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */ -+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */ -+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */ -+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */ -+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */ -+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */ -+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */ -+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */ -+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */ -+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */ -+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */ -+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */ -+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */ -+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */ -+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */ -+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */ -+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */ -+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */ -+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */ -+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */ -+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hf a,b,c 00101bbb000111001BBBCCCCCCAAAAAA. */ -+{ "vmpy2hf", 0x281C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hf 0,b,c 00101bbb000111001BBBCCCCCC111110. */ -+{ "vmpy2hf", 0x281C803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hf<.cc> b,b,c 00101bbb110111001BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hf", 0x28DC8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hf a,b,u6 00101bbb010111001BBBuuuuuuAAAAAA. */ -+{ "vmpy2hf", 0x285C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hf 0,b,u6 00101bbb010111001BBBuuuuuu111110. */ -+{ "vmpy2hf", 0x285C803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hf<.cc> b,b,u6 00101bbb110111001BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hf", 0x28DC8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hf b,b,s12 00101bbb100111001BBBssssssSSSSSS. */ -+{ "vmpy2hf", 0x289C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hf a,limm,c 00101110000111001111CCCCCCAAAAAA. */ -+{ "vmpy2hf", 0x2E1CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hf a,b,limm 00101bbb000111001BBB111110AAAAAA. */ -+{ "vmpy2hf", 0x281C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hf 0,limm,c 00101110000111001111CCCCCC111110. */ -+{ "vmpy2hf", 0x2E1CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hf 0,b,limm 00101bbb000111001BBB111110111110. */ -+{ "vmpy2hf", 0x281C8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hf<.cc> b,b,limm 00101bbb110111001BBB1111100QQQQQ. */ -+{ "vmpy2hf", 0x28DC8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hf<.cc> 0,limm,c 00101110110111001111CCCCCC0QQQQQ. */ -+{ "vmpy2hf", 0x2EDCF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hf a,limm,u6 00101110010111001111uuuuuuAAAAAA. */ -+{ "vmpy2hf", 0x2E5CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hf 0,limm,u6 00101110010111001111uuuuuu111110. */ -+{ "vmpy2hf", 0x2E5CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hf<.cc> 0,limm,u6 00101110110111001111uuuuuu1QQQQQ. */ -+{ "vmpy2hf", 0x2EDCF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hf 0,limm,s12 00101110100111001111ssssssSSSSSS. */ -+{ "vmpy2hf", 0x2E9CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hf a,limm,limm 00101110000111001111111110AAAAAA. */ -+{ "vmpy2hf", 0x2E1CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hf 0,limm,limm 00101110000111001111111110111110. */ -+{ "vmpy2hf", 0x2E1CFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hf<.cc> 0,limm,limm 001011101101110011111111100QQQQQ. */ -+{ "vmpy2hf", 0x2EDCFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hfr a,b,c 00101bbb000111011BBBCCCCCCAAAAAA. */ -+{ "vmpy2hfr", 0x281D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hfr 0,b,c 00101bbb000111011BBBCCCCCC111110. */ -+{ "vmpy2hfr", 0x281D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hfr<.cc> b,b,c 00101bbb110111011BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hfr", 0x28DD8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hfr a,b,u6 00101bbb010111011BBBuuuuuuAAAAAA. */ -+{ "vmpy2hfr", 0x285D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hfr 0,b,u6 00101bbb010111011BBBuuuuuu111110. */ -+{ "vmpy2hfr", 0x285D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hfr<.cc> b,b,u6 00101bbb110111011BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hfr", 0x28DD8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hfr b,b,s12 00101bbb100111011BBBssssssSSSSSS. */ -+{ "vmpy2hfr", 0x289D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hfr a,limm,c 00101110000111011111CCCCCCAAAAAA. */ -+{ "vmpy2hfr", 0x2E1DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hfr a,b,limm 00101bbb000111011BBB111110AAAAAA. */ -+{ "vmpy2hfr", 0x281D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hfr 0,limm,c 00101110000111011111CCCCCC111110. */ -+{ "vmpy2hfr", 0x2E1DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hfr 0,b,limm 00101bbb000111011BBB111110111110. */ -+{ "vmpy2hfr", 0x281D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hfr<.cc> b,b,limm 00101bbb110111011BBB1111100QQQQQ. */ -+{ "vmpy2hfr", 0x28DD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hfr<.cc> 0,limm,c 00101110110111011111CCCCCC0QQQQQ. */ -+{ "vmpy2hfr", 0x2EDDF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hfr a,limm,u6 00101110010111011111uuuuuuAAAAAA. */ -+{ "vmpy2hfr", 0x2E5DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hfr 0,limm,u6 00101110010111011111uuuuuu111110. */ -+{ "vmpy2hfr", 0x2E5DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hfr<.cc> 0,limm,u6 00101110110111011111uuuuuu1QQQQQ. */ -+{ "vmpy2hfr", 0x2EDDF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hfr 0,limm,s12 00101110100111011111ssssssSSSSSS. */ -+{ "vmpy2hfr", 0x2E9DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hfr a,limm,limm 00101110000111011111111110AAAAAA. */ -+{ "vmpy2hfr", 0x2E1DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hfr 0,limm,limm 00101110000111011111111110111110. */ -+{ "vmpy2hfr", 0x2E1DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hfr<.cc> 0,limm,limm 001011101101110111111111100QQQQQ. */ -+{ "vmpy2hfr", 0x2EDDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */ -+{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */ -+{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */ -+{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */ -+{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */ -+{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */ -+{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */ -+{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */ -+{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */ -+{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */ -+{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */ -+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */ -+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */ -+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */ -+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */ -+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */ -+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */ -+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */ -+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */ -+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */ -+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */ -+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */ -+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */ -+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */ -+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */ -+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */ -+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */ -+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */ -+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */ -+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */ -+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */ -+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmpy2hwf a,b,c 00101bbb001000000BBBCCCCCCAAAAAA. */ -+{ "vmpy2hwf", 0x28200000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hwf 0,b,c 00101bbb001000000BBBCCCCCC111110. */ -+{ "vmpy2hwf", 0x2820003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hwf<.cc> b,b,c 00101bbb111000000BBBCCCCCC0QQQQQ. */ -+{ "vmpy2hwf", 0x28E00000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hwf a,b,u6 00101bbb011000000BBBuuuuuuAAAAAA. */ -+{ "vmpy2hwf", 0x28600000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hwf 0,b,u6 00101bbb011000000BBBuuuuuu111110. */ -+{ "vmpy2hwf", 0x2860003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hwf<.cc> b,b,u6 00101bbb111000000BBBuuuuuu1QQQQQ. */ -+{ "vmpy2hwf", 0x28E00020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hwf b,b,s12 00101bbb101000000BBBssssssSSSSSS. */ -+{ "vmpy2hwf", 0x28A00000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hwf a,limm,c 00101110001000000111CCCCCCAAAAAA. */ -+{ "vmpy2hwf", 0x2E207000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hwf a,b,limm 00101bbb001000000BBB111110AAAAAA. */ -+{ "vmpy2hwf", 0x28200F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hwf 0,limm,c 00101110011000000111CCCCCC111110. */ -+{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmpy2hwf 0,b,limm 00101bbb001000000BBB111110111110. */ -+{ "vmpy2hwf", 0x28200FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmpy2hwf<.cc> b,b,limm 00101bbb111000000BBB1111100QQQQQ. */ -+{ "vmpy2hwf", 0x28E00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmpy2hwf<.cc> 0,limm,c 00101110111000000111CCCCCC0QQQQQ. */ -+{ "vmpy2hwf", 0x2EE07000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmpy2hwf a,limm,u6 00101110011000000111uuuuuuAAAAAA. */ -+{ "vmpy2hwf", 0x2E607000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hwf 0,limm,u6 00101110011000000111uuuuuu111110. */ -+{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmpy2hwf<.cc> 0,limm,u6 00101110111000000111uuuuuu1QQQQQ. */ -+{ "vmpy2hwf", 0x2EE07020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmpy2hwf 0,limm,s12 00101110101000000111ssssssSSSSSS. */ -+{ "vmpy2hwf", 0x2EA07000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmpy2hwf a,limm,limm 00101110001000000111111110AAAAAA. */ -+{ "vmpy2hwf", 0x2E207F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hwf 0,limm,limm 00101110001000000111111110111110. */ -+{ "vmpy2hwf", 0x2E207FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmpy2hwf<.cc> 0,limm,limm 001011101110000001111111100QQQQQ. */ -+{ "vmpy2hwf", 0x2EE07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmsub2hf a,b,c 00110bbb000001000BBBCCCCCCAAAAAA. */ -+{ "vmsub2hf", 0x30040000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hf 0,b,c 00110bbb000001000BBBCCCCCC111110. */ -+{ "vmsub2hf", 0x3004003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hf<.cc> b,b,c 00110bbb110001000BBBCCCCCC0QQQQQ. */ -+{ "vmsub2hf", 0x30C40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hf a,b,u6 00110bbb010001000BBBuuuuuuAAAAAA. */ -+{ "vmsub2hf", 0x30440000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hf 0,b,u6 00110bbb010001000BBBuuuuuu111110. */ -+{ "vmsub2hf", 0x3044003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hf<.cc> b,b,u6 00110bbb110001000BBBuuuuuu1QQQQQ. */ -+{ "vmsub2hf", 0x30C40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hf b,b,s12 00110bbb100001000BBBssssssSSSSSS. */ -+{ "vmsub2hf", 0x30840000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hf a,limm,c 00110110000001000111CCCCCCAAAAAA. */ -+{ "vmsub2hf", 0x36047000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hf a,b,limm 00110bbb000001000BBB111110AAAAAA. */ -+{ "vmsub2hf", 0x30040F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hf 0,limm,c 00110110000001000111CCCCCC111110. */ -+{ "vmsub2hf", 0x3604703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hf 0,b,limm 00110bbb000001000BBB111110111110. */ -+{ "vmsub2hf", 0x30040FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hf<.cc> b,b,limm 00110bbb110001000BBB1111100QQQQQ. */ -+{ "vmsub2hf", 0x30C40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmsub2hf<.cc> 0,limm,c 00110110110001000111CCCCCC0QQQQQ. */ -+{ "vmsub2hf", 0x36C47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hf a,limm,u6 00110110010001000111uuuuuuAAAAAA. */ -+{ "vmsub2hf", 0x36447000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hf 0,limm,u6 00110110010001000111uuuuuu111110. */ -+{ "vmsub2hf", 0x3644703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hf<.cc> 0,limm,u6 00110110110001000111uuuuuu1QQQQQ. */ -+{ "vmsub2hf", 0x36C47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hf 0,limm,s12 00110110100001000111ssssssSSSSSS. */ -+{ "vmsub2hf", 0x36847000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hf a,limm,limm 00110110000001000111111110AAAAAA. */ -+{ "vmsub2hf", 0x36047F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hf 0,limm,limm 00110110000001000111111110111110. */ -+{ "vmsub2hf", 0x36047FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hf<.cc> 0,limm,limm 001101101100010001111111100QQQQQ. */ -+{ "vmsub2hf", 0x36C47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmsub2hfr a,b,c 00110bbb000000110BBBCCCCCCAAAAAA. */ -+{ "vmsub2hfr", 0x30030000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hfr 0,b,c 00110bbb000000110BBBCCCCCC111110. */ -+{ "vmsub2hfr", 0x3003003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hfr<.cc> b,b,c 00110bbb110000110BBBCCCCCC0QQQQQ. */ -+{ "vmsub2hfr", 0x30C30000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hfr a,b,u6 00110bbb010000110BBBuuuuuuAAAAAA. */ -+{ "vmsub2hfr", 0x30430000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hfr 0,b,u6 00110bbb010000110BBBuuuuuu111110. */ -+{ "vmsub2hfr", 0x3043003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hfr<.cc> b,b,u6 00110bbb110000110BBBuuuuuu1QQQQQ. */ -+{ "vmsub2hfr", 0x30C30020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hfr b,b,s12 00110bbb100000110BBBssssssSSSSSS. */ -+{ "vmsub2hfr", 0x30830000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hfr a,limm,c 00110110000000110111CCCCCCAAAAAA. */ -+{ "vmsub2hfr", 0x36037000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hfr a,b,limm 00110bbb000000110BBB111110AAAAAA. */ -+{ "vmsub2hfr", 0x30030F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hfr 0,limm,c 00110110000000110111CCCCCC111110. */ -+{ "vmsub2hfr", 0x3603703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hfr 0,b,limm 00110bbb000000110BBB111110111110. */ -+{ "vmsub2hfr", 0x30030FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hfr<.cc> b,b,limm 00110bbb110000110BBB1111100QQQQQ. */ -+{ "vmsub2hfr", 0x30C30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmsub2hfr<.cc> 0,limm,c 00110110110000110111CCCCCC0QQQQQ. */ -+{ "vmsub2hfr", 0x36C37000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hfr a,limm,u6 00110110010000110111uuuuuuAAAAAA. */ -+{ "vmsub2hfr", 0x36437000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hfr 0,limm,u6 00110110010000110111uuuuuu111110. */ -+{ "vmsub2hfr", 0x3643703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hfr<.cc> 0,limm,u6 00110110110000110111uuuuuu1QQQQQ. */ -+{ "vmsub2hfr", 0x36C37020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hfr 0,limm,s12 00110110100000110111ssssssSSSSSS. */ -+{ "vmsub2hfr", 0x36837000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hfr a,limm,limm 00110110000000110111111110AAAAAA. */ -+{ "vmsub2hfr", 0x36037F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hfr 0,limm,limm 00110110000000110111111110111110. */ -+{ "vmsub2hfr", 0x36037FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hfr<.cc> 0,limm,limm 001101101100001101111111100QQQQQ. */ -+{ "vmsub2hfr", 0x36C37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vmsub2hnfr a,b,c 00110bbb000100011BBBCCCCCCAAAAAA. */ -+{ "vmsub2hnfr", 0x30118000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hnfr 0,b,c 00110bbb000100011BBBCCCCCC111110. */ -+{ "vmsub2hnfr", 0x3011803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> b,b,c 00110bbb110100011BBBCCCCCC0QQQQQ. */ -+{ "vmsub2hnfr", 0x30D18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hnfr a,b,u6 00110bbb010100011BBBuuuuuuAAAAAA. */ -+{ "vmsub2hnfr", 0x30518000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hnfr 0,b,u6 00110bbb010100011BBBuuuuuu111110. */ -+{ "vmsub2hnfr", 0x3051803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> b,b,u6 00110bbb110100011BBBuuuuuu1QQQQQ. */ -+{ "vmsub2hnfr", 0x30D18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hnfr b,b,s12 00110bbb100100011BBBssssssSSSSSS. */ -+{ "vmsub2hnfr", 0x30918000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hnfr a,limm,c 00110110000100011111CCCCCCAAAAAA. */ -+{ "vmsub2hnfr", 0x3611F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hnfr a,b,limm 00110bbb000100011BBB111110AAAAAA. */ -+{ "vmsub2hnfr", 0x30118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hnfr 0,limm,c 00110110000100011111CCCCCC111110. */ -+{ "vmsub2hnfr", 0x3611F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vmsub2hnfr 0,b,limm 00110bbb000100011BBB111110111110. */ -+{ "vmsub2hnfr", 0x30118FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> b,b,limm 00110bbb110100011BBB1111100QQQQQ. */ -+{ "vmsub2hnfr", 0x30D18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vmsub2hnfr<.cc> 0,limm,c 00110110110100011111CCCCCC0QQQQQ. */ -+{ "vmsub2hnfr", 0x36D1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vmsub2hnfr a,limm,u6 00110110010100011111uuuuuuAAAAAA. */ -+{ "vmsub2hnfr", 0x3651F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hnfr 0,limm,u6 00110110010100011111uuuuuu111110. */ -+{ "vmsub2hnfr", 0x3651F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> 0,limm,u6 00110110110100011111uuuuuu1QQQQQ. */ -+{ "vmsub2hnfr", 0x36D1F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vmsub2hnfr 0,limm,s12 00110110100100011111ssssssSSSSSS. */ -+{ "vmsub2hnfr", 0x3691F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vmsub2hnfr a,limm,limm 00110110000100011111111110AAAAAA. */ -+{ "vmsub2hnfr", 0x3611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hnfr 0,limm,limm 00110110000100011111111110111110. */ -+{ "vmsub2hnfr", 0x3611FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vmsub2hnfr<.cc> 0,limm,limm 001101101101000111111111100QQQQQ. */ -+{ "vmsub2hnfr", 0x36D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vneg2h b,c 00101bbb001011110BBBCCCCCC101010. */ -+{ "vneg2h", 0x282F002A, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vneg2h 0,c 00101110001011110111CCCCCC101010. */ -+{ "vneg2h", 0x2E2F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vneg2h b,u6 00101bbb011011110BBBuuuuuu101010. */ -+{ "vneg2h", 0x286F002A, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vneg2h 0,u6 00101110011011110111uuuuuu101010. */ -+{ "vneg2h", 0x2E6F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vneg2h b,limm 00101bbb001011110BBB111110101010. */ -+{ "vneg2h", 0x282F0FAA, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vneg2h 0,limm 00101110001011110111111110101010. */ -+{ "vneg2h", 0x2E2F7FAA, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vnegs2h b,c 00101bbb001011110BBBCCCCCC101011. */ -+{ "vnegs2h", 0x282F002B, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vnegs2h 0,c 00101110001011110111CCCCCC101011. */ -+{ "vnegs2h", 0x2E2F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vnegs2h b,u6 00101bbb011011110BBBuuuuuu101011. */ -+{ "vnegs2h", 0x286F002B, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vnegs2h 0,u6 00101110011011110111uuuuuu101011. */ -+{ "vnegs2h", 0x2E6F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vnegs2h b,limm 00101bbb001011110BBB111110101011. */ -+{ "vnegs2h", 0x282F0FAB, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vnegs2h 0,limm 00101110001011110111111110101011. */ -+{ "vnegs2h", 0x2E2F7FAB, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vnorm2h b,c 00101bbb001011110BBBCCCCCC101100. */ -+{ "vnorm2h", 0x282F002C, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vnorm2h 0,c 00101110001011110111CCCCCC101100. */ -+{ "vnorm2h", 0x2E2F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vnorm2h b,u6 00101bbb011011110BBBuuuuuu101100. */ -+{ "vnorm2h", 0x286F002C, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vnorm2h 0,u6 00101110011011110111uuuuuu101100. */ -+{ "vnorm2h", 0x2E6F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vnorm2h b,limm 00101bbb001011110BBB111110101100. */ -+{ "vnorm2h", 0x282F0FAC, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vnorm2h 0,limm 00101110001011110111111110101100. */ -+{ "vnorm2h", 0x2E2F7FAC, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbl b,c 00101bbb001011110BBBCCCCCC011100 */ -+{ "vpack2hbl", 0x282F001C, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbl 0,c 00101110001011110111CCCCCC011100 */ -+{ "vpack2hbl", 0x2E2F701C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbl 0,u6 00101110011011110111uuuuuu011100 */ -+{ "vpack2hbl", 0x2E6F701C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbl b,u6 00101bbb011011110BBBuuuuuu011100 */ -+{ "vpack2hbl", 0x286F001C, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbl 0,limm 00101110001011110111111110011100 */ -+{ "vpack2hbl", 0x2E2F7F9C, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbl b,limm 00101bbb001011110BBB111110011100 */ -+{ "vpack2hbl", 0x282F0F9C, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hblf b,c 00101bbb001011110BBBCCCCCC011110 */ -+{ "vpack2hblf", 0x282F001E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hblf 0,c 00101110001011110111CCCCCC011110 */ -+{ "vpack2hblf", 0x2E2F701E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hblf 0,u6 00101110011011110111uuuuuu011110 */ -+{ "vpack2hblf", 0x2E6F701E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hblf b,u6 00101bbb011011110BBBuuuuuu011110 */ -+{ "vpack2hblf", 0x286F001E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hblf b,limm 00101bbb001011110BBB111110011110 */ -+{ "vpack2hblf", 0x282F0F9E, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hblf 0,limm 00101110001011110111111110011110 */ -+{ "vpack2hblf", 0x2E2F7F9E, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbm b,c 00101bbb001011110BBBCCCCCC011101 */ -+{ "vpack2hbm", 0x282F001D, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbm 0,c 00101110001011110111CCCCCC011101 */ -+{ "vpack2hbm", 0x2E2F701D, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbm b,u6 00101bbb011011110BBBuuuuuu011101 */ -+{ "vpack2hbm", 0x286F001D, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbm 0,u6 00101110011011110111uuuuuu011101 */ -+{ "vpack2hbm", 0x2E6F701D, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbm 0,limm 00101110001011110111111110011101 */ -+{ "vpack2hbm", 0x2E2F7F9D, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbm b,limm 00101bbb001011110BBB111110011101 */ -+{ "vpack2hbm", 0x282F0F9D, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbmf 0,c 00101110001011110111CCCCCC011111 */ -+{ "vpack2hbmf", 0x2E2F701F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbmf b,c 00101bbb001011110BBBCCCCCC011111 */ -+{ "vpack2hbmf", 0x282F001F, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hbmf b,u6 00101bbb011011110BBBuuuuuu011111 */ -+{ "vpack2hbmf", 0x286F001F, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbmf 0,u6 00101110011011110111uuuuuu011111 */ -+{ "vpack2hbmf", 0x2E6F701F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hbmf 0,limm 00101110001011110111111110011111 */ -+{ "vpack2hbmf", 0x2E2F7F9F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hbmf b,limm 00101bbb001011110BBB111110011111 */ -+{ "vpack2hbmf", 0x282F0F9F, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hl 0,b,c 00101bbb001010010BBBCCCCCC111110 */ -+{ "vpack2hl", 0x2829003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hl a,b,c 00101bbb001010010BBBCCCCCCAAAAAA */ -+{ "vpack2hl", 0x28290000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hl<.cc> b,b,c 00101bbb111010010BBBCCCCCC0QQQQQ */ -+{ "vpack2hl", 0x28E90000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vpack2hl<.cc> b,b,u6 00101bbb111010010BBBuuuuuu1QQQQQ */ -+{ "vpack2hl", 0x28E90020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vpack2hl a,b,u6 00101bbb011010010BBBuuuuuuAAAAAA */ -+{ "vpack2hl", 0x28690000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hl 0,b,u6 00101bbb011010010BBBuuuuuu111110 */ -+{ "vpack2hl", 0x2869003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hl b,b,s12 00101bbb101010010BBBssssssSSSSSS */ -+{ "vpack2hl", 0x28A90000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vpack2hl<.cc> 0,limm,c 00101110111010010111CCCCCC0QQQQQ */ -+{ "vpack2hl", 0x2EE97000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vpack2hl 0,limm,c 00101110011010010111CCCCCC111110 */ -+{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hl a,b,limm 00101bbb001010010BBB111110AAAAAA */ -+{ "vpack2hl", 0x28290F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hl a,limm,c 00101110001010010111CCCCCCAAAAAA */ -+{ "vpack2hl", 0x2E297000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hl 0,b,limm 00101bbb001010010BBB111110111110 */ -+{ "vpack2hl", 0x28290FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hl<.cc> b,b,limm 00101bbb111010010BBB1111100QQQQQ */ -+{ "vpack2hl", 0x28E90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vpack2hl a,limm,u6 00101110011010010111uuuuuuAAAAAA */ -+{ "vpack2hl", 0x2E697000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hl 0,limm,u6 00101110011010010111uuuuuu111110 */ -+{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hl<.cc> 0,limm,u6 00101110111010010111uuuuuu1QQQQQ */ -+{ "vpack2hl", 0x2EE97020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vpack2hl 0,limm,s12 00101110101010010111ssssssSSSSSS */ -+{ "vpack2hl", 0x2EA97000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vpack2hl<.cc> 0,limm,limm 001011101110100101111111100QQQQQ */ -+{ "vpack2hl", 0x2EE97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vpack2hl a,limm,limm 00101110001010010111111110AAAAAA */ -+{ "vpack2hl", 0x2E297F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vpack2hl 0,limm,limm 00101110001010010111111110111110 */ -+{ "vpack2hl", 0x2E297FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vpack2hm a,b,c 00101bbb001010011BBBCCCCCCAAAAAA */ -+{ "vpack2hm", 0x28298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hm<.cc> b,b,c 00101bbb111010011BBBCCCCCC0QQQQQ */ -+{ "vpack2hm", 0x28E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vpack2hm 0,b,c 00101bbb001010011BBBCCCCCC111110 */ -+{ "vpack2hm", 0x2829803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hm a,b,u6 00101bbb011010011BBBuuuuuuAAAAAA */ -+{ "vpack2hm", 0x28698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hm 0,b,u6 00101bbb011010011BBBuuuuuu111110 */ -+{ "vpack2hm", 0x2869803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hm<.cc> b,b,u6 00101bbb111010011BBBuuuuuu1QQQQQ */ -+{ "vpack2hm", 0x28E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vpack2hm b,b,s12 00101bbb101010011BBBssssssSSSSSS */ -+{ "vpack2hm", 0x28A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vpack2hm a,b,limm 00101bbb001010011BBB111110AAAAAA */ -+{ "vpack2hm", 0x28298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hm 0,b,limm 00101bbb001010011BBB111110111110 */ -+{ "vpack2hm", 0x28298FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vpack2hm<.cc> 0,limm,c 00101110111010011111CCCCCC0QQQQQ */ -+{ "vpack2hm", 0x2EE9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vpack2hm<.cc> b,b,limm 00101bbb111010011BBB1111100QQQQQ */ -+{ "vpack2hm", 0x28E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vpack2hm a,limm,c 00101110001010011111CCCCCCAAAAAA */ -+{ "vpack2hm", 0x2E29F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hm 0,limm,c 00101110011010011111CCCCCC111110 */ -+{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vpack2hm a,limm,u6 00101110011010011111uuuuuuAAAAAA */ -+{ "vpack2hm", 0x2E69F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hm 0,limm,u6 00101110011010011111uuuuuu111110 */ -+{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vpack2hm<.cc> 0,limm,u6 00101110111010011111uuuuuu1QQQQQ */ -+{ "vpack2hm", 0x2EE9F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vpack2hm 0,limm,s12 00101110101010011111ssssssSSSSSS */ -+{ "vpack2hm", 0x2EA9F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vpack2hm a,limm,limm 00101110001010011111111110AAAAAA */ -+{ "vpack2hm", 0x2E29FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vpack2hm 0,limm,limm 00101110001010011111111110111110 */ -+{ "vpack2hm", 0x2E29FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vpack2hm<.cc> 0,limm,limm 001011101110100111111111100QQQQQ */ -+{ "vpack2hm", 0x2EE9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vperm 0,b,c 00101bbb001011100BBBCCCCCC111110 */ -+{ "vperm", 0x282E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vperm a,b,c 00101bbb001011100BBBCCCCCCAAAAAA */ -+{ "vperm", 0x282E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vperm<.cc> b,b,c 00101bbb111011100BBBCCCCCC0QQQQQ */ -+{ "vperm", 0x28EE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vperm 0,b,u6 00101bbb011011100BBBuuuuuu111110 */ -+{ "vperm", 0x286E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vperm<.cc> b,b,u6 00101bbb111011100BBBuuuuuu1QQQQQ */ -+{ "vperm", 0x28EE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vperm a,b,u6 00101bbb011011100BBBuuuuuuAAAAAA */ -+{ "vperm", 0x286E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vperm b,b,s12 00101bbb101011100BBBssssssSSSSSS */ -+{ "vperm", 0x28AE0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vperm a,b,limm 00101bbb001011100BBB111110AAAAAA */ -+{ "vperm", 0x282E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vperm<.cc> b,b,limm 00101bbb111011100BBB1111100QQQQQ */ -+{ "vperm", 0x28EE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vperm<.cc> 0,limm,c 00101110111011100111CCCCCC0QQQQQ */ -+{ "vperm", 0x2EEE7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vperm a,limm,c 00101110001011100111CCCCCCAAAAAA */ -+{ "vperm", 0x2E2E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vperm 0,b,limm 00101bbb001011100BBB111110111110 */ -+{ "vperm", 0x282E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vperm 0,limm,c 00101110011011100111CCCCCC111110 */ -+{ "vperm", 0x2E6E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vperm<.cc> 0,limm,u6 00101110111011100111uuuuuu1QQQQQ */ -+{ "vperm", 0x2EEE7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vperm 0,limm,u6 00101110011011100111uuuuuu111110 */ -+{ "vperm", 0x2E6E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vperm a,limm,u6 00101110011011100111uuuuuuAAAAAA */ -+{ "vperm", 0x2E6E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vperm 0,limm,s12 00101110101011100111ssssssSSSSSS */ -+{ "vperm", 0x2EAE7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vperm a,limm,limm 00101110001011100111111110AAAAAA */ -+{ "vperm", 0x2E2E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vperm 0,limm,limm 00101110001011100111111110111110 */ -+{ "vperm", 0x2E2E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vperm<.cc> 0,limm,limm 001011101110111001111111100QQQQQ */ -+{ "vperm", 0x2EEE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vrep2hl b,c 00101bbb001011110BBBCCCCCC100010. */ -+{ "vrep2hl", 0x282F0022, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vrep2hl 0,c 00101110001011110111CCCCCC100010. */ -+{ "vrep2hl", 0x2E2F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vrep2hl b,u6 00101bbb011011110BBBuuuuuu100010. */ -+{ "vrep2hl", 0x286F0022, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vrep2hl 0,u6 00101110011011110111uuuuuu100010. */ -+{ "vrep2hl", 0x2E6F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vrep2hl b,limm 00101bbb001011110BBB111110100010. */ -+{ "vrep2hl", 0x282F0FA2, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vrep2hl 0,limm 00101110001011110111111110100010. */ -+{ "vrep2hl", 0x2E2F7FA2, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vrep2hm b,c 00101bbb001011110BBBCCCCCC100011. */ -+{ "vrep2hm", 0x282F0023, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vrep2hm 0,c 00101110001011110111CCCCCC100011. */ -+{ "vrep2hm", 0x2E2F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vrep2hm b,u6 00101bbb011011110BBBuuuuuu100011. */ -+{ "vrep2hm", 0x286F0023, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vrep2hm 0,u6 00101110011011110111uuuuuu100011. */ -+{ "vrep2hm", 0x2E6F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vrep2hm b,limm 00101bbb001011110BBB111110100011. */ -+{ "vrep2hm", 0x282F0FA3, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vrep2hm 0,limm 00101110001011110111111110100011. */ -+{ "vrep2hm", 0x2E2F7FA3, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vsext2bhl b,c 00101bbb001011110BBBCCCCCC100110. */ -+{ "vsext2bhl", 0x282F0026, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vsext2bhl 0,c 00101110001011110111CCCCCC100110. */ -+{ "vsext2bhl", 0x2E2F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vsext2bhl b,u6 00101bbb011011110BBBuuuuuu100110. */ -+{ "vsext2bhl", 0x286F0026, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsext2bhl 0,u6 00101110011011110111uuuuuu100110. */ -+{ "vsext2bhl", 0x2E6F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsext2bhl b,limm 00101bbb001011110BBB111110100110. */ -+{ "vsext2bhl", 0x282F0FA6, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vsext2bhl 0,limm 00101110001011110111111110100110. */ -+{ "vsext2bhl", 0x2E2F7FA6, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vsext2bhm b,c 00101bbb001011110BBBCCCCCC100111. */ -+{ "vsext2bhm", 0x282F0027, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, -+ -+/* vsext2bhm 0,c 00101110001011110111CCCCCC100111. */ -+{ "vsext2bhm", 0x2E2F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, -+ -+/* vsext2bhm b,u6 00101bbb011011110BBBuuuuuu100111. */ -+{ "vsext2bhm", 0x286F0027, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsext2bhm 0,u6 00101110011011110111uuuuuu100111. */ -+{ "vsext2bhm", 0x2E6F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsext2bhm b,limm 00101bbb001011110BBB111110100111. */ -+{ "vsext2bhm", 0x282F0FA7, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, -+ -+/* vsext2bhm 0,limm 00101110001011110111111110100111. */ -+{ "vsext2bhm", 0x2E2F7FA7, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA. */ -+{ "vsub2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub2 0,b,c 00101bbb001111010BBBCCCCCC111110. */ -+{ "vsub2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ. */ -+{ "vsub2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsub2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA. */ -+{ "vsub2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2 0,b,u6 00101bbb011111010BBBuuuuuu111110. */ -+{ "vsub2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ. */ -+{ "vsub2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub2 b,b,s12 00101bbb101111010BBBssssssSSSSSS. */ -+{ "vsub2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub2 a,limm,c 00101110001111010111CCCCCCAAAAAA. */ -+{ "vsub2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub2 a,b,limm 00101bbb001111010BBB111110AAAAAA. */ -+{ "vsub2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2 0,limm,c 00101110001111010111CCCCCC111110. */ -+{ "vsub2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub2 0,b,limm 00101bbb001111010BBB111110111110. */ -+{ "vsub2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ. */ -+{ "vsub2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsub2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ. */ -+{ "vsub2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsub2 a,limm,u6 00101110011111010111uuuuuuAAAAAA. */ -+{ "vsub2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2 0,limm,u6 00101110011111010111uuuuuu111110. */ -+{ "vsub2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ. */ -+{ "vsub2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub2 0,limm,s12 00101110101111010111ssssssSSSSSS. */ -+{ "vsub2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub2 a,limm,limm 00101110001111010111111110AAAAAA. */ -+{ "vsub2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub2 0,limm,limm 00101110001111010111111110111110. */ -+{ "vsub2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ. */ -+{ "vsub2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsub2h a,b,c 00101bbb000101010BBBCCCCCCAAAAAA. */ -+{ "vsub2h", 0x28150000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub2h 0,b,c 00101bbb000101010BBBCCCCCC111110. */ -+{ "vsub2h", 0x2815003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub2h<.cc> b,b,c 00101bbb110101010BBBCCCCCC0QQQQQ. */ -+{ "vsub2h", 0x28D50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsub2h a,b,u6 00101bbb010101010BBBuuuuuuAAAAAA. */ -+{ "vsub2h", 0x28550000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2h 0,b,u6 00101bbb010101010BBBuuuuuu111110. */ -+{ "vsub2h", 0x2855003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2h<.cc> b,b,u6 00101bbb110101010BBBuuuuuu1QQQQQ. */ -+{ "vsub2h", 0x28D50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub2h b,b,s12 00101bbb100101010BBBssssssSSSSSS. */ -+{ "vsub2h", 0x28950000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub2h a,limm,c 00101110000101010111CCCCCCAAAAAA. */ -+{ "vsub2h", 0x2E157000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub2h a,b,limm 00101bbb000101010BBB111110AAAAAA. */ -+{ "vsub2h", 0x28150F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2h 0,limm,c 00101110000101010111CCCCCC111110. */ -+{ "vsub2h", 0x2E15703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub2h 0,b,limm 00101bbb000101010BBB111110111110. */ -+{ "vsub2h", 0x28150FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub2h<.cc> b,b,limm 00101bbb110101010BBB1111100QQQQQ. */ -+{ "vsub2h", 0x28D50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsub2h<.cc> 0,limm,c 00101110110101010111CCCCCC0QQQQQ. */ -+{ "vsub2h", 0x2ED57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsub2h a,limm,u6 00101110010101010111uuuuuuAAAAAA. */ -+{ "vsub2h", 0x2E557000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2h 0,limm,u6 00101110010101010111uuuuuu111110. */ -+{ "vsub2h", 0x2E55703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub2h<.cc> 0,limm,u6 00101110110101010111uuuuuu1QQQQQ. */ -+{ "vsub2h", 0x2ED57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub2h 0,limm,s12 00101110100101010111ssssssSSSSSS. */ -+{ "vsub2h", 0x2E957000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub2h a,limm,limm 00101110000101010111111110AAAAAA. */ -+{ "vsub2h", 0x2E157F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub2h 0,limm,limm 00101110000101010111111110111110. */ -+{ "vsub2h", 0x2E157FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub2h<.cc> 0,limm,limm 001011101101010101111111100QQQQQ. */ -+{ "vsub2h", 0x2ED57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsub4b a,b,c 00101bbb001001010BBBCCCCCCAAAAAA. */ -+{ "vsub4b", 0x28250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub4b 0,b,c 00101bbb001001010BBBCCCCCC111110. */ -+{ "vsub4b", 0x2825003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub4b<.cc> b,b,c 00101bbb111001010BBBCCCCCC0QQQQQ. */ -+{ "vsub4b", 0x28E50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsub4b a,b,u6 00101bbb011001010BBBuuuuuuAAAAAA. */ -+{ "vsub4b", 0x28650000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4b 0,b,u6 00101bbb011001010BBBuuuuuu111110. */ -+{ "vsub4b", 0x2865003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4b<.cc> b,b,u6 00101bbb111001010BBBuuuuuu1QQQQQ. */ -+{ "vsub4b", 0x28E50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub4b b,b,s12 00101bbb101001010BBBssssssSSSSSS. */ -+{ "vsub4b", 0x28A50000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub4b a,limm,c 00101110001001010111CCCCCCAAAAAA. */ -+{ "vsub4b", 0x2E257000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub4b a,b,limm 00101bbb001001010BBB111110AAAAAA. */ -+{ "vsub4b", 0x28250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub4b 0,limm,c 00101110011001010111CCCCCC111110. */ -+{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub4b 0,b,limm 00101bbb001001010BBB111110111110. */ -+{ "vsub4b", 0x28250FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub4b<.cc> b,b,limm 00101bbb111001010BBB1111100QQQQQ. */ -+{ "vsub4b", 0x28E50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsub4b<.cc> 0,limm,c 00101110111001010111CCCCCC0QQQQQ. */ -+{ "vsub4b", 0x2EE57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsub4b a,limm,u6 00101110011001010111uuuuuuAAAAAA. */ -+{ "vsub4b", 0x2E657000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4b 0,limm,u6 00101110011001010111uuuuuu111110. */ -+{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4b<.cc> 0,limm,u6 00101110111001010111uuuuuu1QQQQQ. */ -+{ "vsub4b", 0x2EE57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub4b 0,limm,s12 00101110101001010111ssssssSSSSSS. */ -+{ "vsub4b", 0x2EA57000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub4b a,limm,limm 00101110001001010111111110AAAAAA. */ -+{ "vsub4b", 0x2E257F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub4b 0,limm,limm 00101110001001010111111110111110. */ -+{ "vsub4b", 0x2E257FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub4b<.cc> 0,limm,limm 001011101110010101111111100QQQQQ. */ -+{ "vsub4b", 0x2EE57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsub4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA. */ -+{ "vsub4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub4h 0,b,c 00101bbb001110010BBBCCCCCC111110. */ -+{ "vsub4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsub4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ. */ -+{ "vsub4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsub4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA. */ -+{ "vsub4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4h 0,b,u6 00101bbb011110010BBBuuuuuu111110. */ -+{ "vsub4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ. */ -+{ "vsub4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub4h b,b,s12 00101bbb101110010BBBssssssSSSSSS. */ -+{ "vsub4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub4h a,limm,c 00101110001110010111CCCCCCAAAAAA. */ -+{ "vsub4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub4h a,b,limm 00101bbb001110010BBB111110AAAAAA. */ -+{ "vsub4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub4h 0,limm,c 00101110001110010111CCCCCC111110. */ -+{ "vsub4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsub4h 0,b,limm 00101bbb001110010BBB111110111110. */ -+{ "vsub4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsub4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ. */ -+{ "vsub4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsub4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ. */ -+{ "vsub4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsub4h a,limm,u6 00101110011110010111uuuuuuAAAAAA. */ -+{ "vsub4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4h 0,limm,u6 00101110011110010111uuuuuu111110. */ -+{ "vsub4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsub4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ. */ -+{ "vsub4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsub4h 0,limm,s12 00101110101110010111ssssssSSSSSS. */ -+{ "vsub4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsub4h a,limm,limm 00101110001110010111111110AAAAAA. */ -+{ "vsub4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub4h 0,limm,limm 00101110001110010111111110111110. */ -+{ "vsub4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsub4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ. */ -+{ "vsub4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadd a,b,c 00101bbb001111110BBBCCCCCCAAAAAA. */ -+{ "vsubadd", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd 0,b,c 00101bbb001111110BBBCCCCCC111110. */ -+{ "vsubadd", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ. */ -+{ "vsubadd", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA. */ -+{ "vsubadd", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd 0,b,u6 00101bbb011111110BBBuuuuuu111110. */ -+{ "vsubadd", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ. */ -+{ "vsubadd", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd b,b,s12 00101bbb101111110BBBssssssSSSSSS. */ -+{ "vsubadd", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd a,limm,c 00101110001111110111CCCCCCAAAAAA. */ -+{ "vsubadd", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd a,b,limm 00101bbb001111110BBB111110AAAAAA. */ -+{ "vsubadd", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd 0,limm,c 00101110001111110111CCCCCC111110. */ -+{ "vsubadd", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd 0,b,limm 00101bbb001111110BBB111110111110. */ -+{ "vsubadd", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ. */ -+{ "vsubadd", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadd<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ. */ -+{ "vsubadd", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd a,limm,u6 00101110011111110111uuuuuuAAAAAA. */ -+{ "vsubadd", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd 0,limm,u6 00101110011111110111uuuuuu111110. */ -+{ "vsubadd", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ. */ -+{ "vsubadd", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd 0,limm,s12 00101110101111110111ssssssSSSSSS. */ -+{ "vsubadd", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd a,limm,limm 00101110001111110111111110AAAAAA. */ -+{ "vsubadd", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd 0,limm,limm 00101110001111110111111110111110. */ -+{ "vsubadd", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd<.cc> 0,limm,limm 001011101111111101111111100QQQQQ. */ -+{ "vsubadd", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadd2h a,b,c 00101bbb000101110BBBCCCCCCAAAAAA. */ -+{ "vsubadd2h", 0x28170000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd2h 0,b,c 00101bbb000101110BBBCCCCCC111110. */ -+{ "vsubadd2h", 0x2817003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd2h<.cc> b,b,c 00101bbb110101110BBBCCCCCC0QQQQQ. */ -+{ "vsubadd2h", 0x28D70000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd2h a,b,u6 00101bbb010101110BBBuuuuuuAAAAAA. */ -+{ "vsubadd2h", 0x28570000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd2h 0,b,u6 00101bbb010101110BBBuuuuuu111110. */ -+{ "vsubadd2h", 0x2857003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd2h<.cc> b,b,u6 00101bbb110101110BBBuuuuuu1QQQQQ. */ -+{ "vsubadd2h", 0x28D70020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd2h b,b,s12 00101bbb100101110BBBssssssSSSSSS. */ -+{ "vsubadd2h", 0x28970000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd2h a,limm,c 00101110000101110111CCCCCCAAAAAA. */ -+{ "vsubadd2h", 0x2E177000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd2h a,b,limm 00101bbb000101110BBB111110AAAAAA. */ -+{ "vsubadd2h", 0x28170F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd2h 0,limm,c 00101110000101110111CCCCCC111110. */ -+{ "vsubadd2h", 0x2E17703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd2h 0,b,limm 00101bbb000101110BBB111110111110. */ -+{ "vsubadd2h", 0x28170FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd2h<.cc> b,b,limm 00101bbb110101110BBB1111100QQQQQ. */ -+{ "vsubadd2h", 0x28D70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadd2h<.cc> 0,limm,c 00101110110101110111CCCCCC0QQQQQ. */ -+{ "vsubadd2h", 0x2ED77000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd2h a,limm,u6 00101110010101110111uuuuuuAAAAAA. */ -+{ "vsubadd2h", 0x2E577000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd2h 0,limm,u6 00101110010101110111uuuuuu111110. */ -+{ "vsubadd2h", 0x2E57703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd2h<.cc> 0,limm,u6 00101110110101110111uuuuuu1QQQQQ. */ -+{ "vsubadd2h", 0x2ED77020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd2h 0,limm,s12 00101110100101110111ssssssSSSSSS. */ -+{ "vsubadd2h", 0x2E977000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd2h a,limm,limm 00101110000101110111111110AAAAAA. */ -+{ "vsubadd2h", 0x2E177F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd2h 0,limm,limm 00101110000101110111111110111110. */ -+{ "vsubadd2h", 0x2E177FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd2h<.cc> 0,limm,limm 001011101101011101111111100QQQQQ. */ -+{ "vsubadd2h", 0x2ED77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadd4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA. */ -+{ "vsubadd4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd4h 0,b,c 00101bbb001110110BBBCCCCCC111110. */ -+{ "vsubadd4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ. */ -+{ "vsubadd4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA. */ -+{ "vsubadd4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd4h 0,b,u6 00101bbb011110110BBBuuuuuu111110. */ -+{ "vsubadd4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ. */ -+{ "vsubadd4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd4h b,b,s12 00101bbb101110110BBBssssssSSSSSS. */ -+{ "vsubadd4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd4h a,limm,c 00101110001110110111CCCCCCAAAAAA. */ -+{ "vsubadd4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd4h a,b,limm 00101bbb001110110BBB111110AAAAAA. */ -+{ "vsubadd4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd4h 0,limm,c 00101110001110110111CCCCCC111110. */ -+{ "vsubadd4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadd4h 0,b,limm 00101bbb001110110BBB111110111110. */ -+{ "vsubadd4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadd4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ. */ -+{ "vsubadd4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadd4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ. */ -+{ "vsubadd4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadd4h a,limm,u6 00101110011110110111uuuuuuAAAAAA. */ -+{ "vsubadd4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd4h 0,limm,u6 00101110011110110111uuuuuu111110. */ -+{ "vsubadd4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadd4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ. */ -+{ "vsubadd4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadd4h 0,limm,s12 00101110101110110111ssssssSSSSSS. */ -+{ "vsubadd4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadd4h a,limm,limm 00101110001110110111111110AAAAAA. */ -+{ "vsubadd4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd4h 0,limm,limm 00101110001110110111111110111110. */ -+{ "vsubadd4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadd4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ. */ -+{ "vsubadd4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadds a,b,c 00101bbb001111110BBBCCCCCCAAAAAA */ -+{ "vsubadds", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ */ -+{ "vsubadds", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds 0,b,c 00101bbb001111110BBBCCCCCC111110 */ -+{ "vsubadds", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds 0,b,u6 00101bbb011111110BBBuuuuuu111110 */ -+{ "vsubadds", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA */ -+{ "vsubadds", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ */ -+{ "vsubadds", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds b,b,s12 00101bbb101111110BBBssssssSSSSSS */ -+{ "vsubadds", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds 0,b,limm 00101bbb001111110BBB111110111110 */ -+{ "vsubadds", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds 0,limm,c 00101110001111110111CCCCCC111110 */ -+{ "vsubadds", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ */ -+{ "vsubadds", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds a,limm,c 00101110001111110111CCCCCCAAAAAA */ -+{ "vsubadds", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ */ -+{ "vsubadds", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadds a,b,limm 00101bbb001111110BBB111110AAAAAA */ -+{ "vsubadds", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds 0,limm,u6 00101110011111110111uuuuuu111110 */ -+{ "vsubadds", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ */ -+{ "vsubadds", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds a,limm,u6 00101110011111110111uuuuuuAAAAAA */ -+{ "vsubadds", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds 0,limm,s12 00101110101111110111ssssssSSSSSS */ -+{ "vsubadds", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds a,limm,limm 00101110001111110111111110AAAAAA */ -+{ "vsubadds", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds 0,limm,limm 00101110001111110111111110111110 */ -+{ "vsubadds", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds<.cc> 0,limm,limm 001011101111111101111111100QQQQQ */ -+{ "vsubadds", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadds2h a,b,c 00101bbb000101111BBBCCCCCCAAAAAA. */ -+{ "vsubadds2h", 0x28178000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds2h 0,b,c 00101bbb000101111BBBCCCCCC111110. */ -+{ "vsubadds2h", 0x2817803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds2h<.cc> b,b,c 00101bbb110101111BBBCCCCCC0QQQQQ. */ -+{ "vsubadds2h", 0x28D78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds2h a,b,u6 00101bbb010101111BBBuuuuuuAAAAAA. */ -+{ "vsubadds2h", 0x28578000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds2h 0,b,u6 00101bbb010101111BBBuuuuuu111110. */ -+{ "vsubadds2h", 0x2857803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds2h<.cc> b,b,u6 00101bbb110101111BBBuuuuuu1QQQQQ. */ -+{ "vsubadds2h", 0x28D78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds2h b,b,s12 00101bbb100101111BBBssssssSSSSSS. */ -+{ "vsubadds2h", 0x28978000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds2h a,limm,c 00101110000101111111CCCCCCAAAAAA. */ -+{ "vsubadds2h", 0x2E17F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds2h a,b,limm 00101bbb000101111BBB111110AAAAAA. */ -+{ "vsubadds2h", 0x28178F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds2h 0,limm,c 00101110000101111111CCCCCC111110. */ -+{ "vsubadds2h", 0x2E17F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds2h 0,b,limm 00101bbb000101111BBB111110111110. */ -+{ "vsubadds2h", 0x28178FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds2h<.cc> b,b,limm 00101bbb110101111BBB1111100QQQQQ. */ -+{ "vsubadds2h", 0x28D78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadds2h<.cc> 0,limm,c 00101110110101111111CCCCCC0QQQQQ. */ -+{ "vsubadds2h", 0x2ED7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds2h a,limm,u6 00101110010101111111uuuuuuAAAAAA. */ -+{ "vsubadds2h", 0x2E57F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds2h 0,limm,u6 00101110010101111111uuuuuu111110. */ -+{ "vsubadds2h", 0x2E57F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds2h<.cc> 0,limm,u6 00101110110101111111uuuuuu1QQQQQ. */ -+{ "vsubadds2h", 0x2ED7F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds2h 0,limm,s12 00101110100101111111ssssssSSSSSS. */ -+{ "vsubadds2h", 0x2E97F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds2h a,limm,limm 00101110000101111111111110AAAAAA. */ -+{ "vsubadds2h", 0x2E17FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds2h 0,limm,limm 00101110000101111111111110111110. */ -+{ "vsubadds2h", 0x2E17FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds2h<.cc> 0,limm,limm 001011101101011111111111100QQQQQ. */ -+{ "vsubadds2h", 0x2ED7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadds4h 0,b,c 00101bbb001110110BBBCCCCCC111110 */ -+{ "vsubadds4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ */ -+{ "vsubadds4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA */ -+{ "vsubadds4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds4h 0,b,u6 00101bbb011110110BBBuuuuuu111110 */ -+{ "vsubadds4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ */ -+{ "vsubadds4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA */ -+{ "vsubadds4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds4h b,b,s12 00101bbb101110110BBBssssssSSSSSS */ -+{ "vsubadds4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds4h a,limm,c 00101110001110110111CCCCCCAAAAAA */ -+{ "vsubadds4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds4h 0,b,limm 00101bbb001110110BBB111110111110 */ -+{ "vsubadds4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ */ -+{ "vsubadds4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubadds4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ */ -+{ "vsubadds4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubadds4h a,b,limm 00101bbb001110110BBB111110AAAAAA */ -+{ "vsubadds4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubadds4h 0,limm,c 00101110001110110111CCCCCC111110 */ -+{ "vsubadds4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubadds4h a,limm,u6 00101110011110110111uuuuuuAAAAAA */ -+{ "vsubadds4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds4h 0,limm,u6 00101110011110110111uuuuuu111110 */ -+{ "vsubadds4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubadds4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ */ -+{ "vsubadds4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubadds4h 0,limm,s12 00101110101110110111ssssssSSSSSS */ -+{ "vsubadds4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubadds4h a,limm,limm 00101110001110110111111110AAAAAA */ -+{ "vsubadds4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubadds4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ */ -+{ "vsubadds4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubadds4h 0,limm,limm 00101110001110110111111110111110 */ -+{ "vsubadds4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA */ -+{ "vsubs2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ */ -+{ "vsubs2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs2 0,b,c 00101bbb001111010BBBCCCCCC111110 */ -+{ "vsubs2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ */ -+{ "vsubs2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs2 0,b,u6 00101bbb011111010BBBuuuuuu111110 */ -+{ "vsubs2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA */ -+{ "vsubs2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2 b,b,s12 00101bbb101111010BBBssssssSSSSSS */ -+{ "vsubs2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs2 0,limm,c 00101110001111010111CCCCCC111110 */ -+{ "vsubs2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2 0,b,limm 00101bbb001111010BBB111110111110 */ -+{ "vsubs2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs2 a,b,limm 00101bbb001111010BBB111110AAAAAA */ -+{ "vsubs2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ */ -+{ "vsubs2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ */ -+{ "vsubs2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubs2 a,limm,c 00101110001111010111CCCCCCAAAAAA */ -+{ "vsubs2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2 0,limm,u6 00101110011111010111uuuuuu111110 */ -+{ "vsubs2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ */ -+{ "vsubs2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs2 a,limm,u6 00101110011111010111uuuuuuAAAAAA */ -+{ "vsubs2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2 0,limm,s12 00101110101111010111ssssssSSSSSS */ -+{ "vsubs2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs2 0,limm,limm 00101110001111010111111110111110 */ -+{ "vsubs2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ */ -+{ "vsubs2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubs2 a,limm,limm 00101110001111010111111110AAAAAA */ -+{ "vsubs2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs2h a,b,c 00101bbb000101011BBBCCCCCCAAAAAA. */ -+{ "vsubs2h", 0x28158000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2h 0,b,c 00101bbb000101011BBBCCCCCC111110. */ -+{ "vsubs2h", 0x2815803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2h<.cc> b,b,c 00101bbb110101011BBBCCCCCC0QQQQQ. */ -+{ "vsubs2h", 0x28D58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs2h a,b,u6 00101bbb010101011BBBuuuuuuAAAAAA. */ -+{ "vsubs2h", 0x28558000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2h 0,b,u6 00101bbb010101011BBBuuuuuu111110. */ -+{ "vsubs2h", 0x2855803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2h<.cc> b,b,u6 00101bbb110101011BBBuuuuuu1QQQQQ. */ -+{ "vsubs2h", 0x28D58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs2h b,b,s12 00101bbb100101011BBBssssssSSSSSS. */ -+{ "vsubs2h", 0x28958000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs2h a,limm,c 00101110000101011111CCCCCCAAAAAA. */ -+{ "vsubs2h", 0x2E15F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2h a,b,limm 00101bbb000101011BBB111110AAAAAA. */ -+{ "vsubs2h", 0x28158F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs2h 0,limm,c 00101110000101011111CCCCCC111110. */ -+{ "vsubs2h", 0x2E15F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs2h 0,b,limm 00101bbb000101011BBB111110111110. */ -+{ "vsubs2h", 0x28158FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs2h<.cc> b,b,limm 00101bbb110101011BBB1111100QQQQQ. */ -+{ "vsubs2h", 0x28D58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubs2h<.cc> 0,limm,c 00101110110101011111CCCCCC0QQQQQ. */ -+{ "vsubs2h", 0x2ED5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs2h a,limm,u6 00101110010101011111uuuuuuAAAAAA. */ -+{ "vsubs2h", 0x2E55F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2h 0,limm,u6 00101110010101011111uuuuuu111110. */ -+{ "vsubs2h", 0x2E55F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs2h<.cc> 0,limm,u6 00101110110101011111uuuuuu1QQQQQ. */ -+{ "vsubs2h", 0x2ED5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs2h 0,limm,s12 00101110100101011111ssssssSSSSSS. */ -+{ "vsubs2h", 0x2E95F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs2h a,limm,limm 00101110000101011111111110AAAAAA. */ -+{ "vsubs2h", 0x2E15FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs2h 0,limm,limm 00101110000101011111111110111110. */ -+{ "vsubs2h", 0x2E15FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs2h<.cc> 0,limm,limm 001011101101010111111111100QQQQQ. */ -+{ "vsubs2h", 0x2ED5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubs4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA */ -+{ "vsubs4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ */ -+{ "vsubs4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs4h 0,b,c 00101bbb001110010BBBCCCCCC111110 */ -+{ "vsubs4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, -+ -+/* vsubs4h 0,b,u6 00101bbb011110010BBBuuuuuu111110 */ -+{ "vsubs4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ */ -+{ "vsubs4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA */ -+{ "vsubs4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs4h b,b,s12 00101bbb101110010BBBssssssSSSSSS */ -+{ "vsubs4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ */ -+{ "vsubs4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, -+ -+/* vsubs4h a,b,limm 00101bbb001110010BBB111110AAAAAA */ -+{ "vsubs4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs4h 0,limm,c 00101110001110010111CCCCCC111110 */ -+{ "vsubs4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ */ -+{ "vsubs4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, -+ -+/* vsubs4h 0,b,limm 00101bbb001110010BBB111110111110 */ -+{ "vsubs4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, -+ -+/* vsubs4h a,limm,c 00101110001110010111CCCCCCAAAAAA */ -+{ "vsubs4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, -+ -+/* vsubs4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ */ -+{ "vsubs4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, -+ -+/* vsubs4h a,limm,u6 00101110011110010111uuuuuuAAAAAA */ -+{ "vsubs4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs4h 0,limm,u6 00101110011110010111uuuuuu111110 */ -+{ "vsubs4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* vsubs4h 0,limm,s12 00101110101110010111ssssssSSSSSS */ -+{ "vsubs4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, -+ -+/* vsubs4h a,limm,limm 00101110001110010111111110AAAAAA */ -+{ "vsubs4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* vsubs4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ */ -+{ "vsubs4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, -+ -+/* vsubs4h 0,limm,limm 00101110001110010111111110111110 */ -+{ "vsubs4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, -+ -+/* wevt c 00100000001011110001CCCCCC111111. */ -+{ "wevt", 0x202F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* wevt u6 00100000011011110001uuuuuu111111. */ -+{ "wevt", 0x206F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* wlfc c 00100001001011110001CCCCCC111111. */ -+{ "wlfc", 0x212F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_RC }, { 0 }}, -+ -+/* wlfc u6 00100001011011110001uuuuuu111111. */ -+{ "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, -+ -+/* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA. */ -+{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xbfu<.f> 0,b,c 00100bbb00101101FBBBCCCCCC111110. */ -+{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xbfu<.f><.cc> b,b,c 00100bbb11101101FBBBCCCCCC0QQQQQ. */ -+{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xbfu<.f> a,b,u6 00100bbb01101101FBBBuuuuuuAAAAAA. */ -+{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbfu<.f> 0,b,u6 00100bbb01101101FBBBuuuuuu111110. */ -+{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbfu<.f><.cc> b,b,u6 00100bbb11101101FBBBuuuuuu1QQQQQ. */ -+{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xbfu<.f> b,b,s12 00100bbb10101101FBBBssssssSSSSSS. */ -+{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xbfu<.f> a,limm,c 0010011000101101F111CCCCCCAAAAAA. */ -+{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xbfu<.f> a,b,limm 00100bbb00101101FBBB111110AAAAAA. */ -+{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xbfu<.f> 0,limm,c 0010011000101101F111CCCCCC111110. */ -+{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xbfu<.f> 0,b,limm 00100bbb00101101FBBB111110111110. */ -+{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xbfu<.f><.cc> b,b,limm 00100bbb11101101FBBB1111100QQQQQ. */ -+{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* xbfu<.f><.cc> 0,limm,c 0010011011101101F111CCCCCC0QQQQQ. */ -+{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xbfu<.f> a,limm,u6 0010011001101101F111uuuuuuAAAAAA. */ -+{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbfu<.f> 0,limm,u6 0010011001101101F111uuuuuu111110. */ -+{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xbfu<.f><.cc> 0,limm,u6 0010011011101101F111uuuuuu1QQQQQ. */ -+{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xbfu<.f> 0,limm,s12 0010011010101101F111ssssssSSSSSS. */ -+{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xbfu<.f> a,limm,limm 0010011000101101F111111110AAAAAA. */ -+{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xbfu<.f> 0,limm,limm 0010011000101101F111111110111110. */ -+{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xbfu<.f><.cc> 0,limm,limm 0010011011101101F1111111100QQQQQ. */ -+{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA. */ -+{ "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xor<.f> 0,b,c 00100bbb00000111FBBBCCCCCC111110. */ -+{ "xor", 0x2007003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xor<.f><.cc> b,b,c 00100bbb11000111FBBBCCCCCC0QQQQQ. */ -+{ "xor", 0x20C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xor<.f> a,b,u6 00100bbb01000111FBBBuuuuuuAAAAAA. */ -+{ "xor", 0x20470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xor<.f> 0,b,u6 00100bbb01000111FBBBuuuuuu111110. */ -+{ "xor", 0x2047003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xor<.f><.cc> b,b,u6 00100bbb11000111FBBBuuuuuu1QQQQQ. */ -+{ "xor", 0x20C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xor<.f> b,b,s12 00100bbb10000111FBBBssssssSSSSSS. */ -+{ "xor", 0x20870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xor<.f> a,limm,c 0010011000000111F111CCCCCCAAAAAA. */ -+{ "xor", 0x26077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xor<.f> a,b,limm 00100bbb00000111FBBB111110AAAAAA. */ -+{ "xor", 0x20070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xor<.f> 0,limm,c 0010011000000111F111CCCCCC111110. */ -+{ "xor", 0x2607703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xor<.f> 0,b,limm 00100bbb00000111FBBB111110111110. */ -+{ "xor", 0x20070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xor<.f><.cc> 0,limm,c 0010011011000111F111CCCCCC0QQQQQ. */ -+{ "xor", 0x26C77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xor<.f><.cc> b,b,limm 00100bbb11000111FBBB1111100QQQQQ. */ -+{ "xor", 0x20C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -+ -+/* xor<.f> a,limm,u6 0010011001000111F111uuuuuuAAAAAA. */ -+{ "xor", 0x26477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xor<.f> 0,limm,u6 0010011001000111F111uuuuuu111110. */ -+{ "xor", 0x2647703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xor<.f><.cc> 0,limm,u6 0010011011000111F111uuuuuu1QQQQQ. */ -+{ "xor", 0x26C77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xor<.f> 0,limm,s12 0010011010000111F111ssssssSSSSSS. */ -+{ "xor", 0x26877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xor<.f> a,limm,limm 0010011000000111F111111110AAAAAA. */ -+{ "xor", 0x26077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xor<.f> 0,limm,limm 0010011000000111F111111110111110. */ -+{ "xor", 0x26077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, -+ -+/* xor<.f><.cc> 0,limm,limm 0010011011000111F1111111100QQQQQ. */ -+{ "xor", 0x26C77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, -+ -+/* xor_s b,b,c 01111bbbccc00111. */ -+{ "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, -+ -+/* xpkqb<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA. */ -+{ "xpkqb", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, -+ -+/* xpkqb<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ. */ -+{ "xpkqb", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, -+ -+/* xpkqb<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA. */ -+{ "xpkqb", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, -+ -+/* xpkqb<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ. */ -+{ "xpkqb", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, -+ -+/* xpkqb<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS. */ -+ -+{ "xpkqb", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, -+ -+/* xpkqb<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA. */ -+{ "xpkqb", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, -+ -+/* xpkqb<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA. */ -+{ "xpkqb", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, -+ -+/* xpkqb<.f><.cc> b,b,limm 00110bbb11100010FBBB1111100QQQQQ. */ -+{ "xpkqb", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, -diff --git a/target/arc/operands-v3.def b/target/arc/operands-v3.def -new file mode 100644 -index 0000000000..df9c636bc4 ---- /dev/null -+++ b/target/arc/operands-v3.def -@@ -0,0 +1,133 @@ -+/* -+ * QEMU ARCv3 operands -+ * -+ * Copyright (c) 2020 Synopsys, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+ARC_OPERAND(IGNORED, 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0) -+ARC_OPERAND(RA, 6, 0, 0, ARC_OPERAND_IR, 0) -+ARC_OPERAND(RA_CHK, 6, 0, 0, ARC_OPERAND_IR, 0) -+ARC_OPERAND(RB, 6, 12, 0, ARC_OPERAND_IR, extract_rb) -+ARC_OPERAND(RB_CHK, 6, 12, 0, ARC_OPERAND_IR, extract_rb) -+ARC_OPERAND(RBB_S, 6, 12, 0, ARC_OPERAND_IR, extract_rbb) -+ARC_OPERAND(RC, 6, 6, 0, ARC_OPERAND_IR, 0) -+ARC_OPERAND(RC_CHK, 6, 6, 0, ARC_OPERAND_IR, 0) -+ARC_OPERAND(RBdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rb) -+ARC_OPERAND(RAD, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, 0) -+ARC_OPERAND(RAD_CHK, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, 0) -+ARC_OPERAND(RCD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, 0) -+ARC_OPERAND(RA16, 4, 0, 0, ARC_OPERAND_IR, extract_ras) -+ARC_OPERAND(RA_S, 4, 0, 0, ARC_OPERAND_IR, extract_ras) -+ARC_OPERAND(RB16, 4, 8, 0, ARC_OPERAND_IR, extract_rbs) -+ARC_OPERAND(RB_S, 4, 8, 0, ARC_OPERAND_IR, extract_rbs) -+ARC_OPERAND(RB16dup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rbs) -+ARC_OPERAND(RB_Sdup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rbs) -+ARC_OPERAND(RC16, 4, 5, 0, ARC_OPERAND_IR, extract_rcs) -+ARC_OPERAND(RC_S, 4, 5, 0, ARC_OPERAND_IR, extract_rcs) -+ARC_OPERAND(R6H, 6, 5, 0, ARC_OPERAND_IR, extract_rhv1) -+ARC_OPERAND(R5H, 5, 5, 0, ARC_OPERAND_IR, extract_rhv2) -+ARC_OPERAND(RH_S, 5, 5, 0, ARC_OPERAND_IR, extract_rhv2) -+ARC_OPERAND(R5Hdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rhv2) -+ARC_OPERAND(RH_Sdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rhv2) -+ARC_OPERAND(RG, 5, 5, 0, ARC_OPERAND_IR, extract_g_s) -+ARC_OPERAND(G_S, 5, 5, 0, ARC_OPERAND_IR, extract_g_s) -+ARC_OPERAND(R0, 0, 0, 0, ARC_OPERAND_IR, extract_r0) -+ARC_OPERAND(R0_S, 0, 0, 0, ARC_OPERAND_IR, extract_r0) -+ARC_OPERAND(R1, 1, 0, 0, ARC_OPERAND_IR, extract_r1) -+ARC_OPERAND(R1_S, 1, 0, 0, ARC_OPERAND_IR, extract_r1) -+ARC_OPERAND(R2, 2, 0, 0, ARC_OPERAND_IR, extract_r2) -+ARC_OPERAND(R2_S, 2, 0, 0, ARC_OPERAND_IR, extract_r2) -+ARC_OPERAND(R3, 2, 0, 0, ARC_OPERAND_IR, extract_r3) -+ARC_OPERAND(R3_S, 2, 0, 0, ARC_OPERAND_IR, extract_r3) -+ARC_OPERAND(RSP, 5, 0, 0, ARC_OPERAND_IR, extract_sp) -+ARC_OPERAND(SP_S, 5, 0, 0, ARC_OPERAND_IR, extract_sp) -+ARC_OPERAND(SPdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_sp) -+ARC_OPERAND(SP_Sdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_sp) -+ARC_OPERAND(GP, 5, 0, 0, ARC_OPERAND_IR, extract_gp) -+ARC_OPERAND(GP_S, 5, 0, 0, ARC_OPERAND_IR, extract_gp) -+ARC_OPERAND(PCL_S, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, extract_pcl) -+ARC_OPERAND(BLINK, 5, 0, 0, ARC_OPERAND_IR, extract_blink) -+ARC_OPERAND(BLINK_S, 5, 0, 0, ARC_OPERAND_IR, extract_blink) -+ARC_OPERAND(ILINK1, 5, 0, 0, ARC_OPERAND_IR, extract_ilink1) -+ARC_OPERAND(ILINK2, 5, 0, 0, ARC_OPERAND_IR, extract_ilink2) -+ARC_OPERAND(LIMM, 32, 0, 0, ARC_OPERAND_LIMM, 0) -+ARC_OPERAND(LIMM_S, 32, 0, 0, ARC_OPERAND_LIMM, 0) -+ARC_OPERAND(LO32, 32, 0, 0, ARC_OPERAND_LIMM, 0) -+ARC_OPERAND(HI32, 32, 0, 0, ARC_OPERAND_LIMM, 0) -+ARC_OPERAND(XIMM_S, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, 0) -+ARC_OPERAND(XIMM, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, 0) -+ARC_OPERAND(LIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, 0) -+ARC_OPERAND(XIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE | ARC_OPERAND_SIGNED, 0) -+ARC_OPERAND(ZA, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(ZB, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(ZA_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(ZB_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(ZC_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(RRANGE_EL, 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, extract_rrange) -+ARC_OPERAND(R13_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_rrange) -+ARC_OPERAND(FP_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_fpel) -+ARC_OPERAND(BLINK_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_blinkel) -+ARC_OPERAND(PCL_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_pclel) -+ARC_OPERAND(BRAKET, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0) -+ARC_OPERAND(BRAKETdup, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0) -+ARC_OPERAND(FKT_T, 1, 3, 0, ARC_OPERAND_FAKE, 0) -+ARC_OPERAND(FKT_NT, 1, 3, 0, ARC_OPERAND_FAKE, 0) -+ARC_OPERAND(UIMM6_20, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_20) -+ARC_OPERAND(UIMM6_20R, 6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, extract_uimm6_20) -+ARC_OPERAND(SIMM12_20, 12, 0, 0, ARC_OPERAND_SIGNED, extract_simm12_20) -+ARC_OPERAND(SIMM12_20R, 12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,extract_simm12_20) -+ARC_OPERAND(UIMM12_20, 12, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm12_20) -+ARC_OPERAND(SIMM3_5_S, 3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, extract_simm3s) -+ARC_OPERAND(UIMM7_A32_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm7_a32_11_s) -+ARC_OPERAND(UIMM7_A32_11R_S, 7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, extract_uimm7_a32_11_s) -+ARC_OPERAND(UIMM9_A32_11_S, 9, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm9_a32_11_s) -+ARC_OPERAND(UIMM7_9_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm7_9_s) -+ARC_OPERAND(UIMM3_13_S, 3, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm3_13_s) -+ARC_OPERAND(UIMM3_13R_S, 3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, extract_uimm3_13_s) -+ARC_OPERAND(SIMM11_A32_7_S, 11, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, extract_simm11_a32_7_s) -+ARC_OPERAND(UIMM6_13_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_13_s) -+ARC_OPERAND(UIMM5_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, extract_uimm5_11_s) -+ARC_OPERAND(SIMM9_A16_8, 9, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, extract_simm9_a16_8) -+ARC_OPERAND(UIMM6_8, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_8) -+ARC_OPERAND(SIMM21_A16_5, 21, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm21_a16_5) -+ARC_OPERAND(SIMM25_A16_5, 25, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm25_a16_5) -+ARC_OPERAND(SIMM10_A16_7_S, 10, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm10_a16_7_s) -+ARC_OPERAND(SIMM10_A16_7_Sbis, 10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, extract_simm10_a16_7_s) -+ARC_OPERAND(SIMM7_A16_10_S, 7, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm7_a16_10_s) -+ARC_OPERAND(SIMM21_A32_5, 21, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm21_a32_5) -+ARC_OPERAND(SIMM25_A32_5, 25, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm25_a32_5) -+ARC_OPERAND(SIMM13_A32_5_S, 13, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm13_a32_5_s) -+ARC_OPERAND(SIMM8_A16_9_S, 8, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm8_a16_9_s) -+ARC_OPERAND(UIMM10_6_S_JLIOFF, 12, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, extract_uimm10_6_s) -+ARC_OPERAND(UIMM3_23, 3, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm3_23) -+ARC_OPERAND(UIMM10_6_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm10_6_s) -+ARC_OPERAND(UIMM10_13_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm10_13_s) -+ARC_OPERAND(UIMM6_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_11_s) -+ARC_OPERAND(SIMM9_8, 9, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, extract_simm9_8) -+ARC_OPERAND(SIMM9_8R, 9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, extract_simm9_8) -+ARC_OPERAND(UIMM10_A32_8_S, 10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_uimm10_a32_8_s) -+ARC_OPERAND(SIMM9_7_S, 9, 0, 0, ARC_OPERAND_SIGNED, extract_simm9_7_s) -+ARC_OPERAND(UIMM6_A16_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm6_a16_11_s) -+ARC_OPERAND(UIMM5_A32_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm5_a32_11_s) -+ARC_OPERAND(SIMM11_A32_13_S, 11, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, extract_simm11_a32_13_s) -+ARC_OPERAND(UIMM7_13_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm7_13_s) -+ARC_OPERAND(UIMM6_A16_21, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, extract_uimm6_a16_21) -+ARC_OPERAND(UIMM7_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm7_11_s) -+ARC_OPERAND(UIMM7_A16_20, 7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_uimm7_a16_20) -+ARC_OPERAND(SIMM13_A16_20, 13, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm13_a16_20) -+ARC_OPERAND(UIMM8_8_S, 8, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm8_8_s) -+ARC_OPERAND(UIMM8_8R_S, 8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, extract_uimm8_8_s) -+ARC_OPERAND(W6, 6, 0, 0, ARC_OPERAND_SIGNED, extract_w6) -+ARC_OPERAND(UIMM6_5_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_5_s) -diff --git a/target/arc/operands.def b/target/arc/operands.def -new file mode 100644 -index 0000000000..34b15e0ec2 ---- /dev/null -+++ b/target/arc/operands.def -@@ -0,0 +1,123 @@ -+/* -+ * QEMU ARC operands -+ * -+ * Copyright (c) 2020 Synopsys, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+ARC_OPERAND(IGNORED, 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0) -+ARC_OPERAND(RA, 6, 0, 0, ARC_OPERAND_IR, 0) -+ARC_OPERAND(RA_CHK, 6, 0, 0, ARC_OPERAND_IR, 0) -+ARC_OPERAND(RB, 6, 12, 0, ARC_OPERAND_IR, extract_rb) -+ARC_OPERAND(RB_CHK, 6, 12, 0, ARC_OPERAND_IR, extract_rb) -+ARC_OPERAND(RC, 6, 6, 0, ARC_OPERAND_IR, 0) -+ARC_OPERAND(RBdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rb) -+ARC_OPERAND(RAD, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, 0) -+ARC_OPERAND(RCD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, 0) -+ARC_OPERAND(RA16, 4, 0, 0, ARC_OPERAND_IR, extract_ras) -+ARC_OPERAND(RA_S, 4, 0, 0, ARC_OPERAND_IR, extract_ras) -+ARC_OPERAND(RB16, 4, 8, 0, ARC_OPERAND_IR, extract_rbs) -+ARC_OPERAND(RB_S, 4, 8, 0, ARC_OPERAND_IR, extract_rbs) -+ARC_OPERAND(RB16dup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rbs) -+ARC_OPERAND(RB_Sdup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rbs) -+ARC_OPERAND(RC16, 4, 5, 0, ARC_OPERAND_IR, extract_rcs) -+ARC_OPERAND(RC_S, 4, 5, 0, ARC_OPERAND_IR, extract_rcs) -+ARC_OPERAND(R6H, 6, 5, 0, ARC_OPERAND_IR, extract_rhv1) -+ARC_OPERAND(R5H, 5, 5, 0, ARC_OPERAND_IR, extract_rhv2) -+ARC_OPERAND(RH_S, 5, 5, 0, ARC_OPERAND_IR, extract_rhv2) -+ARC_OPERAND(R5Hdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rhv2) -+ARC_OPERAND(RH_Sdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rhv2) -+ARC_OPERAND(RG, 5, 5, 0, ARC_OPERAND_IR, extract_g_s) -+ARC_OPERAND(G_S, 5, 5, 0, ARC_OPERAND_IR, extract_g_s) -+ARC_OPERAND(R0, 0, 0, 0, ARC_OPERAND_IR, extract_r0) -+ARC_OPERAND(R0_S, 0, 0, 0, ARC_OPERAND_IR, extract_r0) -+ARC_OPERAND(R1, 1, 0, 0, ARC_OPERAND_IR, extract_r1) -+ARC_OPERAND(R1_S, 1, 0, 0, ARC_OPERAND_IR, extract_r1) -+ARC_OPERAND(R2, 2, 0, 0, ARC_OPERAND_IR, extract_r2) -+ARC_OPERAND(R2_S, 2, 0, 0, ARC_OPERAND_IR, extract_r2) -+ARC_OPERAND(R3, 2, 0, 0, ARC_OPERAND_IR, extract_r3) -+ARC_OPERAND(R3_S, 2, 0, 0, ARC_OPERAND_IR, extract_r3) -+ARC_OPERAND(RSP, 5, 0, 0, ARC_OPERAND_IR, extract_sp) -+ARC_OPERAND(SP_S, 5, 0, 0, ARC_OPERAND_IR, extract_sp) -+ARC_OPERAND(SPdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_sp) -+ARC_OPERAND(SP_Sdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_sp) -+ARC_OPERAND(GP, 5, 0, 0, ARC_OPERAND_IR, extract_gp) -+ARC_OPERAND(GP_S, 5, 0, 0, ARC_OPERAND_IR, extract_gp) -+ARC_OPERAND(PCL_S, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, extract_pcl) -+ARC_OPERAND(BLINK, 5, 0, 0, ARC_OPERAND_IR, extract_blink) -+ARC_OPERAND(BLINK_S, 5, 0, 0, ARC_OPERAND_IR, extract_blink) -+ARC_OPERAND(ILINK1, 5, 0, 0, ARC_OPERAND_IR, extract_ilink1) -+ARC_OPERAND(ILINK2, 5, 0, 0, ARC_OPERAND_IR, extract_ilink2) -+ARC_OPERAND(LIMM, 32, 0, 0, ARC_OPERAND_LIMM, 0) -+ARC_OPERAND(LIMM_S, 32, 0, 0, ARC_OPERAND_LIMM, 0) -+ARC_OPERAND(LIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, 0) -+ARC_OPERAND(ZA, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(ZB, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(ZA_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(ZB_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(ZC_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) -+ARC_OPERAND(RRANGE_EL, 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, extract_rrange) -+ARC_OPERAND(R13_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_rrange) -+ARC_OPERAND(FP_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_fpel) -+ARC_OPERAND(BLINK_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_blinkel) -+ARC_OPERAND(PCL_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_pclel) -+ARC_OPERAND(BRAKET, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0) -+ARC_OPERAND(BRAKETdup, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0) -+ARC_OPERAND(FKT_T, 1, 3, 0, ARC_OPERAND_FAKE, 0) -+ARC_OPERAND(FKT_NT, 1, 3, 0, ARC_OPERAND_FAKE, 0) -+ARC_OPERAND(UIMM6_20, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_20) -+ARC_OPERAND(UIMM6_20R, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, extract_uimm6_20) -+ARC_OPERAND(SIMM12_20, 12, 0, 0, ARC_OPERAND_SIGNED, extract_simm12_20) -+ARC_OPERAND(SIMM12_20R, 12, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, extract_simm12_20) -+ARC_OPERAND(UIMM12_20, 12, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm12_20) -+ARC_OPERAND(SIMM3_5_S, 3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, extract_simm3s) -+ARC_OPERAND(UIMM7_A32_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm7_a32_11_s) -+ARC_OPERAND(UIMM7_A32_11R_S, 7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, extract_uimm7_a32_11_s) -+ARC_OPERAND(UIMM7_9_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm7_9_s) -+ARC_OPERAND(UIMM3_13_S, 3, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm3_13_s) -+ARC_OPERAND(UIMM3_13R_S, 3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, extract_uimm3_13_s) -+ARC_OPERAND(SIMM11_A32_7_S, 11, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, extract_simm11_a32_7_s) -+ARC_OPERAND(UIMM6_13_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_13_s) -+ARC_OPERAND(UIMM5_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, extract_uimm5_11_s) -+ARC_OPERAND(SIMM9_A16_8, 9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, extract_simm9_a16_8) -+ARC_OPERAND(UIMM6_8, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_8) -+ARC_OPERAND(SIMM21_A16_5, 21, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm21_a16_5) -+ARC_OPERAND(SIMM25_A16_5, 25, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm25_a16_5) -+ARC_OPERAND(SIMM10_A16_7_S, 10, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm10_a16_7_s) -+ARC_OPERAND(SIMM10_A16_7_Sbis, 10, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, extract_simm10_a16_7_s) -+ARC_OPERAND(SIMM7_A16_10_S, 7, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm7_a16_10_s) -+ARC_OPERAND(SIMM21_A32_5, 21, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm21_a32_5) -+ARC_OPERAND(SIMM25_A32_5, 25, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm25_a32_5) -+ARC_OPERAND(SIMM13_A32_5_S, 13, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm13_a32_5_s) -+ARC_OPERAND(SIMM8_A16_9_S, 8, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm8_a16_9_s) -+ARC_OPERAND(UIMM10_6_S_JLIOFF, 12, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, extract_uimm10_6_s) -+ARC_OPERAND(UIMM3_23, 3, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm3_23) -+ARC_OPERAND(UIMM10_6_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm10_6_s) -+ARC_OPERAND(UIMM6_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_11_s) -+ARC_OPERAND(SIMM9_8, 9, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, extract_simm9_8) -+ARC_OPERAND(SIMM9_8R, 9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, extract_simm9_8) -+ARC_OPERAND(UIMM10_A32_8_S, 10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_uimm10_a32_8_s) -+ARC_OPERAND(SIMM9_7_S, 9, 0, 0, ARC_OPERAND_SIGNED, extract_simm9_7_s) -+ARC_OPERAND(UIMM6_A16_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm6_a16_11_s) -+ARC_OPERAND(UIMM5_A32_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm5_a32_11_s) -+ARC_OPERAND(SIMM11_A32_13_S, 11, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, extract_simm11_a32_13_s) -+ARC_OPERAND(UIMM7_13_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm7_13_s) -+ARC_OPERAND(UIMM6_A16_21, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, extract_uimm6_a16_21) -+ARC_OPERAND(UIMM7_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm7_11_s) -+ARC_OPERAND(UIMM7_A16_20, 7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_uimm7_a16_20) -+ARC_OPERAND(SIMM13_A16_20, 13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm13_a16_20) -+ARC_OPERAND(UIMM8_8_S, 8, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm8_8_s) -+ARC_OPERAND(UIMM8_8R_S, 8, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, extract_uimm8_8_s) -+ARC_OPERAND(W6, 6, 0, 0, ARC_OPERAND_SIGNED, extract_w6) -+ARC_OPERAND(UIMM6_5_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_5_s) -diff --git a/target/arc/regs-detail.def b/target/arc/regs-detail.def -new file mode 100644 -index 0000000000..3e11fb1aa3 ---- /dev/null -+++ b/target/arc/regs-detail.def -@@ -0,0 +1,583 @@ -+/* -+ * QEMU ARC Auxiliary register definitions -+ * -+ * Copyright (c) 2020 Synopsys, Inc. -+ * Contributed by Claudiu Zissulescu (claziss@synopsys.com) -+ * Contributed by Cupertino Miranda (cmiranda@synopsys.com) -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+/* INFO: this list must be kept ordered by address to allow -+ * binary search of register information based on address. -+ */ -+ -+DEF(0xffff,ARC_OPCODE_ARCALL, NONE, unimp_bcr) -+DEF(0x1, ARC_OPCODE_ARCV1, NONE, semaphore) -+DEF(0x2, ARC_OPCODE_ARCALL, NONE, lp_start) -+DEF(0x3, ARC_OPCODE_ARCALL, NONE, lp_end) -+DEF(0x4, ARC_OPCODE_ARCALL, NONE, identity) -+DEF(0x5, ARC_OPCODE_ARCALL, NONE, debug) -+DEF(0x6, ARC_OPCODE_ARCALL, NONE, pc) -+DEF(0x7, ARC_OPCODE_ARCv2HS, NONE, memseg) -+DEF(0x7, ARC_OPCODE_ARCV1, NONE, adcr) -+DEF(0x8, ARC_OPCODE_ARCV1, NONE, apcr) -+DEF(0x8, ARC_OPCODE_ARCv2HS, NONE, exec_ctrl) -+DEF(0x8, ARC_OPCODE_V3_ALL, NONE, exec_ctrl) -+DEF(0x9, ARC_OPCODE_ARCV1, NONE, acr) -+DEF(0x9, ARC_OPCODE_ARCv2EM, NONE, sec_stat) -+DEF(0xa, ARC_OPCODE_ARCALL, NONE, status32) -+DEF(0xb, ARC_OPCODE_ARCV2, NONE, status32_p0) -+DEF(0xc, ARC_OPCODE_ARCv2EM, NONE, sec_extra) -+DEF(0xd, ARC_OPCODE_ARCV2, NONE, aux_user_sp) -+DEF(0xd, ARC_OPCODE_V3_ALL, NONE, aux_user_sp) -+DEF(0xe, ARC_OPCODE_ARC700, NONE, clk_enable) -+DEF(0xe, ARC_OPCODE_ARCV2, NONE, aux_irq_ctrl) -+DEF(0xe, ARC_OPCODE_V3_ALL, NONE, aux_irq_ctrl) -+DEF(0xf, ARC_OPCODE_ARC700, NONE, bpu_flush) -+DEF(0xf, ARC_OPCODE_ARCv2HS, NONE, debugi) -+DEF(0x10, ARC_OPCODE_ARCV1, NONE, ivic) -+DEF(0x10, ARC_OPCODE_ARCALL, NONE, ic_ivic) -+DEF(0x11, ARC_OPCODE_ARCV1, NONE, che_mode) -+DEF(0x11, ARC_OPCODE_ARCALL, NONE, ic_ctrl) -+DEF(0x12, ARC_OPCODE_ARC600, NONE, mulhi) -+DEF(0x12, ARC_OPCODE_ARCv2HS, NONE, ic_startr) -+DEF(0x13, ARC_OPCODE_ARCV1, NONE, lockline) -+DEF(0x13, ARC_OPCODE_ARCV2, NONE, ic_lil) -+DEF(0x14, ARC_OPCODE_ARC600, NONE, dmc_code_ram) -+DEF(0x15, ARC_OPCODE_ARCV1, NONE, tag_addr_mask) -+DEF(0x16, ARC_OPCODE_ARCV1, NONE, tag_data_mask) -+DEF(0x16, ARC_OPCODE_ARCv2HS, NONE, ic_ivir) -+DEF(0x17, ARC_OPCODE_ARCV1, NONE, line_length_mask) -+DEF(0x17, ARC_OPCODE_ARCv2HS, NONE, ic_endr) -+DEF(0x18, ARC_OPCODE_ARC600, NONE, aux_ldst_ram) -+DEF(0x18, ARC_OPCODE_NONE, NONE, aux_dccm) -+DEF(0x19, ARC_OPCODE_ARCV1, NONE, unlockline) -+DEF(0x19, ARC_OPCODE_ARCALL, NONE, ic_ivil) -+DEF(0x1a, ARC_OPCODE_ARCALL, NONE, ic_ram_address) -+DEF(0x1b, ARC_OPCODE_ARCALL, NONE, ic_tag) -+DEF(0x1c, ARC_OPCODE_ARCALL, NONE, ic_wp) -+DEF(0x1d, ARC_OPCODE_ARCALL, NONE, ic_data) -+DEF(0x1e, ARC_OPCODE_ARCALL, NONE, ic_ptag) -+DEF(0x1f, ARC_OPCODE_ARCv2EM, NONE, debugi) -+DEF(0x1f, ARC_OPCODE_ARCv2HS, NONE, ic_ptag_hi) -+DEF(0x20, ARC_OPCODE_ARC600, NONE, sram_seq) -+DEF(0x21, ARC_OPCODE_ARCALL, NONE, count0) -+DEF(0x22, ARC_OPCODE_ARCALL, NONE, control0) -+DEF(0x23, ARC_OPCODE_ARCALL, NONE, limit0) -+DEF(0x24, ARC_OPCODE_ARCV1, NONE, pcport) -+DEF(0x25, ARC_OPCODE_ARC700, NONE, int_vector_base) -+DEF(0x25, ARC_OPCODE_ARCV2, NONE, int_vector_base) -+DEF(0x25, ARC_OPCODE_V3_ALL, NONE, int_vector_base) -+DEF(0x26, ARC_OPCODE_ARC600, NONE, aux_vbfdw_mode) -+DEF(0x27, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm0) -+DEF(0x28, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm1) -+DEF(0x29, ARC_OPCODE_ARC600, NONE, aux_vbfdw_accu) -+DEF(0x2a, ARC_OPCODE_ARC600, NONE, aux_vbfdw_ofst) -+DEF(0x2b, ARC_OPCODE_ARC600, NONE, aux_vbfdw_intstat) -+DEF(0x2c, ARC_OPCODE_ARC600, NONE, aux_xmac0_24) -+DEF(0x2d, ARC_OPCODE_ARC600, NONE, aux_xmac1_24) -+DEF(0x2e, ARC_OPCODE_ARC600, NONE, aux_xmac2_24) -+DEF(0x2f, ARC_OPCODE_ARC600, NONE, aux_fbf_store_16) -+DEF(0x30, ARC_OPCODE_ARCv2EM, NONE, acg_ctrl) -+DEF(0x30, ARC_OPCODE_NONE, NONE, ax0) -+DEF(0x31, ARC_OPCODE_NONE, NONE, ax1) -+DEF(0x32, ARC_OPCODE_NONE, NONE, aux_crc_poly) -+DEF(0x33, ARC_OPCODE_NONE, NONE, aux_crc_mode) -+DEF(0x34, ARC_OPCODE_NONE, NONE, mx0) -+DEF(0x35, ARC_OPCODE_NONE, NONE, mx1) -+DEF(0x36, ARC_OPCODE_NONE, NONE, my0) -+DEF(0x37, ARC_OPCODE_NONE, NONE, my1) -+DEF(0x38, ARC_OPCODE_NONE, NONE, xyconfig) -+DEF(0x38, ARC_OPCODE_ARCv2EM, NONE, aux_kernel_sp) -+DEF(0x39, ARC_OPCODE_NONE, NONE, scratch_a) -+DEF(0x39, ARC_OPCODE_ARCv2EM, NONE, aux_sec_u_sp) -+/* TODO: The commented lines are repeated for specific configurations. */ -+/* -+DEF (0x3a, ARC_OPCODE_NONE, NONE, burstsys) -+DEF (0x3a, ARC_OPCODE_NONE, NONE, tsch) -+*/ -+DEF(0x3a, ARC_OPCODE_ARCv2EM, NONE, aux_sec_k_sp) -+DEF(0x3b, ARC_OPCODE_NONE, NONE, burstxym) -+DEF(0x3c, ARC_OPCODE_NONE, NONE, burstsz) -+DEF(0x3d, ARC_OPCODE_NONE, NONE, burstval) -+DEF(0x3e, ARC_OPCODE_ARCv2EM, NONE, aux_sec_ctrl) -+DEF(0x3f, ARC_OPCODE_ARCv2EM, NONE, erp_control) -+DEF(0x40, ARC_OPCODE_ARCv2EM, NONE, rferp_status0) -+DEF(0x41, ARC_OPCODE_ARCv2EM, NONE, rferp_status1) -+DEF(0x40, ARC_OPCODE_ARC600, NONE, xtp_newval) -+DEF(0x41, ARC_OPCODE_ARCV1, NONE, aux_macmode) -+DEF(0x42, ARC_OPCODE_ARC600, NONE, lsp_newval) -+DEF(0x43, ARC_OPCODE_ARCV1, NONE, aux_irq_lv12) -+DEF(0x43, ARC_OPCODE_ARCV2, NONE, aux_irq_act) -+DEF(0x43, ARC_OPCODE_V3_ALL, NONE, aux_irq_act) -+DEF(0x44, ARC_OPCODE_ARCV1, NONE, aux_xmac0) -+DEF(0x45, ARC_OPCODE_ARCV1, NONE, aux_xmac1) -+DEF(0x46, ARC_OPCODE_ARCV1, NONE, aux_xmac2) -+DEF(0x47, ARC_OPCODE_ARCALL, NONE, dc_ivdc) -+DEF(0x48, ARC_OPCODE_ARCALL, NONE, dc_ctrl) -+DEF(0x49, ARC_OPCODE_ARCALL, NONE, dc_ldl) -+DEF(0x4a, ARC_OPCODE_ARCALL, NONE, dc_ivdl) -+DEF(0x4b, ARC_OPCODE_ARCALL, NONE, dc_flsh) -+DEF(0x4c, ARC_OPCODE_ARCALL, NONE, dc_fldl) -+DEF(0x4d, ARC_OPCODE_ARCV2, NONE, dc_startr) -+DEF(0x4d, ARC_OPCODE_V3_ALL, NONE, dc_startr) -+DEF(0x4e, ARC_OPCODE_ARCV2, NONE, dc_endr) -+DEF(0x4e, ARC_OPCODE_V3_ALL, NONE, dc_endr) -+DEF(0x50, ARC_OPCODE_NONE, NONE, hexdata) -+DEF(0x51, ARC_OPCODE_NONE, NONE, hexctrl) -+DEF(0x52, ARC_OPCODE_NONE, NONE, led) -+DEF(0x56, ARC_OPCODE_NONE, NONE, dilstat) -+DEF(0x57, ARC_OPCODE_ARC600, NONE, swstat) -+DEF(0x58, ARC_OPCODE_ARCALL, NONE, dc_ram_addr) -+DEF(0x59, ARC_OPCODE_ARCALL, NONE, dc_tag) -+DEF(0x5a, ARC_OPCODE_ARCALL, NONE, dc_wp) -+DEF(0x5b, ARC_OPCODE_ARCALL, NONE, dc_data) -+DEF(0x5c, ARC_OPCODE_ARCALL, NONE, dc_ptag) -+DEF(0x5e, ARC_OPCODE_ARCv2HS, NONE, aux_volatile) -+DEF(0x5f, ARC_OPCODE_ARCv2HS, NONE, dc_ptag_hi) -+DEF(0x80, ARC_OPCODE_ARCALL, NONE, ax0) -+DEF(0x81, ARC_OPCODE_ARCALL, NONE, ax1) -+DEF(0x82, ARC_OPCODE_ARCALL, NONE, ax2) -+DEF(0x83, ARC_OPCODE_ARCALL, NONE, ax3) -+DEF(0x84, ARC_OPCODE_ARCALL, NONE, ay0) -+DEF(0x85, ARC_OPCODE_ARCALL, NONE, ay1) -+DEF(0x86, ARC_OPCODE_ARCALL, NONE, ay2) -+DEF(0x87, ARC_OPCODE_ARCALL, NONE, ay3) -+DEF(0x88, ARC_OPCODE_ARCALL, NONE, mx00) -+DEF(0x89, ARC_OPCODE_ARCALL, NONE, mx01) -+DEF(0x8a, ARC_OPCODE_ARCALL, NONE, mx10) -+DEF(0x8b, ARC_OPCODE_ARCALL, NONE, mx11) -+DEF(0x8c, ARC_OPCODE_ARCALL, NONE, mx20) -+DEF(0x8d, ARC_OPCODE_ARCALL, NONE, mx21) -+DEF(0x8e, ARC_OPCODE_ARCALL, NONE, mx30) -+DEF(0x8f, ARC_OPCODE_ARCALL, NONE, mx31) -+DEF(0x90, ARC_OPCODE_ARCALL, NONE, my00) -+DEF(0x91, ARC_OPCODE_ARCALL, NONE, my01) -+DEF(0x92, ARC_OPCODE_ARCALL, NONE, my10) -+DEF(0x93, ARC_OPCODE_ARCALL, NONE, my11) -+DEF(0x94, ARC_OPCODE_ARCALL, NONE, my20) -+DEF(0x95, ARC_OPCODE_ARCALL, NONE, my21) -+DEF(0x96, ARC_OPCODE_ARCALL, NONE, my30) -+DEF(0x97, ARC_OPCODE_ARCALL, NONE, my31) -+DEF(0x98, ARC_OPCODE_ARCALL, NONE, xyconfig) -+DEF(0x99, ARC_OPCODE_ARCALL, NONE, burstsys) -+DEF(0x9a, ARC_OPCODE_ARCALL, NONE, burstxym) -+DEF(0x9b, ARC_OPCODE_ARCALL, NONE, burstsz) -+DEF(0x9c, ARC_OPCODE_ARCALL, NONE, burstval) -+DEF(0x9d, ARC_OPCODE_ARCALL, NONE, xylsbasex) -+DEF(0x9e, ARC_OPCODE_ARCALL, NONE, xylsbasey) -+DEF(0x9f, ARC_OPCODE_ARCALL, NONE, aux_xmaclw_h) -+DEF(0xa0, ARC_OPCODE_ARCALL, NONE, aux_xmaclw_l) -+DEF(0xa1, ARC_OPCODE_ARCALL, NONE, se_ctrl) -+DEF(0xa2, ARC_OPCODE_ARCALL, NONE, se_stat) -+DEF(0xa3, ARC_OPCODE_ARCALL, NONE, se_err) -+DEF(0xa4, ARC_OPCODE_ARCALL, NONE, se_eadr) -+DEF(0xa5, ARC_OPCODE_ARCALL, NONE, se_spc) -+DEF(0xa6, ARC_OPCODE_ARCALL, NONE, sdm_base) -+DEF(0xa7, ARC_OPCODE_ARCALL, NONE, scm_base) -+DEF(0xa8, ARC_OPCODE_ARCALL, NONE, se_dbg_ctrl) -+DEF(0xa9, ARC_OPCODE_ARCALL, NONE, se_dbg_data0) -+DEF(0xaa, ARC_OPCODE_ARCALL, NONE, se_dbg_data1) -+DEF(0xab, ARC_OPCODE_ARCALL, NONE, se_dbg_data2) -+DEF(0xac, ARC_OPCODE_ARCALL, NONE, se_dbg_data3) -+DEF(0xad, ARC_OPCODE_ARCALL, NONE, se_watch) -+DEF(0xc1, ARC_OPCODE_ARC600, NONE, arc600_build_config) -+DEF(0xc1, ARC_OPCODE_ARCALL, NONE, isa_config) -+DEF(0x100, ARC_OPCODE_ARCALL, NONE, count1) -+DEF(0x101, ARC_OPCODE_ARCALL, NONE, control1) -+DEF(0x102, ARC_OPCODE_ARCALL, NONE, limit1) -+DEF(0x103, ARC_OPCODE_ARCV2, NONE, aux_rtc_ctrl) -+DEF(0x103, ARC_OPCODE_V3_ALL, NONE, aux_rtc_ctrl) -+DEF(0x104, ARC_OPCODE_ARCV2, NONE, aux_rtc_low) -+DEF(0x104, ARC_OPCODE_V3_ALL, NONE, aux_rtc_low) -+DEF(0x105, ARC_OPCODE_ARCV2, NONE, aux_rtc_high) -+DEF(0x105, ARC_OPCODE_V3_ALL, NONE, aux_rtc_high) -+DEF(0x200, ARC_OPCODE_ARCV1, NONE, aux_irq_lev) -+DEF(0x200, ARC_OPCODE_ARCV2, NONE, irq_priority_pending) -+DEF(0x201, ARC_OPCODE_ARCALL, NONE, aux_irq_hint) -+DEF(0x202, ARC_OPCODE_ARC600, NONE, aux_inter_core_interrupt) -+DEF(0x206, ARC_OPCODE_ARCV2, NONE, irq_priority) -+DEF(0x206, ARC_OPCODE_V3_ALL, NONE, irq_priority) -+DEF(0x210, ARC_OPCODE_ARC700, NONE, aes_aux_0) -+DEF(0x211, ARC_OPCODE_ARC700, NONE, aes_aux_1) -+DEF(0x212, ARC_OPCODE_ARC700, NONE, aes_aux_2) -+DEF(0x213, ARC_OPCODE_ARC700, NONE, aes_crypt_mode) -+DEF(0x214, ARC_OPCODE_ARC700, NONE, aes_auxs) -+DEF(0x215, ARC_OPCODE_ARC700, NONE, aes_auxi) -+DEF(0x216, ARC_OPCODE_ARC700, NONE, aes_aux_3) -+DEF(0x217, ARC_OPCODE_ARC700, NONE, aes_aux_4) -+DEF(0x218, ARC_OPCODE_ARC700, NONE, arith_ctl_aux) -+DEF(0x219, ARC_OPCODE_ARC700, NONE, des_aux) -+DEF(0x220, ARC_OPCODE_ARCALL, NONE, ap_amv0) -+DEF(0x221, ARC_OPCODE_ARCALL, NONE, ap_amm0) -+DEF(0x222, ARC_OPCODE_ARCALL, NONE, ap_ac0) -+DEF(0x223, ARC_OPCODE_ARCALL, NONE, ap_amv1) -+DEF(0x224, ARC_OPCODE_ARCALL, NONE, ap_amm1) -+DEF(0x225, ARC_OPCODE_ARCALL, NONE, ap_ac1) -+DEF(0x226, ARC_OPCODE_ARCALL, NONE, ap_amv2) -+DEF(0x227, ARC_OPCODE_ARCALL, NONE, ap_amm2) -+DEF(0x228, ARC_OPCODE_ARCALL, NONE, ap_ac2) -+DEF(0x229, ARC_OPCODE_ARCALL, NONE, ap_amv3) -+DEF(0x22a, ARC_OPCODE_ARCALL, NONE, ap_amm3) -+DEF(0x22b, ARC_OPCODE_ARCALL, NONE, ap_ac3) -+DEF(0x22c, ARC_OPCODE_ARCALL, NONE, ap_amv4) -+DEF(0x22d, ARC_OPCODE_ARCALL, NONE, ap_amm4) -+DEF(0x22e, ARC_OPCODE_ARCALL, NONE, ap_ac4) -+DEF(0x22f, ARC_OPCODE_ARCALL, NONE, ap_amv5) -+DEF(0x230, ARC_OPCODE_ARCALL, NONE, ap_amm5) -+DEF(0x231, ARC_OPCODE_ARCALL, NONE, ap_ac5) -+DEF(0x232, ARC_OPCODE_ARCALL, NONE, ap_amv6) -+DEF(0x233, ARC_OPCODE_ARCALL, NONE, ap_amm6) -+DEF(0x234, ARC_OPCODE_ARCALL, NONE, ap_ac6) -+DEF(0x235, ARC_OPCODE_ARCALL, NONE, ap_amv7) -+DEF(0x236, ARC_OPCODE_ARCALL, NONE, ap_amm7) -+DEF(0x237, ARC_OPCODE_ARCALL, NONE, ap_ac7) -+DEF(0x268, ARC_OPCODE_ARCv2EM, NONE, nsc_table_top) -+DEF(0x269, ARC_OPCODE_ARCv2EM, NONE, nsc_table_base) -+DEF(0x290, ARC_OPCODE_ARCV2, NONE, jli_base) -+DEF(0x291, ARC_OPCODE_ARCV2, NONE, ldi_base) -+DEF(0x292, ARC_OPCODE_ARCV2, NONE, ei_base) -+DEF(0x300, ARC_OPCODE_ARCFPX, DPX, fp_status) -+/* -+DEF (0x301, ARC_OPCODE_ARCFPX, DPX, aux_dpfp1l) -+DEF (0x301, ARC_OPCODE_ARCFPX, DPX, d1l) -+*/ -+/* -+DEF (0x302, ARC_OPCODE_ARCFPX, DPX, aux_dpfp1h) -+DEF (0x302, ARC_OPCODE_ARCFPX, DPX, d1h) -+*/ -+DEF(0x302, ARC_OPCODE_ARCv2EM, DPA, d1l) -+/* -+DEF (0x303, ARC_OPCODE_ARCFPX, DPX, aux_dpfp2l) -+DEF (0x303, ARC_OPCODE_ARCFPX, DPX, d2l) -+*/ -+DEF(0x303, ARC_OPCODE_ARCv2EM, DPA, d1h) -+/* -+DEF (0x304, ARC_OPCODE_ARCFPX, DPX, aux_dpfp2h) -+DEF (0x304, ARC_OPCODE_ARCFPX, DPX, d2h) -+*/ -+DEF(0x304, ARC_OPCODE_ARCv2EM, DPA, d2l) -+DEF(0x305, ARC_OPCODE_ARCFPX, DPX, dpfp_status) -+DEF(0x305, ARC_OPCODE_ARCv2EM, DPA, d2h) -+DEF(0x400, ARC_OPCODE_ARCALL, NONE, eret) -+DEF(0x401, ARC_OPCODE_ARCALL, NONE, erbta) -+DEF(0x402, ARC_OPCODE_ARCALL, NONE, erstatus) -+DEF(0x403, ARC_OPCODE_ARCALL, NONE, ecr) -+DEF(0x404, ARC_OPCODE_ARCALL, NONE, efa) -+DEF(0x405, ARC_OPCODE_ARC700, NONE, tlbpd0) -+DEF(0x406, ARC_OPCODE_ARC700, NONE, tlbpd1) -+DEF(0x406, ARC_OPCODE_ARCv2EM, NONE, ersec_stat) -+DEF(0x407, ARC_OPCODE_ARCv2EM, NONE, aux_sec_except) -+DEF(0x407, ARC_OPCODE_ARC700, NONE, tlbindex) -+DEF(0x408, ARC_OPCODE_ARC700, NONE, tlbcommand) -+DEF(0x409, ARC_OPCODE_ARC700, NONE, pid) -+DEF(0x409, ARC_OPCODE_ARCALL, NONE, mpuen) -+DEF(0x40a, ARC_OPCODE_ARCV2, NONE, icause) -+DEF(0x40a, ARC_OPCODE_V3_ALL, NONE, icause) -+DEF(0x40b, ARC_OPCODE_ARCV2, NONE, irq_select) -+DEF(0x40b, ARC_OPCODE_V3_ALL, NONE, irq_select) -+DEF(0x40c, ARC_OPCODE_ARCV2, NONE, irq_enable) -+DEF(0x40c, ARC_OPCODE_V3_ALL, NONE, irq_enable) -+DEF(0x40d, ARC_OPCODE_ARCV2, NONE, irq_trigger) -+DEF(0x40d, ARC_OPCODE_V3_ALL, NONE, irq_trigger) -+DEF(0x40f, ARC_OPCODE_ARCV2, NONE, irq_status) -+DEF(0x40f, ARC_OPCODE_V3_ALL, NONE, irq_status) -+DEF(0x410, ARC_OPCODE_ARCALL, NONE, xpu) -+DEF(0x412, ARC_OPCODE_ARCALL, NONE, bta) -+DEF(0x413, ARC_OPCODE_ARC700, NONE, bta_l1) -+DEF(0x414, ARC_OPCODE_ARC700, NONE, bta_l2) -+DEF(0x415, ARC_OPCODE_ARCV2, NONE, irq_pulse_cancel) -+DEF(0x416, ARC_OPCODE_ARCV2, NONE, irq_pending) -+DEF(0x418, ARC_OPCODE_ARC700, NONE, scratch_data0) -+DEF(0x420, ARC_OPCODE_ARCALL, NONE, mpuic) -+DEF(0x421, ARC_OPCODE_ARCALL, NONE, mpufa) -+DEF(0x422, ARC_OPCODE_ARCALL, NONE, mpurdb0) -+DEF(0x423, ARC_OPCODE_ARCALL, NONE, mpurdp0) -+DEF(0x424, ARC_OPCODE_ARCALL, NONE, mpurdb1) -+DEF(0x425, ARC_OPCODE_ARCALL, NONE, mpurdp1) -+DEF(0x426, ARC_OPCODE_ARCALL, NONE, mpurdb2) -+DEF(0x427, ARC_OPCODE_ARCALL, NONE, mpurdp2) -+DEF(0x428, ARC_OPCODE_ARCALL, NONE, mpurdb3) -+DEF(0x429, ARC_OPCODE_ARCALL, NONE, mpurdp3) -+DEF(0x42a, ARC_OPCODE_ARCALL, NONE, mpurdb4) -+DEF(0x42b, ARC_OPCODE_ARCALL, NONE, mpurdp4) -+DEF(0x42c, ARC_OPCODE_ARCALL, NONE, mpurdb5) -+DEF(0x42d, ARC_OPCODE_ARCALL, NONE, mpurdp5) -+DEF(0x42e, ARC_OPCODE_ARCALL, NONE, mpurdb6) -+DEF(0x42f, ARC_OPCODE_ARCALL, NONE, mpurdp6) -+DEF(0x430, ARC_OPCODE_ARCALL, NONE, mpurdb7) -+DEF(0x431, ARC_OPCODE_ARCALL, NONE, mpurdp7) -+DEF(0x432, ARC_OPCODE_ARCALL, NONE, mpurdb8) -+DEF(0x433, ARC_OPCODE_ARCALL, NONE, mpurdp8) -+DEF(0x434, ARC_OPCODE_ARCALL, NONE, mpurdb9) -+DEF(0x435, ARC_OPCODE_ARCALL, NONE, mpurdp9) -+DEF(0x436, ARC_OPCODE_ARCALL, NONE, mpurdb10) -+DEF(0x437, ARC_OPCODE_ARCALL, NONE, mpurdp10) -+DEF(0x438, ARC_OPCODE_ARCALL, NONE, mpurdb11) -+DEF(0x439, ARC_OPCODE_ARCALL, NONE, mpurdp11) -+DEF(0x43a, ARC_OPCODE_ARCALL, NONE, mpurdb12) -+DEF(0x43b, ARC_OPCODE_ARCALL, NONE, mpurdp12) -+DEF(0x43c, ARC_OPCODE_ARCALL, NONE, mpurdb13) -+DEF(0x43d, ARC_OPCODE_ARCALL, NONE, mpurdp13) -+DEF(0x43e, ARC_OPCODE_ARCALL, NONE, mpurdb14) -+DEF(0x43f, ARC_OPCODE_ARCALL, NONE, mpurdp14) -+DEF(0x440, ARC_OPCODE_ARCALL, NONE, mpurdb15) -+DEF(0x441, ARC_OPCODE_ARCALL, NONE, mpurdp15) -+DEF(0x450, ARC_OPCODE_ARC600, NONE, pm_status) -+DEF(0x451, ARC_OPCODE_ARC600, NONE, wake) -+DEF(0x452, ARC_OPCODE_ARC600, NONE, dvfs_performance) -+DEF(0x453, ARC_OPCODE_ARC600, NONE, pwr_ctrl) -+DEF(0x460, ARC_OPCODE_ARCv2HS, NONE, tlbpd0) -+DEF(0x461, ARC_OPCODE_ARCv2HS, NONE, tlbpd1) -+DEF(0x463, ARC_OPCODE_ARCv2HS, NONE, tlbpd1_hi) -+DEF(0x464, ARC_OPCODE_ARCv2HS, NONE, tlbindex) -+DEF(0x465, ARC_OPCODE_ARCv2HS, NONE, tlbcommand) -+DEF(0x468, ARC_OPCODE_ARCv2HS, NONE, pid) -+DEF(0x46a, ARC_OPCODE_ARCv2HS, NONE, sasid0) -+DEF(0x46b, ARC_OPCODE_ARCv2HS, NONE, sasid1) -+DEF(0x46c, ARC_OPCODE_ARCv2HS, NONE, scratch_data0) -+DEF(0x500, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_idx) -+DEF(0x501, ARC_OPCODE_ARC700, NONE, aux_vlc_read_buf) -+DEF(0x502, ARC_OPCODE_ARC700, NONE, aux_vlc_valid_bits) -+DEF(0x503, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_in) -+DEF(0x504, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_free) -+DEF(0x505, ARC_OPCODE_ARC700, NONE, aux_vlc_ibuf_status) -+DEF(0x506, ARC_OPCODE_ARC700, NONE, aux_vlc_setup) -+DEF(0x507, ARC_OPCODE_ARC700, NONE, aux_vlc_bits) -+DEF(0x508, ARC_OPCODE_ARC700, NONE, aux_vlc_table) -+DEF(0x509, ARC_OPCODE_ARC700, NONE, aux_vlc_get_symbol) -+DEF(0x50a, ARC_OPCODE_ARC700, NONE, aux_vlc_read_symbol) -+DEF(0x510, ARC_OPCODE_ARC700, NONE, aux_ucavlc_setup) -+DEF(0x511, ARC_OPCODE_ARC700, NONE, aux_ucavlc_state) -+DEF(0x512, ARC_OPCODE_ARC700, NONE, aux_cavlc_zero_left) -+DEF(0x514, ARC_OPCODE_ARC700, NONE, aux_uvlc_i_state) -+DEF(0x51c, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_ptr) -+DEF(0x51d, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_end) -+DEF(0x51e, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_esc) -+DEF(0x51f, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_ctrl) -+DEF(0x520, ARC_OPCODE_ARC700, NONE, aux_vlc_get_0bit) -+DEF(0x521, ARC_OPCODE_ARC700, NONE, aux_vlc_get_1bit) -+DEF(0x522, ARC_OPCODE_ARC700, NONE, aux_vlc_get_2bit) -+DEF(0x523, ARC_OPCODE_ARC700, NONE, aux_vlc_get_3bit) -+DEF(0x524, ARC_OPCODE_ARC700, NONE, aux_vlc_get_4bit) -+DEF(0x525, ARC_OPCODE_ARC700, NONE, aux_vlc_get_5bit) -+DEF(0x526, ARC_OPCODE_ARC700, NONE, aux_vlc_get_6bit) -+DEF(0x527, ARC_OPCODE_ARC700, NONE, aux_vlc_get_7bit) -+DEF(0x528, ARC_OPCODE_ARC700, NONE, aux_vlc_get_8bit) -+DEF(0x529, ARC_OPCODE_ARC700, NONE, aux_vlc_get_9bit) -+DEF(0x52a, ARC_OPCODE_ARC700, NONE, aux_vlc_get_10bit) -+DEF(0x52b, ARC_OPCODE_ARC700, NONE, aux_vlc_get_11bit) -+DEF(0x52c, ARC_OPCODE_ARC700, NONE, aux_vlc_get_12bit) -+DEF(0x52d, ARC_OPCODE_ARC700, NONE, aux_vlc_get_13bit) -+DEF(0x52e, ARC_OPCODE_ARC700, NONE, aux_vlc_get_14bit) -+DEF(0x52f, ARC_OPCODE_ARC700, NONE, aux_vlc_get_15bit) -+DEF(0x530, ARC_OPCODE_ARC700, NONE, aux_vlc_get_16bit) -+DEF(0x531, ARC_OPCODE_ARC700, NONE, aux_vlc_get_17bit) -+DEF(0x532, ARC_OPCODE_ARC700, NONE, aux_vlc_get_18bit) -+DEF(0x533, ARC_OPCODE_ARC700, NONE, aux_vlc_get_19bit) -+DEF(0x534, ARC_OPCODE_ARC700, NONE, aux_vlc_get_20bit) -+DEF(0x535, ARC_OPCODE_ARC700, NONE, aux_vlc_get_21bit) -+DEF(0x536, ARC_OPCODE_ARC700, NONE, aux_vlc_get_22bit) -+DEF(0x537, ARC_OPCODE_ARC700, NONE, aux_vlc_get_23bit) -+DEF(0x538, ARC_OPCODE_ARC700, NONE, aux_vlc_get_24bit) -+DEF(0x539, ARC_OPCODE_ARC700, NONE, aux_vlc_get_25bit) -+DEF(0x53a, ARC_OPCODE_ARC700, NONE, aux_vlc_get_26bit) -+DEF(0x53b, ARC_OPCODE_ARC700, NONE, aux_vlc_get_27bit) -+DEF(0x53c, ARC_OPCODE_ARC700, NONE, aux_vlc_get_28bit) -+DEF(0x53d, ARC_OPCODE_ARC700, NONE, aux_vlc_get_29bit) -+DEF(0x53e, ARC_OPCODE_ARC700, NONE, aux_vlc_get_30bit) -+DEF(0x53f, ARC_OPCODE_ARC700, NONE, aux_vlc_get_31bit) -+DEF(0x540, ARC_OPCODE_ARC700, NONE, aux_cabac_ctrl) -+DEF(0x541, ARC_OPCODE_ARC700, NONE, aux_cabac_ctx_state) -+DEF(0x542, ARC_OPCODE_ARC700, NONE, aux_cabac_cod_param) -+DEF(0x543, ARC_OPCODE_ARC700, NONE, aux_cabac_misc0) -+DEF(0x544, ARC_OPCODE_ARC700, NONE, aux_cabac_misc1) -+DEF(0x545, ARC_OPCODE_ARC700, NONE, aux_cabac_misc2) -+DEF(0x700, ARC_OPCODE_ARCALL, NONE, smart_control) -+/* -+DEF (0x701, ARC_OPCODE_ARC700, NONE, smart_data_0) -+DEF (0x701, ARC_OPCODE_ARC600, NONE, smart_data) -+DEF (0x701, ARC_OPCODE_ARC700, NONE, smart_data_2) -+DEF (0x701, ARC_OPCODE_ARC700, NONE, smart_data_3) -+*/ -+ -+ -+/* BCR aux registers */ -+DEF(0x60, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x61, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x62, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x63, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x64, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x65, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x66, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x67, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x68, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x69, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x6a, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x6b, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x6c, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x6d, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x6e, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x6f, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x70, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x71, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x72, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x73, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x74, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x75, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x76, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x77, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x78, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x79, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x7a, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x7c, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x7d, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x7e, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0x7f, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc0, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc1, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc2, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc3, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc4, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc5, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc6, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc7, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc8, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xc9, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xca, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xcb, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xcc, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xcd, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xce, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xcf, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd0, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd1, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd2, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd3, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd4, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd5, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd6, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd7, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd8, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xd9, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xda, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xdb, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xdc, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xdd, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xde, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xdf, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe0, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe1, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe2, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe3, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe4, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe5, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe6, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe7, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe8, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xe9, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xea, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xeb, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xec, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xed, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xee, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xef, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf0, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf1, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf2, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf3, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf4, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf5, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf6, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf7, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf8, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xf9, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xfa, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xfb, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xfc, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xfd, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xfe, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+DEF(0xff, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) -+ -+/* Actual BCR implementations */ -+ -+DEF(0x6d, ARC_OPCODE_ARCv2HS, NONE, mpu_build) -+DEF(0x6d, ARC_OPCODE_V3_ALL, NONE, mpu_build) -+DEF(0x6f, ARC_OPCODE_ARCv2HS, NONE, mmu_build) -+DEF(0x75, ARC_OPCODE_ARCALL, NONE, timer_build) -+DEF(0xf3, ARC_OPCODE_ARCV2, NONE, irq_build) -+DEF(0xf3, ARC_OPCODE_V3_ALL, NONE, irq_build) -+DEF(0x72, ARC_OPCODE_ARCV2, NONE, d_cache_build) -+DEF(0x72, ARC_OPCODE_V3_ALL, NONE, d_cache_build) -+DEF(0x77, ARC_OPCODE_ARCV2, NONE, i_cache_build) -+DEF(0x77, ARC_OPCODE_V3_ALL, NONE, i_cache_build) -+DEF(0x7b, ARC_OPCODE_ARCV2, NONE, mpy_build) -+DEF(0x7b, ARC_OPCODE_V3_ALL, NONE, mpy_build) -+ -+/* OLD BCR definitions */ -+/* -+DEF (0x61, ARC_OPCODE_ARCALL, NONE, dccm_base_build) -+DEF (0x63, ARC_OPCODE_ARCALL, NONE, bta_link_build) -+DEF (0x64, ARC_OPCODE_ARCALL, NONE, vbfdw_build) -+DEF (0x65, ARC_OPCODE_ARCALL, NONE, ea_build) -+DEF (0x66, ARC_OPCODE_ARCALL, NONE, dataspace) -+DEF (0x67, ARC_OPCODE_ARCALL, NONE, memsubsys) -+DEF (0x68, ARC_OPCODE_ARCALL, NONE, vecbase_ac_build) -+DEF (0x69, ARC_OPCODE_ARCALL, NONE, p_base_addr) -+DEF (0x6a, ARC_OPCODE_ARCALL, NONE, data_uncached_build) -+DEF (0x6b, ARC_OPCODE_ARCALL, NONE, fp_build) -+DEF (0x6c, ARC_OPCODE_ARCALL, NONE, dpfp_build) -+DEF (0x6d, ARC_OPCODE_ARCALL, NONE, mpu_build) -+DEF (0x6e, ARC_OPCODE_ARCALL, NONE, rf_build) -+DEF (0x6f, ARC_OPCODE_ARCALL, NONE, mmu_build) -+DEF (0x70, ARC_OPCODE_ARCv2EM, NONE, sec_vecbase_build) -+DEF (0x71, ARC_OPCODE_ARCALL, NONE, vecbase_build) -+DEF (0x73, ARC_OPCODE_ARCALL, NONE, madi_build) -+ -+DEF (0xc1, ARC_OPCODE_ARC600, NONE, arc600_build_config) -+DEF (0xc2, ARC_OPCODE_ARCALL, NONE, isa_config) -+DEF (0xf4, ARC_OPCODE_ARCALL, NONE, hwp_build) -+DEF (0xf5, ARC_OPCODE_ARCALL, NONE, pct_build) -+DEF (0xf6, ARC_OPCODE_ARCALL, NONE, cc_build) -+DEF (0xf7, ARC_OPCODE_ARCALL, NONE, pm_bcr) -+DEF (0xf8, ARC_OPCODE_ARCALL, NONE, scq_switch_build) -+DEF (0xf9, ARC_OPCODE_ARCALL, NONE, vraptor_build) -+DEF (0xfa, ARC_OPCODE_ARCALL, NONE, dma_config) -+DEF (0xfb, ARC_OPCODE_ARCALL, NONE, simd_config) -+DEF (0xfc, ARC_OPCODE_ARCALL, NONE, vlc_build) -+DEF (0xfd, ARC_OPCODE_ARCALL, NONE, simd_dma_build) -+DEF (0xfe, ARC_OPCODE_ARCALL, NONE, ifetch_queue_build) -+*/ -+ -+/* ARCV3 definitions. */ -+ -+DEF (0x7, ARC_OPCODE_V3_ALL, NONE, memseg) -+DEF (0x16, ARC_OPCODE_V3_ALL, NONE, ic_ivir) -+DEF (0x17, ARC_OPCODE_V3_ALL, NONE, ic_endr) -+DEF (0x460, ARC_OPCODE_V3_ALL, NONE, mmu_rtp0) -+DEF (0x461, ARC_OPCODE_V3_ALL, NONE, mmu_rtp0hi) -+DEF (0x462, ARC_OPCODE_V3_ALL, NONE, mmu_rtp1) -+DEF (0x463, ARC_OPCODE_V3_ALL, NONE, mmu_rtp1hi) -+DEF (0x464, ARC_OPCODE_V3_ALL, NONE, tlbindex) -+DEF (0x465, ARC_OPCODE_V3_ALL, NONE, mmuv6_tlbcommand) -+DEF (0x466, ARC_OPCODE_V3_ALL, NONE, mmu_tlb_data0) -+DEF (0x467, ARC_OPCODE_V3_ALL, NONE, mmu_tlb_data1) -+DEF (0x468, ARC_OPCODE_V3_ALL, NONE, mmu_ctrl) -+DEF (0x469, ARC_OPCODE_V3_ALL, NONE, mmu_ttbcr) -+DEF (0x46a, ARC_OPCODE_V3_ALL, NONE, mmu_mem_attr) -+DEF (0x46b, ARC_OPCODE_V3_ALL, NONE, mmu_fault_status) -+DEF (0xc1, ARC_OPCODE_V3_ALL, NONE, isa_config) -+DEF (0x6f, ARC_OPCODE_V3_ALL, NONE, mmuv6_build) -+DEF (0x7f0, ARC_OPCODE_V3_ALL, NONE, hw_pf_build) -+DEF (0x4f, ARC_OPCODE_V3_ALL, NONE, hw_pf_ctrl) -diff --git a/target/arc/regs-impl.c b/target/arc/regs-impl.c -new file mode 100644 -index 0000000000..d168790aa0 ---- /dev/null -+++ b/target/arc/regs-impl.c -@@ -0,0 +1,200 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "qemu/log.h" -+#include "qemu/error-report.h" -+#include "target/arc/regs.h" -+#include "target/arc/mmu.h" -+#include "target/arc/mpu.h" -+#include "target/arc/irq.h" -+#include "target/arc/timer.h" -+#include "target/arc/cache.h" -+ -+static target_ulong get_identity(CPUARCState *env) -+{ -+ target_ulong chipid = 0xffff, arcnum = 0, arcver, res; -+ ARCCPU *cpu = env_archcpu(env); -+ -+ switch (cpu->family) { -+ case ARC_OPCODE_ARC700: -+ arcver = 0x34; -+ break; -+ -+ case ARC_OPCODE_ARCv2EM: -+ arcver = 0x44; -+ break; -+ -+ case ARC_OPCODE_ARCv2HS: -+ arcver = 0x54; -+ break; -+ -+ /* TODO: Add V3/ARC32. */ -+ case ARC_OPCODE_V3_ARC64: -+ arcver = 0x70; -+ break; -+ -+ default: -+ arcver = 0; -+ -+ } -+ -+ /* TODO: in SMP, arcnum depends on the cpu instance. */ -+ res = ((chipid & 0xFFFF) << 16) | ((arcnum & 0xFF) << 8) | (arcver & 0xFF); -+ return res; -+} -+ -+target_ulong -+arc_general_regs_get(const struct arc_aux_reg_detail *aux_reg_detail, -+ void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ ARCCPU *cpu = env_archcpu(env); -+ target_ulong reg = 0; -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_aux_volatile: -+ reg = 0xc0000000; -+ break; -+ -+ case AUX_ID_lp_start: -+ reg = env->lps; -+ break; -+ -+ case AUX_ID_lp_end: -+ reg = env->lpe; -+ break; -+ -+ case AUX_ID_identity: -+ reg = get_identity(env); -+ break; -+ -+ case AUX_ID_exec_ctrl: -+ reg = 0; -+ break; -+ -+ case AUX_ID_debug: -+ reg = 0; -+ break; -+ -+ case AUX_ID_pc: -+ reg = env->pc & 0xfffffffe; -+ break; -+ -+ case AUX_ID_mpy_build: -+ reg = cpu->mpy_build; -+ break; -+ -+ case AUX_ID_isa_config: -+ reg = cpu->isa_config; -+ break; -+ -+ case AUX_ID_eret: -+ reg = env->eret; -+ break; -+ -+ case AUX_ID_erbta: -+ reg = env->erbta; -+ break; -+ -+ case AUX_ID_ecr: -+ reg = env->ecr; -+ break; -+ -+ case AUX_ID_efa: -+ reg = env->efa; -+ break; -+ -+ case AUX_ID_bta: -+ reg = env->bta; -+ break; -+ -+ case AUX_ID_bta_l1: -+ reg = env->bta_l1; -+ break; -+ -+ case AUX_ID_bta_l2: -+ reg = env->bta_l2; -+ break; -+ -+ case AUX_ID_hw_pf_build: -+ reg = 1 << 28; /* version */ -+ break; -+ -+ case AUX_ID_hw_pf_ctrl: -+ reg = (0) /* EN */ -+ | (1 << 1) /* RD_ST */ -+ | (1 << 3) /* WR_ST */ -+ | (3 << 5) /* OUTS */ -+ | (0 << 7); /* AG */ -+ -+ break; -+ -+ case AUX_ID_unimp_bcr: -+ /* TODO: raise instruction error here */ -+ reg = 0; -+ break; -+ -+ default: -+ break; -+ } -+ -+ return reg; -+} -+ -+void -+arc_general_regs_set(const struct arc_aux_reg_detail *aux_reg_detail, -+ target_ulong val, void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_lp_start: -+ env->lps = val; -+ break; -+ -+ case AUX_ID_lp_end: -+ env->lpe = val; -+ break; -+ -+ case AUX_ID_eret: -+ env->eret = val; -+ break; -+ -+ case AUX_ID_erbta: -+ env->erbta = val; -+ break; -+ -+ case AUX_ID_bta: -+ env->bta = val; -+ break; -+ -+ case AUX_ID_ecr: -+ env->ecr = val; -+ break; -+ -+ case AUX_ID_efa: -+ env->efa = val; -+ break; -+ -+ default: -+ break; -+ } -+} -diff --git a/target/arc/regs.c b/target/arc/regs.c -new file mode 100644 -index 0000000000..5374a93f62 ---- /dev/null -+++ b/target/arc/regs.c -@@ -0,0 +1,183 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "qemu/log.h" -+#include "qemu/error-report.h" -+#include "target/arc/regs.h" -+#include "target/arc/mmu.h" -+#include "target/arc/mpu.h" -+#include "target/arc/irq.h" -+#include "target/arc/timer.h" -+#include "target/arc/cache.h" -+ -+struct arc_aux_reg_detail arc_aux_regs_detail[ARC_AUX_REGS_DETAIL_LAST] = { -+#define DEF(NUM, CPU, SUB, NAME) \ -+ { \ -+ NUM, \ -+ (CPU), \ -+ SUB, \ -+ AUX_ID_##NAME, \ -+ #NAME, \ -+ sizeof(#NAME) - 1, \ -+ NULL, \ -+ NULL, \ -+ }, -+#include "target/arc/regs-detail.def" -+#undef DEF -+}; -+ -+struct arc_aux_reg arc_aux_regs[ARC_AUX_REGS_LAST] = { -+#define AUX_REG_GETTER(GET_FUNC) -+#define AUX_REG_SETTER(SET_FUNC) -+#define AUX_REG(NAME, GET_FUNC, SET_FUNC) \ -+ { \ -+ NULL, \ -+ GET_FUNC, \ -+ SET_FUNC \ -+ }, -+#include "target/arc/regs.def" -+#undef AUX_REG -+#undef AUX_REG_GETTER -+#undef AUX_REG_SETTER -+}; -+ -+const char *arc_aux_reg_name[ARC_AUX_REGS_DETAIL_LAST] = { -+#define AUX_REG_GETTER(GET_FUNC) -+#define AUX_REG_SETTER(SET_FUNC) -+#define AUX_REG(NAME, GET, SET) #NAME, -+#include "target/arc/regs.def" -+#undef AUX_REG -+#undef AUX_REG_GETTER -+#undef AUX_REG_SETTER -+ "last_invalid_aux_reg" -+}; -+ -+ -+void arc_aux_regs_init(void) -+{ -+ int i; -+ -+ for (i = 0; i < ARC_AUX_REGS_DETAIL_LAST; i++) { -+ enum arc_aux_reg_enum id = arc_aux_regs_detail[i].id; -+ struct arc_aux_reg_detail *next = arc_aux_regs[id].first; -+ arc_aux_regs_detail[i].next = next; -+ arc_aux_regs_detail[i].aux_reg = &(arc_aux_regs[id]); -+ arc_aux_regs[id].first = &(arc_aux_regs_detail[i]); -+ } -+} -+ -+int -+arc_aux_reg_address_for(enum arc_aux_reg_enum aux_reg_def, -+ int isa_mask) -+{ -+ /* TODO: This must validate for CPU. */ -+ struct arc_aux_reg_detail *detail = arc_aux_regs[aux_reg_def].first; -+ while (detail != NULL) { -+ if ((detail->cpu & isa_mask) != 0) { -+ return detail->address; -+ } -+ detail = detail->next; -+ } -+ assert(0); -+ -+ /* We never get here but to accommodate -Werror ... */ -+ return 0; -+} -+ -+struct arc_aux_reg_detail * -+arc_aux_reg_struct_for_address(int address, int isa_mask) -+{ -+ int i; -+ bool has_default = false; -+ struct arc_aux_reg_detail *default_ret = NULL; -+ -+ /* TODO: Make this a binary search or something faster. */ -+ for (i = 0; i < ARC_AUX_REGS_DETAIL_LAST; i++) { -+ if (arc_aux_regs_detail[i].address == address) { -+ if (arc_aux_regs_detail[i].cpu == ARC_OPCODE_DEFAULT) { -+ has_default = true; -+ default_ret = &(arc_aux_regs_detail[i]); -+ } else if ((arc_aux_regs_detail[i].cpu & isa_mask) != 0) { -+ return &(arc_aux_regs_detail[i]); -+ } -+ } -+ } -+ -+ if (has_default == true) { -+ return default_ret; -+ } -+ -+ return NULL; -+} -+ -+const char *get_auxreg(const struct arc_opcode *opcode, -+ int value, -+ unsigned isa_mask) -+{ -+ unsigned int i; -+ const struct arc_aux_reg_detail *auxr = &arc_aux_regs_detail[0]; -+ -+ if (opcode->insn_class != AUXREG) { -+ return NULL; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(arc_aux_regs); i++, auxr++) { -+ if (!(auxr->cpu & isa_mask)) { -+ continue; -+ } -+ -+ if (auxr->subclass != NONE) { -+ return NULL; -+ } -+ -+ if (auxr->address == value) { -+ return auxr->name; -+ } -+ } -+ return NULL; -+} -+ -+target_ulong __not_implemented_getter( -+ const struct arc_aux_reg_detail *aux_reg_detail ATTRIBUTE_UNUSED, -+ void *data ATTRIBUTE_UNUSED) { -+ assert("SOME AUX_REG_GETTER NOT IMPLEMENTED " == 0); -+} -+void __not_implemented_setter( -+ const struct arc_aux_reg_detail *aux_reg_detail ATTRIBUTE_UNUSED, -+ target_ulong value ATTRIBUTE_UNUSED, -+ void *data ATTRIBUTE_UNUSED) { -+ assert("SOME AUX_REG_SETTER NOT IMPLEMENTED " == 0); -+} -+ -+#define AUX_REG_GETTER(GET_FUNC) \ -+ target_ulong GET_FUNC(const struct arc_aux_reg_detail *a, void *b) \ -+ __attribute__ ((weak, alias("__not_implemented_getter"))); -+#define AUX_REG_SETTER(SET_FUNC) \ -+ void SET_FUNC(const struct arc_aux_reg_detail *a, target_ulong b, \ -+ void *c) \ -+ __attribute__ ((weak, alias("__not_implemented_setter"))); -+#define AUX_REG(NAME, GET, SET) -+ -+#include "target/arc/regs.def" -+ -+#undef AUX_REG -+#undef AUX_REG_GETTER -+#undef AUX_REG_SETTER -diff --git a/target/arc/regs.def b/target/arc/regs.def -new file mode 100644 -index 0000000000..2fd885969a ---- /dev/null -+++ b/target/arc/regs.def -@@ -0,0 +1,434 @@ -+/* -+ * QEMU ARC Auxiliary register definitions -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * Contributed by Claudiu Zissulescu (claziss@synopsys.com) -+ * Contributed by Cupertino Miranda (cmiranda@synopsys.com) -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+AUX_REG_GETTER(arc_general_regs_get) -+AUX_REG_SETTER(arc_general_regs_set) -+AUX_REG_GETTER(arc_status_regs_get) -+AUX_REG_SETTER(arc_status_regs_set) -+AUX_REG_GETTER(aux_irq_get) -+AUX_REG_SETTER(aux_irq_set) -+AUX_REG_GETTER(aux_timer_get) -+AUX_REG_SETTER(aux_timer_set) -+AUX_REG_GETTER(arc_cache_aux_get) -+AUX_REG_SETTER(arc_cache_aux_set) -+AUX_REG_GETTER(arc_mpu_aux_get) -+AUX_REG_SETTER(arc_mpu_aux_set) -+AUX_REG_GETTER(arc_mmu_aux_get) -+AUX_REG_SETTER(arc_mmu_aux_set) -+AUX_REG_SETTER(arc_mmu_aux_set_tlbcmd) -+ -+AUX_REG (unimp_bcr, arc_general_regs_get, NULL) -+AUX_REG (acg_ctrl, NULL, NULL) -+AUX_REG (acr, NULL, NULL) -+AUX_REG (adcr, NULL, NULL) -+AUX_REG (aes_aux_0, NULL, NULL) -+AUX_REG (aes_aux_1, NULL, NULL) -+AUX_REG (aes_aux_2, NULL, NULL) -+AUX_REG (aes_aux_3, NULL, NULL) -+AUX_REG (aes_aux_4, NULL, NULL) -+AUX_REG (aes_auxi, NULL, NULL) -+AUX_REG (aes_auxs, NULL, NULL) -+AUX_REG (aes_crypt_mode, NULL, NULL) -+AUX_REG (ap_ac0, NULL, NULL) -+AUX_REG (ap_ac1, NULL, NULL) -+AUX_REG (ap_ac2, NULL, NULL) -+AUX_REG (ap_ac3, NULL, NULL) -+AUX_REG (ap_ac4, NULL, NULL) -+AUX_REG (ap_ac5, NULL, NULL) -+AUX_REG (ap_ac6, NULL, NULL) -+AUX_REG (ap_ac7, NULL, NULL) -+AUX_REG (ap_amm0, NULL, NULL) -+AUX_REG (ap_amm1, NULL, NULL) -+AUX_REG (ap_amm2, NULL, NULL) -+AUX_REG (ap_amm3, NULL, NULL) -+AUX_REG (ap_amm4, NULL, NULL) -+AUX_REG (ap_amm5, NULL, NULL) -+AUX_REG (ap_amm6, NULL, NULL) -+AUX_REG (ap_amm7, NULL, NULL) -+AUX_REG (ap_amv0, NULL, NULL) -+AUX_REG (ap_amv1, NULL, NULL) -+AUX_REG (ap_amv2, NULL, NULL) -+AUX_REG (ap_amv3, NULL, NULL) -+AUX_REG (ap_amv4, NULL, NULL) -+AUX_REG (ap_amv5, NULL, NULL) -+AUX_REG (ap_amv6, NULL, NULL) -+AUX_REG (ap_amv7, NULL, NULL) -+AUX_REG (apcr, NULL, NULL) -+AUX_REG (arc600_build_config, NULL, NULL) -+AUX_REG (arith_ctl_aux, NULL, NULL) -+AUX_REG (aux_cabac_cod_param, NULL, NULL) -+AUX_REG (aux_cabac_ctrl, NULL, NULL) -+AUX_REG (aux_cabac_ctx_state, NULL, NULL) -+AUX_REG (aux_cabac_misc0, NULL, NULL) -+AUX_REG (aux_cabac_misc1, NULL, NULL) -+AUX_REG (aux_cabac_misc2, NULL, NULL) -+AUX_REG (aux_cavlc_zero_left, NULL, NULL) -+AUX_REG (aux_crc_mode, NULL, NULL) -+AUX_REG (aux_crc_poly, NULL, NULL) -+AUX_REG (aux_dccm, NULL, NULL) -+AUX_REG (aux_dpfp1h, NULL, NULL) -+AUX_REG (aux_dpfp1l, NULL, NULL) -+AUX_REG (aux_dpfp2h, NULL, NULL) -+AUX_REG (aux_dpfp2l, NULL, NULL) -+AUX_REG (aux_fbf_store_16, NULL, NULL) -+AUX_REG (aux_inter_core_interrupt, NULL, NULL) -+AUX_REG (irq_priority, aux_irq_get, aux_irq_set) -+AUX_REG (aux_irq_act, aux_irq_get, aux_irq_set) -+AUX_REG (aux_irq_hint, aux_irq_get, aux_irq_set) -+AUX_REG (aux_irq_lev, NULL, NULL) -+AUX_REG (aux_irq_lv12, NULL, NULL) -+AUX_REG (irq_pending, aux_irq_get, NULL) -+AUX_REG (irq_pulse_cancel, NULL, aux_irq_set) -+AUX_REG (aux_irq_ctrl, aux_irq_get, aux_irq_set) -+AUX_REG (aux_kernel_sp, NULL, NULL) -+AUX_REG (aux_ldst_ram, NULL, NULL) -+AUX_REG (aux_macmode, NULL, NULL) -+AUX_REG (aux_sec_ctrl, NULL, NULL) -+AUX_REG (aux_sec_except, NULL, NULL) -+AUX_REG (aux_sec_k_sp, NULL, NULL) -+AUX_REG (aux_sec_u_sp, NULL, NULL) -+AUX_REG (aux_ucavlc_setup, NULL, NULL) -+AUX_REG (aux_ucavlc_state, NULL, NULL) -+AUX_REG (aux_user_sp, aux_irq_get, aux_irq_set) -+AUX_REG (aux_uvlc_i_state, NULL, NULL) -+AUX_REG (aux_vbfdw_accu, NULL, NULL) -+AUX_REG (aux_vbfdw_bm0, NULL, NULL) -+AUX_REG (aux_vbfdw_bm1, NULL, NULL) -+AUX_REG (aux_vbfdw_intstat, NULL, NULL) -+AUX_REG (aux_vbfdw_mode, NULL, NULL) -+AUX_REG (aux_vbfdw_ofst, NULL, NULL) -+AUX_REG (aux_volatile, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (aux_vlc_bits, NULL, NULL) -+AUX_REG (aux_vlc_buf_free, NULL, NULL) -+AUX_REG (aux_vlc_buf_idx, NULL, NULL) -+AUX_REG (aux_vlc_buf_in, NULL, NULL) -+AUX_REG (aux_vlc_dma_ctrl, NULL, NULL) -+AUX_REG (aux_vlc_dma_end, NULL, NULL) -+AUX_REG (aux_vlc_dma_esc, NULL, NULL) -+AUX_REG (aux_vlc_dma_ptr, NULL, NULL) -+AUX_REG (aux_vlc_get_0bit, NULL, NULL) -+AUX_REG (aux_vlc_get_10bit, NULL, NULL) -+AUX_REG (aux_vlc_get_11bit, NULL, NULL) -+AUX_REG (aux_vlc_get_12bit, NULL, NULL) -+AUX_REG (aux_vlc_get_13bit, NULL, NULL) -+AUX_REG (aux_vlc_get_14bit, NULL, NULL) -+AUX_REG (aux_vlc_get_15bit, NULL, NULL) -+AUX_REG (aux_vlc_get_16bit, NULL, NULL) -+AUX_REG (aux_vlc_get_17bit, NULL, NULL) -+AUX_REG (aux_vlc_get_18bit, NULL, NULL) -+AUX_REG (aux_vlc_get_19bit, NULL, NULL) -+AUX_REG (aux_vlc_get_1bit, NULL, NULL) -+AUX_REG (aux_vlc_get_20bit, NULL, NULL) -+AUX_REG (aux_vlc_get_21bit, NULL, NULL) -+AUX_REG (aux_vlc_get_22bit, NULL, NULL) -+AUX_REG (aux_vlc_get_23bit, NULL, NULL) -+AUX_REG (aux_vlc_get_24bit, NULL, NULL) -+AUX_REG (aux_vlc_get_25bit, NULL, NULL) -+AUX_REG (aux_vlc_get_26bit, NULL, NULL) -+AUX_REG (aux_vlc_get_27bit, NULL, NULL) -+AUX_REG (aux_vlc_get_28bit, NULL, NULL) -+AUX_REG (aux_vlc_get_29bit, NULL, NULL) -+AUX_REG (aux_vlc_get_2bit, NULL, NULL) -+AUX_REG (aux_vlc_get_30bit, NULL, NULL) -+AUX_REG (aux_vlc_get_31bit, NULL, NULL) -+AUX_REG (aux_vlc_get_3bit, NULL, NULL) -+AUX_REG (aux_vlc_get_4bit, NULL, NULL) -+AUX_REG (aux_vlc_get_5bit, NULL, NULL) -+AUX_REG (aux_vlc_get_6bit, NULL, NULL) -+AUX_REG (aux_vlc_get_7bit, NULL, NULL) -+AUX_REG (aux_vlc_get_8bit, NULL, NULL) -+AUX_REG (aux_vlc_get_9bit, NULL, NULL) -+AUX_REG (aux_vlc_get_symbol, NULL, NULL) -+AUX_REG (aux_vlc_ibuf_status, NULL, NULL) -+AUX_REG (aux_vlc_read_buf, NULL, NULL) -+AUX_REG (aux_vlc_read_symbol, NULL, NULL) -+AUX_REG (aux_vlc_setup, NULL, NULL) -+AUX_REG (aux_vlc_table, NULL, NULL) -+AUX_REG (aux_vlc_valid_bits, NULL, NULL) -+AUX_REG (aux_xmac0_24, NULL, NULL) -+AUX_REG (aux_xmac0, NULL, NULL) -+AUX_REG (aux_xmac1_24, NULL, NULL) -+AUX_REG (aux_xmac1, NULL, NULL) -+AUX_REG (aux_xmac2_24, NULL, NULL) -+AUX_REG (aux_xmac2, NULL, NULL) -+AUX_REG (aux_xmaclw_h, NULL, NULL) -+AUX_REG (aux_xmaclw_l, NULL, NULL) -+AUX_REG (ax0, NULL, NULL) -+AUX_REG (ax1, NULL, NULL) -+AUX_REG (ax2, NULL, NULL) -+AUX_REG (ax3, NULL, NULL) -+AUX_REG (ay0, NULL, NULL) -+AUX_REG (ay1, NULL, NULL) -+AUX_REG (ay2, NULL, NULL) -+AUX_REG (ay3, NULL, NULL) -+AUX_REG (bpu_flush, NULL, NULL) -+AUX_REG (bta_l1, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (bta_l2, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (bta_link_build, NULL, NULL) -+AUX_REG (bta, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (burstsys, NULL, NULL) -+AUX_REG (burstsz, NULL, NULL) -+AUX_REG (burstval, NULL, NULL) -+AUX_REG (burstxym, NULL, NULL) -+AUX_REG (cc_build, NULL, NULL) -+AUX_REG (che_mode, NULL, NULL) -+AUX_REG (clk_enable, NULL, NULL) -+AUX_REG (control0, aux_timer_get, aux_timer_set) -+AUX_REG (control1, aux_timer_get, aux_timer_set) -+AUX_REG (count0, aux_timer_get, aux_timer_set) -+AUX_REG (count1, aux_timer_get, aux_timer_set) -+AUX_REG (d1h, NULL, NULL) -+AUX_REG (d1l, NULL, NULL) -+AUX_REG (d2h, NULL, NULL) -+AUX_REG (d2l, NULL, NULL) -+AUX_REG (dataspace, NULL, NULL) -+AUX_REG (data_uncached_build, NULL, NULL) -+AUX_REG (dccm_base_build, NULL, NULL) -+AUX_REG (d_cache_build, arc_cache_aux_get, NULL) -+AUX_REG (dc_ctrl, arc_cache_aux_get, arc_cache_aux_set) -+AUX_REG (dc_data, NULL, NULL) -+AUX_REG (dc_fldl, NULL, arc_cache_aux_set) -+AUX_REG (dc_flsh, NULL, arc_cache_aux_set) -+AUX_REG (dc_ivdc, NULL, arc_cache_aux_set) -+AUX_REG (dc_ivdl, NULL, arc_cache_aux_set) -+AUX_REG (dc_ldl, NULL, NULL) -+AUX_REG (dc_startr, NULL, arc_cache_aux_set) -+AUX_REG (dc_endr, arc_cache_aux_get, arc_cache_aux_set) -+AUX_REG (dc_ptag, NULL, NULL) -+AUX_REG (dc_ptag_hi, arc_cache_aux_get, arc_cache_aux_set) -+AUX_REG (dc_ram_addr, NULL, NULL) -+AUX_REG (dc_tag, NULL, NULL) -+AUX_REG (dc_wp, NULL, NULL) -+AUX_REG (debugi, NULL, NULL) -+AUX_REG (debug, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (des_aux, NULL, NULL) -+AUX_REG (dilstat, NULL, NULL) -+AUX_REG (dma_config, NULL, NULL) -+AUX_REG (dmc_code_ram, NULL, NULL) -+AUX_REG (dpfp_build, NULL, NULL) -+AUX_REG (dpfp_status, NULL, NULL) -+AUX_REG (dvfs_performance, NULL, NULL) -+AUX_REG (ea_build, NULL, NULL) -+AUX_REG (ecr, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (efa, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (ei_base, NULL, NULL) -+AUX_REG (erbta, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (eret, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (erp_control, NULL, NULL) -+AUX_REG (ersec_stat, NULL, NULL) -+AUX_REG (erstatus, arc_status_regs_get, arc_status_regs_set) -+AUX_REG (exec_ctrl, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (fp_build, NULL, NULL) -+AUX_REG (fp_status, NULL, NULL) -+AUX_REG (hexctrl, NULL, NULL) -+AUX_REG (hexdata, NULL, NULL) -+AUX_REG (hwp_build, NULL, NULL) -+AUX_REG (hw_pf_build, arc_general_regs_get, NULL) -+AUX_REG (hw_pf_ctrl, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (icause, aux_irq_get, NULL) -+AUX_REG (irq_select, aux_irq_get, aux_irq_set) -+AUX_REG (irq_enable, aux_irq_get, aux_irq_set) -+AUX_REG (irq_trigger, aux_irq_get, aux_irq_set) -+AUX_REG (irq_status, aux_irq_get, NULL) -+AUX_REG (i_cache_build, arc_cache_aux_get, NULL) -+AUX_REG (ic_ctrl, arc_cache_aux_get, arc_cache_aux_set) -+AUX_REG (ic_data, NULL, NULL) -+AUX_REG (ic_startr, NULL, arc_cache_aux_set) -+AUX_REG (ic_endr, arc_cache_aux_get, arc_cache_aux_set) -+AUX_REG (ic_ivic, NULL, arc_cache_aux_set) -+AUX_REG (ic_ivil, NULL, arc_cache_aux_set) -+AUX_REG (ic_ivir, arc_cache_aux_get, arc_cache_aux_set) -+AUX_REG (ic_lil, NULL, NULL) -+AUX_REG (ic_ptag, arc_cache_aux_get, arc_cache_aux_set) -+AUX_REG (ic_ptag_hi, arc_cache_aux_get, arc_cache_aux_set) -+AUX_REG (ic_ram_address, NULL, NULL) -+AUX_REG (ic_tag, NULL, NULL) -+AUX_REG (ic_wp, NULL, NULL) -+AUX_REG (identity, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (ifetch_queue_build, NULL, NULL) -+AUX_REG (int_vector_base, aux_irq_get, aux_irq_set) -+AUX_REG (irq_build, aux_irq_get, NULL) -+AUX_REG (irq_priority_pending, NULL, NULL) -+AUX_REG (isa_config, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (ivic, NULL, NULL) -+AUX_REG (jli_base, NULL, NULL) -+AUX_REG (ldi_base, NULL, NULL) -+AUX_REG (led, NULL, NULL) -+AUX_REG (limit0, aux_timer_get, aux_timer_set) -+AUX_REG (limit1, aux_timer_get, aux_timer_set) -+AUX_REG (line_length_mask, NULL, NULL) -+AUX_REG (lockline, NULL, NULL) -+AUX_REG (lp_end, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (lp_start, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (lsp_newval, NULL, NULL) -+AUX_REG (madi_build, NULL, NULL) -+AUX_REG (memseg, NULL, NULL) -+AUX_REG (memsubsys, NULL, NULL) -+AUX_REG (mmu_build, arc_mmu_aux_get, NULL) -+AUX_REG (mpu_build, arc_mpu_aux_get, NULL) -+AUX_REG (mpuen, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpufa, NULL, NULL) -+AUX_REG (mpuic, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb0, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb1, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb2, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb3, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb4, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb5, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb6, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb7, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb8, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb9, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb10, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb11, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb12, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb13, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb14, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdb15, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp0, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp1, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp2, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp3, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp4, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp5, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp6, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp7, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp8, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp9, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp10, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp11, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp12, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp13, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp14, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpurdp15, arc_mpu_aux_get, arc_mpu_aux_set) -+AUX_REG (mpy_build, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (mulhi, NULL, NULL) -+AUX_REG (mx00, NULL, NULL) -+AUX_REG (mx01, NULL, NULL) -+AUX_REG (mx0, NULL, NULL) -+AUX_REG (mx10, NULL, NULL) -+AUX_REG (mx11, NULL, NULL) -+AUX_REG (mx1, NULL, NULL) -+AUX_REG (mx20, NULL, NULL) -+AUX_REG (mx21, NULL, NULL) -+AUX_REG (mx30, NULL, NULL) -+AUX_REG (mx31, NULL, NULL) -+AUX_REG (my00, NULL, NULL) -+AUX_REG (my01, NULL, NULL) -+AUX_REG (my0, NULL, NULL) -+AUX_REG (my10, NULL, NULL) -+AUX_REG (my11, NULL, NULL) -+AUX_REG (my1, NULL, NULL) -+AUX_REG (my20, NULL, NULL) -+AUX_REG (my21, NULL, NULL) -+AUX_REG (my30, NULL, NULL) -+AUX_REG (my31, NULL, NULL) -+AUX_REG (nsc_table_base, NULL, NULL) -+AUX_REG (nsc_table_top, NULL, NULL) -+AUX_REG (p_base_addr, NULL, NULL) -+AUX_REG (pc, arc_general_regs_get, arc_general_regs_set) -+AUX_REG (pcport, NULL, NULL) -+AUX_REG (pct_build, NULL, NULL) -+AUX_REG (pid, arc_mmu_aux_get, arc_mmu_aux_set) -+AUX_REG (sasid0, arc_mmu_aux_get, arc_mmu_aux_set) -+AUX_REG (sasid1, arc_mmu_aux_get, arc_mmu_aux_set) -+AUX_REG (pm_bcr, NULL, NULL) -+AUX_REG (pm_status, NULL, NULL) -+AUX_REG (pwr_ctrl, NULL, NULL) -+AUX_REG (rf_build, NULL, NULL) -+AUX_REG (rferp_status0, NULL, NULL) -+AUX_REG (rferp_status1, NULL, NULL) -+AUX_REG (scm_base, NULL, NULL) -+AUX_REG (scq_switch_build, NULL, NULL) -+AUX_REG (scratch_a, NULL, NULL) -+AUX_REG (scratch_data0, arc_mmu_aux_get, arc_mmu_aux_set) -+AUX_REG (sdm_base, NULL, NULL) -+AUX_REG (sec_extra, NULL, NULL) -+AUX_REG (sec_stat, NULL, NULL) -+AUX_REG (se_ctrl, NULL, NULL) -+AUX_REG (sec_vecbase_build, NULL, NULL) -+AUX_REG (se_dbg_ctrl, NULL, NULL) -+AUX_REG (se_dbg_data0, NULL, NULL) -+AUX_REG (se_dbg_data1, NULL, NULL) -+AUX_REG (se_dbg_data2, NULL, NULL) -+AUX_REG (se_dbg_data3, NULL, NULL) -+AUX_REG (se_eadr, NULL, NULL) -+AUX_REG (se_err, NULL, NULL) -+AUX_REG (semaphore, NULL, NULL) -+AUX_REG (se_spc, NULL, NULL) -+AUX_REG (se_stat, NULL, NULL) -+AUX_REG (se_watch, NULL, NULL) -+AUX_REG (simd_config, NULL, NULL) -+AUX_REG (simd_dma_build, NULL, NULL) -+AUX_REG (smart_control, NULL, NULL) -+AUX_REG (smart_data_0, NULL, NULL) -+AUX_REG (smart_data_2, NULL, NULL) -+AUX_REG (smart_data_3, NULL, NULL) -+AUX_REG (smart_data, NULL, NULL) -+AUX_REG (sram_seq, NULL, NULL) -+AUX_REG (status32, arc_status_regs_get, arc_status_regs_set) -+AUX_REG (status32_p0, NULL, NULL) -+AUX_REG (swstat, NULL, NULL) -+AUX_REG (tag_addr_mask, NULL, NULL) -+AUX_REG (tag_data_mask, NULL, NULL) -+AUX_REG (timer_build, aux_timer_get, NULL) -+AUX_REG (tlbcommand, arc_mmu_aux_get, arc_mmu_aux_set_tlbcmd) -+AUX_REG (tlbindex, arc_mmu_aux_get, arc_mmu_aux_set) -+AUX_REG (tlbpd0, arc_mmu_aux_get, arc_mmu_aux_set) -+AUX_REG (tlbpd1_hi, arc_mmu_aux_get, arc_mmu_aux_set) -+AUX_REG (tlbpd1, arc_mmu_aux_get, arc_mmu_aux_set) -+AUX_REG (tsch, NULL, NULL) -+AUX_REG (unlockline, NULL, NULL) -+AUX_REG (vbfdw_build, NULL, NULL) -+AUX_REG (vecbase_ac_build, aux_irq_get, NULL) -+AUX_REG (vecbase_build, NULL, NULL) -+AUX_REG (vlc_build, NULL, NULL) -+AUX_REG (vraptor_build, NULL, NULL) -+AUX_REG (wake, NULL, NULL) -+AUX_REG (xpu, NULL, NULL) -+AUX_REG (xtp_newval, NULL, NULL) -+AUX_REG (xyconfig, NULL, NULL) -+AUX_REG (xylsbasex, NULL, NULL) -+AUX_REG (xylsbasey, NULL, NULL) -+AUX_REG (aux_rtc_ctrl, aux_timer_get, aux_timer_set) -+AUX_REG (aux_rtc_low, aux_timer_get, aux_timer_set) -+AUX_REG (aux_rtc_high, aux_timer_get, aux_timer_set) -+ -+/* ARCV3 specific registers. */ -+ -+AUX_REG_GETTER(arc_mmuv6_aux_get) -+AUX_REG_SETTER(arc_mmuv6_aux_set) -+ -+AUX_REG (mmuv6_build, arc_mmuv6_aux_get, NULL) -+AUX_REG (mmuv6_tlbcommand, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+ -+AUX_REG (mmu_ctrl, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_rtp0, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_rtp0hi, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_rtp1, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_rtp1hi, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_ttbcr, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_tlb_data0, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_tlb_data1, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_fault_status, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -+AUX_REG (mmu_mem_attr, arc_mmuv6_aux_get, arc_mmuv6_aux_set) -diff --git a/target/arc/regs.h b/target/arc/regs.h -new file mode 100644 -index 0000000000..a71bf9b724 ---- /dev/null -+++ b/target/arc/regs.h -@@ -0,0 +1,139 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef ARC_REGS_H -+#define ARC_REGS_H -+ -+#include "exec/cpu-defs.h" -+#include "target/arc/decoder.h" -+ -+/* -+ * BCRs (Build configuration registers) are very special AUX regs -+ * as they are always readable even if corresponding HW module is absent. -+ * Thus we may always safely read them and learn what HW we have. -+ * All other AUX regs outside of 2 BCR areas are only readable if their -+ * HW is really implemented, otherwise "Instruction error" exception -+ * is raised by the CPU. -+ */ -+ -+/* First BCR region. */ -+#define ARC_BCR1_START 0x60 -+#define ARC_BCR1_END 0x7f -+/* Second BCR region. */ -+#define ARC_BCR2_START 0xc0 -+#define ARC_BCR2_END 0xff -+ -+enum arc_aux_reg_enum { -+ ARC_AUX_REGS_INVALID = -1, -+#define AUX_REG_GETTER(GET_FUNC) -+#define AUX_REG_SETTER(SET_FUNC) -+#define AUX_REG(NAME, GET, SET) AUX_ID_##NAME, -+#include "target/arc/regs.def" -+#undef AUX_REG -+#undef AUX_REG_GETTER -+#undef AUX_REG_SETTER -+ ARC_AUX_REGS_LAST -+}; -+ -+enum arc_aux_reg_detail_enum { -+ ARC_AUX_REGS_DETAIL_INVALID = -1, -+#define DEF(NUM, CPU, SUB, NAME) CPU##_##NUM, -+#include "target/arc/regs-detail.def" -+#undef DEF -+ ARC_AUX_REGS_DETAIL_LAST -+}; -+ -+struct arc_aux_regs_data; -+struct arc_aux_reg_detail { -+ /* Register address. */ -+ int address; -+ -+ /* -+ * One bit flags for the opcode. These are primarily used to -+ * indicate specific processors and environments support the -+ * instructions. -+ */ -+ enum arc_cpu_family cpu; -+ -+ /* AUX register subclass. */ -+ insn_subclass_t subclass; -+ -+ /* Enum for aux-reg. */ -+ enum arc_aux_reg_enum id; -+ -+ /* Register name. */ -+ const char *name; -+ -+ /* Size of the string. */ -+ size_t length; -+ -+ /* pointer to the first element in the list. */ -+ struct arc_aux_reg_detail *next; -+ -+ /* pointer to the first element in the list. */ -+ struct arc_aux_reg *aux_reg; -+}; -+ -+typedef void (*aux_reg_set_func)(const struct arc_aux_reg_detail *aux_reg, -+ target_ulong val, void *data); -+typedef target_ulong (*aux_reg_get_func)( -+ const struct arc_aux_reg_detail *aux_reg, -+ void *data); -+ -+struct arc_aux_reg { -+ /* pointer to the first element in the list. */ -+ struct arc_aux_reg_detail *first; -+ -+ /* get and set function for lr and sr helpers */ -+ aux_reg_get_func get_func; -+ aux_reg_set_func set_func; -+}; -+ -+extern struct arc_aux_reg_detail arc_aux_regs_detail[ARC_AUX_REGS_DETAIL_LAST]; -+extern struct arc_aux_reg arc_aux_regs[ARC_AUX_REGS_LAST]; -+extern const char *arc_aux_reg_name[ARC_AUX_REGS_DETAIL_LAST]; -+ -+void arc_aux_regs_init(void); -+int arc_aux_reg_address_for(enum arc_aux_reg_enum, int); -+struct arc_aux_reg_detail *arc_aux_reg_struct_for_address(int, int); -+ -+const char *get_auxreg(const struct arc_opcode *opcode, -+ int value, -+ unsigned isa_mask); -+ -+target_ulong __not_implemented_getter(const struct arc_aux_reg_detail *, -+ void *); -+void __not_implemented_setter(const struct arc_aux_reg_detail *, target_ulong, -+ void *); -+ -+#define AUX_REG_GETTER(GET_FUNC) \ -+ target_ulong GET_FUNC(const struct arc_aux_reg_detail *a, void *b); -+#define AUX_REG_SETTER(SET_FUNC) \ -+ void SET_FUNC(const struct arc_aux_reg_detail *a, target_ulong b, void *c); -+#define AUX_REG(NAME, GET, SET) -+ -+#include "target/arc/regs.def" -+ -+#undef AUX_REG -+#undef AUX_REG_GETTER -+#undef AUX_REG_SETTER -+ -+ -+#endif /* ARC_REGS_H */ -diff --git a/target/arc/semfunc-helper.c b/target/arc/semfunc-helper.c -new file mode 100644 -index 0000000000..4ed2edfba1 ---- /dev/null -+++ b/target/arc/semfunc-helper.c -@@ -0,0 +1,427 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "translate.h" -+#include "qemu/bitops.h" -+#include "tcg/tcg.h" -+#include "semfunc-helper.h" -+#include "translate.h" -+ -+void arc_gen_verifyCCFlag(const DisasCtxt *ctx, TCGv ret) -+{ -+ TCGv c1 = tcg_temp_new(); -+ -+ TCGv nZ = tcg_temp_new(); -+ TCGv nN = tcg_temp_new(); -+ TCGv nV = tcg_temp_new(); -+ TCGv nC = tcg_temp_new(); -+ -+ switch (ctx->insn.cc) { -+ /* AL, RA */ -+ case ARC_COND_AL: -+ tcg_gen_movi_tl(ret, 1); -+ break; -+ /* EQ, Z */ -+ case ARC_COND_EQ: -+ tcg_gen_mov_tl(ret, cpu_Zf); -+ break; -+ /* NE, NZ */ -+ case ARC_COND_NE: -+ tcg_gen_xori_tl(ret, cpu_Zf, 1); -+ break; -+ /* PL, P */ -+ case ARC_COND_PL: -+ tcg_gen_xori_tl(ret, cpu_Nf, 1); -+ break; -+ /* MI, N: */ -+ case ARC_COND_MI: -+ tcg_gen_mov_tl(ret, cpu_Nf); -+ break; -+ /* CS, C, LO */ -+ case ARC_COND_CS: -+ tcg_gen_mov_tl(ret, cpu_Cf); -+ break; -+ /* CC, NC, HS */ -+ case ARC_COND_CC: -+ tcg_gen_xori_tl(ret, cpu_Cf, 1); -+ break; -+ /* VS, V */ -+ case ARC_COND_VS: -+ tcg_gen_mov_tl(ret, cpu_Vf); -+ break; -+ /* VC, NV */ -+ case ARC_COND_VC: -+ tcg_gen_xori_tl(ret, cpu_Vf, 1); -+ break; -+ /* GT */ -+ case ARC_COND_GT: -+ /* (N & V & !Z) | (!N & !V & !Z) === XNOR(N, V) & !Z */ -+ tcg_gen_eqv_tl(ret, cpu_Nf, cpu_Vf); -+ tcg_gen_xori_tl(nZ, cpu_Zf, 1); -+ tcg_gen_and_tl(ret, ret, nZ); -+ break; -+ /* GE */ -+ case ARC_COND_GE: -+ /* (N & V) | (!N & !V) === XNOR(N, V) */ -+ tcg_gen_eqv_tl(ret, cpu_Nf, cpu_Vf); -+ tcg_gen_andi_tl(ret, ret, 1); -+ break; -+ /* LT */ -+ case ARC_COND_LT: -+ /* (N & !V) | (!N & V) === XOR(N, V) */ -+ tcg_gen_xor_tl(ret, cpu_Nf, cpu_Vf); -+ break; -+ /* LE */ -+ case ARC_COND_LE: -+ /* Z | (N & !V) | (!N & V) === XOR(N, V) | Z */ -+ tcg_gen_xor_tl(ret, cpu_Nf, cpu_Vf); -+ tcg_gen_or_tl(ret, ret, cpu_Zf); -+ break; -+ /* HI */ -+ case ARC_COND_HI: -+ /* !C & !Z === !(C | Z) */ -+ tcg_gen_or_tl(ret, cpu_Cf, cpu_Zf); -+ tcg_gen_xori_tl(ret, ret, 1); -+ break; -+ /* LS */ -+ case ARC_COND_LS: -+ /* C & Z */ -+ tcg_gen_or_tl(ret, cpu_Cf, cpu_Zf); -+ break; -+ /* PNZ */ -+ case ARC_COND_PNZ: -+ /* !N & !Z === !(N | Z) */ -+ tcg_gen_or_tl(ret, cpu_Nf, cpu_Zf); -+ tcg_gen_xori_tl(ret, ret, 1); -+ break; -+ -+ default: -+ g_assert_not_reached(); -+ } -+ -+ tcg_temp_free(c1); -+ tcg_temp_free(nZ); -+ tcg_temp_free(nN); -+ tcg_temp_free(nV); -+ tcg_temp_free(nC); -+} -+ -+#define MEMIDX (ctx->mem_idx) -+ -+#ifdef TARGET_ARCV2 -+const MemOp memop_for_size_sign[2][3] = { -+ { MO_UL, MO_UB, MO_UW }, /* non sign-extended */ -+ { MO_UL, MO_SB, MO_SW } /* sign-extended */ -+}; -+#endif -+ -+#ifdef TARGET_ARCV3 -+const MemOp memop_for_size_sign[2][4] = { -+ { MO_UL, MO_UB, MO_UW, MO_Q }, /* non sign-extended */ -+ { MO_SL, MO_SB, MO_SW, MO_Q } /* sign-extended */ -+}; -+#endif -+ -+void arc_gen_set_memory(const DisasCtxt *ctx, TCGv vaddr, int size, -+ TCGv src, bool sign_extend) -+{ -+#ifdef TARGET_ARCV2 -+ assert(size != 0x3); -+#endif -+ -+ tcg_gen_qemu_st_tl(src, vaddr, MEMIDX, -+ memop_for_size_sign[sign_extend][size]); -+} -+ -+void arc_gen_get_memory(const DisasCtxt *ctx, TCGv dest, TCGv vaddr, -+ int size, bool sign_extend) -+{ -+#ifdef TARGET_ARCV2 -+ assert(size != 0x3); -+#endif -+ -+ tcg_gen_qemu_ld_tl(dest, vaddr, MEMIDX, -+ memop_for_size_sign[sign_extend][size]); -+} -+ -+void arc_gen_no_further_loads_pending(const DisasCtxt *ctx, TCGv ret) -+{ -+ /* TODO: To complete on SMP support. */ -+ tcg_gen_movi_tl(ret, 1); -+} -+ -+void arc_gen_set_debug(const DisasCtxt *ctx, bool value) -+{ -+ /* TODO: Could not find a reson to set this. */ -+} -+ -+void -+arc_gen_execute_delayslot(DisasCtxt *ctx, TCGv bta, TCGv take_branch) -+{ -+ assert(ctx->insn.limm_p == 0 && !ctx->in_delay_slot); -+ -+ ctx->in_delay_slot = true; -+ uint32_t cpc = ctx->cpc; -+ uint32_t pcl = ctx->pcl; -+ insn_t insn = ctx->insn; -+ -+ ctx->cpc = ctx->npc; -+ ctx->pcl = ctx->cpc & ((target_ulong) 0xfffffffffffffffc); -+ -+ ++ctx->ds; -+ -+ TCGLabel *do_not_set_bta_and_de = gen_new_label(); -+ tcg_gen_brcondi_tl(TCG_COND_NE, take_branch, 1, do_not_set_bta_and_de); -+ /* -+ * In case an exception should be raised during the execution -+ * of delay slot, bta value is used to set erbta. -+ */ -+ tcg_gen_mov_tl(cpu_bta, bta); -+ /* We are in a delay slot */ -+ tcg_gen_mov_tl(cpu_DEf, take_branch); -+ gen_set_label(do_not_set_bta_and_de); -+ -+ tcg_gen_movi_tl(cpu_is_delay_slot_instruction, 1); -+ -+ /* Set the pc to the next pc */ -+ tcg_gen_movi_tl(cpu_pc, ctx->npc); -+ /* Necessary for the likely call to restore_state_to_opc() */ -+ tcg_gen_insn_start(ctx->npc); -+ -+ DisasJumpType type = ctx->base.is_jmp; -+ ctx->env->enabled_interrupts = false; -+ -+ /* -+ * In case we might be in a situation where the delayslot is in a -+ * different MMU page. Make a fake exception to interrupt -+ * delayslot execution in the context of the branch. -+ * The delayslot will then be re-executed in isolation after the -+ * branch code has set bta and DEf status flag. -+ */ -+ if ((cpc & PAGE_MASK) < 0x80000000 && -+ (cpc & PAGE_MASK) != (ctx->cpc & PAGE_MASK)) { -+ ctx->in_delay_slot = false; -+ TCGv dpc = tcg_const_local_tl(ctx->npc); -+ tcg_gen_mov_tl(cpu_pc, dpc); -+ gen_helper_fake_exception(cpu_env, dpc); -+ tcg_temp_free(dpc); -+ return; -+ } -+ -+ decode_opc(ctx->env, ctx); -+ ctx->env->enabled_interrupts = true; -+ ctx->base.is_jmp = type; -+ -+ tcg_gen_movi_tl(cpu_DEf, 0); -+ tcg_gen_movi_tl(cpu_is_delay_slot_instruction, 0); -+ -+ /* Restore the pc back */ -+ tcg_gen_movi_tl(cpu_pc, cpc); -+ /* Again, restore_state_to_opc() must use recent value */ -+ tcg_gen_insn_start(cpc); -+ -+ assert(ctx->base.is_jmp == DISAS_NEXT); -+ -+ --ctx->ds; -+ -+ /* Restore old values. */ -+ ctx->cpc = cpc; -+ ctx->pcl = pcl; -+ ctx->insn = insn; -+ ctx->in_delay_slot = false; -+ -+ return; -+} -+ -+ -+/* dest = src1 - src2. Compute C, N, V and Z flags */ -+void arc_gen_sub_Cf(TCGv ret, TCGv dest, TCGv src1, TCGv src2) -+{ -+ TCGv t1 = tcg_temp_new(); -+ TCGv t2 = tcg_temp_new(); -+ TCGv t3 = tcg_temp_new(); -+ -+ tcg_gen_not_tl(t1, src1); /* t1 = ~src1 */ -+ tcg_gen_and_tl(t2, t1, src2); /* t2 = ~src1 & src2 */ -+ tcg_gen_or_tl(t3, t1, src2); /* t3 = (~src1 | src2) & dest */ -+ tcg_gen_and_tl(t3, t3, dest); -+ /* t2 = ~src1 & src2 | ~src1 & dest | dest & src2 */ -+ tcg_gen_or_tl(t2, t2, t3); -+ tcg_gen_shri_tl(ret, t2, TARGET_LONG_BITS - 1); /* Cf = t2[31/63] */ -+ -+ tcg_temp_free(t3); -+ tcg_temp_free(t2); -+ tcg_temp_free(t1); -+} -+ -+ -+void arc_gen_get_bit(TCGv ret, TCGv a, TCGv pos) -+{ -+ tcg_gen_rotr_tl(ret, a, pos); -+ tcg_gen_andi_tl(ret, ret, 1); -+} -+ -+/* accumulator += b32 * c32 */ -+void arc_gen_mac(TCGv phi, TCGv b32, TCGv c32) -+{ -+ TCGv plo = tcg_temp_new(); -+ tcg_gen_muls2_tl(plo, phi, b32, c32); -+ -+ /* Adding the product to the accumulator */ -+ tcg_gen_add2_tl(cpu_acclo, cpu_acchi, cpu_acclo, cpu_acchi, plo, phi); -+ tcg_temp_free(plo); -+} -+ -+/* Unsigned version of mac */ -+void arc_gen_macu(TCGv phi, TCGv b32, TCGv c32) -+{ -+ TCGv plo = tcg_temp_new(); -+ tcg_gen_mulu2_tl(plo, phi, b32, c32); -+ -+ /* Adding the product to the accumulator */ -+ tcg_gen_add2_tl(cpu_acclo, cpu_acchi, cpu_acclo, cpu_acchi, plo, phi); -+ tcg_temp_free(plo); -+} -+ -+void tcg_gen_shlfi_tl(TCGv a, int b, TCGv c) -+{ -+ TCGv tmp = tcg_temp_new(); -+ tcg_gen_movi_tl(tmp, b); -+ tcg_gen_shl_tl(a, tmp, c); -+ tcg_temp_free(tmp); -+} -+ -+void arc_gen_extract_bits(TCGv ret, TCGv a, TCGv start, TCGv end) -+{ -+ TCGv tmp1 = tcg_temp_new(); -+ -+ tcg_gen_shr_tl(ret, a, end); -+ -+ tcg_gen_sub_tl(tmp1, start, end); -+ tcg_gen_addi_tl(tmp1, tmp1, 1); -+ tcg_gen_shlfi_tl(tmp1, 1, tmp1); -+ tcg_gen_subi_tl(tmp1, tmp1, 1); -+ -+ tcg_gen_and_tl(ret, ret, tmp1); -+ -+ tcg_temp_free(tmp1); -+} -+ -+void arc_gen_get_register(TCGv ret, enum arc_registers reg) -+{ -+ switch (reg) { -+ case R_SP: -+ tcg_gen_mov_tl(ret, cpu_sp); -+ break; -+ case R_STATUS32: -+ gen_helper_get_status32(ret, cpu_env); -+ break; -+ case R_ACCLO: -+ tcg_gen_mov_tl(ret, cpu_acclo); -+ break; -+ case R_ACCHI: -+ tcg_gen_mov_tl(ret, cpu_acchi); -+ break; -+ default: -+ g_assert_not_reached(); -+ } -+} -+ -+ -+void arc_gen_set_register(enum arc_registers reg, TCGv value) -+{ -+ switch (reg) { -+ case R_SP: -+ tcg_gen_mov_tl(cpu_sp, value); -+ break; -+ case R_STATUS32: -+ gen_helper_set_status32(cpu_env, value); -+ break; -+ case R_ACCLO: -+ tcg_gen_mov_tl(cpu_acclo, value); -+ break; -+ case R_ACCHI: -+ tcg_gen_mov_tl(cpu_acchi, value); -+ break; -+ default: -+ g_assert_not_reached(); -+ } -+} -+ -+ -+/* TODO: Get this from props ... */ -+void arc_has_interrupts(const DisasCtxt *ctx, TCGv ret) -+{ -+ tcg_gen_movi_tl(ret, 1); -+} -+ -+/* -+ *************************************** -+ * Statically inferred return function * -+ *************************************** -+ */ -+ -+TCGv arc_gen_next_reg(const DisasCtxt *ctx, TCGv reg) -+{ -+ int i; -+ for (i = 0; i < 64; i += 2) { -+ if (reg == cpu_r[i]) { -+ return cpu_r[i + 1]; -+ } -+ } -+ /* Check if REG is an odd register. */ -+ for (i = 1; i < 64; i += 2) { -+ /* If so, that is unsanctioned. */ -+ if (reg == cpu_r[i]) { -+ arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); -+ return NULL; -+ } -+ } -+ /* REG was not a register after all. */ -+ g_assert_not_reached(); -+} -+ -+bool arc_target_has_option(enum target_options option) -+{ -+ /* TODO: Fill with meaningful cases. */ -+ switch (option) { -+ case LL64_OPTION: -+ return true; -+ break; -+ default: -+ break; -+ } -+ return false; -+} -+ -+ -+bool arc_is_instruction_operand_a_register(const DisasCtxt *ctx, int nop) -+{ -+ assert(nop < ctx->insn.n_ops); -+ operand_t operand = ctx->insn.operands[nop]; -+ -+ return (operand.type & ARC_OPERAND_IR) != 0; -+} -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/semfunc-helper.h b/target/arc/semfunc-helper.h -new file mode 100644 -index 0000000000..5a89da588c ---- /dev/null -+++ b/target/arc/semfunc-helper.h -@@ -0,0 +1,324 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef SEMFUNC_HELPER_H_ -+#define SEMFUNC_HELPER_H_ -+ -+#include "translate.h" -+#include "qemu/bitops.h" -+#include "tcg/tcg.h" -+#include "target/arc/regs.h" -+ -+typedef enum ARC_COND { -+ ARC_COND_AL = 0x00, -+ ARC_COND_RA = 0x00, -+ ARC_COND_EQ = 0x01, -+ ARC_COND_Z = 0x01, -+ ARC_COND_NE = 0x02, -+ ARC_COND_NZ = 0x02, -+ ARC_COND_PL = 0x03, -+ ARC_COND_P = 0x03, -+ ARC_COND_MI = 0x04, -+ ARC_COND_N = 0x04, -+ ARC_COND_CS = 0x05, -+ ARC_COND_C = 0x05, -+ ARC_COND_LO = 0x05, -+ ARC_COND_CC = 0x06, -+ ARC_COND_NC = 0x06, -+ ARC_COND_HS = 0x06, -+ ARC_COND_VS = 0x07, -+ ARC_COND_V = 0x07, -+ ARC_COND_VC = 0x08, -+ ARC_COND_NV = 0x08, -+ ARC_COND_GT = 0x09, -+ ARC_COND_GE = 0x0a, -+ ARC_COND_LT = 0x0b, -+ ARC_COND_LE = 0x0c, -+ ARC_COND_HI = 0x0d, -+ ARC_COND_LS = 0x0e, -+ ARC_COND_PNZ = 0x0f, -+} ARC_COND; -+ -+#define ARC_HELPER(NAME, RET, ...) \ -+ gen_helper_##NAME(RET, cpu_env, __VA_ARGS__) -+ -+ -+enum arc_registers { -+ R_SP = 0, -+ R_STATUS32, -+ R_ACCLO, -+ R_ACCHI -+}; -+ -+enum target_options { -+ INVALID_TARGET_OPTIONS = -1, -+ DIV_REM_OPTION, -+ STACK_CHECKING, -+ LL64_OPTION -+}; -+ -+/* TODO: Change this to allow something else then ARC HS. */ -+#define LP_START \ -+ (arc_aux_reg_address_for(AUX_ID_lp_start, ARC_OPCODE_ARCv2HS)) -+#define LP_END \ -+ (arc_aux_reg_address_for(AUX_ID_lp_end, ARC_OPCODE_ARCv2HS)) -+ -+#define ReplMask(DEST, SRC, MASK) \ -+ gen_helper_repl_mask(DEST, DEST, SRC, MASK) -+ -+void arc_gen_verifyCCFlag(const DisasCtxt *ctx, TCGv ret); -+#define getCCFlag(R) arc_gen_verifyCCFlag(ctx, R) -+ -+#define getFFlag(R) ((int) ctx->insn.f) -+ -+void to_implement(const DisasCtxt *ctx); -+void to_implement_wo_abort(const DisasCtxt *ctx); -+ -+void arc_gen_set_memory( -+ const DisasCtxt *ctx, TCGv addr, int size, TCGv src, bool sign_extend); -+#define setMemory(ADDRESS, SIZE, VALUE) \ -+ arc_gen_set_memory(ctx, ADDRESS, SIZE, VALUE, getFlagX()) -+void arc_gen_get_memory( -+ const DisasCtxt *ctx, TCGv ret, TCGv addr, int size, bool sign_extend); -+#define getMemory(R, ADDRESS, SIZE) \ -+ arc_gen_get_memory(ctx, R, ADDRESS, SIZE, getFlagX()) -+ -+#define getFlagX() (ctx->insn.x) -+#define getZZFlag() (ctx->insn.zz) -+#define getAAFlag() (ctx->insn.aa) -+ -+#define SignExtend(VALUE, SIZE) VALUE -+void arc_gen_no_further_loads_pending(const DisasCtxt *ctx, TCGv ret); -+#define NoFurtherLoadsPending(R) arc_gen_no_further_loads_pending(ctx, R) -+void arc_gen_set_debug(const DisasCtxt *ctx, bool value); -+#define setDebugLD(A) arc_gen_set_debug(ctx, A) -+void arc_gen_execute_delayslot(DisasCtxt *ctx, TCGv bta, TCGv take_branch); -+#define executeDelaySlot(bta, take_branch) \ -+ arc_gen_execute_delayslot(ctx, bta, take_branch) -+ -+#define shouldExecuteDelaySlot() (ctx->insn.d != 0) -+ -+#define getNFlag(R) cpu_Nf -+#define setNFlag(ELEM) tcg_gen_shri_tl(cpu_Nf, ELEM, (TARGET_LONG_BITS - 1)) -+#ifdef TARGET_ARCV3 -+#define setNFlag32(ELEM) tcg_gen_shri_tl(cpu_Nf, ELEM, 31) -+#endif -+ -+#define setCFlag(ELEM) tcg_gen_andi_tl(cpu_Cf, ELEM, 1) -+#define getCFlag(R) tcg_gen_mov_tl(R, cpu_Cf) -+ -+#define setVFlag(ELEM) tcg_gen_andi_tl(cpu_Vf, ELEM, 1) -+ -+#define setZFlag(ELEM) \ -+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, ELEM, 0); -+ -+#define nextInsnAddressAfterDelaySlot(R) \ -+ { \ -+ ARCCPU *cpu = env_archcpu(ctx->env); \ -+ uint16_t delayslot_buffer[2]; \ -+ uint8_t delayslot_length; \ -+ ctx->env->pc = ctx->cpc; \ -+ ctx->env->stat.is_delay_slot_instruction = 1; \ -+ delayslot_buffer[0] = cpu_lduw_code(ctx->env, ctx->npc); \ -+ delayslot_length = arc_insn_length(delayslot_buffer[0], cpu->family); \ -+ tcg_gen_movi_tl(R, ctx->npc + delayslot_length); \ -+ } -+ -+#define nextInsnAddress(R) tcg_gen_movi_tl(R, ctx->npc) -+#define getPCL(R) tcg_gen_movi_tl(R, ctx->pcl) -+ -+#define setPC(NEW_PC) \ -+ do { \ -+ gen_goto_tb(ctx, 1, NEW_PC); \ -+ ret = ret == DISAS_NEXT ? DISAS_NORETURN : ret; \ -+ } while (0) -+ -+#define setBLINK(BLINK_ADDR) \ -+ tcg_gen_mov_tl(cpu_blink, BLINK_ADDR); -+ -+#ifdef TARGET_ARCV2 -+ -+#define Carry(R, A) tcg_gen_shri_tl(R, A, 31); -+ -+#endif -+ -+ -+#ifdef TARGET_ARCV3 -+ -+#define Carry(R, A) tcg_gen_shri_tl(R, A, 63); -+#define Carry32(R, A) \ -+ tcg_gen_shri_tl(R, A, 31); \ -+ tcg_gen_andi_tl(R, R, 0x1); -+ -+#endif -+ -+#define CarryADD(R, A, B, C) gen_helper_carry_add_flag(R, A, B, C) -+#define OverflowADD(R, A, B, C) gen_helper_overflow_add_flag(R, A, B, C) -+ -+#define CarryADD32(R, A, B, C) gen_helper_carry_add_flag32(R, A, B, C) -+#define OverflowADD32(R, A, B, C) gen_helper_overflow_add_flag32(R, A, B, C) -+ -+void arc_gen_sub_Cf(TCGv ret, TCGv dest, TCGv src1, TCGv src2); -+#define CarrySUB(R, A, B, C) arc_gen_sub_Cf(R, A, B, C); \ -+ tcg_gen_setcondi_tl(TCG_COND_NE, R, R, 0) -+#define OverflowSUB(R, A, B, C) gen_helper_overflow_sub_flag(R, A, B, C) -+ -+#define CarrySUB32(R, A, B, C) gen_helper_carry_sub_flag32(R, A, B, C) -+#define OverflowSUB32(R, A, B, C) gen_helper_overflow_sub_flag32(R, A, B, C) -+ -+ -+#define unsignedLT(R, B, C) tcg_gen_setcond_tl(TCG_COND_LTU, R, B, C) -+#define unsignedGE(R, B, C) tcg_gen_setcond_tl(TCG_COND_GEU, R, B, C) -+#define logicalShiftRight(R, B, C) tcg_gen_shr_tl(R, B, C) -+#define logicalShiftLeft(R, B, C) tcg_gen_shl_tl(R, B, C) -+#define arithmeticShiftRight(R, B, C) tcg_gen_sar_tl(R, B, C) -+#define rotateLeft(R, B, C) tcg_gen_rotl_tl(R, B, C) -+#define rotateRight(R, B, C) tcg_gen_rotr_tl(R, B, C) -+ -+#ifdef TARGET_ARCV3 -+#define rotateLeft32(R, B, C) gen_helper_rotate_left32(R, B, C) -+#define rotateRight32(R, B, C) gen_helper_rotate_right32(R, B, C) -+ -+#define arithmeticShiftRight32(R, B, C) gen_helper_asr_32(R, B, C) -+#endif -+ -+void arc_gen_get_bit(TCGv ret, TCGv a, TCGv pos); -+#define getBit(R, A, POS) arc_gen_get_bit(R, A, POS) -+ -+#define getRegIndex(R, ID) tcg_gen_movi_tl(R, (int) ID) -+ -+#define readAuxReg(R, A) gen_helper_lr(R, cpu_env, A) -+/* -+ * Here, by returning DISAS_UPDATE we are making SR the end -+ * of a Translation Block (TB). This is necessary because -+ * sometimes writing to control registers updates how a TB is -+ * handled, like enabling MMU/MPU. If SR is not marked as the -+ * end, the next instructions are fetched and generated and -+ * the updated outcome (page/region permissions) is not taken -+ * into account. -+ */ -+#define writeAuxReg(NAME, B) \ -+ do { \ -+ gen_helper_sr(cpu_env, B, NAME); \ -+ ret = DISAS_UPDATE; \ -+ } while (0) -+ -+/* -+ * At the end of a SYNC instruction, it is guaranteed that -+ * handling the current interrupt is finished and the raising -+ * pulse signal (if any), is cleared. By marking SYNC as the -+ * end of a TB we gave a chance to interrupt threads to execute. -+ */ -+#define syncReturnDisasUpdate() (ret = DISAS_UPDATE) -+ -+/* -+ * An enter_s may change code like below: -+ * ---- -+ * r13 .. r26 <== shell opcodes -+ * sp <= pc+56 -+ * enter_s -+ * --- -+ * It's not that we are promoting these type of instructions. -+ * nevertheless we must be able to emulate them. Hence, once -+ * again: ret = DISAS_UPDATE -+ */ -+#define helperEnter(U6) \ -+ do { \ -+ gen_helper_enter(cpu_env, U6); \ -+ ret = DISAS_UPDATE; \ -+ } while (0) -+ -+/* A leave_s may jump to blink, hence the DISAS_UPDATE */ -+#define helperLeave(U7) \ -+ do { \ -+ tcg_gen_movi_tl(cpu_pc, ctx->cpc); \ -+ gen_helper_leave(cpu_env, U7); \ -+ TCGv jump_to_blink = tcg_temp_local_new(); \ -+ TCGLabel *done = gen_new_label(); \ -+ tcg_gen_shri_tl(jump_to_blink, U7, 6); \ -+ tcg_gen_brcondi_tl(TCG_COND_EQ, jump_to_blink, 0, done); \ -+ gen_goto_tb(ctx, 1, cpu_pc); \ -+ ret = DISAS_NORETURN; \ -+ gen_set_label(done); \ -+ tcg_temp_free(jump_to_blink); \ -+ } while (0) -+ -+void arc_gen_mac(TCGv phi, TCGv b, TCGv c); -+#define MAC(R, B, C) arc_gen_mac(R, B, C) -+void arc_gen_macu(TCGv phi, TCGv b, TCGv c); -+#define MACU(R, B, C) arc_gen_macu(R, B, C) -+ -+void arc_gen_extract_bits(TCGv ret, TCGv a, TCGv start, TCGv end); -+#define extractBits(R, ELEM, START, END) \ -+ arc_gen_extract_bits(R, ELEM, START, END) -+void arc_gen_get_register(TCGv ret, enum arc_registers reg); -+#define getRegister(R, REG) arc_gen_get_register(R, REG) -+void arc_gen_set_register(enum arc_registers reg, TCGv value); -+#define setRegister(REG, VALUE) \ -+ arc_gen_set_register(REG, VALUE); \ -+ if (REG == R_STATUS32) { \ -+ ret = DISAS_NORETURN; \ -+ } \ -+ -+#define divSigned(R, SRC1, SRC2) tcg_gen_div_tl(R, SRC1, SRC2) -+#define divUnsigned(R, SRC1, SRC2) tcg_gen_divu_tl(R, SRC1, SRC2) -+#define divRemainingSigned(R, SRC1, SRC2) tcg_gen_rem_tl(R, SRC1, SRC2) -+#define divRemainingUnsigned(R, SRC1, SRC2) tcg_gen_remu_tl(R, SRC1, SRC2) -+ -+/* TODO: To implement */ -+#define Halt() -+ -+void arc_has_interrupts(const DisasCtxt *ctx, TCGv ret); -+#define hasInterrupts(R) arc_has_interrupts(ctx, R) -+#define doNothing() -+ -+#define setLF(VALUE) tcg_gen_mov_tl(cpu_lock_lf_var, VALUE) -+#define getLF(R) tcg_gen_mov_tl(R, cpu_lock_lf_var) -+ -+/* Statically inferred return function */ -+ -+TCGv arc_gen_next_reg(const DisasCtxt *ctx, TCGv reg); -+#define nextReg(A) arc_gen_next_reg(ctx, A) -+ -+/* TODO (issue #62): This must be removed. */ -+#define Zero() (ctx->zero) -+ -+bool arc_target_has_option(enum target_options option); -+#define targetHasOption(OPTION) arc_target_has_option(OPTION) -+ -+bool arc_is_instruction_operand_a_register(const DisasCtxt *ctx, int nop); -+#define instructionHasRegisterOperandIn(NOP) \ -+ arc_is_instruction_operand_a_register(ctx, NOP) -+ -+void tcg_gen_shlfi_tl(TCGv a, int b, TCGv c); -+ -+#ifdef TARGET_ARCV3 -+ -+//#define se32to64(A, B) gen_helper_se32to64(A, B) -+#define se32to64(A, B) tcg_gen_ext32s_tl(A, B) -+ -+#endif -+ -+#endif /* SEMFUNC_HELPER_H_ */ -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/semfunc-v2_mapping.def b/target/arc/semfunc-v2_mapping.def -new file mode 100644 -index 0000000000..ab8d9ff123 ---- /dev/null -+++ b/target/arc/semfunc-v2_mapping.def -@@ -0,0 +1,321 @@ -+/* -+ * QEMU ARC SEMANTIC MAPPING. -+ * -+ * Copyright (c) 2020 Synopsys, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+SEMANTIC_FUNCTION(FLAG, 1) -+SEMANTIC_FUNCTION(KFLAG, 1) -+SEMANTIC_FUNCTION(ADD, 3) -+SEMANTIC_FUNCTION(ADD1, 3) -+SEMANTIC_FUNCTION(ADD2, 3) -+SEMANTIC_FUNCTION(ADD3, 3) -+SEMANTIC_FUNCTION(ADC, 3) -+SEMANTIC_FUNCTION(SBC, 3) -+SEMANTIC_FUNCTION(NEG, 2) -+SEMANTIC_FUNCTION(SUB, 3) -+SEMANTIC_FUNCTION(SUB1, 3) -+SEMANTIC_FUNCTION(SUB2, 3) -+SEMANTIC_FUNCTION(SUB3, 3) -+SEMANTIC_FUNCTION(MAX, 3) -+SEMANTIC_FUNCTION(MIN, 3) -+SEMANTIC_FUNCTION(CMP, 2) -+SEMANTIC_FUNCTION(AND, 3) -+SEMANTIC_FUNCTION(OR, 3) -+SEMANTIC_FUNCTION(XOR, 3) -+SEMANTIC_FUNCTION(MOV, 2) -+SEMANTIC_FUNCTION(ASL, 3) -+SEMANTIC_FUNCTION(ASR, 3) -+SEMANTIC_FUNCTION(ASR8, 2) -+SEMANTIC_FUNCTION(ASR16, 2) -+SEMANTIC_FUNCTION(LSL16, 2) -+SEMANTIC_FUNCTION(LSL8, 2) -+SEMANTIC_FUNCTION(LSR, 3) -+SEMANTIC_FUNCTION(LSR16, 2) -+SEMANTIC_FUNCTION(LSR8, 2) -+SEMANTIC_FUNCTION(BIC, 3) -+SEMANTIC_FUNCTION(BCLR, 3) -+SEMANTIC_FUNCTION(BMSK, 3) -+SEMANTIC_FUNCTION(BMSKN, 3) -+SEMANTIC_FUNCTION(BSET, 3) -+SEMANTIC_FUNCTION(BXOR, 3) -+SEMANTIC_FUNCTION(ROL, 2) -+SEMANTIC_FUNCTION(ROL8, 2) -+SEMANTIC_FUNCTION(ROR, 3) -+SEMANTIC_FUNCTION(ROR8, 2) -+SEMANTIC_FUNCTION(RLC, 2) -+SEMANTIC_FUNCTION(RRC, 2) -+SEMANTIC_FUNCTION(SEXB, 2) -+SEMANTIC_FUNCTION(SEXH, 2) -+SEMANTIC_FUNCTION(EXTB, 2) -+SEMANTIC_FUNCTION(EXTH, 2) -+SEMANTIC_FUNCTION(BTST, 2) -+SEMANTIC_FUNCTION(TST, 2) -+SEMANTIC_FUNCTION(XBFU, 3) -+SEMANTIC_FUNCTION(AEX, 2) -+SEMANTIC_FUNCTION(LR, 2) -+SEMANTIC_FUNCTION(CLRI, 1) -+SEMANTIC_FUNCTION(SETI, 1) -+SEMANTIC_FUNCTION(NOP, 0) -+SEMANTIC_FUNCTION(PREALLOC, 0) -+SEMANTIC_FUNCTION(PREFETCH, 2) -+SEMANTIC_FUNCTION(MPY, 3) -+SEMANTIC_FUNCTION(MPYMU, 3) -+SEMANTIC_FUNCTION(MPYM, 3) -+SEMANTIC_FUNCTION(MPYU, 3) -+SEMANTIC_FUNCTION(MPYUW, 3) -+SEMANTIC_FUNCTION(MPYW, 3) -+SEMANTIC_FUNCTION(DIV, 3) -+SEMANTIC_FUNCTION(DIVU, 3) -+SEMANTIC_FUNCTION(REM, 3) -+SEMANTIC_FUNCTION(REMU, 3) -+SEMANTIC_FUNCTION(MAC, 3) -+SEMANTIC_FUNCTION(MACU, 3) -+SEMANTIC_FUNCTION(MACD, 3) -+SEMANTIC_FUNCTION(MACDU, 3) -+SEMANTIC_FUNCTION(ABS, 2) -+SEMANTIC_FUNCTION(SWAP, 2) -+SEMANTIC_FUNCTION(SWAPE, 2) -+SEMANTIC_FUNCTION(NOT, 2) -+SEMANTIC_FUNCTION(BI, 1) -+SEMANTIC_FUNCTION(BIH, 1) -+SEMANTIC_FUNCTION(B, 1) -+SEMANTIC_FUNCTION(B_S, 1) -+SEMANTIC_FUNCTION(BBIT0, 3) -+SEMANTIC_FUNCTION(BBIT1, 3) -+SEMANTIC_FUNCTION(BL, 1) -+SEMANTIC_FUNCTION(J, 1) -+SEMANTIC_FUNCTION(JL, 1) -+SEMANTIC_FUNCTION(SETEQ, 3) -+SEMANTIC_FUNCTION(BREQ, 3) -+SEMANTIC_FUNCTION(SETNE, 3) -+SEMANTIC_FUNCTION(BRNE, 3) -+SEMANTIC_FUNCTION(SETLT, 3) -+SEMANTIC_FUNCTION(BRLT, 3) -+SEMANTIC_FUNCTION(SETGE, 3) -+SEMANTIC_FUNCTION(BRGE, 3) -+SEMANTIC_FUNCTION(SETLE, 3) -+SEMANTIC_FUNCTION(SETGT, 3) -+SEMANTIC_FUNCTION(BRLO, 3) -+SEMANTIC_FUNCTION(SETLO, 3) -+SEMANTIC_FUNCTION(BRHS, 3) -+SEMANTIC_FUNCTION(SETHS, 3) -+SEMANTIC_FUNCTION(EX, 2) -+SEMANTIC_FUNCTION(LLOCK, 2) -+SEMANTIC_FUNCTION(LLOCKD, 2) -+SEMANTIC_FUNCTION(SCOND, 2) -+SEMANTIC_FUNCTION(SCONDD, 2) -+SEMANTIC_FUNCTION(DMB, 1) -+SEMANTIC_FUNCTION(LD, 3) -+SEMANTIC_FUNCTION(LDD, 3) -+SEMANTIC_FUNCTION(ST, 3) -+SEMANTIC_FUNCTION(STD, 3) -+SEMANTIC_FUNCTION(POP, 1) -+SEMANTIC_FUNCTION(PUSH, 1) -+SEMANTIC_FUNCTION(LP, 1) -+SEMANTIC_FUNCTION(NORM, 2) -+SEMANTIC_FUNCTION(NORMH, 2) -+SEMANTIC_FUNCTION(FLS, 2) -+SEMANTIC_FUNCTION(FFS, 2) -+ -+ -+MAPPING(flag, FLAG, 1, 0) -+MAPPING(kflag, KFLAG, 1, 0) -+MAPPING(add, ADD, 3, 1, 2, 0) -+MAPPING(add_s, ADD, 3, 1, 2, 0) -+MAPPING(add1, ADD1, 3, 1, 2, 0) -+MAPPING(add1_s, ADD1, 3, 1, 2, 0) -+MAPPING(add2, ADD2, 3, 1, 2, 0) -+MAPPING(add2_s, ADD2, 3, 1, 2, 0) -+MAPPING(add3, ADD3, 3, 1, 2, 0) -+MAPPING(add3_s, ADD3, 3, 1, 2, 0) -+MAPPING(adc, ADC, 3, 1, 2, 0) -+MAPPING(sbc, SBC, 3, 1, 2, 0) -+MAPPING(neg, NEG, 2, 1, 0) -+MAPPING(neg_s, NEG, 2, 1, 0) -+MAPPING(sub, SUB, 3, 1, 2, 0) -+MAPPING(sub_s, SUB, 3, 1, 2, 0) -+MAPPING(rsub, SUB, 3, 2, 1, 0) -+MAPPING(sub1, SUB1, 3, 1, 2, 0) -+MAPPING(sub2, SUB2, 3, 1, 2, 0) -+MAPPING(sub3, SUB3, 3, 1, 2, 0) -+MAPPING(max, MAX, 3, 1, 2, 0) -+MAPPING(min, MIN, 3, 1, 2, 0) -+MAPPING(cmp, CMP, 2, 0, 1) -+MAPPING(cmp_s, CMP, 2, 0, 1) -+MAPPING(rcmp, CMP, 2, 1, 0) -+MAPPING(and, AND, 3, 1, 2, 0) -+MAPPING(and_s, AND, 3, 1, 2, 0) -+MAPPING(or, OR, 3, 1, 2, 0) -+MAPPING(or_s, OR, 3, 1, 2, 0) -+MAPPING(xor, XOR, 3, 1, 2, 0) -+MAPPING(xor_s, XOR, 3, 1, 2, 0) -+MAPPING(mov, MOV, 2, 1, 0) -+MAPPING(mov_s, MOV, 2, 1, 0) -+CONSTANT(ASL, asl, 2, 268435457) /* For variable @c */ -+MAPPING(asl, ASL, 3, 1, 2, 0) -+CONSTANT(ASL, asl_s, 2, 268435457) /* For variable @c */ -+MAPPING(asl_s, ASL, 3, 1, 2, 0) -+CONSTANT(ASR, asr, 2, 1) /* For variable @c */ -+MAPPING(asr, ASR, 3, 1, 2, 0) -+CONSTANT(ASR, asr_s, 2, 1) /* For variable @c */ -+MAPPING(asr_s, ASR, 3, 1, 2, 0) -+MAPPING(asr8, ASR8, 2, 1, 0) -+MAPPING(asr16, ASR16, 2, 1, 0) -+MAPPING(lsl16, LSL16, 2, 1, 0) -+MAPPING(lsl8, LSL8, 2, 1, 0) -+CONSTANT(LSR, lsr, 2, 1) /* For variable @c */ -+MAPPING(lsr, LSR, 3, 1, 2, 0) -+CONSTANT(LSR, lsr_s, 2, 1) /* For variable @c */ -+MAPPING(lsr_s, LSR, 3, 1, 2, 0) -+MAPPING(lsr16, LSR16, 2, 1, 0) -+MAPPING(lsr8, LSR8, 2, 1, 0) -+MAPPING(bic, BIC, 3, 1, 2, 0) -+MAPPING(bic_s, BIC, 3, 1, 2, 0) -+MAPPING(bclr, BCLR, 3, 2, 1, 0) -+MAPPING(bclr_s, BCLR, 3, 2, 1, 0) -+MAPPING(bmsk, BMSK, 3, 2, 1, 0) -+MAPPING(bmsk_s, BMSK, 3, 2, 1, 0) -+MAPPING(bmskn, BMSKN, 3, 2, 1, 0) -+MAPPING(bset, BSET, 3, 2, 1, 0) -+MAPPING(bset_s, BSET, 3, 2, 1, 0) -+MAPPING(bxor, BXOR, 3, 2, 1, 0) -+MAPPING(rol, ROL, 2, 1, 0) -+MAPPING(rol8, ROL8, 2, 1, 0) -+CONSTANT(ROR, ror, 2, 1) /* For variable @n */ -+MAPPING(ror, ROR, 3, 1, 2, 0) -+MAPPING(ror8, ROR8, 2, 1, 0) -+MAPPING(rlc, RLC, 2, 1, 0) -+MAPPING(rrc, RRC, 2, 1, 0) -+MAPPING(sexb, SEXB, 2, 0, 1) -+MAPPING(sexb_s, SEXB, 2, 0, 1) -+MAPPING(sexh, SEXH, 2, 0, 1) -+MAPPING(sexh_s, SEXH, 2, 0, 1) -+MAPPING(extb, EXTB, 2, 0, 1) -+MAPPING(extb_s, EXTB, 2, 0, 1) -+MAPPING(exth, EXTH, 2, 0, 1) -+MAPPING(exth_s, EXTH, 2, 0, 1) -+MAPPING(btst, BTST, 2, 1, 0) -+MAPPING(btst_s, BTST, 2, 1, 0) -+MAPPING(tst, TST, 2, 0, 1) -+MAPPING(tst_s, TST, 2, 0, 1) -+MAPPING(xbfu, XBFU, 3, 2, 1, 0) -+MAPPING(aex, AEX, 2, 1, 0) -+MAPPING(lr, LR, 2, 0, 1) -+MAPPING(clri, CLRI, 1, 0) -+MAPPING(seti, SETI, 1, 0) -+MAPPING(nop, NOP, 0) -+MAPPING(nop_s, NOP, 0) -+MAPPING(prealloc, PREALLOC, 0) -+CONSTANT(PREFETCH, prefetch, 1, 0) /* For variable @src2 */ -+MAPPING(prefetch, PREFETCH, 2, 0, 1) -+CONSTANT(PREFETCH, prefetchw, 1, 0) /* For variable @src2 */ -+MAPPING(prefetchw, PREFETCH, 2, 0, 1) -+MAPPING(mpy, MPY, 3, 1, 2, 0) -+MAPPING(mpy_s, MPY, 3, 1, 2, 0) -+MAPPING(mpymu, MPYMU, 3, 0, 1, 2) -+MAPPING(mpym, MPYM, 3, 0, 1, 2) -+MAPPING(mpyu, MPYU, 3, 1, 2, 0) -+MAPPING(mpyuw, MPYUW, 3, 0, 1, 2) -+MAPPING(mpyuw_s, MPYUW, 3, 0, 1, 2) -+MAPPING(mpyw, MPYW, 3, 0, 1, 2) -+MAPPING(mpyw_s, MPYW, 3, 0, 1, 2) -+MAPPING(div, DIV, 3, 2, 1, 0) -+MAPPING(divu, DIVU, 3, 2, 0, 1) -+MAPPING(rem, REM, 3, 2, 1, 0) -+MAPPING(remu, REMU, 3, 2, 0, 1) -+MAPPING(mac, MAC, 3, 1, 2, 0) -+MAPPING(macu, MACU, 3, 1, 2, 0) -+MAPPING(macd, MACD, 3, 1, 2, 0) -+MAPPING(macdu, MACDU, 3, 1, 2, 0) -+MAPPING(abs, ABS, 2, 1, 0) -+MAPPING(abs_s, ABS, 2, 1, 0) -+MAPPING(swap, SWAP, 2, 1, 0) -+MAPPING(swape, SWAPE, 2, 1, 0) -+MAPPING(not, NOT, 2, 0, 1) -+MAPPING(not_s, NOT, 2, 0, 1) -+MAPPING(bi, BI, 1, 0) -+MAPPING(bih, BIH, 1, 0) -+MAPPING(b, B, 1, 0) -+MAPPING(beq_s, B_S, 1, 0) -+MAPPING(bne_s, B_S, 1, 0) -+MAPPING(bgt_s, B_S, 1, 0) -+MAPPING(bge_s, B_S, 1, 0) -+MAPPING(blt_s, B_S, 1, 0) -+MAPPING(ble_s, B_S, 1, 0) -+MAPPING(bhi_s, B_S, 1, 0) -+MAPPING(bhs_s, B_S, 1, 0) -+MAPPING(blo_s, B_S, 1, 0) -+MAPPING(bls_s, B_S, 1, 0) -+MAPPING(b_s, B_S, 1, 0) -+MAPPING(bbit0, BBIT0, 3, 0, 1, 2) -+MAPPING(bbit1, BBIT1, 3, 0, 1, 2) -+MAPPING(bl, BL, 1, 0) -+MAPPING(bl_s, BL, 1, 0) -+MAPPING(j, J, 1, 0) -+MAPPING(j_s, J, 1, 0) -+MAPPING(jeq_s, J, 1, 0) -+MAPPING(jne_s, J, 1, 0) -+MAPPING(jl, JL, 1, 0) -+MAPPING(jl_s, JL, 1, 0) -+MAPPING(seteq, SETEQ, 3, 1, 2, 0) -+MAPPING(breq, BREQ, 3, 0, 1, 2) -+MAPPING(breq_s, BREQ, 3, 0, 1, 2) -+MAPPING(setne, SETNE, 3, 1, 2, 0) -+MAPPING(brne, BRNE, 3, 0, 1, 2) -+MAPPING(brne_s, BRNE, 3, 0, 1, 2) -+MAPPING(setlt, SETLT, 3, 1, 2, 0) -+MAPPING(brlt, BRLT, 3, 0, 1, 2) -+MAPPING(setge, SETGE, 3, 1, 2, 0) -+MAPPING(brge, BRGE, 3, 0, 1, 2) -+MAPPING(setle, SETLE, 3, 1, 2, 0) -+MAPPING(setgt, SETGT, 3, 1, 2, 0) -+MAPPING(brlo, BRLO, 3, 0, 1, 2) -+MAPPING(setlo, SETLO, 3, 1, 2, 0) -+MAPPING(brhs, BRHS, 3, 0, 1, 2) -+MAPPING(seths, SETHS, 3, 1, 2, 0) -+MAPPING(ex, EX, 2, 0, 1) -+MAPPING(llock, LLOCK, 2, 0, 1) -+MAPPING(llockd, LLOCKD, 2, 0, 1) -+MAPPING(scond, SCOND, 2, 1, 0) -+MAPPING(scondd, SCONDD, 2, 1, 0) -+MAPPING(dmb, DMB, 1, 0) -+CONSTANT(LD, ld, 2, 0) /* For variable @src2 */ -+MAPPING(ld, LD, 3, 1, 2, 0) -+MAPPING(ld_s, LD, 3, 1, 2, 0) -+MAPPING(ldb_s, LD, 3, 1, 2, 0) -+MAPPING(ldh_s, LD, 3, 1, 2, 0) -+MAPPING(ldw_s, LD, 3, 1, 2, 0) -+CONSTANT(LD, ldi, 2, 0) /* For variable @src2 */ -+MAPPING(ldi, LD, 3, 1, 2, 0) -+CONSTANT(LD, ldi_s, 2, 0) /* For variable @src2 */ -+MAPPING(ldi_s, LD, 3, 1, 2, 0) -+CONSTANT(LDD, ldd, 2, 0) /* For variable @src2 */ -+MAPPING(ldd, LDD, 3, 1, 2, 0) -+CONSTANT(ST, st, 2, 0) /* For variable @src2 */ -+MAPPING(st, ST, 3, 1, 2, 0) -+MAPPING(st_s, ST, 3, 1, 2, 0) -+MAPPING(stb_s, ST, 3, 1, 2, 0) -+MAPPING(sth_s, ST, 3, 1, 2, 0) -+MAPPING(stw_s, ST, 3, 1, 2, 0) -+CONSTANT(STD, std, 2, 0) /* For variable @src2 */ -+MAPPING(std, STD, 3, 1, 2, 0) -+MAPPING(pop_s, POP, 1, 0) -+MAPPING(push_s, PUSH, 1, 0) -+MAPPING(lp, LP, 1, 0) -+MAPPING(norm, NORM, 2, 1, 0) -+MAPPING(normh, NORMH, 2, 1, 0) -+MAPPING(fls, FLS, 2, 1, 0) -+MAPPING(ffs, FFS, 2, 1, 0) -diff --git a/target/arc/semfunc-v3.c b/target/arc/semfunc-v3.c -new file mode 100644 -index 0000000000..fa764bc3e1 ---- /dev/null -+++ b/target/arc/semfunc-v3.c -@@ -0,0 +1,14662 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2017 Cupertino Miranda -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * -+ */ -+ -+#include "qemu/osdep.h" -+#include "translate.h" -+#include "semfunc-v3.h" -+#include "exec/gen-icount.h" -+ -+ -+ -+ -+/* FLAG -+ * Variables: @src -+ * Functions: getCCFlag, getRegister, getBit, hasInterrupts, Halt, ReplMask, targetHasOption, setRegister -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ status32 = getRegister (R_STATUS32); -+ if(((getBit (@src, 0) == 1) && (getBit (status32, 7) == 0))) -+ { -+ if((hasInterrupts () > 0)) -+ { -+ status32 = (status32 | 1); -+ Halt (); -+ }; -+ } -+ else -+ { -+ ReplMask (status32, @src, 3840); -+ if(((getBit (status32, 7) == 0) && (hasInterrupts () > 0))) -+ { -+ ReplMask (status32, @src, 30); -+ if(targetHasOption (DIV_REM_OPTION)) -+ { -+ ReplMask (status32, @src, 8192); -+ }; -+ if(targetHasOption (STACK_CHECKING)) -+ { -+ ReplMask (status32, @src, 16384); -+ }; -+ if(targetHasOption (LL64_OPTION)) -+ { -+ ReplMask (status32, @src, 524288); -+ }; -+ ReplMask (status32, @src, 1048576); -+ }; -+ }; -+ setRegister (R_STATUS32, status32); -+ }; -+} -+ */ -+ -+int -+arc_gen_FLAG (DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_14 = tcg_temp_local_new(); -+ TCGv status32 = tcg_temp_local_new(); -+ TCGv temp_16 = tcg_temp_local_new(); -+ TCGv temp_15 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_18 = tcg_temp_local_new(); -+ TCGv temp_17 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_19 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_20 = tcg_temp_local_new(); -+ TCGv temp_22 = tcg_temp_local_new(); -+ TCGv temp_21 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_23 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_24 = tcg_temp_local_new(); -+ TCGv temp_25 = tcg_temp_local_new(); -+ TCGv temp_26 = tcg_temp_local_new(); -+ TCGv temp_27 = tcg_temp_local_new(); -+ TCGv temp_28 = tcg_temp_local_new(); -+ getCCFlag(temp_13); -+ tcg_gen_mov_tl(cc_flag, temp_13); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ getRegister(temp_14, R_STATUS32); -+ tcg_gen_mov_tl(status32, temp_14); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_movi_tl(temp_16, 0); -+ getBit(temp_15, src, temp_16); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, temp_15, 1); -+ tcg_gen_movi_tl(temp_18, 7); -+ getBit(temp_17, status32, temp_18); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_4, temp_17, 0); -+ tcg_gen_and_tl(temp_5, temp_3, temp_4); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_2);; -+ TCGLabel *done_3 = gen_new_label(); -+ hasInterrupts(temp_19); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_7, temp_19, 0); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); tcg_gen_andi_tl(temp_8, temp_8, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, done_3);; -+ tcg_gen_ori_tl(status32, status32, 1); -+ Halt(); -+ gen_set_label(done_3); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_movi_tl(temp_20, 3840); -+ ReplMask(status32, src, temp_20); -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_movi_tl(temp_22, 7); -+ getBit(temp_21, status32, temp_22); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_9, temp_21, 0); -+ hasInterrupts(temp_23); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_10, temp_23, 0); -+ tcg_gen_and_tl(temp_11, temp_9, temp_10); -+ tcg_gen_xori_tl(temp_12, temp_11, 1); tcg_gen_andi_tl(temp_12, temp_12, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_12, arc_true, done_4);; -+ tcg_gen_movi_tl(temp_24, 30); -+ ReplMask(status32, src, temp_24); -+ if (targetHasOption (DIV_REM_OPTION)) -+ { -+ tcg_gen_movi_tl(temp_25, 8192); -+ ReplMask(status32, src, temp_25); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (targetHasOption (STACK_CHECKING)) -+ { -+ tcg_gen_movi_tl(temp_26, 16384); -+ ReplMask(status32, src, temp_26); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (targetHasOption (LL64_OPTION)) -+ { -+ tcg_gen_movi_tl(temp_27, 524288); -+ ReplMask(status32, src, temp_27); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_movi_tl(temp_28, 1048576); -+ ReplMask(status32, src, temp_28); -+ gen_set_label(done_4); -+ gen_set_label(done_2); -+ setRegister(R_STATUS32, status32); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_14); -+ tcg_temp_free(status32); -+ tcg_temp_free(temp_16); -+ tcg_temp_free(temp_15); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_18); -+ tcg_temp_free(temp_17); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_19); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_20); -+ tcg_temp_free(temp_22); -+ tcg_temp_free(temp_21); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_23); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_24); -+ tcg_temp_free(temp_25); -+ tcg_temp_free(temp_26); -+ tcg_temp_free(temp_27); -+ tcg_temp_free(temp_28); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* KFLAG -+ * Variables: @src -+ * Functions: getCCFlag, getRegister, getBit, hasInterrupts, Halt, ReplMask, targetHasOption, setRegister -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ status32 = getRegister (R_STATUS32); -+ if(((getBit (@src, 0) == 1) && (getBit (status32, 7) == 0))) -+ { -+ if((hasInterrupts () > 0)) -+ { -+ status32 = (status32 | 1); -+ Halt (); -+ }; -+ } -+ else -+ { -+ ReplMask (status32, @src, 3840); -+ if(((getBit (status32, 7) == 0) && (hasInterrupts () > 0))) -+ { -+ ReplMask (status32, @src, 62); -+ if(targetHasOption (DIV_REM_OPTION)) -+ { -+ ReplMask (status32, @src, 8192); -+ }; -+ if(targetHasOption (STACK_CHECKING)) -+ { -+ ReplMask (status32, @src, 16384); -+ }; -+ ReplMask (status32, @src, 65536); -+ if(targetHasOption (LL64_OPTION)) -+ { -+ ReplMask (status32, @src, 524288); -+ }; -+ ReplMask (status32, @src, 1048576); -+ ReplMask (status32, @src, 2147483648); -+ }; -+ }; -+ setRegister (R_STATUS32, status32); -+ }; -+} -+ */ -+ -+int -+arc_gen_KFLAG (DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_14 = tcg_temp_local_new(); -+ TCGv status32 = tcg_temp_local_new(); -+ TCGv temp_16 = tcg_temp_local_new(); -+ TCGv temp_15 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_18 = tcg_temp_local_new(); -+ TCGv temp_17 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_19 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_20 = tcg_temp_local_new(); -+ TCGv temp_22 = tcg_temp_local_new(); -+ TCGv temp_21 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_23 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_24 = tcg_temp_local_new(); -+ TCGv temp_25 = tcg_temp_local_new(); -+ TCGv temp_26 = tcg_temp_local_new(); -+ TCGv temp_27 = tcg_temp_local_new(); -+ TCGv temp_28 = tcg_temp_local_new(); -+ TCGv temp_29 = tcg_temp_local_new(); -+ TCGv temp_30 = tcg_temp_local_new(); -+ getCCFlag(temp_13); -+ tcg_gen_mov_tl(cc_flag, temp_13); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ getRegister(temp_14, R_STATUS32); -+ tcg_gen_mov_tl(status32, temp_14); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_movi_tl(temp_16, 0); -+ getBit(temp_15, src, temp_16); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, temp_15, 1); -+ tcg_gen_movi_tl(temp_18, 7); -+ getBit(temp_17, status32, temp_18); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_4, temp_17, 0); -+ tcg_gen_and_tl(temp_5, temp_3, temp_4); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_2);; -+ TCGLabel *done_3 = gen_new_label(); -+ hasInterrupts(temp_19); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_7, temp_19, 0); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); tcg_gen_andi_tl(temp_8, temp_8, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, done_3);; -+ tcg_gen_ori_tl(status32, status32, 1); -+ Halt(); -+ gen_set_label(done_3); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_movi_tl(temp_20, 3840); -+ ReplMask(status32, src, temp_20); -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_movi_tl(temp_22, 7); -+ getBit(temp_21, status32, temp_22); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_9, temp_21, 0); -+ hasInterrupts(temp_23); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_10, temp_23, 0); -+ tcg_gen_and_tl(temp_11, temp_9, temp_10); -+ tcg_gen_xori_tl(temp_12, temp_11, 1); tcg_gen_andi_tl(temp_12, temp_12, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_12, arc_true, done_4);; -+ tcg_gen_movi_tl(temp_24, 62); -+ ReplMask(status32, src, temp_24); -+ if (targetHasOption (DIV_REM_OPTION)) -+ { -+ tcg_gen_movi_tl(temp_25, 8192); -+ ReplMask(status32, src, temp_25); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (targetHasOption (STACK_CHECKING)) -+ { -+ tcg_gen_movi_tl(temp_26, 16384); -+ ReplMask(status32, src, temp_26); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_movi_tl(temp_27, 65536); -+ ReplMask(status32, src, temp_27); -+ if (targetHasOption (LL64_OPTION)) -+ { -+ tcg_gen_movi_tl(temp_28, 524288); -+ ReplMask(status32, src, temp_28); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_movi_tl(temp_29, 1048576); -+ ReplMask(status32, src, temp_29); -+ tcg_gen_movi_tl(temp_30, 2147483648); -+ ReplMask(status32, src, temp_30); -+ gen_set_label(done_4); -+ gen_set_label(done_2); -+ setRegister(R_STATUS32, status32); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_14); -+ tcg_temp_free(status32); -+ tcg_temp_free(temp_16); -+ tcg_temp_free(temp_15); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_18); -+ tcg_temp_free(temp_17); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_19); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_20); -+ tcg_temp_free(temp_22); -+ tcg_temp_free(temp_21); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_23); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_24); -+ tcg_temp_free(temp_25); -+ tcg_temp_free(temp_26); -+ tcg_temp_free(temp_27); -+ tcg_temp_free(temp_28); -+ tcg_temp_free(temp_29); -+ tcg_temp_free(temp_30); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ADD -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarryADD32, setVFlag, OverflowADD32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ lc = se32to64 (@c); -+ if((cc_flag == true)) -+ { -+ @a = ((lb + lc) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarryADD32 (@a, lb, lc)); -+ setVFlag (OverflowADD32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADD (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ se32to64(temp_5, c); -+ tcg_gen_mov_tl(lc, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_add_tl(temp_6, lb, lc); -+ tcg_gen_andi_tl(a, temp_6, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarryADD32(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setCFlag(temp_7); -+ OverflowADD32(temp_10, a, lb, lc); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ setVFlag(temp_9); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ADD1 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarryADD32, setVFlag, OverflowADD32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ lc = se32to64 (@c); -+ if((cc_flag == true)) -+ { -+ @a = ((lb + (lc << 1)) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarryADD32 (@a, lb, lc)); -+ setVFlag (OverflowADD32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADD1 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ se32to64(temp_5, c); -+ tcg_gen_mov_tl(lc, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_shli_tl(temp_7, lc, 1); -+ tcg_gen_add_tl(temp_6, lb, temp_7); -+ tcg_gen_andi_tl(a, temp_6, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarryADD32(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ OverflowADD32(temp_11, a, lb, lc); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setVFlag(temp_10); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ADD2 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarryADD32, setVFlag, OverflowADD32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ lc = se32to64 (@c); -+ if((cc_flag == true)) -+ { -+ @a = ((lb + (lc << 2)) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarryADD32 (@a, lb, lc)); -+ setVFlag (OverflowADD32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADD2 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ se32to64(temp_5, c); -+ tcg_gen_mov_tl(lc, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_shli_tl(temp_7, lc, 2); -+ tcg_gen_add_tl(temp_6, lb, temp_7); -+ tcg_gen_andi_tl(a, temp_6, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarryADD32(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ OverflowADD32(temp_11, a, lb, lc); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setVFlag(temp_10); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ADD3 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarryADD32, setVFlag, OverflowADD32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ lc = se32to64 (@c); -+ if((cc_flag == true)) -+ { -+ @a = ((lb + (lc << 3)) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarryADD32 (@a, lb, lc)); -+ setVFlag (OverflowADD32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADD3 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ se32to64(temp_5, c); -+ tcg_gen_mov_tl(lc, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_shli_tl(temp_7, lc, 3); -+ tcg_gen_add_tl(temp_6, lb, temp_7); -+ tcg_gen_andi_tl(a, temp_6, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarryADD32(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ OverflowADD32(temp_11, a, lb, lc); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setVFlag(temp_10); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ADC -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getCFlag, getFFlag, setZFlag, setNFlag32, setCFlag, CarryADD32, setVFlag, OverflowADD32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ lc = se32to64 (@c); -+ if((cc_flag == true)) -+ { -+ @a = ((lb + lc) + getCFlag ()); -+ @a = (@a & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarryADD32 (@a, lb, lc)); -+ setVFlag (OverflowADD32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADC (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ se32to64(temp_5, c); -+ tcg_gen_mov_tl(lc, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_add_tl(temp_6, lb, lc); -+ getCFlag(temp_8); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_add_tl(a, temp_6, temp_7); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarryADD32(temp_10, a, lb, lc); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ setCFlag(temp_9); -+ OverflowADD32(temp_12, a, lb, lc); -+ tcg_gen_mov_tl(temp_11, temp_12); -+ setVFlag(temp_11); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SBC -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getCFlag, getFFlag, setZFlag, setNFlag32, setCFlag, CarryADD32, setVFlag, OverflowADD32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ lc = se32to64 (@c); -+ if((cc_flag == true)) -+ { -+ @a = ((lb - lc) - getCFlag ()); -+ @a = (@a & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarryADD32 (@a, lb, lc)); -+ setVFlag (OverflowADD32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SBC (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ se32to64(temp_5, c); -+ tcg_gen_mov_tl(lc, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_sub_tl(temp_6, lb, lc); -+ getCFlag(temp_8); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_sub_tl(a, temp_6, temp_7); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarryADD32(temp_10, a, lb, lc); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ setCFlag(temp_9); -+ OverflowADD32(temp_12, a, lb, lc); -+ tcg_gen_mov_tl(temp_11, temp_12); -+ setVFlag(temp_11); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* NEG -+ * Variables: @b, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarrySUB32, setVFlag, OverflowSUB32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ if((cc_flag == true)) -+ { -+ @a = (0 - @b); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarrySUB32 (@a, 0, lb)); -+ setVFlag (OverflowSUB32 (@a, 0, lb)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_NEG (DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_subfi_tl(a, 0, b); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ tcg_gen_movi_tl(temp_7, 0); -+ CarrySUB32(temp_6, a, temp_7, lb); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+ tcg_gen_movi_tl(temp_10, 0); -+ OverflowSUB32(temp_9, a, temp_10, lb); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setVFlag(temp_8); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SUB -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarrySUB32, setVFlag, OverflowSUB32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ if((cc_flag == true)) -+ { -+ lc = se32to64 (@c); -+ @a = ((lb - lc) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarrySUB32 (@a, lb, lc)); -+ setVFlag (OverflowSUB32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SUB (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ se32to64(temp_5, c); -+ tcg_gen_mov_tl(lc, temp_5); -+ tcg_gen_sub_tl(temp_6, lb, lc); -+ tcg_gen_andi_tl(a, temp_6, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarrySUB32(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setCFlag(temp_7); -+ OverflowSUB32(temp_10, a, lb, lc); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ setVFlag(temp_9); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SUB1 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarrySUB32, setVFlag, OverflowSUB32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ if((cc_flag == true)) -+ { -+ lc = (se32to64 (@c) << 1); -+ @a = ((lb - lc) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarrySUB32 (@a, lb, lc)); -+ setVFlag (OverflowSUB32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SUB1 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ se32to64(temp_6, c); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_shli_tl(lc, temp_5, 1); -+ tcg_gen_sub_tl(temp_7, lb, lc); -+ tcg_gen_andi_tl(a, temp_7, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarrySUB32(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ OverflowSUB32(temp_11, a, lb, lc); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setVFlag(temp_10); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SUB2 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarrySUB32, setVFlag, OverflowSUB32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ if((cc_flag == true)) -+ { -+ lc = (se32to64 (@c) << 2); -+ @a = ((lb - lc) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarrySUB32 (@a, lb, lc)); -+ setVFlag (OverflowSUB32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SUB2 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ se32to64(temp_6, c); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_shli_tl(lc, temp_5, 2); -+ tcg_gen_sub_tl(temp_7, lb, lc); -+ tcg_gen_andi_tl(a, temp_7, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarrySUB32(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ OverflowSUB32(temp_11, a, lb, lc); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setVFlag(temp_10); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SUB3 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarrySUB32, setVFlag, OverflowSUB32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ if((cc_flag == true)) -+ { -+ lc = (se32to64 (@c) << 3); -+ @a = ((lb - lc) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setCFlag (CarrySUB32 (@a, lb, lc)); -+ setVFlag (OverflowSUB32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SUB3 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ se32to64(temp_4, b); -+ tcg_gen_mov_tl(lb, temp_4); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ se32to64(temp_6, c); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_shli_tl(lc, temp_5, 3); -+ tcg_gen_sub_tl(temp_7, lb, lc); -+ tcg_gen_andi_tl(a, temp_7, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ CarrySUB32(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ OverflowSUB32(temp_11, a, lb, lc); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setVFlag(temp_10); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MAX -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarrySUB32, setVFlag, OverflowSUB32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ if((cc_flag == true)) -+ { -+ lc = se32to64 (@c); -+ alu = (lb - lc); -+ if((lc >= lb)) -+ { -+ @a = lc; -+ } -+ else -+ { -+ @a = lb; -+ }; -+ alu = (alu & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (alu); -+ setNFlag32 (alu); -+ setCFlag (CarrySUB32 (@a, lb, lc)); -+ setVFlag (OverflowSUB32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MAX (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ se32to64(temp_6, b); -+ tcg_gen_mov_tl(lb, temp_6); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ se32to64(temp_7, c); -+ tcg_gen_mov_tl(lc, temp_7); -+ tcg_gen_sub_tl(alu, lb, lc); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_3, lc, lb); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, lc); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, lb); -+ gen_set_label(done_2); -+ tcg_gen_andi_tl(alu, alu, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(alu); -+ setNFlag32(alu); -+ CarrySUB32(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ OverflowSUB32(temp_11, a, lb, lc); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setVFlag(temp_10); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(lc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MIN -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64, getFFlag, setZFlag, setNFlag32, setCFlag, CarrySUB32, setVFlag, OverflowSUB32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = se32to64 (@b); -+ if((cc_flag == true)) -+ { -+ lc = se32to64 (@c); -+ alu = (lb - lc); -+ if((lc <= lb)) -+ { -+ @a = lc; -+ } -+ else -+ { -+ @a = lb; -+ }; -+ alu = (alu & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (alu); -+ setNFlag32 (alu); -+ setCFlag (CarrySUB32 (@a, lb, lc)); -+ setVFlag (OverflowSUB32 (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MIN (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ se32to64(temp_6, b); -+ tcg_gen_mov_tl(lb, temp_6); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ se32to64(temp_7, c); -+ tcg_gen_mov_tl(lc, temp_7); -+ tcg_gen_sub_tl(alu, lb, lc); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LE, temp_3, lc, lb); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, lc); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, lb); -+ gen_set_label(done_2); -+ tcg_gen_andi_tl(alu, alu, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(alu); -+ setNFlag32(alu); -+ CarrySUB32(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ OverflowSUB32(temp_11, a, lb, lc); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setVFlag(temp_10); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(lc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* CMP -+ * Variables: @b, @c -+ * Functions: getCCFlag, setZFlag, setNFlag32, setCFlag, CarrySUB32, setVFlag, OverflowSUB32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ v = 4294967295; -+ lb = (@b & v); -+ lc = (@c & v); -+ alu = (lb - lc); -+ alu = (alu & 4294967295); -+ setZFlag (alu); -+ setNFlag32 (alu); -+ setCFlag (CarrySUB32 (alu, lb, lc)); -+ setVFlag (OverflowSUB32 (alu, lb, lc)); -+ }; -+} -+ */ -+ -+int -+arc_gen_CMP (DisasCtxt *ctx, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv v = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_movi_tl(v, 4294967295); -+ tcg_gen_and_tl(lb, b, v); -+ tcg_gen_and_tl(lc, c, v); -+ tcg_gen_sub_tl(alu, lb, lc); -+ tcg_gen_andi_tl(alu, alu, 4294967295); -+ setZFlag(alu); -+ setNFlag32(alu); -+ CarrySUB32(temp_5, alu, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB32(temp_7, alu, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(v); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* AND -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = (@b & @c); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_AND (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_and_tl(a, b, c); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* OR -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = (@b | @c); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_OR (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_or_tl(a, b, c); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* XOR -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = (@b ^ @c); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_XOR (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_xor_tl(a, b, c); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MOV -+ * Variables: @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = @b; -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MOV (DisasCtxt *ctx, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(a, b); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ASL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32, setCFlag, getBit, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = (@b & 4294967295); -+ lc = (@c & 31); -+ la = (lb << lc); -+ la = (la & 4294967295); -+ @a = la; -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ if((lc == 0)) -+ { -+ setCFlag (0); -+ } -+ else -+ { -+ setCFlag (getBit (lb, (32 - lc))); -+ }; -+ if((@c == 268435457)) -+ { -+ t1 = getBit (la, 31); -+ t2 = getBit (lb, 31); -+ if((t1 == t2)) -+ { -+ setVFlag (0); -+ } -+ else -+ { -+ setVFlag (1); -+ }; -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ASL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_15 = tcg_temp_local_new(); -+ TCGv temp_14 = tcg_temp_local_new(); -+ TCGv t1 = tcg_temp_local_new(); -+ TCGv temp_17 = tcg_temp_local_new(); -+ TCGv temp_16 = tcg_temp_local_new(); -+ TCGv t2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_18 = tcg_temp_local_new(); -+ TCGv temp_19 = tcg_temp_local_new(); -+ getCCFlag(temp_9); -+ tcg_gen_mov_tl(cc_flag, temp_9); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lb, b, 4294967295); -+ tcg_gen_andi_tl(lc, c, 31); -+ tcg_gen_shl_tl(la, lb, lc); -+ tcg_gen_andi_tl(la, la, 4294967295); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, lc, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(temp_10, 0); -+ setCFlag(temp_10); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_subfi_tl(temp_13, 32, lc); -+ getBit(temp_12, lb, temp_13); -+ tcg_gen_mov_tl(temp_11, temp_12); -+ setCFlag(temp_11); -+ gen_set_label(done_2); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_5, c, 268435457); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, done_3);; -+ tcg_gen_movi_tl(temp_15, 31); -+ getBit(temp_14, la, temp_15); -+ tcg_gen_mov_tl(t1, temp_14); -+ tcg_gen_movi_tl(temp_17, 31); -+ getBit(temp_16, lb, temp_17); -+ tcg_gen_mov_tl(t2, temp_16); -+ TCGLabel *else_4 = gen_new_label(); -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_7, t1, t2); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); tcg_gen_andi_tl(temp_8, temp_8, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, else_4);; -+ tcg_gen_movi_tl(temp_18, 0); -+ setVFlag(temp_18); -+ tcg_gen_br(done_4); -+ gen_set_label(else_4); -+ tcg_gen_movi_tl(temp_19, 1); -+ setVFlag(temp_19); -+ gen_set_label(done_4); -+ gen_set_label(done_3); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(la); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_15); -+ tcg_temp_free(temp_14); -+ tcg_temp_free(t1); -+ tcg_temp_free(temp_17); -+ tcg_temp_free(temp_16); -+ tcg_temp_free(t2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_18); -+ tcg_temp_free(temp_19); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ASR -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, arithmeticShiftRight32, getFFlag, setZFlag, setNFlag32, setCFlag, getBit -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = (@b & 4294967295); -+ lc = (@c & 31); -+ @a = arithmeticShiftRight32 (lb, lc); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ if((lc == 0)) -+ { -+ setCFlag (0); -+ } -+ else -+ { -+ setCFlag (getBit (lb, (lc - 1))); -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ASR (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lb, b, 4294967295); -+ tcg_gen_andi_tl(lc, c, 31); -+ arithmeticShiftRight32(temp_6, lb, lc); -+ tcg_gen_mov_tl(a, temp_6); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, lc, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(temp_7, 0); -+ setCFlag(temp_7); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_subi_tl(temp_10, lc, 1); -+ getBit(temp_9, lb, temp_10); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ gen_set_label(done_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ASR8 -+ * Variables: @b, @a -+ * Functions: getCCFlag, arithmeticShiftRight32, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = (@b & 4294967295); -+ @a = arithmeticShiftRight32 (lb, 8); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ASR8 (DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lb, b, 4294967295); -+ tcg_gen_movi_tl(temp_5, 8); -+ arithmeticShiftRight32(temp_4, lb, temp_5); -+ tcg_gen_mov_tl(a, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ASR16 -+ * Variables: @b, @a -+ * Functions: getCCFlag, arithmeticShiftRight32, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = (@b & 4294967295); -+ @a = arithmeticShiftRight32 (lb, 16); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ASR16 (DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lb, b, 4294967295); -+ tcg_gen_movi_tl(temp_5, 16); -+ arithmeticShiftRight32(temp_4, lb, temp_5); -+ tcg_gen_mov_tl(a, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LSL16 -+ * Variables: @b, @a -+ * Functions: getCCFlag, logicalShiftLeft, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = (@b & 4294967295); -+ @a = logicalShiftLeft (lb, 16); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_LSL16 (DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lb, b, 4294967295); -+ tcg_gen_movi_tl(temp_5, 16); -+ logicalShiftLeft(temp_4, lb, temp_5); -+ tcg_gen_mov_tl(a, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LSL8 -+ * Variables: @b, @a -+ * Functions: getCCFlag, logicalShiftLeft, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = (@b & 4294967295); -+ @a = logicalShiftLeft (lb, 8); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_LSL8 (DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lb, b, 4294967295); -+ tcg_gen_movi_tl(temp_5, 8); -+ logicalShiftLeft(temp_4, lb, temp_5); -+ tcg_gen_mov_tl(a, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LSR -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag32, setCFlag, getBit -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = (@b & 4294967295); -+ lc = (@c & 31); -+ @a = logicalShiftRight (lb, lc); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ if((lc == 0)) -+ { -+ setCFlag (0); -+ } -+ else -+ { -+ setCFlag (getBit (lb, (lc - 1))); -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_LSR (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lb, b, 4294967295); -+ tcg_gen_andi_tl(lc, c, 31); -+ logicalShiftRight(temp_6, lb, lc); -+ tcg_gen_mov_tl(a, temp_6); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, lc, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(temp_7, 0); -+ setCFlag(temp_7); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_subi_tl(temp_10, lc, 1); -+ getBit(temp_9, lb, temp_10); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ gen_set_label(done_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LSR16 -+ * Variables: @b, @a -+ * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = (@b & 4294967295); -+ @a = logicalShiftRight (lb, 16); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_LSR16 (DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lb, b, 4294967295); -+ tcg_gen_movi_tl(temp_5, 16); -+ logicalShiftRight(temp_4, lb, temp_5); -+ tcg_gen_mov_tl(a, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LSR8 -+ * Variables: @b, @a -+ * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = (@b & 4294967295); -+ @a = logicalShiftRight (lb, 8); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_LSR8 (DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lb, b, 4294967295); -+ tcg_gen_movi_tl(temp_5, 8); -+ logicalShiftRight(temp_4, lb, temp_5); -+ tcg_gen_mov_tl(a, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BIC -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = (@b & ~@c); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BIC (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_not_tl(temp_4, c); -+ tcg_gen_and_tl(a, b, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BCLR -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = (1 << (@c & 31)); -+ @a = (@b & ~tmp); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BCLR (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_4, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, temp_4); -+ tcg_gen_not_tl(temp_5, tmp); -+ tcg_gen_and_tl(a, b, temp_5); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BMSK -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp1 = ((@c & 31) + 1); -+ if((tmp1 == 32)) -+ { -+ tmp2 = 0xffffffff; -+ } -+ else -+ { -+ tmp2 = ((1 << tmp1) - 1); -+ }; -+ @a = (@b & tmp2); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BMSK (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_6, c, 31); -+ tcg_gen_addi_tl(tmp1, temp_6, 1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, tmp1, 32); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(tmp2, 0xffffffff); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_shlfi_tl(temp_7, 1, tmp1); -+ tcg_gen_subi_tl(tmp2, temp_7, 1); -+ gen_set_label(done_2); -+ tcg_gen_and_tl(a, b, tmp2); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BMSKN -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp1 = ((@c & 31) + 1); -+ if((tmp1 == 32)) -+ { -+ tmp2 = 0xffffffff; -+ } -+ else -+ { -+ tmp2 = ((1 << tmp1) - 1); -+ }; -+ @a = (@b & ~tmp2); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BMSKN (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_6, c, 31); -+ tcg_gen_addi_tl(tmp1, temp_6, 1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, tmp1, 32); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(tmp2, 0xffffffff); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_shlfi_tl(temp_7, 1, tmp1); -+ tcg_gen_subi_tl(tmp2, temp_7, 1); -+ gen_set_label(done_2); -+ tcg_gen_not_tl(temp_8, tmp2); -+ tcg_gen_and_tl(a, b, temp_8); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BSET -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = (1 << (@c & 31)); -+ @a = (@b | tmp); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BSET (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_4, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, temp_4); -+ tcg_gen_or_tl(a, b, tmp); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BXOR -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = (1 << @c); -+ @a = (@b ^ tmp); -+ f_flag = getFFlag (); -+ @a = (@a & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BXOR (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_shlfi_tl(tmp, 1, c); -+ tcg_gen_xor_tl(a, b, tmp); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(tmp); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ROL -+ * Variables: @src, @n, @dest -+ * Functions: getCCFlag, rotateLeft32, getFFlag, setZFlag, setNFlag32, setCFlag, extractBits -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lsrc = (@src & 4294967295); -+ ln = (@n & 31); -+ @dest = rotateLeft32 (lsrc, ln); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ setCFlag (extractBits (lsrc, 31, 31)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ROL (DisasCtxt *ctx, TCGv src, TCGv n, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv ln = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lsrc, src, 4294967295); -+ tcg_gen_andi_tl(ln, n, 31); -+ rotateLeft32(temp_4, lsrc, ln); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+ tcg_gen_movi_tl(temp_8, 31); -+ tcg_gen_movi_tl(temp_7, 31); -+ extractBits(temp_6, lsrc, temp_7, temp_8); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(ln); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ROL8 -+ * Variables: @src, @dest -+ * Functions: getCCFlag, rotateLeft32, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lsrc = (@src & 4294967295); -+ @dest = rotateLeft32 (lsrc, 8); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ROL8 (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lsrc, src, 4294967295); -+ tcg_gen_movi_tl(temp_5, 8); -+ rotateLeft32(temp_4, lsrc, temp_5); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ROR -+ * Variables: @src, @n, @dest -+ * Functions: getCCFlag, rotateRight32, getFFlag, setZFlag, setNFlag32, setCFlag, extractBits -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lsrc = (@src & 4294967295); -+ ln = (@n & 31); -+ @dest = rotateRight32 (lsrc, ln); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ setCFlag (extractBits (lsrc, (ln - 1), (ln - 1))); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ROR (DisasCtxt *ctx, TCGv src, TCGv n, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv ln = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lsrc, src, 4294967295); -+ tcg_gen_andi_tl(ln, n, 31); -+ rotateRight32(temp_4, lsrc, ln); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+ tcg_gen_subi_tl(temp_8, ln, 1); -+ tcg_gen_subi_tl(temp_7, ln, 1); -+ extractBits(temp_6, lsrc, temp_7, temp_8); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(ln); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ROR8 -+ * Variables: @src, @dest -+ * Functions: getCCFlag, rotateRight32, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lsrc = (@src & 4294967295); -+ @dest = rotateRight32 (lsrc, 8); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ROR8 (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lsrc, src, 4294967295); -+ tcg_gen_movi_tl(temp_5, 8); -+ rotateRight32(temp_4, lsrc, temp_5); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* RLC -+ * Variables: @src, @dest -+ * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag32, setCFlag, extractBits -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lsrc = (@src & 4294967295); -+ @dest = (lsrc << 1); -+ @dest = (@dest | getCFlag ()); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ setCFlag (extractBits (lsrc, 31, 31)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_RLC (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lsrc, src, 4294967295); -+ tcg_gen_shli_tl(dest, lsrc, 1); -+ getCFlag(temp_5); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ tcg_gen_or_tl(dest, dest, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+ tcg_gen_movi_tl(temp_9, 31); -+ tcg_gen_movi_tl(temp_8, 31); -+ extractBits(temp_7, lsrc, temp_8, temp_9); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setCFlag(temp_6); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* RRC -+ * Variables: @src, @dest -+ * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag32, setCFlag, extractBits -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lsrc = (@src & 4294967295); -+ @dest = (lsrc >> 1); -+ @dest = (@dest | (getCFlag () << 31)); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ setCFlag (extractBits (lsrc, 0, 0)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_RRC (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(lsrc, src, 4294967295); -+ tcg_gen_shri_tl(dest, lsrc, 1); -+ getCFlag(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_shli_tl(temp_4, temp_5, 31); -+ tcg_gen_or_tl(dest, dest, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+ tcg_gen_movi_tl(temp_10, 0); -+ tcg_gen_movi_tl(temp_9, 0); -+ extractBits(temp_8, lsrc, temp_9, temp_10); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setCFlag(temp_7); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SEXB -+ * Variables: @dest, @src -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @dest = arithmeticShiftRight ((@src << 56), 56); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SEXB (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_6, 56); -+ tcg_gen_shli_tl(temp_5, src, 56); -+ arithmeticShiftRight(temp_4, temp_5, temp_6); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SEXH -+ * Variables: @dest, @src -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @dest = arithmeticShiftRight ((@src << 48), 48); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SEXH (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_6, 48); -+ tcg_gen_shli_tl(temp_5, src, 48); -+ arithmeticShiftRight(temp_4, temp_5, temp_6); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* EXTB -+ * Variables: @dest, @src -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @dest = (@src & 255); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_EXTB (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(dest, src, 255); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* EXTH -+ * Variables: @dest, @src -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @dest = (@src & 65535); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_EXTH (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(dest, src, 65535); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BTST -+ * Variables: @c, @b -+ * Functions: getCCFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = (1 << (@c & 31)); -+ alu = (@b & tmp); -+ alu = (alu & 4294967295); -+ setZFlag (alu); -+ setNFlag32 (alu); -+ }; -+} -+ */ -+ -+int -+arc_gen_BTST (DisasCtxt *ctx, TCGv c, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_4, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, temp_4); -+ tcg_gen_and_tl(alu, b, tmp); -+ tcg_gen_andi_tl(alu, alu, 4294967295); -+ setZFlag(alu); -+ setNFlag32(alu); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ tcg_temp_free(alu); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* TST -+ * Variables: @b, @c -+ * Functions: getCCFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ alu = (@b & @c); -+ alu = (alu & 4294967295); -+ setZFlag (alu); -+ setNFlag32 (alu); -+ }; -+} -+ */ -+ -+int -+arc_gen_TST (DisasCtxt *ctx, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_and_tl(alu, b, c); -+ tcg_gen_andi_tl(alu, alu, 4294967295); -+ setZFlag(alu); -+ setNFlag32(alu); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(alu); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* XBFU -+ * Variables: @src2, @src1, @dest -+ * Functions: getCCFlag, extractBits, getFFlag, setZFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ N = extractBits (@src2, 4, 0); -+ M = (extractBits (@src2, 9, 5) + 1); -+ tmp1 = (@src1 >> N); -+ tmp2 = ((1 << M) - 1); -+ @dest = (tmp1 & tmp2); -+ @dest = (@dest & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_XBFU (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv N = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv M = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_6, 0); -+ tcg_gen_movi_tl(temp_5, 4); -+ extractBits(temp_4, src2, temp_5, temp_6); -+ tcg_gen_mov_tl(N, temp_4); -+ tcg_gen_movi_tl(temp_10, 5); -+ tcg_gen_movi_tl(temp_9, 9); -+ extractBits(temp_8, src2, temp_9, temp_10); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_addi_tl(M, temp_7, 1); -+ tcg_gen_shr_tl(tmp1, src1, N); -+ tcg_gen_shlfi_tl(temp_11, 1, M); -+ tcg_gen_subi_tl(tmp2, temp_11, 1); -+ tcg_gen_and_tl(dest, tmp1, tmp2); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(N); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(M); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(tmp2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* AEX -+ * Variables: @src2, @b -+ * Functions: getCCFlag, readAuxReg, writeAuxReg -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = readAuxReg (@src2); -+ writeAuxReg (@src2, @b); -+ @b = tmp; -+ }; -+} -+ */ -+ -+int -+arc_gen_AEX (DisasCtxt *ctx, TCGv src2, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ readAuxReg(temp_4, src2); -+ tcg_gen_mov_tl(tmp, temp_4); -+ writeAuxReg(src2, b); -+ tcg_gen_mov_tl(b, tmp); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LR -+ * Variables: @dest, @src -+ * Functions: readAuxReg -+--- code --- -+{ -+ @dest = readAuxReg (@src); -+} -+ */ -+ -+int -+arc_gen_LR (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ -+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) -+ gen_io_start(); -+ -+ TCGv temp_1 = tcg_temp_local_new(); -+ readAuxReg(temp_1, src); -+ tcg_gen_andi_tl(temp_1, temp_1, 0xffffffff); -+ tcg_gen_mov_tl(dest, temp_1); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* CLRI -+ * Variables: @c -+ * Functions: getRegister, setRegister -+--- code --- -+{ -+ status32 = getRegister (R_STATUS32); -+ ie = (status32 & 2147483648); -+ ie = (ie >> 27); -+ e = ((status32 & 30) >> 1); -+ a = 32; -+ @c = ((ie | e) | a); -+ mask = 2147483648; -+ mask = ~mask; -+ status32 = (status32 & mask); -+ setRegister (R_STATUS32, status32); -+} -+ */ -+ -+int -+arc_gen_CLRI (DisasCtxt *ctx, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv status32 = tcg_temp_local_new(); -+ TCGv ie = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv e = tcg_temp_local_new(); -+ TCGv a = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv mask = tcg_temp_local_new(); -+ getRegister(temp_1, R_STATUS32); -+ tcg_gen_mov_tl(status32, temp_1); -+ tcg_gen_andi_tl(ie, status32, 2147483648); -+ tcg_gen_shri_tl(ie, ie, 27); -+ tcg_gen_andi_tl(temp_2, status32, 30); -+ tcg_gen_shri_tl(e, temp_2, 1); -+ tcg_gen_movi_tl(a, 32); -+ tcg_gen_or_tl(temp_3, ie, e); -+ tcg_gen_or_tl(c, temp_3, a); -+ tcg_gen_movi_tl(mask, 2147483648); -+ tcg_gen_not_tl(mask, mask); -+ tcg_gen_and_tl(status32, status32, mask); -+ setRegister(R_STATUS32, status32); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(status32); -+ tcg_temp_free(ie); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(e); -+ tcg_temp_free(a); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(mask); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETI -+ * Variables: @c -+ * Functions: getRegister, setRegister -+--- code --- -+{ -+ status32 = getRegister (R_STATUS32); -+ e_mask = 30; -+ e_mask = ~e_mask; -+ e_value = ((@c & 15) << 1); -+ temp1 = (@c & 32); -+ if((temp1 != 0)) -+ { -+ status32 = ((status32 & e_mask) | e_value); -+ ie_mask = 2147483648; -+ ie_mask = ~ie_mask; -+ ie_value = ((@c & 16) << 27); -+ status32 = ((status32 & ie_mask) | ie_value); -+ } -+ else -+ { -+ status32 = (status32 | 2147483648); -+ temp2 = (@c & 16); -+ if((temp2 != 0)) -+ { -+ status32 = ((status32 & e_mask) | e_value); -+ }; -+ }; -+ setRegister (R_STATUS32, status32); -+} -+ */ -+ -+int -+arc_gen_SETI (DisasCtxt *ctx, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv status32 = tcg_temp_local_new(); -+ TCGv e_mask = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv e_value = tcg_temp_local_new(); -+ TCGv temp1 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv ie_mask = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv ie_value = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getRegister(temp_5, R_STATUS32); -+ tcg_gen_mov_tl(status32, temp_5); -+ tcg_gen_movi_tl(e_mask, 30); -+ tcg_gen_not_tl(e_mask, e_mask); -+ tcg_gen_andi_tl(temp_6, c, 15); -+ tcg_gen_shli_tl(e_value, temp_6, 1); -+ tcg_gen_andi_tl(temp1, c, 32); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_1, temp1, 0); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_and_tl(temp_7, status32, e_mask); -+ tcg_gen_or_tl(status32, temp_7, e_value); -+ tcg_gen_movi_tl(ie_mask, 2147483648); -+ tcg_gen_not_tl(ie_mask, ie_mask); -+ tcg_gen_andi_tl(temp_8, c, 16); -+ tcg_gen_shli_tl(ie_value, temp_8, 27); -+ tcg_gen_and_tl(temp_9, status32, ie_mask); -+ tcg_gen_or_tl(status32, temp_9, ie_value); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_ori_tl(status32, status32, 2147483648); -+ tcg_gen_andi_tl(temp2, c, 16); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, temp2, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2);; -+ tcg_gen_and_tl(temp_10, status32, e_mask); -+ tcg_gen_or_tl(status32, temp_10, e_value); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ setRegister(R_STATUS32, status32); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(status32); -+ tcg_temp_free(e_mask); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(e_value); -+ tcg_temp_free(temp1); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(ie_mask); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(ie_value); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* NOP -+ * Variables: -+ * Functions: doNothing -+--- code --- -+{ -+ doNothing (); -+} -+ */ -+ -+int -+arc_gen_NOP (DisasCtxt *ctx) -+{ -+ int ret = DISAS_NEXT; -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* PREALLOC -+ * Variables: -+ * Functions: doNothing -+--- code --- -+{ -+ doNothing (); -+} -+ */ -+ -+int -+arc_gen_PREALLOC (DisasCtxt *ctx) -+{ -+ int ret = DISAS_NEXT; -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* PREFETCH -+ * Variables: @src1, @src2 -+ * Functions: getAAFlag, doNothing -+--- code --- -+{ -+ AA = getAAFlag (); -+ if(((AA == 1) || (AA == 2))) -+ { -+ @src1 = (@src1 + @src2); -+ } -+ else -+ { -+ doNothing (); -+ }; -+} -+ */ -+ -+int -+arc_gen_PREFETCH (DisasCtxt *ctx, TCGv src1, TCGv src2) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ AA = getAAFlag (); -+ if (((AA == 1) || (AA == 2))) -+ { -+ tcg_gen_add_tl(src1, src1, src2); -+; -+ } -+ else -+ { -+ doNothing(); -+; -+ } -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MPY -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, HELPER, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ _b = @b; -+ _c = @c; -+ @a = ((_b * _c) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ high_part = HELPER (mpym, _b, _c); -+ tmp1 = (high_part & 2147483648); -+ tmp2 = (@a & 2147483648); -+ setZFlag (@a); -+ setNFlag32 (high_part); -+ setVFlag ((tmp1 != tmp2)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MPY (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv _b = tcg_temp_local_new(); -+ TCGv _c = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv high_part = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(_b, b); -+ tcg_gen_mov_tl(_c, c); -+ tcg_gen_mul_tl(temp_4, _b, _c); -+ tcg_gen_andi_tl(a, temp_4, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ ARC_HELPER(mpym, high_part, _b, _c); -+ tcg_gen_andi_tl(tmp1, high_part, 2147483648); -+ tcg_gen_andi_tl(tmp2, a, 2147483648); -+ setZFlag(a); -+ setNFlag32(high_part); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_5, tmp1, tmp2); -+ setVFlag(temp_5); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(_b); -+ tcg_temp_free(_c); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(high_part); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MPYMU -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, HELPER, getFFlag, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = HELPER (mpymu, @b, @c); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (0); -+ setVFlag (0); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MPYMU (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ ARC_HELPER(mpymu, a, b, c); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ tcg_gen_movi_tl(temp_4, 0); -+ setNFlag32(temp_4); -+ tcg_gen_movi_tl(temp_5, 0); -+ setVFlag(temp_5); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MPYM -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, HELPER, getFFlag, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = HELPER (mpym, @b, @c); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setVFlag (0); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MPYM (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ ARC_HELPER(mpym, a, b, c); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ tcg_gen_movi_tl(temp_4, 0); -+ setVFlag(temp_4); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MPYU -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, HELPER, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ _b = @b; -+ _c = @c; -+ @a = ((_b * _c) & 4294967295); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ high_part = HELPER (mpym, _b, _c); -+ setZFlag (@a); -+ setNFlag32 (0); -+ setVFlag ((high_part > 0)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MPYU (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv _b = tcg_temp_local_new(); -+ TCGv _c = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv high_part = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(_b, b); -+ tcg_gen_mov_tl(_c, c); -+ tcg_gen_mul_tl(temp_4, _b, _c); -+ tcg_gen_andi_tl(a, temp_4, 4294967295); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ ARC_HELPER(mpym, high_part, _b, _c); -+ setZFlag(a); -+ tcg_gen_movi_tl(temp_5, 0); -+ setNFlag32(temp_5); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_6, high_part, 0); -+ setVFlag(temp_6); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(_b); -+ tcg_temp_free(_c); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(high_part); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MPYUW -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = ((@b & 65535) * (@c & 65535)); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (0); -+ setVFlag (0); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MPYUW (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_5, c, 65535); -+ tcg_gen_andi_tl(temp_4, b, 65535); -+ tcg_gen_mul_tl(a, temp_4, temp_5); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ tcg_gen_movi_tl(temp_6, 0); -+ setNFlag32(temp_6); -+ tcg_gen_movi_tl(temp_7, 0); -+ setVFlag(temp_7); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MPYW -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = (arithmeticShiftRight ((@b << 48), 48) * arithmeticShiftRight ((@c << 48), 48)); -+ @a = (@a & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag32 (@a); -+ setVFlag (0); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MPYW (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_11, 48); -+ tcg_gen_shli_tl(temp_10, c, 48); -+ tcg_gen_movi_tl(temp_7, 48); -+ tcg_gen_shli_tl(temp_6, b, 48); -+ arithmeticShiftRight(temp_5, temp_6, temp_7); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ arithmeticShiftRight(temp_9, temp_10, temp_11); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ tcg_gen_mul_tl(a, temp_4, temp_8); -+ tcg_gen_andi_tl(a, a, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag32(a); -+ tcg_gen_movi_tl(temp_12, 0); -+ setVFlag(temp_12); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_12); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* DIV -+ * Variables: @src2, @src1, @dest -+ * Functions: getCCFlag, divSigned, getFFlag, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ if(((@src2 != 0) && ((@src1 != 2147483648) || (@src2 != 4294967295)))) -+ { -+ @dest = divSigned (@src1, @src2); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ setVFlag (0); -+ }; -+ } -+ else -+ { -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_DIV (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_9); -+ tcg_gen_mov_tl(cc_flag, temp_9); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_4, src1, 2147483648); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_5, src2, 4294967295); -+ tcg_gen_or_tl(temp_6, temp_4, temp_5); -+ tcg_gen_and_tl(temp_7, temp_3, temp_6); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); tcg_gen_andi_tl(temp_8, temp_8, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, else_2);; -+ divSigned(temp_10, src1, src2); -+ tcg_gen_mov_tl(dest, temp_10); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+ tcg_gen_movi_tl(temp_11, 0); -+ setVFlag(temp_11); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* DIVU -+ * Variables: @src2, @dest, @src1 -+ * Functions: getCCFlag, divUnsigned, getFFlag, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ if((@src2 != 0)) -+ { -+ @dest = divUnsigned (@src1, @src2); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (0); -+ setVFlag (0); -+ }; -+ } -+ else -+ { -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_DIVU (DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ divUnsigned(temp_6, src1, src2); -+ tcg_gen_mov_tl(dest, temp_6); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ tcg_gen_movi_tl(temp_7, 0); -+ setNFlag32(temp_7); -+ tcg_gen_movi_tl(temp_8, 0); -+ setVFlag(temp_8); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* REM -+ * Variables: @src2, @src1, @dest -+ * Functions: getCCFlag, divRemainingSigned, getFFlag, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ if(((@src2 != 0) && ((@src1 != 2147483648) || (@src2 != 4294967295)))) -+ { -+ @dest = divRemainingSigned (@src1, @src2); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ setVFlag (0); -+ }; -+ } -+ else -+ { -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_REM (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_9); -+ tcg_gen_mov_tl(cc_flag, temp_9); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_4, src1, 2147483648); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_5, src2, 4294967295); -+ tcg_gen_or_tl(temp_6, temp_4, temp_5); -+ tcg_gen_and_tl(temp_7, temp_3, temp_6); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); tcg_gen_andi_tl(temp_8, temp_8, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, else_2);; -+ divRemainingSigned(temp_10, src1, src2); -+ tcg_gen_mov_tl(dest, temp_10); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+ tcg_gen_movi_tl(temp_11, 0); -+ setVFlag(temp_11); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* REMU -+ * Variables: @src2, @dest, @src1 -+ * Functions: getCCFlag, divRemainingUnsigned, getFFlag, setZFlag, setNFlag32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ if((@src2 != 0)) -+ { -+ @dest = divRemainingUnsigned (@src1, @src2); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (0); -+ setVFlag (0); -+ }; -+ } -+ else -+ { -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_REMU (DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ divRemainingUnsigned(temp_6, src1, src2); -+ tcg_gen_mov_tl(dest, temp_6); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ tcg_gen_movi_tl(temp_7, 0); -+ setNFlag32(temp_7); -+ tcg_gen_movi_tl(temp_8, 0); -+ setVFlag(temp_8); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MAC -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getRegister, MAC, getFFlag, setNFlag32, OverflowADD, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ old_acchi = getRegister (R_ACCHI); -+ high_mul = MAC (@b, @c); -+ @a = getRegister (R_ACCLO); -+ @a = @a & 0xffffffff; -+ if((getFFlag () == true)) -+ { -+ new_acchi = getRegister (R_ACCHI); -+ setNFlag32 (new_acchi); -+ if((OverflowADD (new_acchi, old_acchi, high_mul) == true)) -+ { -+ setVFlag (1); -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MAC (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv old_acchi = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv high_mul = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv new_acchi = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ getRegister(temp_6, R_ACCHI); -+ tcg_gen_mov_tl(old_acchi, temp_6); -+ MAC(temp_7, b, c); -+ tcg_gen_mov_tl(high_mul, temp_7); -+ getRegister(temp_8, R_ACCLO); -+ tcg_gen_andi_tl(a, a, 0xffffffff); -+ tcg_gen_mov_tl(a, temp_8); -+ if ((getFFlag () == true)) -+ { -+ getRegister(temp_9, R_ACCHI); -+ tcg_gen_mov_tl(new_acchi, temp_9); -+ setNFlag32(new_acchi); -+ TCGLabel *done_2 = gen_new_label(); -+ OverflowADD(temp_10, new_acchi, old_acchi, high_mul); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, temp_10, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2);; -+ tcg_gen_movi_tl(temp_11, 1); -+ setVFlag(temp_11); -+ gen_set_label(done_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(old_acchi); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(high_mul); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(new_acchi); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MACU -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getRegister, MACU, getFFlag, CarryADD32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ old_acchi = getRegister (R_ACCHI); -+ high_mul = MACU (@b, @c); -+ @a = getRegister (R_ACCLO); -+ if((getFFlag () == true)) -+ { -+ new_acchi = getRegister (R_ACCHI); -+ if((CarryADD32 (new_acchi, old_acchi, high_mul) == true)) -+ { -+ setVFlag (1); -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MACU (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv old_acchi = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv high_mul = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv new_acchi = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ getRegister(temp_6, R_ACCHI); -+ tcg_gen_mov_tl(old_acchi, temp_6); -+ MACU(temp_7, b, c); -+ tcg_gen_mov_tl(high_mul, temp_7); -+ getRegister(temp_8, R_ACCLO); -+ tcg_gen_mov_tl(a, temp_8); -+ if ((getFFlag () == true)) -+ { -+ getRegister(temp_9, R_ACCHI); -+ tcg_gen_mov_tl(new_acchi, temp_9); -+ TCGLabel *done_2 = gen_new_label(); -+ CarryADD32(temp_10, new_acchi, old_acchi, high_mul); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, temp_10, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2);; -+ tcg_gen_movi_tl(temp_11, 1); -+ setVFlag(temp_11); -+ gen_set_label(done_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(old_acchi); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(high_mul); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(new_acchi); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MACD -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getRegister, MAC, nextReg, getFFlag, setNFlag32, OverflowADD32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ old_acchi = getRegister (R_ACCHI); -+ high_mul = MAC (@b, @c); -+ @a = getRegister (R_ACCLO); -+ pair = nextReg (a); -+ pair = getRegister (R_ACCHI); -+ if((getFFlag () == true)) -+ { -+ new_acchi = getRegister (R_ACCHI); -+ setNFlag32 (new_acchi); -+ if((OverflowADD32 (new_acchi, old_acchi, high_mul) == true)) -+ { -+ setVFlag (1); -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MACD (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv old_acchi = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv high_mul = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv pair = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv new_acchi = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ getRegister(temp_6, R_ACCHI); -+ tcg_gen_mov_tl(old_acchi, temp_6); -+ MAC(temp_7, b, c); -+ tcg_gen_mov_tl(high_mul, temp_7); -+ getRegister(temp_8, R_ACCLO); -+ tcg_gen_mov_tl(a, temp_8); -+ pair = nextReg (a); -+ getRegister(temp_9, R_ACCHI); -+ tcg_gen_mov_tl(pair, temp_9); -+ if ((getFFlag () == true)) -+ { -+ getRegister(temp_10, R_ACCHI); -+ tcg_gen_mov_tl(new_acchi, temp_10); -+ setNFlag32(new_acchi); -+ TCGLabel *done_2 = gen_new_label(); -+ OverflowADD32(temp_11, new_acchi, old_acchi, high_mul); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, temp_11, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2);; -+ tcg_gen_movi_tl(temp_12, 1); -+ setVFlag(temp_12); -+ gen_set_label(done_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(old_acchi); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(high_mul); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(new_acchi); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_12); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MACDU -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getRegister, MACU, nextReg, getFFlag, CarryADD32, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ old_acchi = getRegister (R_ACCHI); -+ high_mul = MACU (@b, @c); -+ @a = getRegister (R_ACCLO); -+ pair = nextReg (a); -+ pair = getRegister (R_ACCHI); -+ if((getFFlag () == true)) -+ { -+ new_acchi = getRegister (R_ACCHI); -+ if((CarryADD32 (new_acchi, old_acchi, high_mul) == true)) -+ { -+ setVFlag (1); -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MACDU (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv old_acchi = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv high_mul = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv pair = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv new_acchi = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ getRegister(temp_6, R_ACCHI); -+ tcg_gen_mov_tl(old_acchi, temp_6); -+ MACU(temp_7, b, c); -+ tcg_gen_mov_tl(high_mul, temp_7); -+ getRegister(temp_8, R_ACCLO); -+ tcg_gen_mov_tl(a, temp_8); -+ pair = nextReg (a); -+ getRegister(temp_9, R_ACCHI); -+ tcg_gen_mov_tl(pair, temp_9); -+ if ((getFFlag () == true)) -+ { -+ getRegister(temp_10, R_ACCHI); -+ tcg_gen_mov_tl(new_acchi, temp_10); -+ TCGLabel *done_2 = gen_new_label(); -+ CarryADD32(temp_11, new_acchi, old_acchi, high_mul); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, temp_11, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2);; -+ tcg_gen_movi_tl(temp_12, 1); -+ setVFlag(temp_12); -+ gen_set_label(done_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(old_acchi); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(high_mul); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(new_acchi); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_12); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ABS -+ * Variables: @src, @dest -+ * Functions: se32to64, Carry32, getFFlag, setZFlag, setNFlag32, setCFlag, Zero, setVFlag, getNFlag -+--- code --- -+{ -+ lsrc = se32to64 (@src); -+ alu = (0 - lsrc); -+ if((Carry32 (lsrc) == 1)) -+ { -+ @dest = alu; -+ } -+ else -+ { -+ @dest = lsrc; -+ }; -+ @dest = (@dest & 4294967295); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ setCFlag (Zero ()); -+ setVFlag (getNFlag ()); -+ }; -+} -+ */ -+ -+int -+arc_gen_ABS (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ se32to64(temp_3, src); -+ tcg_gen_mov_tl(lsrc, temp_3); -+ tcg_gen_subfi_tl(alu, 0, lsrc); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ Carry32(temp_4, lsrc); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, temp_4, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(dest, alu); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_mov_tl(dest, lsrc); -+ gen_set_label(done_1); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+ tcg_gen_mov_tl(temp_5, Zero()); -+ setCFlag(temp_5); -+ tcg_gen_mov_tl(temp_6, getNFlag()); -+ setVFlag(temp_6); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(temp_3); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SWAP -+ * Variables: @src, @dest -+ * Functions: getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ tmp1 = (@src << 16); -+ tmp2 = ((@src >> 16) & 65535); -+ @dest = (tmp1 | tmp2); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ }; -+} -+ */ -+ -+int -+arc_gen_SWAP (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ int f_flag; -+ tcg_gen_shli_tl(tmp1, src, 16); -+ tcg_gen_shri_tl(temp_1, src, 16); -+ tcg_gen_andi_tl(tmp2, temp_1, 65535); -+ tcg_gen_or_tl(dest, tmp1, tmp2); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(tmp2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SWAPE -+ * Variables: @src, @dest -+ * Functions: getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ tmp1 = ((@src << 24) & 4278190080); -+ tmp2 = ((@src << 8) & 16711680); -+ tmp3 = ((@src >> 8) & 65280); -+ tmp4 = ((@src >> 24) & 255); -+ @dest = (((tmp1 | tmp2) | tmp3) | tmp4); -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ }; -+} -+ */ -+ -+int -+arc_gen_SWAPE (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv tmp3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ int f_flag; -+ tcg_gen_shli_tl(temp_1, src, 24); -+ tcg_gen_andi_tl(tmp1, temp_1, 4278190080); -+ tcg_gen_shli_tl(temp_2, src, 8); -+ tcg_gen_andi_tl(tmp2, temp_2, 16711680); -+ tcg_gen_shri_tl(temp_3, src, 8); -+ tcg_gen_andi_tl(tmp3, temp_3, 65280); -+ tcg_gen_shri_tl(temp_4, src, 24); -+ tcg_gen_andi_tl(tmp4, temp_4, 255); -+ tcg_gen_or_tl(temp_6, tmp1, tmp2); -+ tcg_gen_or_tl(temp_5, temp_6, tmp3); -+ tcg_gen_or_tl(dest, temp_5, tmp4); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(temp_1); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(tmp3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* NOT -+ * Variables: @dest, @src -+ * Functions: getFFlag, setZFlag, setNFlag32 -+--- code --- -+{ -+ @dest = ~@src; -+ f_flag = getFFlag (); -+ @dest = (@dest & 4294967295); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag32 (@dest); -+ }; -+} -+ */ -+ -+int -+arc_gen_NOT (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ int f_flag; -+ tcg_gen_not_tl(dest, src); -+ f_flag = getFFlag (); -+ tcg_gen_andi_tl(dest, dest, 4294967295); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag32(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BI -+ * Variables: @c -+ * Functions: setPC, nextInsnAddress -+--- code --- -+{ -+ setPC ((nextInsnAddress () + (@c << 2))); -+} -+ */ -+ -+int -+arc_gen_BI (DisasCtxt *ctx, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ tcg_gen_shli_tl(temp_4, c, 2); -+ nextInsnAddress(temp_3); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ tcg_gen_add_tl(temp_1, temp_2, temp_4); -+ setPC(temp_1); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BIH -+ * Variables: @c -+ * Functions: setPC, nextInsnAddress -+--- code --- -+{ -+ setPC ((nextInsnAddress () + (@c << 1))); -+} -+ */ -+ -+int -+arc_gen_BIH (DisasCtxt *ctx, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ tcg_gen_shli_tl(temp_4, c, 1); -+ nextInsnAddress(temp_3); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ tcg_gen_add_tl(temp_1, temp_2, temp_4); -+ setPC(temp_1); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* B -+ * Variables: @rd -+ * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ take_branch = false; -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ take_branch = true; -+ }; -+ bta = (getPCL () + @rd); -+ if((shouldExecuteDelaySlot () == true)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((cc_flag == true)) -+ { -+ setPC (bta); -+ }; -+} -+ */ -+ -+int -+arc_gen_B (DisasCtxt *ctx, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_1); -+ getPCL(temp_7); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ tcg_gen_add_tl(bta, temp_6, rd); -+ if ((shouldExecuteDelaySlot () == true)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2);; -+ setPC(bta); -+ gen_set_label(done_2); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* B_S -+ * Variables: @rd -+ * Functions: getCCFlag, setPC, getPCL -+--- code --- -+{ -+ take_branch = false; -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ }; -+ if((cc_flag == true)) -+ { -+ setPC ((getPCL () + @rd)); -+ }; -+} -+ */ -+ -+int -+arc_gen_B_S (DisasCtxt *ctx, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ gen_set_label(done_1); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2);; -+ getPCL(temp_8); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_add_tl(temp_6, temp_7, rd); -+ setPC(temp_6); -+ gen_set_label(done_2); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BBIT0 -+ * Variables: @b, @c, @rd -+ * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ take_branch = false; -+ cc_flag = getCCFlag (); -+ p_b = @b; -+ p_c = (@c & 31); -+ tmp = (1 << p_c); -+ if((cc_flag == true)) -+ { -+ if(((p_b && tmp) == 0)) -+ { -+ take_branch = true; -+ }; -+ }; -+ bta = (getPCL () + @rd); -+ if((shouldExecuteDelaySlot () == true)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((cc_flag == true)) -+ { -+ if(((p_b && tmp) == 0)) -+ { -+ setPC (bta); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BBIT0 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_11); -+ tcg_gen_mov_tl(cc_flag, temp_11); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_andi_tl(p_c, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, p_c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_and_tl(temp_3, p_b, tmp); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_4, temp_3, 0); -+ tcg_gen_xori_tl(temp_5, temp_4, 1); tcg_gen_andi_tl(temp_5, temp_5, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_5, arc_true, done_2);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ getPCL(temp_13); -+ tcg_gen_mov_tl(temp_12, temp_13); -+ tcg_gen_add_tl(bta, temp_12, rd); -+ if ((shouldExecuteDelaySlot () == true)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_6, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_7, temp_6, 1); tcg_gen_andi_tl(temp_7, temp_7, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_7, arc_true, done_3);; -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_and_tl(temp_8, p_b, tmp); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_9, temp_8, 0); -+ tcg_gen_xori_tl(temp_10, temp_9, 1); tcg_gen_andi_tl(temp_10, temp_10, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_10, arc_true, done_4);; -+ setPC(bta); -+ gen_set_label(done_4); -+ gen_set_label(done_3); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(tmp); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BBIT1 -+ * Variables: @b, @c, @rd -+ * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ take_branch = false; -+ cc_flag = getCCFlag (); -+ p_b = @b; -+ p_c = (@c & 31); -+ tmp = (1 << p_c); -+ if((cc_flag == true)) -+ { -+ if(((p_b && tmp) != 0)) -+ { -+ take_branch = true; -+ }; -+ }; -+ bta = (getPCL () + @rd); -+ if((shouldExecuteDelaySlot () == true)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((cc_flag == true)) -+ { -+ if(((p_b && tmp) != 0)) -+ { -+ setPC (bta); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BBIT1 (DisasCtxt *ctx, TCGv b, TCGv c, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_11); -+ tcg_gen_mov_tl(cc_flag, temp_11); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_andi_tl(p_c, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, p_c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_and_tl(temp_3, p_b, tmp); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_4, temp_3, 0); -+ tcg_gen_xori_tl(temp_5, temp_4, 1); tcg_gen_andi_tl(temp_5, temp_5, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_5, arc_true, done_2);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ getPCL(temp_13); -+ tcg_gen_mov_tl(temp_12, temp_13); -+ tcg_gen_add_tl(bta, temp_12, rd); -+ if ((shouldExecuteDelaySlot () == true)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_6, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_7, temp_6, 1); tcg_gen_andi_tl(temp_7, temp_7, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_7, arc_true, done_3);; -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_and_tl(temp_8, p_b, tmp); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_9, temp_8, 0); -+ tcg_gen_xori_tl(temp_10, temp_9, 1); tcg_gen_andi_tl(temp_10, temp_10, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_10, arc_true, done_4);; -+ setPC(bta); -+ gen_set_label(done_4); -+ gen_set_label(done_3); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(tmp); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BL -+ * Variables: @rd -+ * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, setBLINK, nextInsnAddressAfterDelaySlot, executeDelaySlot, nextInsnAddress, setPC -+--- code --- -+{ -+ take_branch = false; -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ take_branch = true; -+ }; -+ bta = (getPCL () + @rd); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ if(take_branch) -+ { -+ setBLINK (nextInsnAddressAfterDelaySlot ()); -+ }; -+ executeDelaySlot (bta, take_branch); -+ } -+ else -+ { -+ if(take_branch) -+ { -+ setBLINK (nextInsnAddress ()); -+ }; -+ }; -+ if((cc_flag == true)) -+ { -+ setPC (bta); -+ }; -+} -+ */ -+ -+int -+arc_gen_BL (DisasCtxt *ctx, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_1); -+ getPCL(temp_9); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ tcg_gen_add_tl(bta, temp_8, rd); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_xori_tl(temp_3, take_branch, 1); tcg_gen_andi_tl(temp_3, temp_3, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_3, arc_true, done_2);; -+ nextInsnAddressAfterDelaySlot(temp_11); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setBLINK(temp_10); -+ gen_set_label(done_2); -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_xori_tl(temp_4, take_branch, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_3);; -+ nextInsnAddress(temp_13); -+ tcg_gen_mov_tl(temp_12, temp_13); -+ setBLINK(temp_12); -+ gen_set_label(done_3); -+; -+ } -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_5, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, done_4);; -+ setPC(bta); -+ gen_set_label(done_4); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* J -+ * Variables: @src -+ * Functions: getCCFlag, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ take_branch = false; -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ take_branch = true; -+ }; -+ bta = @src; -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((cc_flag == true)) -+ { -+ setPC (bta); -+ }; -+} -+ */ -+ -+int -+arc_gen_J (DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_1); -+ tcg_gen_mov_tl(bta, src); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2);; -+ setPC(bta); -+ gen_set_label(done_2); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* JL -+ * Variables: @src -+ * Functions: getCCFlag, shouldExecuteDelaySlot, setBLINK, nextInsnAddressAfterDelaySlot, executeDelaySlot, nextInsnAddress, setPC -+--- code --- -+{ -+ take_branch = false; -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ take_branch = true; -+ }; -+ bta = @src; -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ if(take_branch) -+ { -+ setBLINK (nextInsnAddressAfterDelaySlot ()); -+ }; -+ executeDelaySlot (bta, take_branch); -+ } -+ else -+ { -+ if(take_branch) -+ { -+ setBLINK (nextInsnAddress ()); -+ }; -+ }; -+ if((cc_flag == true)) -+ { -+ setPC (bta); -+ }; -+} -+ */ -+ -+int -+arc_gen_JL (DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_1); -+ tcg_gen_mov_tl(bta, src); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_xori_tl(temp_3, take_branch, 1); tcg_gen_andi_tl(temp_3, temp_3, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_3, arc_true, done_2);; -+ nextInsnAddressAfterDelaySlot(temp_9); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setBLINK(temp_8); -+ gen_set_label(done_2); -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_xori_tl(temp_4, take_branch, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_3);; -+ nextInsnAddress(temp_11); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setBLINK(temp_10); -+ gen_set_label(done_3); -+; -+ } -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_5, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, done_4);; -+ setPC(bta); -+ gen_set_label(done_4); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETEQ -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b == p_c)) -+ { -+ } -+ else -+ { -+ }; -+ if((p_b == p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETEQ (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_8, p_b); -+ tcg_gen_mov_tl(p_b, temp_8); -+ se32to64(temp_9, p_c); -+ tcg_gen_mov_tl(p_c, temp_9); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BREQ -+ * Variables: @b, @c, @offset -+ * Functions: se32to64, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b == p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((p_b == p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BREQ (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_5, p_b); -+ tcg_gen_mov_tl(p_b, temp_5); -+ se32to64(temp_6, p_c); -+ tcg_gen_mov_tl(p_c, temp_6); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_8); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_add_tl(bta, temp_7, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETNE -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b != p_c)) -+ { -+ } -+ else -+ { -+ }; -+ if((p_b != p_c)) -+ { -+ @a = 0; -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETNE (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_8, p_b); -+ tcg_gen_mov_tl(p_b, temp_8); -+ se32to64(temp_9, p_c); -+ tcg_gen_mov_tl(p_c, temp_9); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRNE -+ * Variables: @b, @c, @offset -+ * Functions: se32to64, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b != p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((p_b != p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRNE (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_5, p_b); -+ tcg_gen_mov_tl(p_b, temp_5); -+ se32to64(temp_6, p_c); -+ tcg_gen_mov_tl(p_c, temp_6); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_8); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_add_tl(bta, temp_7, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETLT -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b < p_c)) -+ { -+ } -+ else -+ { -+ }; -+ if((p_b < p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETLT (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_8, p_b); -+ tcg_gen_mov_tl(p_b, temp_8); -+ se32to64(temp_9, p_c); -+ tcg_gen_mov_tl(p_c, temp_9); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRLT -+ * Variables: @b, @c, @offset -+ * Functions: se32to64, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b < p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((p_b < p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRLT (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_5, p_b); -+ tcg_gen_mov_tl(p_b, temp_5); -+ se32to64(temp_6, p_c); -+ tcg_gen_mov_tl(p_c, temp_6); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_8); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_add_tl(bta, temp_7, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETGE -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b >= p_c)) -+ { -+ } -+ else -+ { -+ }; -+ if((p_b >= p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETGE (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_8, p_b); -+ tcg_gen_mov_tl(p_b, temp_8); -+ se32to64(temp_9, p_c); -+ tcg_gen_mov_tl(p_c, temp_9); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRGE -+ * Variables: @b, @c, @offset -+ * Functions: se32to64, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b >= p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((p_b >= p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRGE (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_5, p_b); -+ tcg_gen_mov_tl(p_b, temp_5); -+ se32to64(temp_6, p_c); -+ tcg_gen_mov_tl(p_c, temp_6); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_8); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_add_tl(bta, temp_7, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETLE -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b <= p_c)) -+ { -+ } -+ else -+ { -+ }; -+ if((p_b <= p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETLE (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_8, p_b); -+ tcg_gen_mov_tl(p_b, temp_8); -+ se32to64(temp_9, p_c); -+ tcg_gen_mov_tl(p_c, temp_9); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LE, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETGT -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, se32to64 -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = (@b & 4294967295); -+ p_c = (@c & 4294967295); -+ p_b = se32to64 (p_b); -+ p_c = se32to64 (p_c); -+ take_branch = false; -+ if((p_b > p_c)) -+ { -+ } -+ else -+ { -+ }; -+ if((p_b > p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETGT (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(p_b, b, 4294967295); -+ tcg_gen_andi_tl(p_c, c, 4294967295); -+ se32to64(temp_8, p_b); -+ tcg_gen_mov_tl(p_b, temp_8); -+ se32to64(temp_9, p_c); -+ tcg_gen_mov_tl(p_c, temp_9); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GT, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GT, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); tcg_gen_andi_tl(temp_6, temp_6, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRLO -+ * Variables: @b, @c, @offset -+ * Functions: se32to64, unsignedLT, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = se32to64 (@b); -+ p_c = se32to64 (@c); -+ take_branch = false; -+ if(unsignedLT (p_b, p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if(unsignedLT (p_b, p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRLO (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ se32to64(temp_3, b); -+ tcg_gen_mov_tl(p_b, temp_3); -+ se32to64(temp_4, c); -+ tcg_gen_mov_tl(p_c, temp_4); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedLT(temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_5, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_7); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ tcg_gen_add_tl(bta, temp_6, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedLT(temp_8, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_8, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(p_b); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETLO -+ * Variables: @b, @c, @a -+ * Functions: se32to64, unsignedLT -+--- code --- -+{ -+ p_b = se32to64 (@b); -+ p_c = se32to64 (@c); -+ take_branch = false; -+ if(unsignedLT (p_b, p_c)) -+ { -+ } -+ else -+ { -+ }; -+ if(unsignedLT (p_b, p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETLO (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ se32to64(temp_3, b); -+ tcg_gen_mov_tl(p_b, temp_3); -+ se32to64(temp_4, c); -+ tcg_gen_mov_tl(p_c, temp_4); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedLT(temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_5, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1);; -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedLT(temp_6, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_6, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(p_b); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRHS -+ * Variables: @b, @c, @offset -+ * Functions: se32to64, unsignedGE, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = se32to64 (@b); -+ p_c = se32to64 (@c); -+ take_branch = false; -+ if(unsignedGE (p_b, p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if(unsignedGE (p_b, p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRHS (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ se32to64(temp_3, b); -+ tcg_gen_mov_tl(p_b, temp_3); -+ se32to64(temp_4, c); -+ tcg_gen_mov_tl(p_c, temp_4); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedGE(temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_5, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_7); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ tcg_gen_add_tl(bta, temp_6, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedGE(temp_8, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_8, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(p_b); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETHS -+ * Variables: @b, @c, @a -+ * Functions: se32to64, unsignedGE -+--- code --- -+{ -+ p_b = se32to64 (@b); -+ p_c = se32to64 (@c); -+ take_branch = false; -+ if(unsignedGE (p_b, p_c)) -+ { -+ } -+ else -+ { -+ }; -+ if(unsignedGE (p_b, p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETHS (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ se32to64(temp_3, b); -+ tcg_gen_mov_tl(p_b, temp_3); -+ se32to64(temp_4, c); -+ tcg_gen_mov_tl(p_c, temp_4); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedGE(temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_5, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1);; -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedGE(temp_6, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_6, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(p_b); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* EX -+ * Variables: @b, @c -+ * Functions: getMemory, setMemory -+--- code --- -+{ -+ temp = @b; -+ @b = getMemory (@c, LONG); -+ setMemory (@c, LONG, temp); -+} -+ */ -+ -+int -+arc_gen_EX (DisasCtxt *ctx, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(temp, b); -+ getMemory(temp_1, c, LONG); -+ tcg_gen_mov_tl(b, temp_1); -+ setMemory(c, LONG, temp); -+ tcg_temp_free(temp); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LLOCK -+ * Variables: @dest, @src -+ * Functions: getMemory, setLF -+--- code --- -+{ -+ @dest = getMemory (@src, LONG); -+ setLF (1); -+} -+ */ -+ -+int -+arc_gen_LLOCK (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ getMemory(temp_1, src, LONG); -+ tcg_gen_mov_tl(dest, temp_1); -+ tcg_gen_movi_tl(temp_2, 1); -+ setLF(temp_2); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LLOCKD -+ * Variables: @dest, @src -+ * Functions: getMemory, nextReg, setLF -+--- code --- -+{ -+ @dest = getMemory (@src, LONG); -+ pair = nextReg (dest); -+ pair = getMemory ((@src + 4), LONG); -+ setLF (1); -+} -+ */ -+ -+int -+arc_gen_LLOCKD (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv pair = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getMemory(temp_1, src, LONG); -+ tcg_gen_mov_tl(dest, temp_1); -+ pair = nextReg (dest); -+ tcg_gen_addi_tl(temp_3, src, 4); -+ getMemory(temp_2, temp_3, LONG); -+ tcg_gen_mov_tl(pair, temp_2); -+ tcg_gen_movi_tl(temp_4, 1); -+ setLF(temp_4); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SCOND -+ * Variables: @src, @dest -+ * Functions: getLF, setMemory, setZFlag, setLF -+--- code --- -+{ -+ lf = getLF (); -+ if((lf == 1)) -+ { -+ setMemory (@src, LONG, @dest); -+ }; -+ setZFlag (!lf); -+ setLF (0); -+} -+ */ -+ -+int -+arc_gen_SCOND (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv lf = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getLF(temp_3); -+ tcg_gen_mov_tl(lf, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, lf, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ setMemory(src, LONG, dest); -+ gen_set_label(done_1); -+ tcg_gen_xori_tl(temp_4, lf, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ setZFlag(temp_4); -+ tcg_gen_movi_tl(temp_5, 0); -+ setLF(temp_5); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(lf); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SCONDD -+ * Variables: @src, @dest -+ * Functions: getLF, setMemory, nextReg, setZFlag, setLF -+--- code --- -+{ -+ lf = getLF (); -+ if((lf == 1)) -+ { -+ setMemory (@src, LONG, @dest); -+ pair = nextReg (dest); -+ setMemory ((@src + 4), LONG, pair); -+ }; -+ setZFlag (!lf); -+ setLF (0); -+} -+ */ -+ -+int -+arc_gen_SCONDD (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv lf = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv pair = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getLF(temp_3); -+ tcg_gen_mov_tl(lf, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, lf, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ setMemory(src, LONG, dest); -+ pair = nextReg (dest); -+ tcg_gen_addi_tl(temp_4, src, 4); -+ setMemory(temp_4, LONG, pair); -+ gen_set_label(done_1); -+ tcg_gen_xori_tl(temp_5, lf, 1); tcg_gen_andi_tl(temp_5, temp_5, 1);; -+ setZFlag(temp_5); -+ tcg_gen_movi_tl(temp_6, 0); -+ setLF(temp_6); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(lf); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* DMB -+ * Variables: @a -+ * Functions: -+--- code --- -+{ -+ @a = @a; -+} -+ */ -+ -+int -+arc_gen_DMB (DisasCtxt *ctx, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LD -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setDebugLD, getMemory, getFlagX, SignExtend, NoFurtherLoadsPending -+--- code --- -+{ -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ address = 0; -+ if(((AA == 0) || (AA == 1))) -+ { -+ address = (@src1 + @src2); -+ }; -+ if((AA == 2)) -+ { -+ address = @src1; -+ }; -+ if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ address = (@src1 + (@src2 << 2)); -+ }; -+ if(((AA == 3) && (ZZ == 2))) -+ { -+ address = (@src1 + (@src2 << 1)); -+ }; -+ l_src1 = @src1; -+ l_src2 = @src2; -+ setDebugLD (1); -+ new_dest = getMemory (address, ZZ); -+ if(((AA == 1) || (AA == 2))) -+ { -+ @src1 = (l_src1 + l_src2); -+ }; -+ if((getFlagX () == 1)) -+ { -+ new_dest = SignExtend (new_dest, ZZ); -+ }; -+ if(NoFurtherLoadsPending ()) -+ { -+ setDebugLD (0); -+ }; -+ @dest = new_dest; -+} -+ */ -+ -+int -+arc_gen_LD (DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv l_src1 = tcg_temp_local_new(); -+ TCGv l_src2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv new_dest = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) -+ { -+ tcg_gen_add_tl(address, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if ((AA == 2)) -+ { -+ tcg_gen_mov_tl(address, src1); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ tcg_gen_shli_tl(temp_2, src2, 2); -+ tcg_gen_add_tl(address, src1, temp_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && (ZZ == 2))) -+ { -+ tcg_gen_shli_tl(temp_3, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_3); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_mov_tl(l_src1, src1); -+ tcg_gen_mov_tl(l_src2, src2); -+ tcg_gen_movi_tl(temp_4, 1); -+ setDebugLD(temp_4); -+ getMemory(temp_5, address, ZZ); -+ tcg_gen_mov_tl(new_dest, temp_5); -+ if (((AA == 1) || (AA == 2))) -+ { -+ tcg_gen_add_tl(src1, l_src1, l_src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if ((getFlagX () == 1)) -+ { -+ new_dest = SignExtend (new_dest, ZZ); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *done_1 = gen_new_label(); -+ NoFurtherLoadsPending(temp_6); -+ tcg_gen_xori_tl(temp_1, temp_6, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_7, 0); -+ setDebugLD(temp_7); -+ gen_set_label(done_1); -+ tcg_gen_mov_tl(dest, new_dest); -+ tcg_temp_free(address); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(l_src1); -+ tcg_temp_free(l_src2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(new_dest); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LDD -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setDebugLD, getMemory, nextReg, NoFurtherLoadsPending -+--- code --- -+{ -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ address = 0; -+ if(((AA == 0) || (AA == 1))) -+ { -+ address = (@src1 + @src2); -+ }; -+ if((AA == 2)) -+ { -+ address = @src1; -+ }; -+ if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ address = (@src1 + (@src2 << 2)); -+ }; -+ if(((AA == 3) && (ZZ == 2))) -+ { -+ address = (@src1 + (@src2 << 1)); -+ }; -+ l_src1 = @src1; -+ l_src2 = @src2; -+ setDebugLD (1); -+ new_dest = getMemory (address, LONG); -+ pair = nextReg (dest); -+ pair = getMemory ((address + 4), LONG); -+ if(((AA == 1) || (AA == 2))) -+ { -+ @src1 = (l_src1 + l_src2); -+ }; -+ if(NoFurtherLoadsPending ()) -+ { -+ setDebugLD (0); -+ }; -+ @dest = new_dest; -+} -+ */ -+ -+int -+arc_gen_LDD (DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv l_src1 = tcg_temp_local_new(); -+ TCGv l_src2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv new_dest = tcg_temp_local_new(); -+ TCGv pair = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) -+ { -+ tcg_gen_add_tl(address, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if ((AA == 2)) -+ { -+ tcg_gen_mov_tl(address, src1); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ tcg_gen_shli_tl(temp_2, src2, 2); -+ tcg_gen_add_tl(address, src1, temp_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && (ZZ == 2))) -+ { -+ tcg_gen_shli_tl(temp_3, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_3); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_mov_tl(l_src1, src1); -+ tcg_gen_mov_tl(l_src2, src2); -+ tcg_gen_movi_tl(temp_4, 1); -+ setDebugLD(temp_4); -+ getMemory(temp_5, address, LONG); -+ tcg_gen_mov_tl(new_dest, temp_5); -+ pair = nextReg (dest); -+ tcg_gen_addi_tl(temp_7, address, 4); -+ getMemory(temp_6, temp_7, LONG); -+ tcg_gen_mov_tl(pair, temp_6); -+ if (((AA == 1) || (AA == 2))) -+ { -+ tcg_gen_add_tl(src1, l_src1, l_src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *done_1 = gen_new_label(); -+ NoFurtherLoadsPending(temp_8); -+ tcg_gen_xori_tl(temp_1, temp_8, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_9, 0); -+ setDebugLD(temp_9); -+ gen_set_label(done_1); -+ tcg_gen_mov_tl(dest, new_dest); -+ tcg_temp_free(address); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(l_src1); -+ tcg_temp_free(l_src2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(new_dest); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_9); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ST -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setMemory -+--- code --- -+{ -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ address = 0; -+ if(((AA == 0) || (AA == 1))) -+ { -+ address = (@src1 + @src2); -+ }; -+ if((AA == 2)) -+ { -+ address = @src1; -+ }; -+ if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ address = (@src1 + (@src2 << 2)); -+ }; -+ if(((AA == 3) && (ZZ == 2))) -+ { -+ address = (@src1 + (@src2 << 1)); -+ }; -+ setMemory (address, ZZ, @dest); -+ if(((AA == 1) || (AA == 2))) -+ { -+ @src1 = (@src1 + @src2); -+ }; -+} -+ */ -+ -+int -+arc_gen_ST (DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) -+ { -+ tcg_gen_add_tl(address, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if ((AA == 2)) -+ { -+ tcg_gen_mov_tl(address, src1); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ tcg_gen_shli_tl(temp_1, src2, 2); -+ tcg_gen_add_tl(address, src1, temp_1); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && (ZZ == 2))) -+ { -+ tcg_gen_shli_tl(temp_2, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ setMemory(address, ZZ, dest); -+ if (((AA == 1) || (AA == 2))) -+ { -+ tcg_gen_add_tl(src1, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(address); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* STD -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setMemory, instructionHasRegisterOperandIn, nextReg, getBit -+--- code --- -+{ -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ address = 0; -+ if(((AA == 0) || (AA == 1))) -+ { -+ address = (@src1 + @src2); -+ }; -+ if((AA == 2)) -+ { -+ address = @src1; -+ }; -+ if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ address = (@src1 + (@src2 << 2)); -+ }; -+ if(((AA == 3) && (ZZ == 2))) -+ { -+ address = (@src1 + (@src2 << 1)); -+ }; -+ setMemory (address, LONG, @dest); -+ if(instructionHasRegisterOperandIn (0)) -+ { -+ pair = nextReg (dest); -+ } -+ else -+ { -+ if((getBit (@dest, 31) == 1)) -+ { -+ pair = 4294967295; -+ } -+ else -+ { -+ pair = 0; -+ }; -+ }; -+ setMemory ((address + 4), LONG, pair); -+ if(((AA == 1) || (AA == 2))) -+ { -+ @src1 = (@src1 + @src2); -+ }; -+} -+ */ -+ -+int -+arc_gen_STD (DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv pair = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) -+ { -+ tcg_gen_add_tl(address, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if ((AA == 2)) -+ { -+ tcg_gen_mov_tl(address, src1); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ tcg_gen_shli_tl(temp_3, src2, 2); -+ tcg_gen_add_tl(address, src1, temp_3); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && (ZZ == 2))) -+ { -+ tcg_gen_shli_tl(temp_4, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_4); -+; -+ } -+ else -+ { -+ ; -+ } -+ setMemory(address, LONG, dest); -+ if (instructionHasRegisterOperandIn (0)) -+ { -+ pair = nextReg (dest); -+; -+ } -+ else -+ { -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_movi_tl(temp_6, 31); -+ getBit(temp_5, dest, temp_6); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, temp_5, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_movi_tl(pair, 4294967295); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_movi_tl(pair, 0); -+ gen_set_label(done_1); -+; -+ } -+ tcg_gen_addi_tl(temp_7, address, 4); -+ setMemory(temp_7, LONG, pair); -+ if (((AA == 1) || (AA == 2))) -+ { -+ tcg_gen_add_tl(src1, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(address); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* POP -+ * Variables: @dest -+ * Functions: getMemory, getRegister, setRegister -+--- code --- -+{ -+ new_dest = getMemory (getRegister (R_SP), LONG); -+ setRegister (R_SP, (getRegister (R_SP) + 4)); -+ @dest = new_dest; -+} -+ */ -+ -+int -+arc_gen_POP (DisasCtxt *ctx, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv new_dest = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getRegister(temp_3, R_SP); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ getMemory(temp_1, temp_2, LONG); -+ tcg_gen_mov_tl(new_dest, temp_1); -+ getRegister(temp_6, R_SP); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_addi_tl(temp_4, temp_5, 4); -+ setRegister(R_SP, temp_4); -+ tcg_gen_mov_tl(dest, new_dest); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(new_dest); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* PUSH -+ * Variables: @src -+ * Functions: setMemory, getRegister, setRegister -+--- code --- -+{ -+ local_src = @src; -+ setMemory ((getRegister (R_SP) - 4), LONG, local_src); -+ setRegister (R_SP, (getRegister (R_SP) - 4)); -+} -+ */ -+ -+int -+arc_gen_PUSH (DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv local_src = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(local_src, src); -+ getRegister(temp_3, R_SP); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ tcg_gen_subi_tl(temp_1, temp_2, 4); -+ setMemory(temp_1, LONG, local_src); -+ getRegister(temp_6, R_SP); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_subi_tl(temp_4, temp_5, 4); -+ setRegister(R_SP, temp_4); -+ tcg_temp_free(local_src); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LP -+ * Variables: @rd -+ * Functions: getCCFlag, getRegIndex, writeAuxReg, nextInsnAddress, getPCL, setPC -+--- code --- -+{ -+ if((getCCFlag () == true)) -+ { -+ lp_start_index = getRegIndex (LP_START); -+ lp_end_index = getRegIndex (LP_END); -+ writeAuxReg (lp_start_index, nextInsnAddress ()); -+ writeAuxReg (lp_end_index, (getPCL () + @rd)); -+ } -+ else -+ { -+ setPC ((getPCL () + @rd)); -+ }; -+} -+ */ -+ -+int -+arc_gen_LP (DisasCtxt *ctx, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lp_start_index = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lp_end_index = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ getCCFlag(temp_3); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, temp_3, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ getRegIndex(temp_4, LP_START); -+ tcg_gen_mov_tl(lp_start_index, temp_4); -+ getRegIndex(temp_5, LP_END); -+ tcg_gen_mov_tl(lp_end_index, temp_5); -+ nextInsnAddress(temp_7); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ writeAuxReg(lp_start_index, temp_6); -+ getPCL(temp_10); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ tcg_gen_add_tl(temp_8, temp_9, rd); -+ writeAuxReg(lp_end_index, temp_8); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ getPCL(temp_13); -+ tcg_gen_mov_tl(temp_12, temp_13); -+ tcg_gen_add_tl(temp_11, temp_12, rd); -+ setPC(temp_11); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lp_start_index); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lp_end_index); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+ -+ -+/* -+ * NORM -+ * Variables: @src, @dest -+ * Functions: CRLSB, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = @src; -+ * psrc = SignExtend16to32 (psrc); -+ * @dest = 32 - CRLSB (psrc); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_NORM(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ tcg_gen_mov_tl(psrc, src); -+ tcg_gen_ext32s_tl(psrc, psrc); -+ tcg_gen_clrsb_tl(dest, psrc); -+ tcg_gen_subi_tl(dest, dest, 32); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ -+ return ret; -+} -+ -+ -+/* -+ * NORMH -+ * Variables: @src, @dest -+ * Functions: SignExtend16to32, CRLSB, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = (@src & 65535); -+ * psrc = SignExtend16to32 (psrc); -+ * @dest = CRLSB (psrc); -+ * @dest = (@dest - 16); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_NORMH(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ tcg_gen_andi_tl(psrc, src, 65535); -+ tcg_gen_ext16s_tl(psrc, psrc); -+ tcg_gen_clrsb_tl(dest, psrc); -+ tcg_gen_subi_tl(dest, dest, 16); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ -+ return ret; -+} -+ -+ -+/* -+ * FLS -+ * Variables: @src, @dest -+ * Functions: CLZ, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = @src & 0xffffffff; -+ * if((psrc == 0)) -+ * { -+ * @dest = 0; -+ * } -+ * else -+ * { -+ * @dest = 63 - CLZ (psrc, 32); -+ * }; -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_FLS(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ tcg_gen_andi_tl(psrc, src, 0xffffffff); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, psrc, 0); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_movi_tl(dest, 0); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_movi_tl(temp_5, 32); -+ tcg_gen_clz_tl(temp_4, psrc, temp_5); -+ tcg_gen_mov_tl(temp_3, temp_4); -+ tcg_gen_subfi_tl(dest, 63, temp_3); -+ gen_set_label(done_1); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* -+ * FFS -+ * Variables: @src, @dest -+ * Functions: CTZ, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = @src; -+ * if((psrc == 0)) -+ * { -+ * @dest = 31; -+ * } -+ * else -+ * { -+ * @dest = CTZ (psrc, 32); -+ * }; -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_FFS(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(psrc, src); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, psrc, 0); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_movi_tl(dest, 31); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_movi_tl(temp_4, 32); -+ tcg_gen_ctz_tl(temp_3, psrc, temp_4); -+ tcg_gen_mov_tl(dest, temp_3); -+ gen_set_label(done_1); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ -+ return ret; -+} -+ -+ -+ -+/* -+ * Long instructions -+ */ -+ -+ -+/* ADDL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, setVFlag, OverflowADD -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ lc = @c; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = @c; -+ @a = (@b + @c); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarryADD (@a, lb, lc)); -+ setVFlag (OverflowADD (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADDL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_add_tl(a, b, c); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowADD(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ADD1L -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, setVFlag, OverflowADD -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ lc = @c; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = @c; -+ @a = (@b + (@c << 1)); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarryADD (@a, lb, lc)); -+ setVFlag (OverflowADD (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADD1L (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_shli_tl(temp_4, c, 1); -+ tcg_gen_add_tl(a, b, temp_4); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_6, a, lb, lc); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+ OverflowADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setVFlag(temp_7); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ADD2L -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, setVFlag, OverflowADD -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ lc = @c; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = @c; -+ @a = (@b + (@c << 2)); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarryADD (@a, lb, lc)); -+ setVFlag (OverflowADD (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADD2L (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_shli_tl(temp_4, c, 2); -+ tcg_gen_add_tl(a, b, temp_4); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_6, a, lb, lc); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+ OverflowADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setVFlag(temp_7); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ADD3L -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, setVFlag, OverflowADD -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ lc = @c; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = @c; -+ @a = (@b + (@c << 3)); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarryADD (@a, lb, lc)); -+ setVFlag (OverflowADD (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADD3L (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_shli_tl(temp_4, c, 3); -+ tcg_gen_add_tl(a, b, temp_4); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_6, a, lb, lc); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+ OverflowADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setVFlag(temp_7); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ADCL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, setVFlag, OverflowADD -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ lc = @c; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = @c; -+ @a = ((@b + @c) + getCFlag ()); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarryADD (@a, lb, lc)); -+ setVFlag (OverflowADD (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ADCL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_add_tl(temp_4, b, c); -+ getCFlag(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(a, temp_4, temp_5); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setCFlag(temp_7); -+ OverflowADD(temp_10, a, lb, lc); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ setVFlag(temp_9); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SBCL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, setVFlag, OverflowADD -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ lc = @c; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = @c; -+ @a = ((@b - @c) - getCFlag ()); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarryADD (@a, lb, lc)); -+ setVFlag (OverflowADD (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SBCL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_sub_tl(temp_4, b, c); -+ getCFlag(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_sub_tl(a, temp_4, temp_5); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setCFlag(temp_7); -+ OverflowADD(temp_10, a, lb, lc); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ setVFlag(temp_9); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SUBL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, setVFlag, OverflowSUB -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = @c; -+ @a = (@b - @c); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarrySUB (@a, lb, lc)); -+ setVFlag (OverflowSUB (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SUBL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_sub_tl(a, b, c); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarrySUB(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SUB1L -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, setVFlag, OverflowSUB -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = (@c << 1); -+ @a = (@b - lc); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarrySUB (@a, lb, lc)); -+ setVFlag (OverflowSUB (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SUB1L (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_shli_tl(lc, c, 1); -+ tcg_gen_sub_tl(a, b, lc); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarrySUB(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SUB2L -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, setVFlag, OverflowSUB -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = (@c << 2); -+ @a = (@b - lc); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarrySUB (@a, lb, lc)); -+ setVFlag (OverflowSUB (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SUB2L (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_shli_tl(lc, c, 2); -+ tcg_gen_sub_tl(a, b, lc); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarrySUB(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SUB3L -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, setVFlag, OverflowSUB -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = (@c << 3); -+ @a = (@b - lc); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ setCFlag (CarrySUB (@a, lb, lc)); -+ setVFlag (OverflowSUB (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SUB3L (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_shli_tl(lc, c, 3); -+ tcg_gen_sub_tl(a, b, lc); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ CarrySUB(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MAXL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, setVFlag, OverflowSUB -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = @c; -+ alu = (lb - lc); -+ if((lc >= lb)) -+ { -+ @a = lc; -+ } -+ else -+ { -+ @a = lb; -+ }; -+ if((getFFlag () == true)) -+ { -+ setZFlag (alu); -+ setNFlag (alu); -+ setCFlag (CarrySUB (@a, lb, lc)); -+ setVFlag (OverflowSUB (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MAXL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_sub_tl(alu, lb, lc); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_3, lc, lb); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, lc); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, lb); -+ gen_set_label(done_2); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(alu); -+ setNFlag(alu); -+ CarrySUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setCFlag(temp_6); -+ OverflowSUB(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setVFlag(temp_8); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MINL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, setVFlag, OverflowSUB -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ lb = @b; -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = @c; -+ alu = (lb - lc); -+ if((lc <= lb)) -+ { -+ @a = lc; -+ } -+ else -+ { -+ @a = lb; -+ }; -+ if((getFFlag () == true)) -+ { -+ setZFlag (alu); -+ setNFlag (alu); -+ setCFlag (CarrySUB (@a, lb, lc)); -+ setVFlag (OverflowSUB (@a, lb, lc)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MINL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_sub_tl(alu, lb, lc); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LE, temp_3, lc, lb); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, lc); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, lb); -+ gen_set_label(done_2); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(alu); -+ setNFlag(alu); -+ CarrySUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setCFlag(temp_6); -+ OverflowSUB(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setVFlag(temp_8); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* CMPL -+ * Variables: @b, @c -+ * Functions: getCCFlag, setZFlag, setNFlag, setCFlag, CarrySUB, setVFlag, OverflowSUB -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ alu = (@b - @c); -+ setZFlag (alu); -+ setNFlag (alu); -+ setCFlag (CarrySUB (alu, @b, @c)); -+ setVFlag (OverflowSUB (alu, @b, @c)); -+ }; -+} -+ */ -+ -+int -+arc_gen_CMPL (DisasCtxt *ctx, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_sub_tl(alu, b, c); -+ setZFlag(alu); -+ setNFlag(alu); -+ CarrySUB(temp_5, alu, b, c); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, alu, b, c); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ANDL -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = (@b & @c); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ANDL (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_and_tl(a, b, c); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ORL -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = (@b | @c); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ORL (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_or_tl(a, b, c); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* XORL -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = (@b ^ @c); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_XORL (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_xor_tl(a, b, c); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* MOVL -+ * Variables: @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = @b; -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MOVL (DisasCtxt *ctx, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(a, b); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+/* MOVHL -+ * Variables: @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = @b << 32; -+ @a = @b -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_MOVHL (DisasCtxt *ctx, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ -+ //tmp = @b << 32; -+ //@a = tmp; -+ -+ tcg_gen_shli_tl(temp_4, b, 32); -+ tcg_gen_mov_tl(a, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ASLL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, getBit -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = (@c & 63); -+ @a = (lb << lc); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ if((lc == 0)) -+ { -+ setCFlag (0); -+ } -+ else -+ { -+ setCFlag (getBit (lb, (64 - lc))); -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ASLL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_andi_tl(lc, c, 63); -+ tcg_gen_shl_tl(a, lb, lc); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, lc, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(temp_6, 0); -+ setCFlag(temp_6); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_subfi_tl(temp_9, 64, lc); -+ getBit(temp_8, lb, temp_9); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setCFlag(temp_7); -+ gen_set_label(done_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ASRL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag, setCFlag, getBit -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = (@c & 63); -+ @a = arithmeticShiftRight (lb, lc); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ if((lc == 0)) -+ { -+ setCFlag (0); -+ } -+ else -+ { -+ setCFlag (getBit (lb, (lc - 1))); -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ASRL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_andi_tl(lc, c, 63); -+ arithmeticShiftRight(temp_6, lb, lc); -+ tcg_gen_mov_tl(a, temp_6); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, lc, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(temp_7, 0); -+ setCFlag(temp_7); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_subi_tl(temp_10, lc, 1); -+ getBit(temp_9, lb, temp_10); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ gen_set_label(done_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LSRL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag, setCFlag, getBit -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lb = @b; -+ lc = (@c & 63); -+ @a = logicalShiftRight (lb, lc); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ if((lc == 0)) -+ { -+ setCFlag (0); -+ } -+ else -+ { -+ setCFlag (getBit (lb, (lc - 1))); -+ }; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_LSRL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_andi_tl(lc, c, 63); -+ logicalShiftRight(temp_6, lb, lc); -+ tcg_gen_mov_tl(a, temp_6); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, lc, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(temp_7, 0); -+ setCFlag(temp_7); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_subi_tl(temp_10, lc, 1); -+ getBit(temp_9, lb, temp_10); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ gen_set_label(done_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+ -+/* BICL -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @a = (@b & ~@c); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BICL (DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_not_tl(temp_4, c); -+ tcg_gen_and_tl(a, b, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BCLRL -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = (1 << (@c & 63)); -+ @a = (@b & ~tmp); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BCLRL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_4, c, 63); -+ tcg_gen_shlfi_tl(tmp, 1, temp_4); -+ tcg_gen_not_tl(temp_5, tmp); -+ tcg_gen_and_tl(a, b, temp_5); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BMSKL -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp1 = ((@c & 63) + 1); -+ if((tmp1 == 64)) -+ { -+ tmp2 = 0xffffffffffffffff; -+ } -+ else -+ { -+ tmp2 = ((1 << tmp1) - 1); -+ }; -+ @a = (@b & tmp2); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BMSKL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_6, c, 63); -+ tcg_gen_addi_tl(tmp1, temp_6, 1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, tmp1, 64); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(tmp2, 0xffffffffffffffff); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_shlfi_tl(temp_7, 1, tmp1); -+ tcg_gen_subi_tl(tmp2, temp_7, 1); -+ gen_set_label(done_2); -+ tcg_gen_and_tl(a, b, tmp2); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BMSKNL -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp1 = ((@c & 63) + 1); -+ if((tmp1 == 64)) -+ { -+ tmp2 = 0xffffffffffffffff; -+ } -+ else -+ { -+ tmp2 = ((1 << tmp1) - 1); -+ }; -+ @a = (@b & ~tmp2); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BMSKNL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_6, c, 63); -+ tcg_gen_addi_tl(tmp1, temp_6, 1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, tmp1, 64); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_movi_tl(tmp2, 0xffffffffffffffff); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_shlfi_tl(temp_7, 1, tmp1); -+ tcg_gen_subi_tl(tmp2, temp_7, 1); -+ gen_set_label(done_2); -+ tcg_gen_not_tl(temp_8, tmp2); -+ tcg_gen_and_tl(a, b, temp_8); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BSETL -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = (1 << (@c & 63)); -+ @a = (@b | tmp); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BSETL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_4, c, 63); -+ tcg_gen_shlfi_tl(tmp, 1, temp_4); -+ tcg_gen_or_tl(a, b, tmp); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BXORL -+ * Variables: @c, @a, @b -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = (1 << @c); -+ @a = (@b ^ tmp); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@a); -+ setNFlag (@a); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_BXORL (DisasCtxt *ctx, TCGv c, TCGv a, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_shlfi_tl(tmp, 1, c); -+ tcg_gen_xor_tl(a, b, tmp); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(a); -+ setNFlag(a); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(tmp); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ROLL -+ * Variables: @src, @dest -+ * Functions: getCCFlag, rotateLeft, getFFlag, setZFlag, setNFlag, setCFlag, extractBits -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ lsrc = @src; -+ @dest = rotateLeft (lsrc, 1); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ setCFlag (extractBits (lsrc, 63, 63)); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_ROLL (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(lsrc, src); -+ tcg_gen_movi_tl(temp_5, 1); -+ rotateLeft(temp_4, lsrc, temp_5); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_movi_tl(temp_9, 63); -+ tcg_gen_movi_tl(temp_8, 63); -+ extractBits(temp_7, lsrc, temp_8, temp_9); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setCFlag(temp_6); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SEXBL -+ * Variables: @dest, @src -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @dest = arithmeticShiftRight ((@src << 24), 24); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SEXBL (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_6, 56); -+ tcg_gen_shli_tl(temp_5, src, 56); -+ arithmeticShiftRight(temp_4, temp_5, temp_6); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SEXHL -+ * Variables: @dest, @src -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @dest = arithmeticShiftRight ((@src << 16), 16); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SEXHL (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_6, 48); -+ tcg_gen_shli_tl(temp_5, src, 48); -+ arithmeticShiftRight(temp_4, temp_5, temp_6); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* SEXWL -+ * Variables: @dest, @src -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ @dest = arithmeticShiftRight ((@src << 32), 32); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SEXWL (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_6, 32); -+ tcg_gen_shli_tl(temp_5, src, 32); -+ arithmeticShiftRight(temp_4, temp_5, temp_6); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BTSTL -+ * Variables: @c, @b -+ * Functions: getCCFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = (1 << (@c & 63)); -+ alu = (@b & tmp); -+ setZFlag (alu); -+ setNFlag (alu); -+ }; -+} -+ */ -+ -+int -+arc_gen_BTSTL (DisasCtxt *ctx, TCGv c, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_andi_tl(temp_4, c, 63); -+ tcg_gen_shlfi_tl(tmp, 1, temp_4); -+ tcg_gen_and_tl(alu, b, tmp); -+ setZFlag(alu); -+ setNFlag(alu); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ tcg_temp_free(alu); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* TSTL -+ * Variables: @b, @c -+ * Functions: getCCFlag, setZFlag, setNFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ alu = (@b & @c); -+ setZFlag (alu); -+ setNFlag (alu); -+ }; -+} -+ */ -+ -+int -+arc_gen_TSTL (DisasCtxt *ctx, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_and_tl(alu, b, c); -+ setZFlag(alu); -+ setNFlag(alu); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(alu); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* XBFUL -+ * Variables: @src2, @src1, @dest -+ * Functions: getCCFlag, extractBits, getFFlag, setZFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ N = extractBits (@src2, 5, 0); -+ M = (extractBits (@src2, 11, 6) + 1); -+ tmp1 = (@src1 >> N); -+ tmp2 = ((1 << M) - 1); -+ @dest = (tmp1 & tmp2); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_XBFUL (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv N = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv M = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_6, 0); -+ tcg_gen_movi_tl(temp_5, 5); -+ extractBits(temp_4, src2, temp_5, temp_6); -+ tcg_gen_mov_tl(N, temp_4); -+ tcg_gen_movi_tl(temp_10, 6); -+ tcg_gen_movi_tl(temp_9, 11); -+ extractBits(temp_8, src2, temp_9, temp_10); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_addi_tl(M, temp_7, 1); -+ tcg_gen_shr_tl(tmp1, src1, N); -+ tcg_gen_shlfi_tl(temp_11, 1, M); -+ tcg_gen_subi_tl(tmp2, temp_11, 1); -+ tcg_gen_and_tl(dest, tmp1, tmp2); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(N); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(M); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(tmp2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* AEXL -+ * Variables: @src2, @b -+ * Functions: getCCFlag, readAuxReg, writeAuxReg -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ tmp = readAuxReg (@src2); -+ writeAuxReg (@src2, @b); -+ @b = tmp; -+ }; -+} -+ */ -+ -+int -+arc_gen_AEXL (DisasCtxt *ctx, TCGv src2, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ readAuxReg(temp_4, src2); -+ tcg_gen_mov_tl(tmp, temp_4); -+ writeAuxReg(src2, b); -+ tcg_gen_mov_tl(b, tmp); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LRL -+ * Variables: @dest, @src -+ * Functions: readAuxReg -+--- code --- -+{ -+ @dest = readAuxReg (@src); -+} -+ */ -+ -+int -+arc_gen_LRL (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ -+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) -+ gen_io_start(); -+ -+ TCGv temp_1 = tcg_temp_local_new(); -+ readAuxReg(temp_1, src); -+ tcg_gen_mov_tl(dest, temp_1); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* DIVL -+ * Variables: @src2, @src1, @dest -+ * Functions: getCCFlag, divSigned, getFFlag, setZFlag, setNFlag, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ if(((@src2 != 0) && ((@src1 != 2147483648) || (@src2 != 4294967295)))) -+ { -+ @dest = divSigned (@src1, @src2); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ setVFlag (0); -+ }; -+ } -+ else -+ { -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_DIVL (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_9); -+ tcg_gen_mov_tl(cc_flag, temp_9); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_4, src1, 2147483648); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_5, src2, 4294967295); -+ tcg_gen_or_tl(temp_6, temp_4, temp_5); -+ tcg_gen_and_tl(temp_7, temp_3, temp_6); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); tcg_gen_andi_tl(temp_8, temp_8, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, else_2);; -+ divSigned(temp_10, src1, src2); -+ tcg_gen_mov_tl(dest, temp_10); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_movi_tl(temp_11, 0); -+ setVFlag(temp_11); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* DIVUL -+ * Variables: @src2, @dest, @src1 -+ * Functions: getCCFlag, divUnsigned, getFFlag, setZFlag, setNFlag, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ if((@src2 != 0)) -+ { -+ @dest = divUnsigned (@src1, @src2); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (0); -+ setVFlag (0); -+ }; -+ } -+ else -+ { -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_DIVUL (DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ divUnsigned(temp_6, src1, src2); -+ tcg_gen_mov_tl(dest, temp_6); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ tcg_gen_movi_tl(temp_7, 0); -+ setNFlag(temp_7); -+ tcg_gen_movi_tl(temp_8, 0); -+ setVFlag(temp_8); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* REML -+ * Variables: @src2, @src1, @dest -+ * Functions: getCCFlag, divRemainingSigned, getFFlag, setZFlag, setNFlag, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ if(((@src2 != 0) && ((@src1 != 2147483648) || (@src2 != 4294967295)))) -+ { -+ @dest = divRemainingSigned (@src1, @src2); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ setVFlag (0); -+ }; -+ } -+ else -+ { -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_REML (DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_9); -+ tcg_gen_mov_tl(cc_flag, temp_9); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_4, src1, 2147483648); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_5, src2, 4294967295); -+ tcg_gen_or_tl(temp_6, temp_4, temp_5); -+ tcg_gen_and_tl(temp_7, temp_3, temp_6); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); tcg_gen_andi_tl(temp_8, temp_8, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, else_2);; -+ divRemainingSigned(temp_10, src1, src2); -+ tcg_gen_mov_tl(dest, temp_10); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_movi_tl(temp_11, 0); -+ setVFlag(temp_11); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* REMUL -+ * Variables: @src2, @dest, @src1 -+ * Functions: getCCFlag, divRemainingUnsigned, getFFlag, setZFlag, setNFlag, setVFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ if((@src2 != 0)) -+ { -+ @dest = divRemainingUnsigned (@src1, @src2); -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (0); -+ setVFlag (0); -+ }; -+ } -+ else -+ { -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_REMUL (DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ divRemainingUnsigned(temp_6, src1, src2); -+ tcg_gen_mov_tl(dest, temp_6); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ tcg_gen_movi_tl(temp_7, 0); -+ setNFlag(temp_7); -+ tcg_gen_movi_tl(temp_8, 0); -+ setVFlag(temp_8); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* ABSL -+ * Variables: @src, @dest -+ * Functions: Carry, getFFlag, setZFlag, setNFlag, setCFlag, Zero, setVFlag, getNFlag -+--- code --- -+{ -+ lsrc = @src; -+ alu = (0 - lsrc); -+ if((Carry (lsrc) == 1)) -+ { -+ @dest = alu; -+ } -+ else -+ { -+ @dest = lsrc; -+ }; -+ if((getFFlag () == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ setCFlag (Zero ()); -+ setVFlag (getNFlag ()); -+ }; -+} -+ */ -+ -+int -+arc_gen_ABSL (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(lsrc, src); -+ tcg_gen_subfi_tl(alu, 0, lsrc); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ Carry(temp_3, lsrc); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, temp_3, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(dest, alu); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_mov_tl(dest, lsrc); -+ gen_set_label(done_1); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_mov_tl(temp_4, Zero()); -+ setCFlag(temp_4); -+ tcg_gen_mov_tl(temp_5, getNFlag()); -+ setVFlag(temp_5); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(lsrc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SWAPL -+ * Variables: @src, @dest -+ * Functions: getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ tmp1 = (@src << 16); -+ tmp2 = ((@src >> 16) & 65535); -+ @dest = (tmp1 | tmp2); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ }; -+} -+ */ -+ -+int -+arc_gen_SWAPL (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ int f_flag; -+ tcg_gen_shli_tl(tmp1, src, 16); -+ tcg_gen_shri_tl(temp_1, src, 16); -+ tcg_gen_andi_tl(tmp2, temp_1, 65535); -+ tcg_gen_or_tl(dest, tmp1, tmp2); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(tmp2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SWAPEL -+ * Variables: @src, @dest -+ * Functions: getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ tmp1 = ((@src << 24) & 4278190080); -+ tmp2 = ((@src << 8) & 16711680); -+ tmp3 = ((@src >> 8) & 65280); -+ tmp4 = ((@src >> 24) & 255); -+ @dest = (((tmp1 | tmp2) | tmp3) | tmp4); -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ }; -+} -+ */ -+ -+int -+arc_gen_SWAPEL (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv tmp3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ int f_flag; -+ tcg_gen_shli_tl(temp_1, src, 24); -+ tcg_gen_andi_tl(tmp1, temp_1, 4278190080); -+ tcg_gen_shli_tl(temp_2, src, 8); -+ tcg_gen_andi_tl(tmp2, temp_2, 16711680); -+ tcg_gen_shri_tl(temp_3, src, 8); -+ tcg_gen_andi_tl(tmp3, temp_3, 65280); -+ tcg_gen_shri_tl(temp_4, src, 24); -+ tcg_gen_andi_tl(tmp4, temp_4, 255); -+ tcg_gen_or_tl(temp_6, tmp1, tmp2); -+ tcg_gen_or_tl(temp_5, temp_6, tmp3); -+ tcg_gen_or_tl(dest, temp_5, tmp4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(temp_1); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(tmp3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* NOTL -+ * Variables: @dest, @src -+ * Functions: getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ @dest = ~@src; -+ f_flag = getFFlag (); -+ if((f_flag == true)) -+ { -+ setZFlag (@dest); -+ setNFlag (@dest); -+ }; -+} -+ */ -+ -+int -+arc_gen_NOTL (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ int f_flag; -+ tcg_gen_not_tl(dest, src); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) -+ { -+ setZFlag(dest); -+ setNFlag(dest); -+; -+ } -+ else -+ { -+ ; -+ } -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETEQL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = @b; -+ p_c = @c; -+ if((p_b == p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETEQL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BREQL -+ * Variables: @b, @c, @offset -+ * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = @b; -+ p_c = @c; -+ take_branch = false; -+ if((p_b == p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((p_b == p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BREQL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(bta, temp_5, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETNEL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = @b; -+ p_c = @c; -+ if((p_b != p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETNEL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRNEL -+ * Variables: @b, @c, @offset -+ * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = @b; -+ p_c = @c; -+ take_branch = false; -+ if((p_b != p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((p_b != p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRNEL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(bta, temp_5, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETLTL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = @b; -+ p_c = @c; -+ if((p_b < p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETLTL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRLTL -+ * Variables: @b, @c, @offset -+ * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = @b; -+ p_c = @c; -+ take_branch = false; -+ if((p_b < p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((p_b < p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRLTL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(bta, temp_5, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETGEL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = @b; -+ p_c = @c; -+ if((p_b >= p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETGEL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv v = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(v); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(p_b); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRGEL -+ * Variables: @b, @c, @offset -+ * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = @b; -+ p_c = @c; -+ take_branch = false; -+ if((p_b >= p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if((p_b >= p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRGEL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(bta, temp_5, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETLEL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = @b; -+ p_c = @c; -+ if((p_b <= p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETLEL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv v = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(v); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(p_b); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETGTL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+--- code --- -+{ -+ cc_flag = getCCFlag (); -+ if((cc_flag == true)) -+ { -+ p_b = @b; -+ p_c = @c; -+ if((p_b > p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETGTL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv v = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GT, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(v); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(p_b); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRLOL -+ * Variables: @b, @c, @offset -+ * Functions: unsignedLT, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = @b; -+ p_c = @c; -+ take_branch = false; -+ if(unsignedLT (p_b, p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if(unsignedLT (p_b, p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRLOL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedLT(temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_3, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_5); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ tcg_gen_add_tl(bta, temp_4, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedLT(temp_6, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_6, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETLOL -+ * Variables: @b, @c, @a -+ * Functions: unsignedLT -+--- code --- -+{ -+ p_b = @b; -+ p_c = @c; -+ if(unsignedLT (p_b, p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETLOL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedLT(temp_2, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_2, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_1); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* BRHSL -+ * Variables: @b, @c, @offset -+ * Functions: unsignedGE, getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+--- code --- -+{ -+ p_b = @b; -+ p_c = @c; -+ take_branch = false; -+ if(unsignedGE (p_b, p_c)) -+ { -+ take_branch = true; -+ } -+ else -+ { -+ }; -+ bta = (getPCL () + @offset); -+ if((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot (bta, take_branch); -+ }; -+ if(unsignedGE (p_b, p_c)) -+ { -+ setPC (bta); -+ } -+ else -+ { -+ }; -+} -+ */ -+ -+int -+arc_gen_BRHSL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedGE(temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_3, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1);; -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_5); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ tcg_gen_add_tl(bta, temp_4, offset); -+ if ((shouldExecuteDelaySlot () == 1)) -+ { -+ executeDelaySlot(bta, take_branch); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedGE(temp_6, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_6, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2);; -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SETHSL -+ * Variables: @b, @c, @a -+ * Functions: unsignedGE -+--- code --- -+{ -+ p_b = @b; -+ p_c = @c; -+ if(unsignedGE (p_b, p_c)) -+ { -+ @a = true; -+ } -+ else -+ { -+ @a = false; -+ }; -+} -+ */ -+ -+int -+arc_gen_SETHSL (DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedGE(temp_2, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_2, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1);; -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_1); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* EXL -+ * Variables: @b, @c -+ * Functions: getMemory, setMemory -+--- code --- -+{ -+ temp = @b; -+ @b = getMemory (@c, LONG); -+ setMemory (@c, LONG, temp); -+} -+ */ -+ -+int -+arc_gen_EXL (DisasCtxt *ctx, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(temp, b); -+ getMemory(temp_1, c, LONG); -+ tcg_gen_mov_tl(b, temp_1); -+ setMemory(c, LONG, temp); -+ tcg_temp_free(temp); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LLOCKL -+ * Variables: @dest, @src -+ * Functions: getMemory, setLF -+--- code --- -+{ -+ @dest = getMemory (@src, LONG); -+ setLF (1); -+} -+ */ -+ -+int -+arc_gen_LLOCKL (DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ getMemory(temp_1, src, LONGLONG); -+ tcg_gen_mov_tl(dest, temp_1); -+ tcg_gen_movi_tl(temp_2, 1); -+ setLF(temp_2); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* SCONDL -+ * Variables: @src, @dest -+ * Functions: getLF, setMemory, setZFlag, setLF -+--- code --- -+{ -+ lf = getLF (); -+ if((lf == 1)) -+ { -+ setMemory (@src, LONG, @dest); -+ }; -+ setZFlag (!lf); -+ setLF (0); -+} -+ */ -+ -+int -+arc_gen_SCONDL (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv lf = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getLF(temp_3); -+ tcg_gen_mov_tl(lf, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, lf, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);; -+ setMemory(src, LONGLONG, dest); -+ gen_set_label(done_1); -+ tcg_gen_xori_tl(temp_4, lf, 1); tcg_gen_andi_tl(temp_4, temp_4, 1);; -+ setZFlag(temp_4); -+ tcg_gen_movi_tl(temp_5, 0); -+ setLF(temp_5); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(lf); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* LDL -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setDebugLD, getMemory, getFlagX, SignExtend, NoFurtherLoadsPending -+--- code --- -+{ -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ address = 0; -+ if(((AA == 0) || (AA == 1))) -+ { -+ address = (@src1 + @src2); -+ }; -+ if((AA == 2)) -+ { -+ address = @src1; -+ }; -+ if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ address = (@src1 + (@src2 << 2)); -+ }; -+ if(((AA == 3) && (ZZ == 2))) -+ { -+ address = (@src1 + (@src2 << 1)); -+ }; -+ l_src1 = @src1; -+ l_src2 = @src2; -+ setDebugLD (1); -+ new_dest = getMemory (address, ZZ); -+ if(((AA == 1) || (AA == 2))) -+ { -+ @src1 = (l_src1 + l_src2); -+ }; -+ if((getFlagX () == 1)) -+ { -+ new_dest = SignExtend (new_dest, ZZ); -+ }; -+ if(NoFurtherLoadsPending ()) -+ { -+ setDebugLD (0); -+ }; -+ @dest = new_dest; -+} -+ */ -+ -+int -+arc_gen_LDL (DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv l_src1 = tcg_temp_local_new(); -+ TCGv l_src2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv new_dest = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) -+ { -+ tcg_gen_add_tl(address, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if ((AA == 2)) -+ { -+ tcg_gen_mov_tl(address, src1); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ tcg_gen_shli_tl(temp_2, src2, 3); -+ tcg_gen_add_tl(address, src1, temp_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && (ZZ == 2))) -+ { -+ tcg_gen_shli_tl(temp_3, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_3); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_gen_mov_tl(l_src1, src1); -+ tcg_gen_mov_tl(l_src2, src2); -+ tcg_gen_movi_tl(temp_4, 1); -+ setDebugLD(temp_4); -+ getMemory(temp_5, address, ZZ); -+ tcg_gen_mov_tl(new_dest, temp_5); -+ if (((AA == 1) || (AA == 2))) -+ { -+ tcg_gen_add_tl(src1, l_src1, l_src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if ((getFlagX () == 1)) -+ { -+ new_dest = SignExtend (new_dest, ZZ); -+; -+ } -+ else -+ { -+ ; -+ } -+ TCGLabel *done_1 = gen_new_label(); -+ NoFurtherLoadsPending(temp_6); -+ tcg_gen_xori_tl(temp_1, temp_6, 1); tcg_gen_andi_tl(temp_1, temp_1, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, done_1);; -+ tcg_gen_movi_tl(temp_7, 0); -+ setDebugLD(temp_7); -+ gen_set_label(done_1); -+ tcg_gen_mov_tl(dest, new_dest); -+ tcg_temp_free(address); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(l_src1); -+ tcg_temp_free(l_src2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(new_dest); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* STL -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setMemory -+--- code --- -+{ -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ address = 0; -+ if(((AA == 0) || (AA == 1))) -+ { -+ address = (@src1 + @src2); -+ }; -+ if((AA == 2)) -+ { -+ address = @src1; -+ }; -+ if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ address = (@src1 + (@src2 << 2)); -+ }; -+ if(((AA == 3) && (ZZ == 2))) -+ { -+ address = (@src1 + (@src2 << 1)); -+ }; -+ setMemory (address, ZZ, @dest); -+ if(((AA == 1) || (AA == 2))) -+ { -+ @src1 = (@src1 + @src2); -+ }; -+} -+ */ -+ -+int -+arc_gen_STL (DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) -+ { -+ tcg_gen_add_tl(address, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if ((AA == 2)) -+ { -+ tcg_gen_mov_tl(address, src1); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ tcg_gen_shli_tl(temp_1, src2, 3); -+ tcg_gen_add_tl(address, src1, temp_1); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && (ZZ == 2))) -+ { -+ tcg_gen_shli_tl(temp_2, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_2); -+; -+ } -+ else -+ { -+ ; -+ } -+ setMemory(address, ZZ, dest); -+ if (((AA == 1) || (AA == 2))) -+ { -+ tcg_gen_add_tl(src1, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(address); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+/* STDL -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setMemory, instructionHasRegisterOperandIn, nextReg, getBit -+--- code --- -+{ -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ address = 0; -+ if(((AA == 0) || (AA == 1))) -+ { -+ address = (@src1 + @src2); -+ }; -+ if((AA == 2)) -+ { -+ address = @src1; -+ }; -+ if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ address = (@src1 + (@src2 << 2)); -+ }; -+ if(((AA == 3) && (ZZ == 2))) -+ { -+ address = (@src1 + (@src2 << 1)); -+ }; -+ setMemory (address, LONG, @dest); -+ if(instructionHasRegisterOperandIn (0)) -+ { -+ pair = nextReg (dest); -+ } -+ else -+ { -+ if((getBit (@dest, 31) == 1)) -+ { -+ pair = 4294967295; -+ } -+ else -+ { -+ pair = 0; -+ }; -+ }; -+ setMemory ((address + 4), LONG, pair); -+ if(((AA == 1) || (AA == 2))) -+ { -+ @src1 = (@src1 + @src2); -+ }; -+} -+ */ -+ -+int -+arc_gen_STDL (DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv pair = NULL; -+ bool pair_initialized = FALSE; -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) -+ { -+ tcg_gen_add_tl(address, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ if ((AA == 2)) -+ { -+ tcg_gen_mov_tl(address, src1); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ { -+ tcg_gen_shli_tl(temp_3, src2, 2); -+ tcg_gen_add_tl(address, src1, temp_3); -+; -+ } -+ else -+ { -+ ; -+ } -+ if (((AA == 3) && (ZZ == 2))) -+ { -+ tcg_gen_shli_tl(temp_4, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_4); -+; -+ } -+ else -+ { -+ ; -+ } -+ setMemory(address, LONG, dest); -+ if (instructionHasRegisterOperandIn (0)) -+ { -+ pair = nextReg (dest); -+; -+ } -+ else -+ { -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_movi_tl(temp_6, 31); -+ getBit(temp_5, dest, temp_6); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, temp_5, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); tcg_gen_andi_tl(temp_2, temp_2, 1);; -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1);; -+ pair = tcg_temp_local_new(); -+ pair_initialized = TRUE; -+ tcg_gen_movi_tl(pair, 4294967295); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_movi_tl(pair, 0); -+ gen_set_label(done_1); -+; -+ } -+ tcg_gen_addi_tl(temp_7, address, 4); -+ setMemory(temp_7, LONG, pair); -+ if (((AA == 1) || (AA == 2))) -+ { -+ tcg_gen_add_tl(src1, src1, src2); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(address); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ if (pair_initialized) { -+ tcg_temp_free(pair); -+ } -+ -+ return ret; -+} -+ -+ -+ -+ -+/* POPL -+ * Variables: @dest -+ * Functions: getMemory, getRegister, setRegister -+--- code --- -+{ -+ new_dest = getMemory (getRegister (R_SP), LONG); -+ setRegister (R_SP, (getRegister (R_SP) + 4)); -+ @dest = new_dest; -+} -+ */ -+ -+int -+arc_gen_POPL (DisasCtxt *ctx, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv new_dest = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getRegister(temp_3, R_SP); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ getMemory(temp_1, temp_2, LONGLONG); -+ tcg_gen_mov_tl(new_dest, temp_1); -+ getRegister(temp_6, R_SP); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_addi_tl(temp_4, temp_5, 8); -+ setRegister(R_SP, temp_4); -+ tcg_gen_mov_tl(dest, new_dest); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(new_dest); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* PUSHL -+ * Variables: @src -+ * Functions: setMemory, getRegister, setRegister -+--- code --- -+{ -+ local_src = @src; -+ setMemory ((getRegister (R_SP) - 8), LONG, local_src); -+ setRegister (R_SP, (getRegister (R_SP) - 8)); -+} -+ */ -+ -+int -+arc_gen_PUSHL (DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv local_src = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(local_src, src); -+ getRegister(temp_3, R_SP); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ tcg_gen_subi_tl(temp_1, temp_2, 8); -+ setMemory(temp_1, LONGLONG, local_src); -+ getRegister(temp_6, R_SP); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_subi_tl(temp_4, temp_5, 8); -+ setRegister(R_SP, temp_4); -+ tcg_temp_free(local_src); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* NORML -+ * Variables: @src, @dest -+ * Functions: HELPER, getFFlag, setZFlag, setNFlag -+--- code --- -+{ -+ psrc = @src; -+ i = HELPER (norml, psrc); -+ @dest = (63 - i); -+ if((getFFlag () == true)) -+ { -+ setZFlag (psrc); -+ setNFlag (psrc); -+ }; -+} -+ */ -+ -+int -+arc_gen_NORML (DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ TCGv i = tcg_temp_local_new(); -+ tcg_gen_mov_tl(psrc, src); -+ ARC_HELPER(norml, i, psrc); -+ tcg_gen_subfi_tl(dest, 63, i); -+ if ((getFFlag () == true)) -+ { -+ setZFlag(psrc); -+ setNFlag(psrc); -+; -+ } -+ else -+ { -+ ; -+ } -+ tcg_temp_free(psrc); -+ tcg_temp_free(i); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* -+ * FLSL -+ * Variables: @src, @dest -+ * Functions: CLZ, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = @src; -+ * if((psrc == 0)) -+ * { -+ * @dest = 0; -+ * } -+ * else -+ * { -+ * @dest = 63 - CLZ (psrc, 64); -+ * }; -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_FLSL(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(psrc, src); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, psrc, 0); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_movi_tl(dest, 0); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_movi_tl(temp_5, 64); -+ tcg_gen_clz_tl(temp_4, psrc, temp_5); -+ tcg_gen_mov_tl(temp_3, temp_4); -+ tcg_gen_subfi_tl(dest, 63, temp_3); -+ gen_set_label(done_1); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* -+ * FFSL -+ * Variables: @src, @dest -+ * Functions: CTZ, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = @src; -+ * if((psrc == 0)) -+ * { -+ * @dest = 63; -+ * } -+ * else -+ * { -+ * @dest = CTZ (psrc, 64); -+ * }; -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_FFSL(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(psrc, src); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, psrc, 0); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_movi_tl(dest, 31); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_movi_tl(temp_4, 32); -+ tcg_gen_ctz_tl(temp_3, psrc, temp_4); -+ tcg_gen_mov_tl(dest, temp_3); -+ gen_set_label(done_1); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ -+ return ret; -+} -+ -+ -+ -+ -+ -+/* DBNZL -+ * Variables: @a, @offset -+ * Functions: getPCL, setPC -+--- code --- -+{ -+ bta = getPCL() + @offset; -+ if (shouldExecuteDelaySlot() == 1) -+ { -+ take_branch = true; -+ if (@a == 1) -+ { -+ take_branch = false; -+ }; -+ executeDelaySlot (bta, take_branch); -+ }; -+ @a = @a - 1 -+ if(@a != 0) { -+ setPC(getPCL () + @offset) -+ } -+} -+ */ -+ -+int -+arc_gen_DBNZL (DisasCtxt *ctx, TCGv a, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGLabel *do_not_branch = gen_new_label(); -+ TCGLabel *keep_take_branch_1 = gen_new_label(); -+ TCGv bta = tcg_temp_local_new(); -+ -+ getPCL(bta); -+ tcg_gen_add_tl(bta, bta, offset); -+ -+ if (shouldExecuteDelaySlot() == 1) { -+ TCGv take_branch = tcg_const_local_tl(1); -+ tcg_gen_brcondi_tl(TCG_COND_NE, a, 1, keep_take_branch_1); -+ tcg_temp_free(take_branch); -+ tcg_gen_mov_tl(take_branch, tcg_const_local_tl(0)); -+ gen_set_label(keep_take_branch_1); -+ executeDelaySlot(bta, take_branch); -+ tcg_temp_free(take_branch); -+ } -+ -+ tcg_gen_subi_tl(a, a, 1); -+ tcg_gen_brcondi_tl(TCG_COND_EQ, a, 0, do_not_branch); -+ setPC(bta); -+ gen_set_label(do_not_branch); -+ tcg_temp_free(bta); -+ -+ return ret; -+} -diff --git a/target/arc/semfunc-v3.h b/target/arc/semfunc-v3.h -new file mode 100644 -index 0000000000..9403d8f1dc ---- /dev/null -+++ b/target/arc/semfunc-v3.h -@@ -0,0 +1,55 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2017 Cupertino Miranda -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR dest PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef __ARC_SEMFUNC_H__ -+#define __ARC_SEMFUNC_H__ -+ -+#include "translate.h" -+#include "semfunc-helper.h" -+ -+/* TODO (issue #62): these must be removed */ -+#define arc_false (ctx->zero) -+#define arc_true (ctx->one) -+ -+#define LONG 0 -+#define BYTE 1 -+#define WORD 2 -+#define LONGLONG 3 -+ -+#define SEMANTIC_FUNCTION_PROTOTYPE_0(NAME) \ -+ int arc_gen_##NAME (DisasCtxt *); -+#define SEMANTIC_FUNCTION_PROTOTYPE_1(NAME) \ -+ int arc_gen_##NAME (DisasCtxt *, TCGv); -+#define SEMANTIC_FUNCTION_PROTOTYPE_2(NAME) \ -+ int arc_gen_##NAME (DisasCtxt *, TCGv, TCGv); -+#define SEMANTIC_FUNCTION_PROTOTYPE_3(NAME) \ -+ int arc_gen_##NAME (DisasCtxt *, TCGv, TCGv, TCGv); -+#define SEMANTIC_FUNCTION_PROTOTYPE_4(NAME) \ -+ int arc_gen_##NAME (DisasCtxt *, TCGv, TCGv, TCGv, TCGv); -+ -+#define MAPPING(MNEMONIC, NAME, NOPS, ...) -+#define CONSTANT(...) -+#define SEMANTIC_FUNCTION(NAME, NOPS) \ -+ SEMANTIC_FUNCTION_PROTOTYPE_##NOPS(NAME) -+ -+#include "semfunc_mapping.def" -+#include "extra_mapping.def" -+ -+#endif /* __ARC_SEMFUNC_H__ */ -diff --git a/target/arc/semfunc-v3_mapping.def b/target/arc/semfunc-v3_mapping.def -new file mode 100644 -index 0000000000..2ecb55128a ---- /dev/null -+++ b/target/arc/semfunc-v3_mapping.def -@@ -0,0 +1,468 @@ -+SEMANTIC_FUNCTION(FLAG, 1) -+SEMANTIC_FUNCTION(KFLAG, 1) -+SEMANTIC_FUNCTION(ADD, 3) -+SEMANTIC_FUNCTION(ADD1, 3) -+SEMANTIC_FUNCTION(ADD2, 3) -+SEMANTIC_FUNCTION(ADD3, 3) -+SEMANTIC_FUNCTION(ADC, 3) -+SEMANTIC_FUNCTION(SBC, 3) -+SEMANTIC_FUNCTION(NEG, 2) -+SEMANTIC_FUNCTION(SUB, 3) -+SEMANTIC_FUNCTION(SUB1, 3) -+SEMANTIC_FUNCTION(SUB2, 3) -+SEMANTIC_FUNCTION(SUB3, 3) -+SEMANTIC_FUNCTION(MAX, 3) -+SEMANTIC_FUNCTION(MIN, 3) -+SEMANTIC_FUNCTION(CMP, 2) -+SEMANTIC_FUNCTION(AND, 3) -+SEMANTIC_FUNCTION(OR, 3) -+SEMANTIC_FUNCTION(XOR, 3) -+SEMANTIC_FUNCTION(MOV, 2) -+SEMANTIC_FUNCTION(ASL, 3) -+SEMANTIC_FUNCTION(ASR, 3) -+SEMANTIC_FUNCTION(ASR8, 2) -+SEMANTIC_FUNCTION(ASR16, 2) -+SEMANTIC_FUNCTION(LSL16, 2) -+SEMANTIC_FUNCTION(LSL8, 2) -+SEMANTIC_FUNCTION(LSR, 3) -+SEMANTIC_FUNCTION(LSR16, 2) -+SEMANTIC_FUNCTION(LSR8, 2) -+SEMANTIC_FUNCTION(BIC, 3) -+SEMANTIC_FUNCTION(BCLR, 3) -+SEMANTIC_FUNCTION(BMSK, 3) -+SEMANTIC_FUNCTION(BMSKN, 3) -+SEMANTIC_FUNCTION(BSET, 3) -+SEMANTIC_FUNCTION(BXOR, 3) -+SEMANTIC_FUNCTION(ROL, 3) -+SEMANTIC_FUNCTION(ROL8, 2) -+SEMANTIC_FUNCTION(ROR, 3) -+SEMANTIC_FUNCTION(ROR8, 2) -+SEMANTIC_FUNCTION(RLC, 2) -+SEMANTIC_FUNCTION(RRC, 2) -+SEMANTIC_FUNCTION(SEXB, 2) -+SEMANTIC_FUNCTION(SEXH, 2) -+SEMANTIC_FUNCTION(EXTB, 2) -+SEMANTIC_FUNCTION(EXTH, 2) -+SEMANTIC_FUNCTION(BTST, 2) -+SEMANTIC_FUNCTION(TST, 2) -+SEMANTIC_FUNCTION(XBFU, 3) -+SEMANTIC_FUNCTION(AEX, 2) -+SEMANTIC_FUNCTION(LR, 2) -+SEMANTIC_FUNCTION(CLRI, 1) -+SEMANTIC_FUNCTION(SETI, 1) -+SEMANTIC_FUNCTION(NOP, 0) -+SEMANTIC_FUNCTION(PREALLOC, 0) -+SEMANTIC_FUNCTION(PREFETCH, 2) -+SEMANTIC_FUNCTION(MPY, 3) -+SEMANTIC_FUNCTION(MPYMU, 3) -+SEMANTIC_FUNCTION(MPYM, 3) -+SEMANTIC_FUNCTION(MPYU, 3) -+SEMANTIC_FUNCTION(MPYUW, 3) -+SEMANTIC_FUNCTION(MPYW, 3) -+SEMANTIC_FUNCTION(DIV, 3) -+SEMANTIC_FUNCTION(DIVU, 3) -+SEMANTIC_FUNCTION(REM, 3) -+SEMANTIC_FUNCTION(REMU, 3) -+SEMANTIC_FUNCTION(MAC, 3) -+SEMANTIC_FUNCTION(MACU, 3) -+SEMANTIC_FUNCTION(MACD, 3) -+SEMANTIC_FUNCTION(MACDU, 3) -+SEMANTIC_FUNCTION(ABS, 2) -+SEMANTIC_FUNCTION(SWAP, 2) -+SEMANTIC_FUNCTION(SWAPE, 2) -+SEMANTIC_FUNCTION(NOT, 2) -+SEMANTIC_FUNCTION(BI, 1) -+SEMANTIC_FUNCTION(BIH, 1) -+SEMANTIC_FUNCTION(B, 1) -+SEMANTIC_FUNCTION(B_S, 1) -+SEMANTIC_FUNCTION(BBIT0, 3) -+SEMANTIC_FUNCTION(BBIT1, 3) -+SEMANTIC_FUNCTION(BL, 1) -+SEMANTIC_FUNCTION(J, 1) -+SEMANTIC_FUNCTION(JL, 1) -+SEMANTIC_FUNCTION(SETEQ, 3) -+SEMANTIC_FUNCTION(BREQ, 3) -+SEMANTIC_FUNCTION(SETNE, 3) -+SEMANTIC_FUNCTION(BRNE, 3) -+SEMANTIC_FUNCTION(SETLT, 3) -+SEMANTIC_FUNCTION(BRLT, 3) -+SEMANTIC_FUNCTION(SETGE, 3) -+SEMANTIC_FUNCTION(BRGE, 3) -+SEMANTIC_FUNCTION(SETLE, 3) -+SEMANTIC_FUNCTION(SETGT, 3) -+SEMANTIC_FUNCTION(BRLO, 3) -+SEMANTIC_FUNCTION(SETLO, 3) -+SEMANTIC_FUNCTION(BRHS, 3) -+SEMANTIC_FUNCTION(SETHS, 3) -+SEMANTIC_FUNCTION(EX, 2) -+SEMANTIC_FUNCTION(LLOCK, 2) -+SEMANTIC_FUNCTION(LLOCKD, 2) -+SEMANTIC_FUNCTION(SCOND, 2) -+SEMANTIC_FUNCTION(SCONDD, 2) -+SEMANTIC_FUNCTION(DMB, 1) -+SEMANTIC_FUNCTION(LD, 3) -+SEMANTIC_FUNCTION(LDD, 3) -+SEMANTIC_FUNCTION(ST, 3) -+SEMANTIC_FUNCTION(STD, 3) -+SEMANTIC_FUNCTION(POP, 1) -+SEMANTIC_FUNCTION(PUSH, 1) -+SEMANTIC_FUNCTION(LP, 1) -+SEMANTIC_FUNCTION(NORM, 2) -+SEMANTIC_FUNCTION(NORMH, 2) -+SEMANTIC_FUNCTION(FLS, 2) -+SEMANTIC_FUNCTION(FFS, 2) -+ -+ -+MAPPING(flag, FLAG, 1, 0) -+MAPPING(kflag, KFLAG, 1, 0) -+MAPPING(add, ADD, 3, 1, 2, 0) -+MAPPING(add_s, ADD, 3, 1, 2, 0) -+MAPPING(add1, ADD1, 3, 1, 2, 0) -+MAPPING(add1_s, ADD1, 3, 1, 2, 0) -+MAPPING(add2, ADD2, 3, 1, 2, 0) -+MAPPING(add2_s, ADD2, 3, 1, 2, 0) -+MAPPING(add3, ADD3, 3, 1, 2, 0) -+MAPPING(add3_s, ADD3, 3, 1, 2, 0) -+MAPPING(adc, ADC, 3, 1, 2, 0) -+MAPPING(sbc, SBC, 3, 1, 2, 0) -+MAPPING(neg, NEG, 2, 1, 0) -+MAPPING(neg_s, NEG, 2, 1, 0) -+MAPPING(sub, SUB, 3, 1, 2, 0) -+MAPPING(sub_s, SUB, 3, 1, 2, 0) -+MAPPING(rsub, SUB, 3, 2, 1, 0) -+MAPPING(sub1, SUB1, 3, 1, 2, 0) -+MAPPING(sub2, SUB2, 3, 1, 2, 0) -+MAPPING(sub3, SUB3, 3, 1, 2, 0) -+MAPPING(max, MAX, 3, 1, 2, 0) -+MAPPING(min, MIN, 3, 1, 2, 0) -+MAPPING(cmp, CMP, 2, 0, 1) -+MAPPING(cmp_s, CMP, 2, 0, 1) -+MAPPING(rcmp, CMP, 2, 1, 0) -+MAPPING(and, AND, 3, 0, 1, 2) -+MAPPING(and_s, AND, 3, 0, 1, 2) -+MAPPING(or, OR, 3, 0, 1, 2) -+MAPPING(or_s, OR, 3, 0, 1, 2) -+MAPPING(xor, XOR, 3, 0, 1, 2) -+MAPPING(xor_s, XOR, 3, 0, 1, 2) -+MAPPING(mov, MOV, 2, 0, 1) -+MAPPING(mov_s, MOV, 2, 0, 1) -+CONSTANT(ASL, asl, 2, 268435457) /* For variable @c */ -+MAPPING(asl, ASL, 3, 1, 2, 0) -+CONSTANT(ASL, asl_s, 2, 268435457) /* For variable @c */ -+MAPPING(asl_s, ASL, 3, 1, 2, 0) -+CONSTANT(ASR, asr, 2, 1) /* For variable @c */ -+MAPPING(asr, ASR, 3, 1, 2, 0) -+CONSTANT(ASR, asr_s, 2, 1) /* For variable @c */ -+MAPPING(asr_s, ASR, 3, 1, 2, 0) -+MAPPING(asr8, ASR8, 2, 1, 0) -+MAPPING(asr16, ASR16, 2, 1, 0) -+MAPPING(lsl16, LSL16, 2, 1, 0) -+MAPPING(lsl8, LSL8, 2, 1, 0) -+CONSTANT(LSR, lsr, 2, 1) /* For variable @c */ -+MAPPING(lsr, LSR, 3, 1, 2, 0) -+CONSTANT(LSR, lsr_s, 2, 1) /* For variable @c */ -+MAPPING(lsr_s, LSR, 3, 1, 2, 0) -+MAPPING(lsr16, LSR16, 2, 1, 0) -+MAPPING(lsr8, LSR8, 2, 1, 0) -+MAPPING(bic, BIC, 3, 0, 1, 2) -+MAPPING(bic_s, BIC, 3, 0, 1, 2) -+MAPPING(bclr, BCLR, 3, 2, 0, 1) -+MAPPING(bclr_s, BCLR, 3, 2, 0, 1) -+MAPPING(bmsk, BMSK, 3, 2, 0, 1) -+MAPPING(bmsk_s, BMSK, 3, 2, 0, 1) -+MAPPING(bmskn, BMSKN, 3, 2, 0, 1) -+MAPPING(bset, BSET, 3, 2, 0, 1) -+MAPPING(bset_s, BSET, 3, 2, 0, 1) -+MAPPING(bxor, BXOR, 3, 2, 0, 1) -+CONSTANT(ROL, rol, 2, 1) /* For variable @n */ -+MAPPING(rol, ROL, 3, 1, 2, 0) -+MAPPING(rol8, ROL8, 2, 1, 0) -+CONSTANT(ROR, ror, 2, 1) /* For variable @n */ -+MAPPING(ror, ROR, 3, 1, 2, 0) -+MAPPING(ror8, ROR8, 2, 1, 0) -+MAPPING(rlc, RLC, 2, 1, 0) -+MAPPING(rrc, RRC, 2, 1, 0) -+MAPPING(sexb, SEXB, 2, 0, 1) -+MAPPING(sexb_s, SEXB, 2, 0, 1) -+MAPPING(sexh, SEXH, 2, 0, 1) -+MAPPING(sexh_s, SEXH, 2, 0, 1) -+MAPPING(extb, EXTB, 2, 0, 1) -+MAPPING(extb_s, EXTB, 2, 0, 1) -+MAPPING(exth, EXTH, 2, 0, 1) -+MAPPING(exth_s, EXTH, 2, 0, 1) -+MAPPING(btst, BTST, 2, 1, 0) -+MAPPING(btst_s, BTST, 2, 1, 0) -+MAPPING(tst, TST, 2, 0, 1) -+MAPPING(tst_s, TST, 2, 0, 1) -+MAPPING(xbfu, XBFU, 3, 2, 1, 0) -+MAPPING(aex, AEX, 2, 1, 0) -+MAPPING(lr, LR, 2, 0, 1) -+MAPPING(clri, CLRI, 1, 0) -+MAPPING(seti, SETI, 1, 0) -+MAPPING(nop, NOP, 0) -+MAPPING(nop_s, NOP, 0) -+MAPPING(prealloc, PREALLOC, 0) -+MAPPING(prefetch, PREFETCH, 2, 0, 1) -+MAPPING(prefetchw, PREFETCH, 2, 0, 1) -+MAPPING(mpy, MPY, 3, 1, 2, 0) -+MAPPING(mpy_s, MPY, 3, 1, 2, 0) -+MAPPING(mpymu, MPYMU, 3, 0, 1, 2) -+MAPPING(mpym, MPYM, 3, 0, 1, 2) -+MAPPING(mpyu, MPYU, 3, 1, 2, 0) -+MAPPING(mpyuw, MPYUW, 3, 0, 1, 2) -+MAPPING(mpyuw_s, MPYUW, 3, 0, 1, 2) -+MAPPING(mpyw, MPYW, 3, 0, 1, 2) -+MAPPING(mpyw_s, MPYW, 3, 0, 1, 2) -+MAPPING(div, DIV, 3, 2, 1, 0) -+MAPPING(divu, DIVU, 3, 2, 0, 1) -+MAPPING(rem, REM, 3, 2, 1, 0) -+MAPPING(remu, REMU, 3, 2, 0, 1) -+MAPPING(mac, MAC, 3, 1, 2, 0) -+MAPPING(macu, MACU, 3, 1, 2, 0) -+MAPPING(macd, MACD, 3, 1, 2, 0) -+MAPPING(macdu, MACDU, 3, 1, 2, 0) -+MAPPING(abs, ABS, 2, 1, 0) -+MAPPING(abs_s, ABS, 2, 1, 0) -+MAPPING(swap, SWAP, 2, 1, 0) -+MAPPING(swape, SWAPE, 2, 1, 0) -+MAPPING(not, NOT, 2, 0, 1) -+MAPPING(not_s, NOT, 2, 0, 1) -+MAPPING(bi, BI, 1, 0) -+MAPPING(bih, BIH, 1, 0) -+MAPPING(b, B, 1, 0) -+MAPPING(beq_s, B_S, 1, 0) -+MAPPING(bne_s, B_S, 1, 0) -+MAPPING(bgt_s, B_S, 1, 0) -+MAPPING(bge_s, B_S, 1, 0) -+MAPPING(blt_s, B_S, 1, 0) -+MAPPING(ble_s, B_S, 1, 0) -+MAPPING(bhi_s, B_S, 1, 0) -+MAPPING(bhs_s, B_S, 1, 0) -+MAPPING(blo_s, B_S, 1, 0) -+MAPPING(bls_s, B_S, 1, 0) -+MAPPING(b_s, B_S, 1, 0) -+MAPPING(bbit0, BBIT0, 3, 0, 1, 2) -+MAPPING(bbit1, BBIT1, 3, 0, 1, 2) -+MAPPING(bl, BL, 1, 0) -+MAPPING(bl_s, BL, 1, 0) -+MAPPING(j, J, 1, 0) -+MAPPING(j_s, J, 1, 0) -+MAPPING(jeq_s, J, 1, 0) -+MAPPING(jne_s, J, 1, 0) -+MAPPING(jl, JL, 1, 0) -+MAPPING(jl_s, JL, 1, 0) -+MAPPING(seteq, SETEQ, 3, 1, 2, 0) -+MAPPING(breq, BREQ, 3, 0, 1, 2) -+MAPPING(setne, SETNE, 3, 1, 2, 0) -+MAPPING(brne, BRNE, 3, 0, 1, 2) -+MAPPING(setlt, SETLT, 3, 1, 2, 0) -+MAPPING(brlt, BRLT, 3, 0, 1, 2) -+MAPPING(setge, SETGE, 3, 1, 2, 0) -+MAPPING(brge, BRGE, 3, 0, 1, 2) -+MAPPING(setle, SETLE, 3, 1, 2, 0) -+MAPPING(setgt, SETGT, 3, 1, 2, 0) -+MAPPING(brlo, BRLO, 3, 0, 1, 2) -+MAPPING(setlo, SETLO, 3, 1, 2, 0) -+MAPPING(brhs, BRHS, 3, 0, 1, 2) -+MAPPING(seths, SETHS, 3, 1, 2, 0) -+MAPPING(ex, EX, 2, 0, 1) -+MAPPING(llock, LLOCK, 2, 0, 1) -+MAPPING(scond, SCOND, 2, 1, 0) -+MAPPING(dmb, DMB, 1, 0) -+CONSTANT(LD, ld, 2, 0) /* For variable @src2 */ -+MAPPING(ld, LD, 3, 1, 2, 0) -+MAPPING(ld_s, LD, 3, 1, 2, 0) -+CONSTANT(LD, ldb, 2, 0) /* For variable @src2 */ -+MAPPING(ldb, LD, 3, 1, 2, 0) -+MAPPING(ldb_s, LD, 3, 1, 2, 0) -+CONSTANT(LD, ldh, 2, 0) /* For variable @src2 */ -+MAPPING(ldh, LD, 3, 1, 2, 0) -+MAPPING(ldh_s, LD, 3, 1, 2, 0) -+CONSTANT(ST, st, 2, 0) /* For variable @src2 */ -+MAPPING(st, ST, 3, 1, 2, 0) -+MAPPING(st_s, ST, 3, 1, 2, 0) -+MAPPING(stb_s, ST, 3, 1, 2, 0) -+MAPPING(sth_s, ST, 3, 1, 2, 0) -+MAPPING(norm, NORM, 2, 1, 0) -+MAPPING(normh, NORMH, 2, 1, 0) -+MAPPING(fls, FLS, 2, 1, 0) -+MAPPING(ffs, FFS, 2, 1, 0) -+ -+/* Long instruction */ -+ -+SEMANTIC_FUNCTION(ADDL, 3) -+SEMANTIC_FUNCTION(ADD1L, 3) -+SEMANTIC_FUNCTION(ADD2L, 3) -+SEMANTIC_FUNCTION(ADD3L, 3) -+SEMANTIC_FUNCTION(ADCL, 3) -+SEMANTIC_FUNCTION(SBCL, 3) -+SEMANTIC_FUNCTION(SUBL, 3) -+SEMANTIC_FUNCTION(SUB1L, 3) -+SEMANTIC_FUNCTION(SUB2L, 3) -+SEMANTIC_FUNCTION(SUB3L, 3) -+SEMANTIC_FUNCTION(MAXL, 3) -+SEMANTIC_FUNCTION(MINL, 3) -+SEMANTIC_FUNCTION(CMPL, 2) -+SEMANTIC_FUNCTION(ANDL, 3) -+SEMANTIC_FUNCTION(ORL, 3) -+SEMANTIC_FUNCTION(XORL, 3) -+SEMANTIC_FUNCTION(MOVL, 2) -+SEMANTIC_FUNCTION(MOVHL, 2) -+SEMANTIC_FUNCTION(ASLL, 3) -+SEMANTIC_FUNCTION(ASRL, 3) -+SEMANTIC_FUNCTION(LSRL, 3) -+SEMANTIC_FUNCTION(BICL, 3) -+SEMANTIC_FUNCTION(BCLRL, 3) -+SEMANTIC_FUNCTION(BMSKL, 3) -+SEMANTIC_FUNCTION(BMSKNL, 3) -+SEMANTIC_FUNCTION(BSETL, 3) -+SEMANTIC_FUNCTION(BXORL, 3) -+SEMANTIC_FUNCTION(ROLL, 2) -+SEMANTIC_FUNCTION(SEXBL, 2) -+SEMANTIC_FUNCTION(SEXHL, 2) -+SEMANTIC_FUNCTION(BTSTL, 2) -+SEMANTIC_FUNCTION(TSTL, 2) -+SEMANTIC_FUNCTION(XBFUL, 3) -+SEMANTIC_FUNCTION(AEXL, 2) -+SEMANTIC_FUNCTION(LRL, 2) -+SEMANTIC_FUNCTION(DIVL, 3) -+SEMANTIC_FUNCTION(DIVUL, 3) -+SEMANTIC_FUNCTION(REML, 3) -+SEMANTIC_FUNCTION(REMUL, 3) -+SEMANTIC_FUNCTION(ABSL, 2) -+SEMANTIC_FUNCTION(SWAPL, 2) -+SEMANTIC_FUNCTION(SWAPEL, 2) -+SEMANTIC_FUNCTION(NOTL, 2) -+SEMANTIC_FUNCTION(SETEQL, 3) -+SEMANTIC_FUNCTION(BREQL, 3) -+SEMANTIC_FUNCTION(SETNEL, 3) -+SEMANTIC_FUNCTION(BRNEL, 3) -+SEMANTIC_FUNCTION(SETLTL, 3) -+SEMANTIC_FUNCTION(BRLTL, 3) -+SEMANTIC_FUNCTION(SETGEL, 3) -+SEMANTIC_FUNCTION(BRGEL, 3) -+SEMANTIC_FUNCTION(SETLEL, 3) -+SEMANTIC_FUNCTION(SETGTL, 3) -+SEMANTIC_FUNCTION(BRLOL, 3) -+SEMANTIC_FUNCTION(SETLOL, 3) -+SEMANTIC_FUNCTION(BRHSL, 3) -+SEMANTIC_FUNCTION(SETHSL, 3) -+SEMANTIC_FUNCTION(EXL, 2) -+SEMANTIC_FUNCTION(LLOCKL, 2) -+SEMANTIC_FUNCTION(SCONDL, 2) -+SEMANTIC_FUNCTION(LDL, 3) -+SEMANTIC_FUNCTION(STL, 3) -+SEMANTIC_FUNCTION(STDL, 3) -+SEMANTIC_FUNCTION(POPL, 1) -+SEMANTIC_FUNCTION(NORML, 2) -+SEMANTIC_FUNCTION(FLSL, 2) -+SEMANTIC_FUNCTION(FFSL, 2) -+SEMANTIC_FUNCTION(DBNZL, 2) -+SEMANTIC_FUNCTION(SEXWL, 2) -+SEMANTIC_FUNCTION(PUSHL, 1) -+ -+MAPPING(absl, ABSL, 2, 1, 0) -+MAPPING(adcl, ADCL, 3, 1, 2, 0) -+MAPPING(add1l, ADD1L, 3, 1, 2, 0) -+MAPPING(add2l, ADD2L, 3, 1, 2, 0) -+MAPPING(add3l, ADD3L, 3, 1, 2, 0) -+MAPPING(addl, ADDL, 3, 1, 2, 0) -+MAPPING(addl_s, ADDL, 3, 1, 2, 0) -+MAPPING(aexl, AEXL, 2, 1, 0) -+MAPPING(andl, ANDL, 3, 0, 1, 2) -+MAPPING(andl_s, ANDL, 3, 0, 1, 2) -+MAPPING(asll, ASLL, 3, 1, 2, 0) -+MAPPING(asrl, ASRL, 3, 1, 2, 0) -+MAPPING(bclrl, BCLRL, 3, 2, 0, 1) -+MAPPING(bicl, BICL, 3, 0, 1, 2) -+MAPPING(bmskl, BMSKL, 3, 2, 0, 1) -+MAPPING(bmsknl, BMSKNL, 3, 2, 0, 1) -+ -+MAPPING(breql, BREQL, 3, 0, 1, 2) -+MAPPING(brnel, BRNEL, 3, 0, 1, 2) -+MAPPING(brltl, BRLTL, 3, 0, 1, 2) -+MAPPING(brgel, BRGEL, 3, 0, 1, 2) -+MAPPING(brlol, BRLOL, 3, 0, 1, 2) -+MAPPING(brhsl, BRHSL, 3, 0, 1, 2) -+MAPPING(bsetl, BSETL, 3, 2, 0, 1) -+MAPPING(btstl, BTSTL, 2, 1, 0) -+MAPPING(bxorl, BXORL, 3, 2, 0, 1) -+MAPPING(cmpl, CMPL, 2, 0, 1) -+ -+MAPPING(divl, DIVL, 3, 2, 1, 0) -+MAPPING(divul, DIVUL, 3, 2, 0, 1) -+ -+MAPPING(exl, EXL, 2, 0, 1) -+MAPPING(flsl, FLSL, 2, 1, 0) -+MAPPING(ffsl, FFSL, 2, 1, 0) -+ -+CONSTANT(LDL, ldl, 2, 0) /* For variable @src2 */ -+MAPPING(ldl, LDL, 3, 1, 2, 0) -+ -+CONSTANT(STL, stl, 2, 0) /* For variable @src2 */ -+MAPPING(stl, STL, 3, 1, 2, 0) -+ -+MAPPING(llockl, LLOCKL, 2, 0, 1) -+ -+MAPPING(lrl, LRL, 2, 0, 1) -+ -+CONSTANT(LSRL, lsrl, 2, 1) /* For variable @c */ -+MAPPING(lsrl, LSRL, 3, 1, 2, 0) -+ -+MAPPING(maxl, MAXL, 3, 1, 2, 0) -+MAPPING(minl, MINL, 3, 1, 2, 0) -+ -+MAPPING(movl, MOVL, 2, 0, 1) -+MAPPING(movl_s, MOVL, 2, 0, 1) -+ -+MAPPING(movhl, MOVHL, 2, 0, 1) -+MAPPING(movhl_s, MOVHL, 2, 0, 1) -+ -+MAPPING(norml, NORML, 2, 1, 0) -+MAPPING(notl, NOTL, 2, 0, 1) -+MAPPING(orl, ORL, 3, 0, 1, 2) -+MAPPING(orl_s, ORL, 3, 0, 1, 2) -+MAPPING(xorl, XORL, 3, 0, 1, 2) -+MAPPING(rcmpl, CMPL, 2, 1, 0) -+MAPPING(reml, REML, 3, 2, 1, 0) -+MAPPING(remul, REMUL, 3, 2, 0, 1) -+ -+MAPPING(roll, ROLL, 2, 1, 0) -+MAPPING(rsubl, SUBL, 3, 2, 1, 0) -+MAPPING(sbcl, SBCL, 3, 1, 2, 0) -+MAPPING(scondl, SCONDL, 2, 1, 0) -+ -+MAPPING(seteql, SETEQL, 3, 1, 2, 0) -+MAPPING(setgel, SETGEL, 3, 1, 2, 0) -+MAPPING(setgtl, SETGTL, 3, 1, 2, 0) -+MAPPING(sethsl, SETHSL, 3, 1, 2, 0) -+MAPPING(setlel, SETLEL, 3, 1, 2, 0) -+MAPPING(setlol, SETLOL, 3, 1, 2, 0) -+MAPPING(setltl, SETLTL, 3, 1, 2, 0) -+MAPPING(setnel, SETNEL, 3, 1, 2, 0) -+ -+MAPPING(sexbl, SEXBL, 2, 0, 1) -+MAPPING(sexhl, SEXHL, 2, 0, 1) -+MAPPING(sexwl, SEXWL, 2, 0, 1) -+ -+CONSTANT(STDL, stdl, 2, 0) /* For variable @src2 */ -+MAPPING(stdl, STDL, 3, 1, 2, 0) -+ -+MAPPING(subl, SUBL, 3, 1, 2, 0) -+MAPPING(subl_s, SUBL, 3, 1, 2, 0) -+MAPPING(sub1l, SUB1L, 3, 1, 2, 0) -+MAPPING(sub2l, SUB2L, 3, 1, 2, 0) -+MAPPING(sub3l, SUB3L, 3, 1, 2, 0) -+ -+MAPPING(swapl, SWAPL, 2, 1, 0) -+MAPPING(swapel, SWAPEL, 2, 1, 0) -+MAPPING(tstl, TSTL, 2, 0, 1) -+ -+MAPPING(xbful, XBFUL, 3, 2, 1, 0) -+ -+MAPPING(pushl_s, PUSHL, 1, 0) -+MAPPING(pushdl_s, PUSHL, 1, 0) -+MAPPING(popl_s, POPL, 1, 0) -+MAPPING(popdl_s, POPL, 1, 0) -+ -+MAPPING(dbnz, DBNZL, 2, 0, 1) -diff --git a/target/arc/semfunc.c b/target/arc/semfunc.c -new file mode 100644 -index 0000000000..784d2a7ced ---- /dev/null -+++ b/target/arc/semfunc.c -@@ -0,0 +1,8441 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "translate.h" -+#include "target/arc/semfunc.h" -+#include "exec/gen-icount.h" -+ -+/* -+ * FLAG -+ * Variables: @src -+ * Functions: getCCFlag, getRegister, getBit, hasInterrupts, Halt, ReplMask, -+ * targetHasOption, setRegister -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * status32 = getRegister (R_STATUS32); -+ * if(((getBit (@src, 0) == 1) && (getBit (status32, 7) == 0))) -+ * { -+ * if((hasInterrupts () > 0)) -+ * { -+ * status32 = (status32 | 1); -+ * Halt (); -+ * }; -+ * } -+ * else -+ * { -+ * ReplMask (status32, @src, 3840); -+ * if(((getBit (status32, 7) == 0) && (hasInterrupts () > 0))) -+ * { -+ * ReplMask (status32, @src, 30); -+ * if(targetHasOption (DIV_REM_OPTION)) -+ * { -+ * ReplMask (status32, @src, 8192); -+ * }; -+ * if(targetHasOption (STACK_CHECKING)) -+ * { -+ * ReplMask (status32, @src, 16384); -+ * }; -+ * if(targetHasOption (LL64_OPTION)) -+ * { -+ * ReplMask (status32, @src, 524288); -+ * }; -+ * ReplMask (status32, @src, 1048576); -+ * }; -+ * }; -+ * setRegister (R_STATUS32, status32); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_FLAG(DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_14 = tcg_temp_local_new(); -+ TCGv status32 = tcg_temp_local_new(); -+ TCGv temp_16 = tcg_temp_local_new(); -+ TCGv temp_15 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_18 = tcg_temp_local_new(); -+ TCGv temp_17 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_19 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_20 = tcg_temp_local_new(); -+ TCGv temp_22 = tcg_temp_local_new(); -+ TCGv temp_21 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_23 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_24 = tcg_temp_local_new(); -+ TCGv temp_25 = tcg_temp_local_new(); -+ TCGv temp_26 = tcg_temp_local_new(); -+ TCGv temp_27 = tcg_temp_local_new(); -+ TCGv temp_28 = tcg_temp_local_new(); -+ getCCFlag(temp_13); -+ tcg_gen_mov_tl(cc_flag, temp_13); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ getRegister(temp_14, R_STATUS32); -+ tcg_gen_mov_tl(status32, temp_14); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_movi_tl(temp_16, 0); -+ getBit(temp_15, src, temp_16); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, temp_15, 1); -+ tcg_gen_movi_tl(temp_18, 7); -+ getBit(temp_17, status32, temp_18); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_4, temp_17, 0); -+ tcg_gen_and_tl(temp_5, temp_3, temp_4); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_2); -+ TCGLabel *done_3 = gen_new_label(); -+ hasInterrupts(temp_19); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_7, temp_19, 0); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); -+ tcg_gen_andi_tl(temp_8, temp_8, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, done_3); -+ tcg_gen_ori_tl(status32, status32, 1); -+ Halt(); -+ gen_set_label(done_3); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_movi_tl(temp_20, 3840); -+ ReplMask(status32, src, temp_20); -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_movi_tl(temp_22, 7); -+ getBit(temp_21, status32, temp_22); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_9, temp_21, 0); -+ hasInterrupts(temp_23); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_10, temp_23, 0); -+ tcg_gen_and_tl(temp_11, temp_9, temp_10); -+ tcg_gen_xori_tl(temp_12, temp_11, 1); -+ tcg_gen_andi_tl(temp_12, temp_12, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_12, arc_true, done_4); -+ tcg_gen_movi_tl(temp_24, 30); -+ ReplMask(status32, src, temp_24); -+ if (targetHasOption (DIV_REM_OPTION)) { -+ tcg_gen_movi_tl(temp_25, 8192); -+ ReplMask(status32, src, temp_25); -+ } -+ if (targetHasOption (STACK_CHECKING)) { -+ tcg_gen_movi_tl(temp_26, 16384); -+ ReplMask(status32, src, temp_26); -+ } -+ if (targetHasOption (LL64_OPTION)) { -+ tcg_gen_movi_tl(temp_27, 524288); -+ ReplMask(status32, src, temp_27); -+ } -+ tcg_gen_movi_tl(temp_28, 1048576); -+ ReplMask(status32, src, temp_28); -+ gen_set_label(done_4); -+ gen_set_label(done_2); -+ setRegister(R_STATUS32, status32); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_14); -+ tcg_temp_free(status32); -+ tcg_temp_free(temp_16); -+ tcg_temp_free(temp_15); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_18); -+ tcg_temp_free(temp_17); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_19); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_20); -+ tcg_temp_free(temp_22); -+ tcg_temp_free(temp_21); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_23); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_24); -+ tcg_temp_free(temp_25); -+ tcg_temp_free(temp_26); -+ tcg_temp_free(temp_27); -+ tcg_temp_free(temp_28); -+ -+ return ret; -+} -+ -+ -+/* -+ * KFLAG -+ * Variables: @src -+ * Functions: getCCFlag, getRegister, getBit, hasInterrupts, Halt, ReplMask, -+ * targetHasOption, setRegister -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * status32 = getRegister (R_STATUS32); -+ * if(((getBit (@src, 0) == 1) && (getBit (status32, 7) == 0))) -+ * { -+ * if((hasInterrupts () > 0)) -+ * { -+ * status32 = (status32 | 1); -+ * Halt (); -+ * }; -+ * } -+ * else -+ * { -+ * ReplMask (status32, @src, 3840); -+ * if(((getBit (status32, 7) == 0) && (hasInterrupts () > 0))) -+ * { -+ * ReplMask (status32, @src, 62); -+ * if(targetHasOption (DIV_REM_OPTION)) -+ * { -+ * ReplMask (status32, @src, 8192); -+ * }; -+ * if(targetHasOption (STACK_CHECKING)) -+ * { -+ * ReplMask (status32, @src, 16384); -+ * }; -+ * ReplMask (status32, @src, 65536); -+ * if(targetHasOption (LL64_OPTION)) -+ * { -+ * ReplMask (status32, @src, 524288); -+ * }; -+ * ReplMask (status32, @src, 1048576); -+ * ReplMask (status32, @src, 2147483648); -+ * }; -+ * }; -+ * setRegister (R_STATUS32, status32); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_KFLAG(DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_14 = tcg_temp_local_new(); -+ TCGv status32 = tcg_temp_local_new(); -+ TCGv temp_16 = tcg_temp_local_new(); -+ TCGv temp_15 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_18 = tcg_temp_local_new(); -+ TCGv temp_17 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_19 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_20 = tcg_temp_local_new(); -+ TCGv temp_22 = tcg_temp_local_new(); -+ TCGv temp_21 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_23 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_24 = tcg_temp_local_new(); -+ TCGv temp_25 = tcg_temp_local_new(); -+ TCGv temp_26 = tcg_temp_local_new(); -+ TCGv temp_27 = tcg_temp_local_new(); -+ TCGv temp_28 = tcg_temp_local_new(); -+ TCGv temp_29 = tcg_temp_local_new(); -+ TCGv temp_30 = tcg_temp_local_new(); -+ getCCFlag(temp_13); -+ tcg_gen_mov_tl(cc_flag, temp_13); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ getRegister(temp_14, R_STATUS32); -+ tcg_gen_mov_tl(status32, temp_14); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_movi_tl(temp_16, 0); -+ getBit(temp_15, src, temp_16); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, temp_15, 1); -+ tcg_gen_movi_tl(temp_18, 7); -+ getBit(temp_17, status32, temp_18); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_4, temp_17, 0); -+ tcg_gen_and_tl(temp_5, temp_3, temp_4); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_2); -+ TCGLabel *done_3 = gen_new_label(); -+ hasInterrupts(temp_19); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_7, temp_19, 0); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); -+ tcg_gen_andi_tl(temp_8, temp_8, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, done_3); -+ tcg_gen_ori_tl(status32, status32, 1); -+ Halt(); -+ gen_set_label(done_3); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_movi_tl(temp_20, 3840); -+ ReplMask(status32, src, temp_20); -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_movi_tl(temp_22, 7); -+ getBit(temp_21, status32, temp_22); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_9, temp_21, 0); -+ hasInterrupts(temp_23); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_10, temp_23, 0); -+ tcg_gen_and_tl(temp_11, temp_9, temp_10); -+ tcg_gen_xori_tl(temp_12, temp_11, 1); -+ tcg_gen_andi_tl(temp_12, temp_12, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_12, arc_true, done_4); -+ tcg_gen_movi_tl(temp_24, 62); -+ ReplMask(status32, src, temp_24); -+ if (targetHasOption (DIV_REM_OPTION)) { -+ tcg_gen_movi_tl(temp_25, 8192); -+ ReplMask(status32, src, temp_25); -+ } -+ if (targetHasOption (STACK_CHECKING)) { -+ tcg_gen_movi_tl(temp_26, 16384); -+ ReplMask(status32, src, temp_26); -+ } -+ tcg_gen_movi_tl(temp_27, 65536); -+ ReplMask(status32, src, temp_27); -+ if (targetHasOption (LL64_OPTION)) { -+ tcg_gen_movi_tl(temp_28, 524288); -+ ReplMask(status32, src, temp_28); -+ } -+ tcg_gen_movi_tl(temp_29, 1048576); -+ ReplMask(status32, src, temp_29); -+ tcg_gen_movi_tl(temp_30, 2147483648); -+ ReplMask(status32, src, temp_30); -+ gen_set_label(done_4); -+ gen_set_label(done_2); -+ setRegister(R_STATUS32, status32); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_14); -+ tcg_temp_free(status32); -+ tcg_temp_free(temp_16); -+ tcg_temp_free(temp_15); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_18); -+ tcg_temp_free(temp_17); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_19); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_20); -+ tcg_temp_free(temp_22); -+ tcg_temp_free(temp_21); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_23); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_24); -+ tcg_temp_free(temp_25); -+ tcg_temp_free(temp_26); -+ tcg_temp_free(temp_27); -+ tcg_temp_free(temp_28); -+ tcg_temp_free(temp_29); -+ tcg_temp_free(temp_30); -+ -+ return ret; -+} -+ -+ -+/* -+ * ADD -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, -+ * setVFlag, OverflowADD -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * lc = @c; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = @c; -+ * @a = (@b + @c); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarryADD (@a, lb, lc)); -+ * setVFlag (OverflowADD (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ADD(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_add_tl(a, b, c); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowADD(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * ADD1 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, -+ * setVFlag, OverflowADD -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * lc = @c; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = @c; -+ * @a = (@b + (@c << 1)); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarryADD (@a, lb, lc)); -+ * setVFlag (OverflowADD (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ADD1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_shli_tl(temp_4, c, 1); -+ tcg_gen_add_tl(a, b, temp_4); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_6, a, lb, lc); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+ OverflowADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setVFlag(temp_7); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+/* -+ * ADD2 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, -+ * setVFlag, OverflowADD -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * lc = @c; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = @c; -+ * @a = (@b + (@c << 2)); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarryADD (@a, lb, lc)); -+ * setVFlag (OverflowADD (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ADD2(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_shli_tl(temp_4, c, 2); -+ tcg_gen_add_tl(a, b, temp_4); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_6, a, lb, lc); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+ OverflowADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setVFlag(temp_7); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+/* -+ * ADD3 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, -+ * setVFlag, OverflowADD -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * lc = @c; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = @c; -+ * @a = (@b + (@c << 3)); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarryADD (@a, lb, lc)); -+ * setVFlag (OverflowADD (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ADD3(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_shli_tl(temp_4, c, 3); -+ tcg_gen_add_tl(a, b, temp_4); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_6, a, lb, lc); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+ OverflowADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setVFlag(temp_7); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+/* -+ * ADC -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, -+ * CarryADD, setVFlag, OverflowADD -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * lc = @c; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = @c; -+ * @a = ((@b + @c) + getCFlag ()); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarryADD (@a, lb, lc)); -+ * setVFlag (OverflowADD (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ADC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_add_tl(temp_4, b, c); -+ getCFlag(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(a, temp_4, temp_5); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setCFlag(temp_7); -+ OverflowADD(temp_10, a, lb, lc); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ setVFlag(temp_9); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ -+ return ret; -+} -+ -+ -+/* -+ * SBC -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, -+ * CarryADD, setVFlag, OverflowADD -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * lc = @c; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = @c; -+ * @a = ((@b - @c) - getCFlag ()); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarryADD (@a, lb, lc)); -+ * setVFlag (OverflowADD (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SBC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_sub_tl(temp_4, b, c); -+ getCFlag(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_sub_tl(a, temp_4, temp_5); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarryADD(temp_8, a, lb, lc); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setCFlag(temp_7); -+ OverflowADD(temp_10, a, lb, lc); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ setVFlag(temp_9); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ -+ return ret; -+} -+ -+ -+/* -+ * NEG -+ * Variables: @b, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, -+ * setVFlag, OverflowSUB -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * @a = (0 - @b); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarrySUB (@a, 0, lb)); -+ * setVFlag (OverflowSUB (@a, 0, lb)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_NEG(DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_subfi_tl(a, 0, b); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ tcg_gen_movi_tl(temp_6, 0); -+ CarrySUB(temp_5, a, temp_6, lb); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ tcg_gen_movi_tl(temp_9, 0); -+ OverflowSUB(temp_8, a, temp_9, lb); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setVFlag(temp_7); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+/* -+ * SUB -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, -+ * setVFlag, OverflowSUB -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = @c; -+ * @a = (@b - @c); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarrySUB (@a, lb, lc)); -+ * setVFlag (OverflowSUB (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SUB(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_sub_tl(a, b, c); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarrySUB(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * SUB1 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, -+ * setVFlag, OverflowSUB -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = (@c << 1); -+ * @a = (@b - lc); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarrySUB (@a, lb, lc)); -+ * setVFlag (OverflowSUB (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SUB1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_shli_tl(lc, c, 1); -+ tcg_gen_sub_tl(a, b, lc); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarrySUB(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * SUB2 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, -+ * setVFlag, OverflowSUB -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = (@c << 2); -+ * @a = (@b - lc); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarrySUB (@a, lb, lc)); -+ * setVFlag (OverflowSUB (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SUB2(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_shli_tl(lc, c, 2); -+ tcg_gen_sub_tl(a, b, lc); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarrySUB(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * SUB3 -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, -+ * setVFlag, OverflowSUB -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = (@c << 3); -+ * @a = (@b - lc); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setCFlag (CarrySUB (@a, lb, lc)); -+ * setVFlag (OverflowSUB (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SUB3(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_shli_tl(lc, c, 3); -+ tcg_gen_sub_tl(a, b, lc); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ CarrySUB(temp_5, a, lb, lc); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * MAX -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, -+ * setVFlag, OverflowSUB -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = @c; -+ * alu = (lb - lc); -+ * if((lc >= lb)) -+ * { -+ * @a = lc; -+ * } -+ * else -+ * { -+ * @a = lb; -+ * }; -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (alu); -+ * setNFlag (alu); -+ * setCFlag (CarrySUB (@a, lb, lc)); -+ * setVFlag (OverflowSUB (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MAX(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_sub_tl(alu, lb, lc); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_3, lc, lb); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_mov_tl(a, lc); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, lb); -+ gen_set_label(done_2); -+ if ((getFFlag () == true)) { -+ setZFlag(alu); -+ setNFlag(alu); -+ CarrySUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setCFlag(temp_6); -+ OverflowSUB(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setVFlag(temp_8); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+/* -+ * MIN -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, -+ * setVFlag, OverflowSUB -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * lb = @b; -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = @c; -+ * alu = (lb - lc); -+ * if((lc <= lb)) -+ * { -+ * @a = lc; -+ * } -+ * else -+ * { -+ * @a = lb; -+ * }; -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (alu); -+ * setNFlag (alu); -+ * setCFlag (CarrySUB (@a, lb, lc)); -+ * setVFlag (OverflowSUB (@a, lb, lc)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MIN(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ tcg_gen_mov_tl(lb, b); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_mov_tl(lc, c); -+ tcg_gen_sub_tl(alu, lb, lc); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LE, temp_3, lc, lb); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_mov_tl(a, lc); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, lb); -+ gen_set_label(done_2); -+ if ((getFFlag () == true)) { -+ setZFlag(alu); -+ setNFlag(alu); -+ CarrySUB(temp_7, a, lb, lc); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setCFlag(temp_6); -+ OverflowSUB(temp_9, a, lb, lc); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setVFlag(temp_8); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+/* -+ * CMP -+ * Variables: @b, @c -+ * Functions: getCCFlag, setZFlag, setNFlag, setCFlag, CarrySUB, setVFlag, -+ * OverflowSUB -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * alu = (@b - @c); -+ * setZFlag (alu); -+ * setNFlag (alu); -+ * setCFlag (CarrySUB (alu, @b, @c)); -+ * setVFlag (OverflowSUB (alu, @b, @c)); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_CMP(DisasCtxt *ctx, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_sub_tl(alu, b, c); -+ setZFlag(alu); -+ setNFlag(alu); -+ CarrySUB(temp_5, alu, b, c); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ setCFlag(temp_4); -+ OverflowSUB(temp_7, alu, b, c); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setVFlag(temp_6); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * AND -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * la = (@b & @c); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_AND(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_and_tl(la, b, c); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * OR -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * la = (@b | @c); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_OR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_or_tl(la, b, c); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * XOR -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * la = (@b ^ @c); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_XOR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_xor_tl(la, b, c); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * MOV -+ * Variables: @b, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * la = @b; -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MOV(DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(la, b); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * ASL -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, getBit, -+ * setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = (@c & 31); -+ * la = (lb << lc); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * if((lc == 0)) -+ * { -+ * setCFlag (0); -+ * } -+ * else -+ * { -+ * setCFlag (getBit (lb, (32 - lc))); -+ * }; -+ * if((@c == 268435457)) -+ * { -+ * t1 = getBit (la, 31); -+ * t2 = getBit (lb, 31); -+ * if((t1 == t2)) -+ * { -+ * setVFlag (0); -+ * } -+ * else -+ * { -+ * setVFlag (1); -+ * }; -+ * }; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ASL(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_15 = tcg_temp_local_new(); -+ TCGv temp_14 = tcg_temp_local_new(); -+ TCGv t1 = tcg_temp_local_new(); -+ TCGv temp_17 = tcg_temp_local_new(); -+ TCGv temp_16 = tcg_temp_local_new(); -+ TCGv t2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_18 = tcg_temp_local_new(); -+ TCGv temp_19 = tcg_temp_local_new(); -+ getCCFlag(temp_9); -+ tcg_gen_mov_tl(cc_flag, temp_9); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_andi_tl(lc, c, 31); -+ tcg_gen_shl_tl(la, lb, lc); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, lc, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_movi_tl(temp_10, 0); -+ setCFlag(temp_10); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_subfi_tl(temp_13, 32, lc); -+ getBit(temp_12, lb, temp_13); -+ tcg_gen_mov_tl(temp_11, temp_12); -+ setCFlag(temp_11); -+ gen_set_label(done_2); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_5, c, 268435457); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, done_3); -+ tcg_gen_movi_tl(temp_15, 31); -+ getBit(temp_14, la, temp_15); -+ tcg_gen_mov_tl(t1, temp_14); -+ tcg_gen_movi_tl(temp_17, 31); -+ getBit(temp_16, lb, temp_17); -+ tcg_gen_mov_tl(t2, temp_16); -+ TCGLabel *else_4 = gen_new_label(); -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_7, t1, t2); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); -+ tcg_gen_andi_tl(temp_8, temp_8, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, else_4); -+ tcg_gen_movi_tl(temp_18, 0); -+ setVFlag(temp_18); -+ tcg_gen_br(done_4); -+ gen_set_label(else_4); -+ tcg_gen_movi_tl(temp_19, 1); -+ setVFlag(temp_19); -+ gen_set_label(done_4); -+ gen_set_label(done_3); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(la); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_15); -+ tcg_temp_free(temp_14); -+ tcg_temp_free(t1); -+ tcg_temp_free(temp_17); -+ tcg_temp_free(temp_16); -+ tcg_temp_free(t2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_18); -+ tcg_temp_free(temp_19); -+ -+ return ret; -+} -+ -+ -+/* -+ * ASR -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag, -+ * setCFlag, getBit -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = (@c & 31); -+ * la = arithmeticShiftRight (lb, lc); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * if((lc == 0)) -+ * { -+ * setCFlag (0); -+ * } -+ * else -+ * { -+ * setCFlag (getBit (lb, (lc - 1))); -+ * }; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ASR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_andi_tl(lc, c, 31); -+ arithmeticShiftRight(temp_6, lb, lc); -+ tcg_gen_mov_tl(la, temp_6); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, lc, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_movi_tl(temp_7, 0); -+ setCFlag(temp_7); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_subi_tl(temp_10, lc, 1); -+ getBit(temp_9, lb, temp_10); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ gen_set_label(done_2); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(la); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+/* -+ * ASR8 -+ * Variables: @b, @a -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * la = arithmeticShiftRight (lb, 8); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ASR8(DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_movi_tl(temp_5, 8); -+ arithmeticShiftRight(temp_4, lb, temp_5); -+ tcg_gen_mov_tl(la, temp_4); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * ASR16 -+ * Variables: @b, @a -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * la = arithmeticShiftRight (lb, 16); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ASR16(DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_movi_tl(temp_5, 16); -+ arithmeticShiftRight(temp_4, lb, temp_5); -+ tcg_gen_mov_tl(la, temp_4); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * LSL16 -+ * Variables: @b, @a -+ * Functions: getCCFlag, logicalShiftLeft, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * la = logicalShiftLeft (@b, 16); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_LSL16(DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_movi_tl(temp_5, 16); -+ logicalShiftLeft(temp_4, b, temp_5); -+ tcg_gen_mov_tl(la, temp_4); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * LSL8 -+ * Variables: @b, @a -+ * Functions: getCCFlag, logicalShiftLeft, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * la = logicalShiftLeft (@b, 8); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_LSL8(DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_movi_tl(temp_5, 8); -+ logicalShiftLeft(temp_4, b, temp_5); -+ tcg_gen_mov_tl(la, temp_4); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * LSR -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag, -+ * setCFlag, getBit -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lb = @b; -+ * lc = (@c & 31); -+ * la = logicalShiftRight (lb, lc); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * if((lc == 0)) -+ * { -+ * setCFlag (0); -+ * } -+ * else -+ * { -+ * setCFlag (getBit (lb, (lc - 1))); -+ * }; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_LSR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lb = tcg_temp_local_new(); -+ TCGv lc = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lb, b); -+ tcg_gen_andi_tl(lc, c, 31); -+ logicalShiftRight(temp_6, lb, lc); -+ tcg_gen_mov_tl(la, temp_6); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, lc, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_movi_tl(temp_7, 0); -+ setCFlag(temp_7); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_subi_tl(temp_10, lc, 1); -+ getBit(temp_9, lb, temp_10); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setCFlag(temp_8); -+ gen_set_label(done_2); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lb); -+ tcg_temp_free(lc); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(la); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+/* -+ * LSR16 -+ * Variables: @b, @a -+ * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * la = logicalShiftRight (@b, 16); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_LSR16(DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_movi_tl(temp_5, 16); -+ logicalShiftRight(temp_4, b, temp_5); -+ tcg_gen_mov_tl(la, temp_4); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * LSR8 -+ * Variables: @b, @a -+ * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * la = logicalShiftRight (@b, 8); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_LSR8(DisasCtxt *ctx, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_movi_tl(temp_5, 8); -+ logicalShiftRight(temp_4, b, temp_5); -+ tcg_gen_mov_tl(la, temp_4); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * BIC -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * la = (@b & ~@c); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BIC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_not_tl(temp_4, c); -+ tcg_gen_and_tl(la, b, temp_4); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * BCLR -+ * Variables: @c, @b, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * tmp = (1 << (@c & 31)); -+ * la = (@b & ~tmp); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BCLR(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_andi_tl(temp_4, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, temp_4); -+ tcg_gen_not_tl(temp_5, tmp); -+ tcg_gen_and_tl(la, b, temp_5); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * BMSK -+ * Variables: @c, @b, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * tmp1 = ((@c & 31) + 1); -+ * if((tmp1 == 32)) -+ * { -+ * tmp2 = 4294967295; -+ * } -+ * else -+ * { -+ * tmp2 = ((1 << tmp1) - 1); -+ * }; -+ * la = (@b & tmp2); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BMSK(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_andi_tl(temp_6, c, 31); -+ tcg_gen_addi_tl(tmp1, temp_6, 1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, tmp1, 32); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_movi_tl(tmp2, 4294967295); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_shlfi_tl(temp_7, 1, tmp1); -+ tcg_gen_subi_tl(tmp2, temp_7, 1); -+ gen_set_label(done_2); -+ tcg_gen_and_tl(la, b, tmp2); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * BMSKN -+ * Variables: @c, @b, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * tmp1 = ((@c & 31) + 1); -+ * if((tmp1 == 32)) -+ * { -+ * tmp2 = 4294967295; -+ * } -+ * else -+ * { -+ * tmp2 = ((1 << tmp1) - 1); -+ * }; -+ * la = (@b & ~tmp2); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BMSKN(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_andi_tl(temp_6, c, 31); -+ tcg_gen_addi_tl(tmp1, temp_6, 1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_3, tmp1, 32); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_movi_tl(tmp2, 4294967295); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_shlfi_tl(temp_7, 1, tmp1); -+ tcg_gen_subi_tl(tmp2, temp_7, 1); -+ gen_set_label(done_2); -+ tcg_gen_not_tl(temp_8, tmp2); -+ tcg_gen_and_tl(la, b, temp_8); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * BSET -+ * Variables: @c, @b, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * tmp = (1 << (@c & 31)); -+ * la = (@b | tmp); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BSET(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_andi_tl(temp_4, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, temp_4); -+ tcg_gen_or_tl(la, b, tmp); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * BXOR -+ * Variables: @c, @b, @a -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * tmp = (1 << @c); -+ * la = (@b ^ tmp); -+ * @a = la; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (la); -+ * setNFlag (la); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BXOR(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv la = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_shlfi_tl(tmp, 1, c); -+ tcg_gen_xor_tl(la, b, tmp); -+ tcg_gen_mov_tl(a, la); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(la); -+ setNFlag(la); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(tmp); -+ tcg_temp_free(la); -+ -+ return ret; -+} -+ -+ -+/* -+ * ROL -+ * Variables: @src, @dest -+ * Functions: getCCFlag, rotateLeft, getFFlag, setZFlag, setNFlag, setCFlag, -+ * extractBits -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lsrc = @src; -+ * @dest = rotateLeft (lsrc, 1); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * setCFlag (extractBits (lsrc, 31, 31)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ROL(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lsrc, src); -+ tcg_gen_movi_tl(temp_5, 1); -+ rotateLeft(temp_4, lsrc, temp_5); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_movi_tl(temp_9, 31); -+ tcg_gen_movi_tl(temp_8, 31); -+ extractBits(temp_7, lsrc, temp_8, temp_9); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setCFlag(temp_6); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * ROL8 -+ * Variables: @src, @dest -+ * Functions: getCCFlag, rotateLeft, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lsrc = @src; -+ * @dest = rotateLeft (lsrc, 8); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ROL8(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lsrc, src); -+ tcg_gen_movi_tl(temp_5, 8); -+ rotateLeft(temp_4, lsrc, temp_5); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * ROR -+ * Variables: @src, @n, @dest -+ * Functions: getCCFlag, rotateRight, getFFlag, setZFlag, setNFlag, -+ * setCFlag, extractBits -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lsrc = @src; -+ * ln = (@n & 31); -+ * @dest = rotateRight (lsrc, ln); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * setCFlag (extractBits (lsrc, (ln - 1), (ln - 1))); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ROR(DisasCtxt *ctx, TCGv src, TCGv n, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv ln = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lsrc, src); -+ tcg_gen_andi_tl(ln, n, 31); -+ rotateRight(temp_4, lsrc, ln); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_subi_tl(temp_8, ln, 1); -+ tcg_gen_subi_tl(temp_7, ln, 1); -+ extractBits(temp_6, lsrc, temp_7, temp_8); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ setCFlag(temp_5); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(ln); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+/* -+ * ROR8 -+ * Variables: @src, @dest -+ * Functions: getCCFlag, rotateRight, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lsrc = @src; -+ * @dest = rotateRight (lsrc, 8); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ROR8(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lsrc, src); -+ tcg_gen_movi_tl(temp_5, 8); -+ rotateRight(temp_4, lsrc, temp_5); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * RLC -+ * Variables: @src, @dest -+ * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, -+ * extractBits -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lsrc = @src; -+ * @dest = (lsrc << 1); -+ * @dest = (@dest | getCFlag ()); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * setCFlag (extractBits (lsrc, 31, 31)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_RLC(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lsrc, src); -+ tcg_gen_shli_tl(dest, lsrc, 1); -+ getCFlag(temp_5); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ tcg_gen_or_tl(dest, dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_movi_tl(temp_9, 31); -+ tcg_gen_movi_tl(temp_8, 31); -+ extractBits(temp_7, lsrc, temp_8, temp_9); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ setCFlag(temp_6); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * RRC -+ * Variables: @src, @dest -+ * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, -+ * extractBits -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * lsrc = @src; -+ * @dest = (lsrc >> 1); -+ * @dest = (@dest | (getCFlag () << 31)); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * setCFlag (extractBits (lsrc, 0, 0)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_RRC(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(lsrc, src); -+ tcg_gen_shri_tl(dest, lsrc, 1); -+ getCFlag(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_shli_tl(temp_4, temp_5, 31); -+ tcg_gen_or_tl(dest, dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_movi_tl(temp_10, 0); -+ tcg_gen_movi_tl(temp_9, 0); -+ extractBits(temp_8, lsrc, temp_9, temp_10); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ setCFlag(temp_7); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(lsrc); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+/* -+ * SEXB -+ * Variables: @dest, @src -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * @dest = arithmeticShiftRight ((@src << 24), 24); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SEXB(DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_movi_tl(temp_6, 24); -+ tcg_gen_shli_tl(temp_5, src, 24); -+ arithmeticShiftRight(temp_4, temp_5, temp_6); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * SEXH -+ * Variables: @dest, @src -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * @dest = arithmeticShiftRight ((@src << 16), 16); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SEXH(DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_movi_tl(temp_6, 16); -+ tcg_gen_shli_tl(temp_5, src, 16); -+ arithmeticShiftRight(temp_4, temp_5, temp_6); -+ tcg_gen_mov_tl(dest, temp_4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * EXTB -+ * Variables: @dest, @src -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * @dest = (@src & 255); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_EXTB(DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_andi_tl(dest, src, 255); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+/* -+ * EXTH -+ * Variables: @dest, @src -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * @dest = (@src & 65535); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_EXTH(DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ int f_flag; -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_andi_tl(dest, src, 65535); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+/* -+ * BTST -+ * Variables: @c, @b -+ * Functions: getCCFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * tmp = (1 << (@c & 31)); -+ * alu = (@b & tmp); -+ * setZFlag (alu); -+ * setNFlag (alu); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BTST(DisasCtxt *ctx, TCGv c, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_andi_tl(temp_4, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, temp_4); -+ tcg_gen_and_tl(alu, b, tmp); -+ setZFlag(alu); -+ setNFlag(alu); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ tcg_temp_free(alu); -+ -+ return ret; -+} -+ -+ -+/* -+ * TST -+ * Variables: @b, @c -+ * Functions: getCCFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * alu = (@b & @c); -+ * setZFlag (alu); -+ * setNFlag (alu); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_TST(DisasCtxt *ctx, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_and_tl(alu, b, c); -+ setZFlag(alu); -+ setNFlag(alu); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(alu); -+ -+ return ret; -+} -+ -+ -+/* -+ * XBFU -+ * Variables: @src2, @src1, @dest -+ * Functions: getCCFlag, extractBits, getFFlag, setZFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * N = extractBits (@src2, 4, 0); -+ * M = (extractBits (@src2, 9, 5) + 1); -+ * tmp1 = (@src1 >> N); -+ * tmp2 = ((1 << M) - 1); -+ * @dest = (tmp1 & tmp2); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@dest); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_XBFU(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv N = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv M = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_movi_tl(temp_6, 0); -+ tcg_gen_movi_tl(temp_5, 4); -+ extractBits(temp_4, src2, temp_5, temp_6); -+ tcg_gen_mov_tl(N, temp_4); -+ tcg_gen_movi_tl(temp_10, 5); -+ tcg_gen_movi_tl(temp_9, 9); -+ extractBits(temp_8, src2, temp_9, temp_10); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_addi_tl(M, temp_7, 1); -+ tcg_gen_shr_tl(tmp1, src1, N); -+ tcg_gen_shlfi_tl(temp_11, 1, M); -+ tcg_gen_subi_tl(tmp2, temp_11, 1); -+ tcg_gen_and_tl(dest, tmp1, tmp2); -+ if ((getFFlag () == true)) { -+ setZFlag(dest); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(N); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(M); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(tmp2); -+ -+ return ret; -+} -+ -+ -+/* -+ * AEX -+ * Variables: @src2, @b -+ * Functions: getCCFlag, readAuxReg, writeAuxReg -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * tmp = readAuxReg (@src2); -+ * writeAuxReg (@src2, @b); -+ * @b = tmp; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_AEX(DisasCtxt *ctx, TCGv src2, TCGv b) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ readAuxReg(temp_4, src2); -+ tcg_gen_mov_tl(tmp, temp_4); -+ writeAuxReg(src2, b); -+ tcg_gen_mov_tl(b, tmp); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp); -+ -+ return ret; -+} -+ -+ -+/* -+ * LR -+ * Variables: @dest, @src -+ * Functions: readAuxReg -+ * --- code --- -+ * { -+ * @dest = readAuxReg (@src); -+ * } -+ */ -+ -+int -+arc_gen_LR(DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ -+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) -+ gen_io_start(); -+ -+ TCGv temp_1 = tcg_temp_local_new(); -+ readAuxReg(temp_1, src); -+ tcg_gen_mov_tl(dest, temp_1); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+/* -+ * CLRI -+ * Variables: @c -+ * Functions: getRegister, setRegister -+ * --- code --- -+ * { -+ * status32 = getRegister (R_STATUS32); -+ * ie = (status32 & 2147483648); -+ * ie = (ie >> 27); -+ * e = ((status32 & 30) >> 1); -+ * a = 32; -+ * @c = ((ie | e) | a); -+ * mask = 2147483648; -+ * mask = ~mask; -+ * status32 = (status32 & mask); -+ * setRegister (R_STATUS32, status32); -+ * } -+ */ -+ -+int -+arc_gen_CLRI(DisasCtxt *ctx, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv status32 = tcg_temp_local_new(); -+ TCGv ie = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv e = tcg_temp_local_new(); -+ TCGv a = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv mask = tcg_temp_local_new(); -+ getRegister(temp_1, R_STATUS32); -+ tcg_gen_mov_tl(status32, temp_1); -+ tcg_gen_andi_tl(ie, status32, 2147483648); -+ tcg_gen_shri_tl(ie, ie, 27); -+ tcg_gen_andi_tl(temp_2, status32, 30); -+ tcg_gen_shri_tl(e, temp_2, 1); -+ tcg_gen_movi_tl(a, 32); -+ tcg_gen_or_tl(temp_3, ie, e); -+ tcg_gen_or_tl(c, temp_3, a); -+ tcg_gen_movi_tl(mask, 2147483648); -+ tcg_gen_not_tl(mask, mask); -+ tcg_gen_and_tl(status32, status32, mask); -+ setRegister(R_STATUS32, status32); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(status32); -+ tcg_temp_free(ie); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(e); -+ tcg_temp_free(a); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(mask); -+ -+ return ret; -+} -+ -+ -+/* -+ * SETI -+ * Variables: @c -+ * Functions: getRegister, setRegister -+ * --- code --- -+ * { -+ * status32 = getRegister (R_STATUS32); -+ * e_mask = 30; -+ * e_mask = ~e_mask; -+ * e_value = ((@c & 15) << 1); -+ * temp1 = (@c & 32); -+ * if((temp1 != 0)) -+ * { -+ * status32 = ((status32 & e_mask) | e_value); -+ * ie_mask = 2147483648; -+ * ie_mask = ~ie_mask; -+ * ie_value = ((@c & 16) << 27); -+ * status32 = ((status32 & ie_mask) | ie_value); -+ * } -+ * else -+ * { -+ * status32 = (status32 | 2147483648); -+ * temp2 = (@c & 16); -+ * if((temp2 != 0)) -+ * { -+ * status32 = ((status32 & e_mask) | e_value); -+ * }; -+ * }; -+ * setRegister (R_STATUS32, status32); -+ * } -+ */ -+ -+int -+arc_gen_SETI(DisasCtxt *ctx, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv status32 = tcg_temp_local_new(); -+ TCGv e_mask = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv e_value = tcg_temp_local_new(); -+ TCGv temp1 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv ie_mask = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv ie_value = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ getRegister(temp_5, R_STATUS32); -+ tcg_gen_mov_tl(status32, temp_5); -+ tcg_gen_movi_tl(e_mask, 30); -+ tcg_gen_not_tl(e_mask, e_mask); -+ tcg_gen_andi_tl(temp_6, c, 15); -+ tcg_gen_shli_tl(e_value, temp_6, 1); -+ tcg_gen_andi_tl(temp1, c, 32); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_1, temp1, 0); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_and_tl(temp_7, status32, e_mask); -+ tcg_gen_or_tl(status32, temp_7, e_value); -+ tcg_gen_movi_tl(ie_mask, 2147483648); -+ tcg_gen_not_tl(ie_mask, ie_mask); -+ tcg_gen_andi_tl(temp_8, c, 16); -+ tcg_gen_shli_tl(ie_value, temp_8, 27); -+ tcg_gen_and_tl(temp_9, status32, ie_mask); -+ tcg_gen_or_tl(status32, temp_9, ie_value); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_ori_tl(status32, status32, 2147483648); -+ tcg_gen_andi_tl(temp2, c, 16); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, temp2, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2); -+ tcg_gen_and_tl(temp_10, status32, e_mask); -+ tcg_gen_or_tl(status32, temp_10, e_value); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ setRegister(R_STATUS32, status32); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(status32); -+ tcg_temp_free(e_mask); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(e_value); -+ tcg_temp_free(temp1); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(ie_mask); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(ie_value); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+/* -+ * NOP -+ * Variables: -+ * Functions: doNothing -+ * --- code --- -+ * { -+ * doNothing (); -+ * } -+ */ -+ -+int -+arc_gen_NOP(DisasCtxt *ctx) -+{ -+ int ret = DISAS_NEXT; -+ -+ return ret; -+} -+ -+ -+/* -+ * PREALLOC -+ * Variables: -+ * Functions: doNothing -+ * --- code --- -+ * { -+ * doNothing (); -+ * } -+ */ -+ -+int -+arc_gen_PREALLOC(DisasCtxt *ctx) -+{ -+ int ret = DISAS_NEXT; -+ -+ return ret; -+} -+ -+ -+/* -+ * PREFETCH -+ * Variables: @src1, @src2 -+ * Functions: getAAFlag, doNothing -+ * --- code --- -+ * { -+ * AA = getAAFlag (); -+ * if(((AA == 1) || (AA == 2))) -+ * { -+ * @src1 = (@src1 + @src2); -+ * } -+ * else -+ * { -+ * doNothing (); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_PREFETCH(DisasCtxt *ctx, TCGv src1, TCGv src2) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ AA = getAAFlag (); -+ if (((AA == 1) || (AA == 2))) { -+ tcg_gen_add_tl(src1, src1, src2); -+ } else { -+ doNothing(); -+ } -+ -+ return ret; -+} -+ -+ -+/* -+ * MPY -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, HELPER, setZFlag, setNFlag, setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * _b = @b; -+ * _c = @c; -+ * @a = ((_b * _c) & 4294967295); -+ * if((getFFlag () == true)) -+ * { -+ * high_part = HELPER (mpym, _b, _c); -+ * tmp1 = (high_part & 2147483648); -+ * tmp2 = (@a & 2147483648); -+ * setZFlag (@a); -+ * setNFlag (high_part); -+ * setVFlag ((tmp1 != tmp2)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MPY(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv _b = tcg_temp_local_new(); -+ TCGv _c = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv high_part = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(_b, b); -+ tcg_gen_mov_tl(_c, c); -+ tcg_gen_mul_tl(temp_4, _b, _c); -+ tcg_gen_andi_tl(a, temp_4, 4294967295); -+ if ((getFFlag () == true)) { -+ ARC_HELPER(mpym, high_part, _b, _c); -+ tcg_gen_andi_tl(tmp1, high_part, 2147483648); -+ tcg_gen_andi_tl(tmp2, a, 2147483648); -+ setZFlag(a); -+ setNFlag(high_part); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_5, tmp1, tmp2); -+ setVFlag(temp_5); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(_b); -+ tcg_temp_free(_c); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(high_part); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+/* -+ * MPYMU -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, HELPER, getFFlag, setZFlag, setNFlag, setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * @a = HELPER (mpymu, @b, @c); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (0); -+ * setVFlag (0); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MPYMU(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ ARC_HELPER(mpymu, a, b, c); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ tcg_gen_movi_tl(temp_4, 0); -+ setNFlag(temp_4); -+ tcg_gen_movi_tl(temp_5, 0); -+ setVFlag(temp_5); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+/* -+ * MPYM -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, HELPER, getFFlag, setZFlag, setNFlag, setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * @a = HELPER (mpym, @b, @c); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setVFlag (0); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MPYM(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ ARC_HELPER(mpym, a, b, c); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ tcg_gen_movi_tl(temp_4, 0); -+ setVFlag(temp_4); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * MPYU -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getFFlag, HELPER, setZFlag, setNFlag, setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * _b = @b; -+ * _c = @c; -+ * @a = ((_b * _c) & 4294967295); -+ * if((getFFlag () == true)) -+ * { -+ * high_part = HELPER (mpym, _b, _c); -+ * setZFlag (@a); -+ * setNFlag (0); -+ * setVFlag ((high_part > 0)); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MPYU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv _b = tcg_temp_local_new(); -+ TCGv _c = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv high_part = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(_b, b); -+ tcg_gen_mov_tl(_c, c); -+ tcg_gen_mul_tl(temp_4, _b, _c); -+ tcg_gen_andi_tl(a, temp_4, 4294967295); -+ if ((getFFlag () == true)) { -+ ARC_HELPER(mpym, high_part, _b, _c); -+ setZFlag(a); -+ tcg_gen_movi_tl(temp_5, 0); -+ setNFlag(temp_5); -+ tcg_gen_setcondi_tl(TCG_COND_GT, temp_6, high_part, 0); -+ setVFlag(temp_6); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(_b); -+ tcg_temp_free(_c); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(high_part); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * MPYUW -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * @a = ((@b & 65535) * (@c & 65535)); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (0); -+ * setVFlag (0); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MPYUW(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_andi_tl(temp_5, c, 65535); -+ tcg_gen_andi_tl(temp_4, b, 65535); -+ tcg_gen_mul_tl(a, temp_4, temp_5); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ tcg_gen_movi_tl(temp_6, 0); -+ setNFlag(temp_6); -+ tcg_gen_movi_tl(temp_7, 0); -+ setVFlag(temp_7); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+/* -+ * MPYW -+ * Variables: @a, @b, @c -+ * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag, -+ * setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * @a = (arithmeticShiftRight ((@b << 16), 16) -+ * * arithmeticShiftRight ((@c << 16), 16)); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@a); -+ * setNFlag (@a); -+ * setVFlag (0); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MPYW(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ getCCFlag(temp_3); -+ tcg_gen_mov_tl(cc_flag, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_movi_tl(temp_11, 16); -+ tcg_gen_shli_tl(temp_10, c, 16); -+ tcg_gen_movi_tl(temp_7, 16); -+ tcg_gen_shli_tl(temp_6, b, 16); -+ arithmeticShiftRight(temp_5, temp_6, temp_7); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ arithmeticShiftRight(temp_9, temp_10, temp_11); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ tcg_gen_mul_tl(a, temp_4, temp_8); -+ if ((getFFlag () == true)) { -+ setZFlag(a); -+ setNFlag(a); -+ tcg_gen_movi_tl(temp_12, 0); -+ setVFlag(temp_12); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_12); -+ -+ return ret; -+} -+ -+ -+/* -+ * DIV -+ * Variables: @src2, @src1, @dest -+ * Functions: getCCFlag, divSigned, getFFlag, setZFlag, setNFlag, setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * if(((@src2 != 0) && ((@src1 != 2147483648) || (@src2 != 4294967295)))) -+ * { -+ * @dest = divSigned (@src1, @src2); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * setVFlag (0); -+ * }; -+ * } -+ * else -+ * { -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_DIV(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_9); -+ tcg_gen_mov_tl(cc_flag, temp_9); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_4, src1, 2147483648); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_5, src2, 4294967295); -+ tcg_gen_or_tl(temp_6, temp_4, temp_5); -+ tcg_gen_and_tl(temp_7, temp_3, temp_6); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); -+ tcg_gen_andi_tl(temp_8, temp_8, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, else_2); -+ divSigned(temp_10, src1, src2); -+ tcg_gen_mov_tl(dest, temp_10); -+ if ((getFFlag () == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_movi_tl(temp_11, 0); -+ setVFlag(temp_11); -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+/* -+ * DIVU -+ * Variables: @src2, @dest, @src1 -+ * Functions: getCCFlag, divUnsigned, getFFlag, setZFlag, setNFlag, -+ * setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * if((@src2 != 0)) -+ * { -+ * @dest = divUnsigned (@src1, @src2); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (0); -+ * setVFlag (0); -+ * }; -+ * } -+ * else -+ * { -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_DIVU(DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ divUnsigned(temp_6, src1, src2); -+ tcg_gen_mov_tl(dest, temp_6); -+ if ((getFFlag () == true)) { -+ setZFlag(dest); -+ tcg_gen_movi_tl(temp_7, 0); -+ setNFlag(temp_7); -+ tcg_gen_movi_tl(temp_8, 0); -+ setVFlag(temp_8); -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+/* -+ * REM -+ * Variables: @src2, @src1, @dest -+ * Functions: getCCFlag, divRemainingSigned, getFFlag, setZFlag, setNFlag, -+ * setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * if(((@src2 != 0) && ((@src1 != 2147483648) || (@src2 != 4294967295)))) -+ * { -+ * @dest = divRemainingSigned (@src1, @src2); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * setVFlag (0); -+ * }; -+ * } -+ * else -+ * { -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_REM(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_9); -+ tcg_gen_mov_tl(cc_flag, temp_9); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_4, src1, 2147483648); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_5, src2, 4294967295); -+ tcg_gen_or_tl(temp_6, temp_4, temp_5); -+ tcg_gen_and_tl(temp_7, temp_3, temp_6); -+ tcg_gen_xori_tl(temp_8, temp_7, 1); -+ tcg_gen_andi_tl(temp_8, temp_8, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, else_2); -+ divRemainingSigned(temp_10, src1, src2); -+ tcg_gen_mov_tl(dest, temp_10); -+ if ((getFFlag () == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_movi_tl(temp_11, 0); -+ setVFlag(temp_11); -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+/* -+ * REMU -+ * Variables: @src2, @dest, @src1 -+ * Functions: getCCFlag, divRemainingUnsigned, getFFlag, setZFlag, setNFlag, -+ * setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * if((@src2 != 0)) -+ * { -+ * @dest = divRemainingUnsigned (@src1, @src2); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (0); -+ * setVFlag (0); -+ * }; -+ * } -+ * else -+ * { -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_REMU(DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ divRemainingUnsigned(temp_6, src1, src2); -+ tcg_gen_mov_tl(dest, temp_6); -+ if ((getFFlag () == true)) { -+ setZFlag(dest); -+ tcg_gen_movi_tl(temp_7, 0); -+ setNFlag(temp_7); -+ tcg_gen_movi_tl(temp_8, 0); -+ setVFlag(temp_8); -+ } -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+/* -+ * MAC -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getRegister, MAC, getFFlag, setNFlag, OverflowADD, -+ * setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * old_acchi = getRegister (R_ACCHI); -+ * high_mul = MAC (@b, @c); -+ * @a = getRegister (R_ACCLO); -+ * if((getFFlag () == true)) -+ * { -+ * new_acchi = getRegister (R_ACCHI); -+ * setNFlag (new_acchi); -+ * if((OverflowADD (new_acchi, old_acchi, high_mul) == true)) -+ * { -+ * setVFlag (1); -+ * }; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MAC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv old_acchi = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv high_mul = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv new_acchi = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ getRegister(temp_6, R_ACCHI); -+ tcg_gen_mov_tl(old_acchi, temp_6); -+ MAC(temp_7, b, c); -+ tcg_gen_mov_tl(high_mul, temp_7); -+ getRegister(temp_8, R_ACCLO); -+ tcg_gen_mov_tl(a, temp_8); -+ if ((getFFlag () == true)) { -+ getRegister(temp_9, R_ACCHI); -+ tcg_gen_mov_tl(new_acchi, temp_9); -+ setNFlag(new_acchi); -+ TCGLabel *done_2 = gen_new_label(); -+ OverflowADD(temp_10, new_acchi, old_acchi, high_mul); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, temp_10, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2); -+ tcg_gen_movi_tl(temp_11, 1); -+ setVFlag(temp_11); -+ gen_set_label(done_2); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(old_acchi); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(high_mul); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(new_acchi); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+/* -+ * MACU -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getRegister, MACU, getFFlag, CarryADD, setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * old_acchi = getRegister (R_ACCHI); -+ * high_mul = MACU (@b, @c); -+ * @a = getRegister (R_ACCLO); -+ * if((getFFlag () == true)) -+ * { -+ * new_acchi = getRegister (R_ACCHI); -+ * if((CarryADD (new_acchi, old_acchi, high_mul) == true)) -+ * { -+ * setVFlag (1); -+ * }; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MACU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv old_acchi = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv high_mul = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv new_acchi = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ getRegister(temp_6, R_ACCHI); -+ tcg_gen_mov_tl(old_acchi, temp_6); -+ MACU(temp_7, b, c); -+ tcg_gen_mov_tl(high_mul, temp_7); -+ getRegister(temp_8, R_ACCLO); -+ tcg_gen_mov_tl(a, temp_8); -+ if ((getFFlag () == true)) { -+ getRegister(temp_9, R_ACCHI); -+ tcg_gen_mov_tl(new_acchi, temp_9); -+ TCGLabel *done_2 = gen_new_label(); -+ CarryADD(temp_10, new_acchi, old_acchi, high_mul); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, temp_10, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2); -+ tcg_gen_movi_tl(temp_11, 1); -+ setVFlag(temp_11); -+ gen_set_label(done_2); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(old_acchi); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(high_mul); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(new_acchi); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+/* -+ * MACD -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getRegister, MAC, nextReg, getFFlag, setNFlag, -+ * OverflowADD, setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * old_acchi = getRegister (R_ACCHI); -+ * high_mul = MAC (@b, @c); -+ * @a = getRegister (R_ACCLO); -+ * pair = nextReg (a); -+ * pair = getRegister (R_ACCHI); -+ * if((getFFlag () == true)) -+ * { -+ * new_acchi = getRegister (R_ACCHI); -+ * setNFlag (new_acchi); -+ * if((OverflowADD (new_acchi, old_acchi, high_mul) == true)) -+ * { -+ * setVFlag (1); -+ * }; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MACD(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv old_acchi = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv high_mul = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv pair = NULL; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv new_acchi = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ getRegister(temp_6, R_ACCHI); -+ tcg_gen_mov_tl(old_acchi, temp_6); -+ MAC(temp_7, b, c); -+ tcg_gen_mov_tl(high_mul, temp_7); -+ getRegister(temp_8, R_ACCLO); -+ tcg_gen_mov_tl(a, temp_8); -+ pair = nextReg (a); -+ getRegister(temp_9, R_ACCHI); -+ tcg_gen_mov_tl(pair, temp_9); -+ if ((getFFlag () == true)) { -+ getRegister(temp_10, R_ACCHI); -+ tcg_gen_mov_tl(new_acchi, temp_10); -+ setNFlag(new_acchi); -+ TCGLabel *done_2 = gen_new_label(); -+ OverflowADD(temp_11, new_acchi, old_acchi, high_mul); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, temp_11, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2); -+ tcg_gen_movi_tl(temp_12, 1); -+ setVFlag(temp_12); -+ gen_set_label(done_2); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(old_acchi); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(high_mul); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(new_acchi); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_12); -+ -+ return ret; -+} -+ -+ -+/* -+ * MACDU -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag, getRegister, MACU, nextReg, getFFlag, CarryADD, -+ * setVFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * old_acchi = getRegister (R_ACCHI); -+ * high_mul = MACU (@b, @c); -+ * @a = getRegister (R_ACCLO); -+ * pair = nextReg (a); -+ * pair = getRegister (R_ACCHI); -+ * if((getFFlag () == true)) -+ * { -+ * new_acchi = getRegister (R_ACCHI); -+ * if((CarryADD (new_acchi, old_acchi, high_mul) == true)) -+ * { -+ * setVFlag (1); -+ * }; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_MACDU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv old_acchi = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv high_mul = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv pair = NULL; -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv new_acchi = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ getRegister(temp_6, R_ACCHI); -+ tcg_gen_mov_tl(old_acchi, temp_6); -+ MACU(temp_7, b, c); -+ tcg_gen_mov_tl(high_mul, temp_7); -+ getRegister(temp_8, R_ACCLO); -+ tcg_gen_mov_tl(a, temp_8); -+ pair = nextReg (a); -+ getRegister(temp_9, R_ACCHI); -+ tcg_gen_mov_tl(pair, temp_9); -+ if ((getFFlag () == true)) { -+ getRegister(temp_10, R_ACCHI); -+ tcg_gen_mov_tl(new_acchi, temp_10); -+ TCGLabel *done_2 = gen_new_label(); -+ CarryADD(temp_11, new_acchi, old_acchi, high_mul); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, temp_11, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2); -+ tcg_gen_movi_tl(temp_12, 1); -+ setVFlag(temp_12); -+ gen_set_label(done_2); -+ } -+ gen_set_label(done_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(old_acchi); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(high_mul); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(new_acchi); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_12); -+ -+ return ret; -+} -+ -+ -+/* -+ * ABS -+ * Variables: @src, @dest -+ * Functions: Carry, getFFlag, setZFlag, setNFlag, setCFlag, Zero, setVFlag, -+ * getNFlag -+ * --- code --- -+ * { -+ * lsrc = @src; -+ * alu = (0 - lsrc); -+ * if((Carry (lsrc) == 1)) -+ * { -+ * @dest = alu; -+ * } -+ * else -+ * { -+ * @dest = lsrc; -+ * }; -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * setCFlag (Zero ()); -+ * setVFlag (getNFlag ()); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ABS(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv lsrc = tcg_temp_local_new(); -+ TCGv alu = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(lsrc, src); -+ tcg_gen_subfi_tl(alu, 0, lsrc); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ Carry(temp_3, lsrc); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, temp_3, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_mov_tl(dest, alu); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_mov_tl(dest, lsrc); -+ gen_set_label(done_1); -+ if ((getFFlag () == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ tcg_gen_mov_tl(temp_4, Zero()); -+ setCFlag(temp_4); -+ tcg_gen_mov_tl(temp_5, getNFlag()); -+ setVFlag(temp_5); -+ } -+ tcg_temp_free(lsrc); -+ tcg_temp_free(alu); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+/* -+ * SWAP -+ * Variables: @src, @dest -+ * Functions: getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * tmp1 = (@src << 16); -+ * tmp2 = ((@src >> 16) & 65535); -+ * @dest = (tmp1 | tmp2); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SWAP(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ int f_flag; -+ tcg_gen_shli_tl(tmp1, src, 16); -+ tcg_gen_shri_tl(temp_1, src, 16); -+ tcg_gen_andi_tl(tmp2, temp_1, 65535); -+ tcg_gen_or_tl(dest, tmp1, tmp2); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ } -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(tmp2); -+ -+ return ret; -+} -+ -+ -+/* -+ * SWAPE -+ * Variables: @src, @dest -+ * Functions: getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * tmp1 = ((@src << 24) & 4278190080); -+ * tmp2 = ((@src << 8) & 16711680); -+ * tmp3 = ((@src >> 8) & 65280); -+ * tmp4 = ((@src >> 24) & 255); -+ * @dest = (((tmp1 | tmp2) | tmp3) | tmp4); -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SWAPE(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv tmp1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv tmp2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv tmp3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv tmp4 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ int f_flag; -+ tcg_gen_shli_tl(temp_1, src, 24); -+ tcg_gen_andi_tl(tmp1, temp_1, 4278190080); -+ tcg_gen_shli_tl(temp_2, src, 8); -+ tcg_gen_andi_tl(tmp2, temp_2, 16711680); -+ tcg_gen_shri_tl(temp_3, src, 8); -+ tcg_gen_andi_tl(tmp3, temp_3, 65280); -+ tcg_gen_shri_tl(temp_4, src, 24); -+ tcg_gen_andi_tl(tmp4, temp_4, 255); -+ tcg_gen_or_tl(temp_6, tmp1, tmp2); -+ tcg_gen_or_tl(temp_5, temp_6, tmp3); -+ tcg_gen_or_tl(dest, temp_5, tmp4); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ } -+ tcg_temp_free(temp_1); -+ tcg_temp_free(tmp1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(tmp2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(tmp3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(tmp4); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+/* -+ * NOT -+ * Variables: @dest, @src -+ * Functions: getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * @dest = ~@src; -+ * f_flag = getFFlag (); -+ * if((f_flag == true)) -+ * { -+ * setZFlag (@dest); -+ * setNFlag (@dest); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_NOT(DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ int f_flag; -+ tcg_gen_not_tl(dest, src); -+ f_flag = getFFlag (); -+ if ((f_flag == true)) { -+ setZFlag(dest); -+ setNFlag(dest); -+ } -+ return ret; -+} -+ -+ -+/* -+ * BI -+ * Variables: @c -+ * Functions: setPC, getPCL -+ * --- code --- -+ * { -+ * setPC ((nextInsnAddress () + (@c << 2))); -+ * } -+ */ -+ -+int -+arc_gen_BI(DisasCtxt *ctx, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ tcg_gen_shli_tl(temp_4, c, 2); -+ nextInsnAddress(temp_3); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ tcg_gen_add_tl(temp_1, temp_2, temp_4); -+ setPC(temp_1); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+/* -+ * BIH -+ * Variables: @c -+ * Functions: setPC, getPCL -+ * --- code --- -+ * { -+ * setPC ((nextInsnAddress () + (@c << 1))); -+ * } -+ */ -+ -+int -+arc_gen_BIH(DisasCtxt *ctx, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ tcg_gen_shli_tl(temp_4, c, 1); -+ nextInsnAddress(temp_3); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ tcg_gen_add_tl(temp_1, temp_2, temp_4); -+ setPC(temp_1); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+/* -+ * B -+ * Variables: @rd -+ * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, executeDelaySlot, -+ * setPC -+ * --- code --- -+ * { -+ * take_branch = false; -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * take_branch = true; -+ * }; -+ * bta = (getPCL () + @rd); -+ * if((shouldExecuteDelaySlot () == true)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if((cc_flag == true)) -+ * { -+ * setPC (bta); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_B(DisasCtxt *ctx, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_1); -+ getPCL(temp_7); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ tcg_gen_add_tl(bta, temp_6, rd); -+ if ((shouldExecuteDelaySlot () == true)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2); -+ setPC(bta); -+ gen_set_label(done_2); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * B_S -+ * Variables: @rd -+ * Functions: getCCFlag, setPC, getPCL -+ * --- code --- -+ * { -+ * take_branch = false; -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * }; -+ * if((cc_flag == true)) -+ * { -+ * setPC ((getPCL () + @rd)); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_B_S(DisasCtxt *ctx, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ gen_set_label(done_1); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2); -+ getPCL(temp_8); -+ tcg_gen_mov_tl(temp_7, temp_8); -+ tcg_gen_add_tl(temp_6, temp_7, rd); -+ setPC(temp_6); -+ gen_set_label(done_2); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * BBIT0 -+ * Variables: @b, @c, @rd -+ * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, executeDelaySlot, -+ * setPC -+ * --- code --- -+ * { -+ * take_branch = false; -+ * cc_flag = getCCFlag (); -+ * p_b = @b; -+ * p_c = (@c & 31); -+ * tmp = (1 << p_c); -+ * if((cc_flag == true)) -+ * { -+ * if(((p_b && tmp) == 0)) -+ * { -+ * take_branch = true; -+ * }; -+ * }; -+ * bta = (getPCL () + @rd); -+ * if((shouldExecuteDelaySlot () == true)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if((cc_flag == true)) -+ * { -+ * if(((p_b && tmp) == 0)) -+ * { -+ * setPC (bta); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BBIT0(DisasCtxt *ctx, TCGv b, TCGv c, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_11); -+ tcg_gen_mov_tl(cc_flag, temp_11); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_andi_tl(p_c, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, p_c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_and_tl(temp_3, p_b, tmp); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_4, temp_3, 0); -+ tcg_gen_xori_tl(temp_5, temp_4, 1); -+ tcg_gen_andi_tl(temp_5, temp_5, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_5, arc_true, done_2); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ getPCL(temp_13); -+ tcg_gen_mov_tl(temp_12, temp_13); -+ tcg_gen_add_tl(bta, temp_12, rd); -+ if ((shouldExecuteDelaySlot () == true)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_6, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_7, temp_6, 1); -+ tcg_gen_andi_tl(temp_7, temp_7, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_7, arc_true, done_3); -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_and_tl(temp_8, p_b, tmp); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_9, temp_8, 0); -+ tcg_gen_xori_tl(temp_10, temp_9, 1); -+ tcg_gen_andi_tl(temp_10, temp_10, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_10, arc_true, done_4); -+ setPC(bta); -+ gen_set_label(done_4); -+ gen_set_label(done_3); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(tmp); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+/* -+ * BBIT1 -+ * Variables: @b, @c, @rd -+ * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, executeDelaySlot, -+ * setPC -+ * --- code --- -+ * { -+ * take_branch = false; -+ * cc_flag = getCCFlag (); -+ * p_b = @b; -+ * p_c = (@c & 31); -+ * tmp = (1 << p_c); -+ * if((cc_flag == true)) -+ * { -+ * if(((p_b && tmp) != 0)) -+ * { -+ * take_branch = true; -+ * }; -+ * }; -+ * bta = (getPCL () + @rd); -+ * if((shouldExecuteDelaySlot () == true)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if((cc_flag == true)) -+ * { -+ * if(((p_b && tmp) != 0)) -+ * { -+ * setPC (bta); -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BBIT1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_11); -+ tcg_gen_mov_tl(cc_flag, temp_11); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_andi_tl(p_c, c, 31); -+ tcg_gen_shlfi_tl(tmp, 1, p_c); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_and_tl(temp_3, p_b, tmp); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_4, temp_3, 0); -+ tcg_gen_xori_tl(temp_5, temp_4, 1); -+ tcg_gen_andi_tl(temp_5, temp_5, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_5, arc_true, done_2); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_2); -+ gen_set_label(done_1); -+ getPCL(temp_13); -+ tcg_gen_mov_tl(temp_12, temp_13); -+ tcg_gen_add_tl(bta, temp_12, rd); -+ if ((shouldExecuteDelaySlot () == true)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_6, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_7, temp_6, 1); -+ tcg_gen_andi_tl(temp_7, temp_7, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_7, arc_true, done_3); -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_and_tl(temp_8, p_b, tmp); -+ tcg_gen_setcondi_tl(TCG_COND_NE, temp_9, temp_8, 0); -+ tcg_gen_xori_tl(temp_10, temp_9, 1); -+ tcg_gen_andi_tl(temp_10, temp_10, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_10, arc_true, done_4); -+ setPC(bta); -+ gen_set_label(done_4); -+ gen_set_label(done_3); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(tmp); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_10); -+ -+ return ret; -+} -+ -+ -+/* -+ * BL -+ * Variables: @rd -+ * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, setBLINK, -+ * nextInsnAddressAfterDelaySlot, executeDelaySlot, -+ * nextInsnAddress, setPC -+ * --- code --- -+ * { -+ * take_branch = false; -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * take_branch = true; -+ * }; -+ * bta = (getPCL () + @rd); -+ * if((shouldExecuteDelaySlot () == 1)) -+ * { -+ * if(take_branch) -+ * { -+ * setBLINK (nextInsnAddressAfterDelaySlot ()); -+ * }; -+ * executeDelaySlot (bta, take_branch); -+ * } -+ * else -+ * { -+ * if(take_branch) -+ * { -+ * setBLINK (nextInsnAddress ()); -+ * }; -+ * }; -+ * if((cc_flag == true)) -+ * { -+ * setPC (bta); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BL(DisasCtxt *ctx, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_1); -+ getPCL(temp_9); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ tcg_gen_add_tl(bta, temp_8, rd); -+ if ((shouldExecuteDelaySlot () == 1)) { -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_xori_tl(temp_3, take_branch, 1); -+ tcg_gen_andi_tl(temp_3, temp_3, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_3, arc_true, done_2); -+ nextInsnAddressAfterDelaySlot(temp_11); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setBLINK(temp_10); -+ gen_set_label(done_2); -+ executeDelaySlot(bta, take_branch); -+ } else { -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_xori_tl(temp_4, take_branch, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_3); -+ nextInsnAddress(temp_13); -+ tcg_gen_mov_tl(temp_12, temp_13); -+ setBLINK(temp_12); -+ gen_set_label(done_3); -+ } -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_5, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, done_4); -+ setPC(bta); -+ gen_set_label(done_4); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * J -+ * Variables: @src -+ * Functions: getCCFlag, shouldExecuteDelaySlot, executeDelaySlot, setPC -+ * --- code --- -+ * { -+ * take_branch = false; -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * take_branch = true; -+ * }; -+ * bta = @src; -+ * if((shouldExecuteDelaySlot () == 1)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if((cc_flag == true)) -+ * { -+ * setPC (bta); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_J(DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_5); -+ tcg_gen_mov_tl(cc_flag, temp_5); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_1); -+ tcg_gen_mov_tl(bta, src); -+ if ((shouldExecuteDelaySlot () == 1)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_2); -+ setPC(bta); -+ gen_set_label(done_2); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * JL -+ * Variables: @src -+ * Functions: getCCFlag, shouldExecuteDelaySlot, setBLINK, -+ * nextInsnAddressAfterDelaySlot, executeDelaySlot, -+ * nextInsnAddress, setPC -+ * --- code --- -+ * { -+ * take_branch = false; -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * take_branch = true; -+ * }; -+ * bta = @src; -+ * if((shouldExecuteDelaySlot () == 1)) -+ * { -+ * if(take_branch) -+ * { -+ * setBLINK (nextInsnAddressAfterDelaySlot ()); -+ * }; -+ * executeDelaySlot (bta, take_branch); -+ * } -+ * else -+ * { -+ * if(take_branch) -+ * { -+ * setBLINK (nextInsnAddress ()); -+ * }; -+ * }; -+ * if((cc_flag == true)) -+ * { -+ * setPC (bta); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_JL(DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ gen_set_label(done_1); -+ tcg_gen_mov_tl(bta, src); -+ if ((shouldExecuteDelaySlot () == 1)) { -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_xori_tl(temp_3, take_branch, 1); -+ tcg_gen_andi_tl(temp_3, temp_3, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_3, arc_true, done_2); -+ nextInsnAddressAfterDelaySlot(temp_9); -+ tcg_gen_mov_tl(temp_8, temp_9); -+ setBLINK(temp_8); -+ gen_set_label(done_2); -+ executeDelaySlot(bta, take_branch); -+ } else { -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_xori_tl(temp_4, take_branch, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, done_3); -+ nextInsnAddress(temp_11); -+ tcg_gen_mov_tl(temp_10, temp_11); -+ setBLINK(temp_10); -+ gen_set_label(done_3); -+ } -+ TCGLabel *done_4 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_5, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, done_4); -+ setPC(bta); -+ gen_set_label(done_4); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_11); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * SETEQ -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b == p_c)) -+ * { -+ * } -+ * else -+ * { -+ * }; -+ * if((p_b == p_c)) -+ * { -+ * @a = true; -+ * } -+ * else -+ * { -+ * @a = false; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SETEQ(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3); -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * BREQ -+ * Variables: @b, @c, @offset -+ * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+ * --- code --- -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b == p_c)) -+ * { -+ * take_branch = true; -+ * } -+ * else -+ * { -+ * }; -+ * bta = (getPCL () + @offset); -+ * if((shouldExecuteDelaySlot () == 1)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if((p_b == p_c)) -+ * { -+ * setPC (bta); -+ * } -+ * else -+ * { -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BREQ(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(bta, temp_5, offset); -+ if ((shouldExecuteDelaySlot () == 1)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * SETNE -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b != p_c)) -+ * { -+ * } -+ * else -+ * { -+ * }; -+ * if((p_b != p_c)) -+ * { -+ * @a = true; -+ * } -+ * else -+ * { -+ * @a = false; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SETNE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3); -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * BRNE -+ * Variables: @b, @c, @offset -+ * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+ * --- code --- -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b != p_c)) -+ * { -+ * take_branch = true; -+ * } -+ * else -+ * { -+ * }; -+ * bta = (getPCL () + @offset); -+ * if((shouldExecuteDelaySlot () == 1)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if((p_b != p_c)) -+ * { -+ * setPC (bta); -+ * } -+ * else -+ * { -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BRNE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(bta, temp_5, offset); -+ if ((shouldExecuteDelaySlot () == 1)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_NE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * SETLT -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b < p_c)) -+ * { -+ * } -+ * else -+ * { -+ * }; -+ * if((p_b < p_c)) -+ * { -+ * @a = true; -+ * } -+ * else -+ * { -+ * @a = false; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SETLT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3); -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * BRLT -+ * Variables: @b, @c, @offset -+ * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+ * --- code --- -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b < p_c)) -+ * { -+ * take_branch = true; -+ * } -+ * else -+ * { -+ * }; -+ * bta = (getPCL () + @offset); -+ * if((shouldExecuteDelaySlot () == 1)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if((p_b < p_c)) -+ * { -+ * setPC (bta); -+ * } -+ * else -+ * { -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BRLT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(bta, temp_5, offset); -+ if ((shouldExecuteDelaySlot () == 1)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LT, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * SETGE -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b >= p_c)) -+ * { -+ * } -+ * else -+ * { -+ * }; -+ * if((p_b >= p_c)) -+ * { -+ * @a = true; -+ * } -+ * else -+ * { -+ * @a = false; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SETGE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3); -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * BRGE -+ * Variables: @b, @c, @offset -+ * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC -+ * --- code --- -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b >= p_c)) -+ * { -+ * take_branch = true; -+ * } -+ * else -+ * { -+ * }; -+ * bta = (getPCL () + @offset); -+ * if((shouldExecuteDelaySlot () == 1)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if((p_b >= p_c)) -+ * { -+ * setPC (bta); -+ * } -+ * else -+ * { -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BRGE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_1, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_6); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_add_tl(bta, temp_5, offset); -+ if ((shouldExecuteDelaySlot () == 1)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * SETLE -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b <= p_c)) -+ * { -+ * } -+ * else -+ * { -+ * }; -+ * if((p_b <= p_c)) -+ * { -+ * @a = true; -+ * } -+ * else -+ * { -+ * @a = false; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SETLE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LE, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_LE, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3); -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * SETGT -+ * Variables: @b, @c, @a -+ * Functions: getCCFlag -+ * --- code --- -+ * { -+ * cc_flag = getCCFlag (); -+ * if((cc_flag == true)) -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if((p_b > p_c)) -+ * { -+ * } -+ * else -+ * { -+ * }; -+ * if((p_b > p_c)) -+ * { -+ * @a = true; -+ * } -+ * else -+ * { -+ * @a = false; -+ * }; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SETGT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv cc_flag = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getCCFlag(temp_7); -+ tcg_gen_mov_tl(cc_flag, temp_7); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GT, temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_4, temp_3, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_4, arc_true, else_2); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ TCGLabel *else_3 = gen_new_label(); -+ TCGLabel *done_3 = gen_new_label(); -+ tcg_gen_setcond_tl(TCG_COND_GT, temp_5, p_b, p_c); -+ tcg_gen_xori_tl(temp_6, temp_5, 1); -+ tcg_gen_andi_tl(temp_6, temp_6, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_6, arc_true, else_3); -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_3); -+ gen_set_label(else_3); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_3); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(cc_flag); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * BRLO -+ * Variables: @b, @c, @offset -+ * Functions: unsignedLT, getPCL, shouldExecuteDelaySlot, executeDelaySlot, -+ * setPC -+ * --- code --- -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if(unsignedLT (p_b, p_c)) -+ * { -+ * take_branch = true; -+ * } -+ * else -+ * { -+ * }; -+ * bta = (getPCL () + @offset); -+ * if((shouldExecuteDelaySlot () == 1)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if(unsignedLT (p_b, p_c)) -+ * { -+ * setPC (bta); -+ * } -+ * else -+ * { -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BRLO(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedLT(temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_3, 1); -+ tcg_gen_andi_tl(temp_1, temp_1, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_5); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ tcg_gen_add_tl(bta, temp_4, offset); -+ if ((shouldExecuteDelaySlot () == 1)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedLT(temp_6, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_6, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2); -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+/* -+ * SETLO -+ * Variables: @b, @c, @a -+ * Functions: unsignedLT -+ * --- code --- -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if(unsignedLT (p_b, p_c)) -+ * { -+ * } -+ * else -+ * { -+ * }; -+ * if(unsignedLT (p_b, p_c)) -+ * { -+ * @a = true; -+ * } -+ * else -+ * { -+ * @a = false; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SETLO(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedLT(temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_3, 1); -+ tcg_gen_andi_tl(temp_1, temp_1, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedLT(temp_4, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_4, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2); -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+/* -+ * BRHS -+ * Variables: @b, @c, @offset -+ * Functions: unsignedGE, getPCL, shouldExecuteDelaySlot, executeDelaySlot, -+ * setPC -+ * --- code --- -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if(unsignedGE (p_b, p_c)) -+ * { -+ * take_branch = true; -+ * } -+ * else -+ * { -+ * }; -+ * bta = (getPCL () + @offset); -+ * if((shouldExecuteDelaySlot () == 1)) -+ * { -+ * executeDelaySlot (bta, take_branch); -+ * }; -+ * if(unsignedGE (p_b, p_c)) -+ * { -+ * setPC (bta); -+ * } -+ * else -+ * { -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_BRHS(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv bta = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedGE(temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_3, 1); -+ tcg_gen_andi_tl(temp_1, temp_1, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1); -+ tcg_gen_mov_tl(take_branch, arc_true); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ getPCL(temp_5); -+ tcg_gen_mov_tl(temp_4, temp_5); -+ tcg_gen_add_tl(bta, temp_4, offset); -+ if ((shouldExecuteDelaySlot () == 1)) { -+ executeDelaySlot(bta, take_branch); -+ } -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedGE(temp_6, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_6, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2); -+ setPC(bta); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(bta); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+/* -+ * SETHS -+ * Variables: @b, @c, @a -+ * Functions: unsignedGE -+ * --- code --- -+ * { -+ * p_b = @b; -+ * p_c = @c; -+ * take_branch = false; -+ * if(unsignedGE (p_b, p_c)) -+ * { -+ * } -+ * else -+ * { -+ * }; -+ * if(unsignedGE (p_b, p_c)) -+ * { -+ * @a = true; -+ * } -+ * else -+ * { -+ * @a = false; -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_SETHS(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ TCGv p_b = tcg_temp_local_new(); -+ TCGv p_c = tcg_temp_local_new(); -+ TCGv take_branch = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(p_b, b); -+ tcg_gen_mov_tl(p_c, c); -+ tcg_gen_mov_tl(take_branch, arc_false); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ unsignedGE(temp_3, p_b, p_c); -+ tcg_gen_xori_tl(temp_1, temp_3, 1); -+ tcg_gen_andi_tl(temp_1, temp_1, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, else_1); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ gen_set_label(done_1); -+ TCGLabel *else_2 = gen_new_label(); -+ TCGLabel *done_2 = gen_new_label(); -+ unsignedGE(temp_4, p_b, p_c); -+ tcg_gen_xori_tl(temp_2, temp_4, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_2); -+ tcg_gen_mov_tl(a, arc_true); -+ tcg_gen_br(done_2); -+ gen_set_label(else_2); -+ tcg_gen_mov_tl(a, arc_false); -+ gen_set_label(done_2); -+ tcg_temp_free(p_b); -+ tcg_temp_free(p_c); -+ tcg_temp_free(take_branch); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+/* -+ * EX -+ * Variables: @b, @c -+ * Functions: getMemory, setMemory -+ * --- code --- -+ * { -+ * temp = @b; -+ * @b = getMemory (@c, LONG); -+ * setMemory (@c, LONG, temp); -+ * } -+ */ -+ -+int -+arc_gen_EX(DisasCtxt *ctx, TCGv b, TCGv c) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(temp, b); -+ getMemory(temp_1, c, LONG); -+ tcg_gen_mov_tl(b, temp_1); -+ setMemory(c, LONG, temp); -+ tcg_temp_free(temp); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+ -+/* -+ * LLOCK -+ * Variables: @dest, @src -+ * Functions: getMemory, setLF -+ * --- code --- -+ * { -+ * @dest = getMemory (@src, LONG); -+ * setLF (1); -+ * } -+ */ -+ -+int -+arc_gen_LLOCK(DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ getMemory(temp_1, src, LONG); -+ tcg_gen_mov_tl(dest, temp_1); -+ tcg_gen_movi_tl(temp_2, 1); -+ setLF(temp_2); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+/* -+ * LLOCKD -+ * Variables: @dest, @src -+ * Functions: getMemory, nextReg, setLF -+ * --- code --- -+ * { -+ * @dest = getMemory (@src, LONG); -+ * pair = nextReg (dest); -+ * pair = getMemory ((@src + 4), LONG); -+ * setLF (1); -+ * } -+ */ -+ -+int -+arc_gen_LLOCKD(DisasCtxt *ctx, TCGv dest, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv pair = NULL; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getMemory(temp_1, src, LONG); -+ tcg_gen_mov_tl(dest, temp_1); -+ pair = nextReg (dest); -+ tcg_gen_addi_tl(temp_3, src, 4); -+ getMemory(temp_2, temp_3, LONG); -+ tcg_gen_mov_tl(pair, temp_2); -+ tcg_gen_movi_tl(temp_4, 1); -+ setLF(temp_4); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * SCOND -+ * Variables: @src, @dest -+ * Functions: getLF, setMemory, setZFlag, setLF -+ * --- code --- -+ * { -+ * lf = getLF (); -+ * if((lf == 1)) -+ * { -+ * setMemory (@src, LONG, @dest); -+ * }; -+ * setZFlag (!lf); -+ * setLF (0); -+ * } -+ */ -+ -+int -+arc_gen_SCOND(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv lf = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ getLF(temp_3); -+ tcg_gen_mov_tl(lf, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, lf, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ setMemory(src, LONG, dest); -+ gen_set_label(done_1); -+ tcg_gen_xori_tl(temp_4, lf, 1); -+ tcg_gen_andi_tl(temp_4, temp_4, 1); -+ setZFlag(temp_4); -+ tcg_gen_movi_tl(temp_5, 0); -+ setLF(temp_5); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(lf); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ -+ return ret; -+} -+ -+ -+/* -+ * SCONDD -+ * Variables: @src, @dest -+ * Functions: getLF, setMemory, nextReg, setZFlag, setLF -+ * --- code --- -+ * { -+ * lf = getLF (); -+ * if((lf == 1)) -+ * { -+ * setMemory (@src, LONG, @dest); -+ * pair = nextReg (dest); -+ * setMemory ((@src + 4), LONG, pair); -+ * }; -+ * setZFlag (!lf); -+ * setLF (0); -+ * } -+ */ -+ -+int -+arc_gen_SCONDD(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv lf = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv pair = NULL; -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ getLF(temp_3); -+ tcg_gen_mov_tl(lf, temp_3); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, lf, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ setMemory(src, LONG, dest); -+ pair = nextReg (dest); -+ tcg_gen_addi_tl(temp_4, src, 4); -+ setMemory(temp_4, LONG, pair); -+ gen_set_label(done_1); -+ tcg_gen_xori_tl(temp_5, lf, 1); -+ tcg_gen_andi_tl(temp_5, temp_5, 1); -+ setZFlag(temp_5); -+ tcg_gen_movi_tl(temp_6, 0); -+ setLF(temp_6); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(lf); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_6); -+ -+ return ret; -+} -+ -+ -+/* -+ * DMB -+ * Variables: @a -+ * Functions: -+ * --- code --- -+ * { -+ * @a = @a; -+ * } -+ */ -+ -+int -+arc_gen_DMB(DisasCtxt *ctx, TCGv a) -+{ -+ int ret = DISAS_NEXT; -+ -+ return ret; -+} -+ -+ -+/* -+ * LD -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setDebugLD, getMemory, getFlagX, -+ * SignExtend, NoFurtherLoadsPending -+ * --- code --- -+ * { -+ * AA = getAAFlag (); -+ * ZZ = getZZFlag (); -+ * address = 0; -+ * if(((AA == 0) || (AA == 1))) -+ * { -+ * address = (@src1 + @src2); -+ * }; -+ * if((AA == 2)) -+ * { -+ * address = @src1; -+ * }; -+ * if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ * { -+ * address = (@src1 + (@src2 << 2)); -+ * }; -+ * if(((AA == 3) && (ZZ == 2))) -+ * { -+ * address = (@src1 + (@src2 << 1)); -+ * }; -+ * l_src1 = @src1; -+ * l_src2 = @src2; -+ * setDebugLD (1); -+ * new_dest = getMemory (address, ZZ); -+ * if(((AA == 1) || (AA == 2))) -+ * { -+ * @src1 = (l_src1 + l_src2); -+ * }; -+ * if((getFlagX () == 1)) -+ * { -+ * new_dest = SignExtend (new_dest, ZZ); -+ * }; -+ * if(NoFurtherLoadsPending ()) -+ * { -+ * setDebugLD (0); -+ * }; -+ * @dest = new_dest; -+ * } -+ */ -+ -+int -+arc_gen_LD(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv l_src1 = tcg_temp_local_new(); -+ TCGv l_src2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv new_dest = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) { -+ tcg_gen_add_tl(address, src1, src2); -+ } -+ if ((AA == 2)) { -+ tcg_gen_mov_tl(address, src1); -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) { -+ tcg_gen_shli_tl(temp_2, src2, 2); -+ tcg_gen_add_tl(address, src1, temp_2); -+ } -+ if (((AA == 3) && (ZZ == 2))) { -+ tcg_gen_shli_tl(temp_3, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_3); -+ } -+ tcg_gen_mov_tl(l_src1, src1); -+ tcg_gen_mov_tl(l_src2, src2); -+ tcg_gen_movi_tl(temp_4, 1); -+ setDebugLD(temp_4); -+ getMemory(temp_5, address, ZZ); -+ tcg_gen_mov_tl(new_dest, temp_5); -+ if (((AA == 1) || (AA == 2))) { -+ tcg_gen_add_tl(src1, l_src1, l_src2); -+ } -+ if ((getFlagX () == 1)) { -+ new_dest = SignExtend (new_dest, ZZ); -+ } -+ TCGLabel *done_1 = gen_new_label(); -+ NoFurtherLoadsPending(temp_6); -+ tcg_gen_xori_tl(temp_1, temp_6, 1); -+ tcg_gen_andi_tl(temp_1, temp_1, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, done_1); -+ tcg_gen_movi_tl(temp_7, 0); -+ setDebugLD(temp_7); -+ gen_set_label(done_1); -+ tcg_gen_mov_tl(dest, new_dest); -+ tcg_temp_free(address); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(l_src1); -+ tcg_temp_free(l_src2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(new_dest); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_7); -+ -+ return ret; -+} -+ -+ -+/* -+ * LDD -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setDebugLD, getMemory, nextReg, -+ * NoFurtherLoadsPending -+ * --- code --- -+ * { -+ * AA = getAAFlag (); -+ * ZZ = getZZFlag (); -+ * address = 0; -+ * if(((AA == 0) || (AA == 1))) -+ * { -+ * address = (@src1 + @src2); -+ * }; -+ * if((AA == 2)) -+ * { -+ * address = @src1; -+ * }; -+ * if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ * { -+ * address = (@src1 + (@src2 << 2)); -+ * }; -+ * if(((AA == 3) && (ZZ == 2))) -+ * { -+ * address = (@src1 + (@src2 << 1)); -+ * }; -+ * l_src1 = @src1; -+ * l_src2 = @src2; -+ * setDebugLD (1); -+ * new_dest = getMemory (address, LONG); -+ * pair = nextReg (dest); -+ * pair = getMemory ((address + 4), LONG); -+ * if(((AA == 1) || (AA == 2))) -+ * { -+ * @src1 = (l_src1 + l_src2); -+ * }; -+ * if(NoFurtherLoadsPending ()) -+ * { -+ * setDebugLD (0); -+ * }; -+ * @dest = new_dest; -+ * } -+ */ -+ -+int -+arc_gen_LDD(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv l_src1 = tcg_temp_local_new(); -+ TCGv l_src2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv new_dest = tcg_temp_local_new(); -+ TCGv pair = NULL; -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) { -+ tcg_gen_add_tl(address, src1, src2); -+ } -+ if ((AA == 2)) { -+ tcg_gen_mov_tl(address, src1); -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) { -+ tcg_gen_shli_tl(temp_2, src2, 2); -+ tcg_gen_add_tl(address, src1, temp_2); -+ } -+ if (((AA == 3) && (ZZ == 2))) { -+ tcg_gen_shli_tl(temp_3, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_3); -+ } -+ tcg_gen_mov_tl(l_src1, src1); -+ tcg_gen_mov_tl(l_src2, src2); -+ tcg_gen_movi_tl(temp_4, 1); -+ setDebugLD(temp_4); -+ getMemory(temp_5, address, LONG); -+ tcg_gen_mov_tl(new_dest, temp_5); -+ pair = nextReg (dest); -+ tcg_gen_addi_tl(temp_7, address, 4); -+ getMemory(temp_6, temp_7, LONG); -+ tcg_gen_mov_tl(pair, temp_6); -+ if (((AA == 1) || (AA == 2))) { -+ tcg_gen_add_tl(src1, l_src1, l_src2); -+ } -+ TCGLabel *done_1 = gen_new_label(); -+ NoFurtherLoadsPending(temp_8); -+ tcg_gen_xori_tl(temp_1, temp_8, 1); -+ tcg_gen_andi_tl(temp_1, temp_1, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_1, arc_true, done_1); -+ tcg_gen_movi_tl(temp_9, 0); -+ setDebugLD(temp_9); -+ gen_set_label(done_1); -+ tcg_gen_mov_tl(dest, new_dest); -+ tcg_temp_free(address); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(l_src1); -+ tcg_temp_free(l_src2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(new_dest); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_9); -+ -+ return ret; -+} -+ -+ -+/* -+ * ST -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setMemory -+ * --- code --- -+ * { -+ * AA = getAAFlag (); -+ * ZZ = getZZFlag (); -+ * address = 0; -+ * if(((AA == 0) || (AA == 1))) -+ * { -+ * address = (@src1 + @src2); -+ * }; -+ * if((AA == 2)) -+ * { -+ * address = @src1; -+ * }; -+ * if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ * { -+ * address = (@src1 + (@src2 << 2)); -+ * }; -+ * if(((AA == 3) && (ZZ == 2))) -+ * { -+ * address = (@src1 + (@src2 << 1)); -+ * }; -+ * setMemory (address, ZZ, @dest); -+ * if(((AA == 1) || (AA == 2))) -+ * { -+ * @src1 = (@src1 + @src2); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_ST(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) { -+ tcg_gen_add_tl(address, src1, src2); -+ } -+ if ((AA == 2)) { -+ tcg_gen_mov_tl(address, src1); -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) { -+ tcg_gen_shli_tl(temp_1, src2, 2); -+ tcg_gen_add_tl(address, src1, temp_1); -+ } -+ if (((AA == 3) && (ZZ == 2))) { -+ tcg_gen_shli_tl(temp_2, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_2); -+ } -+ setMemory(address, ZZ, dest); -+ if (((AA == 1) || (AA == 2))) { -+ tcg_gen_add_tl(src1, src1, src2); -+ } -+ tcg_temp_free(address); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ -+ return ret; -+} -+ -+ -+/* -+ * STD -+ * Variables: @src1, @src2, @dest -+ * Functions: getAAFlag, getZZFlag, setMemory, -+ * instructionHasRegisterOperandIn, nextReg, getBit -+ * --- code --- -+ * { -+ * AA = getAAFlag (); -+ * ZZ = getZZFlag (); -+ * address = 0; -+ * if(((AA == 0) || (AA == 1))) -+ * { -+ * address = (@src1 + @src2); -+ * }; -+ * if((AA == 2)) -+ * { -+ * address = @src1; -+ * }; -+ * if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) -+ * { -+ * address = (@src1 + (@src2 << 2)); -+ * }; -+ * if(((AA == 3) && (ZZ == 2))) -+ * { -+ * address = (@src1 + (@src2 << 1)); -+ * }; -+ * setMemory (address, LONG, @dest); -+ * if(instructionHasRegisterOperandIn (0)) -+ * { -+ * pair = nextReg (dest); -+ * setMemory ((address + 4), LONG, pair); -+ * } -+ * else -+ * { -+ * tmp = 0; -+ * if(getBit (@dest, 31) == 1) -+ * { -+ * tmp = 4294967295; -+ * } -+ * setMemory ((address + 4), LONG, tmp); -+ * }; -+ * if(((AA == 1) || (AA == 2))) -+ * { -+ * @src1 = (@src1 + @src2); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_STD(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ int AA; -+ int ZZ; -+ TCGv address = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv pair = NULL; -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv tmp = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ AA = getAAFlag (); -+ ZZ = getZZFlag (); -+ tcg_gen_movi_tl(address, 0); -+ if (((AA == 0) || (AA == 1))) { -+ tcg_gen_add_tl(address, src1, src2); -+ } -+ if ((AA == 2)) { -+ tcg_gen_mov_tl(address, src1); -+ } -+ if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) { -+ tcg_gen_shli_tl(temp_3, src2, 2); -+ tcg_gen_add_tl(address, src1, temp_3); -+ } -+ if (((AA == 3) && (ZZ == 2))) { -+ tcg_gen_shli_tl(temp_4, src2, 1); -+ tcg_gen_add_tl(address, src1, temp_4); -+ } -+ setMemory(address, LONG, dest); -+ if (instructionHasRegisterOperandIn (0)) { -+ pair = nextReg (dest); -+ tcg_gen_addi_tl(temp_5, address, 4); -+ setMemory(temp_5, LONG, pair); -+ } else { -+ tcg_gen_movi_tl(tmp, 0); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_movi_tl(temp_7, 31); -+ getBit(temp_6, dest, temp_7); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, temp_6, 1); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1); -+ tcg_gen_movi_tl(tmp, 4294967295); -+ gen_set_label(done_1); -+ tcg_gen_addi_tl(temp_8, address, 4); -+ setMemory(temp_8, LONG, tmp); -+ } -+ if (((AA == 1) || (AA == 2))) { -+ tcg_gen_add_tl(src1, src1, src2); -+ } -+ tcg_temp_free(address); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(tmp); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_8); -+ -+ return ret; -+} -+ -+ -+/* -+ * POP -+ * Variables: @dest -+ * Functions: getMemory, getRegister, setRegister -+ * --- code --- -+ * { -+ * new_dest = getMemory (getRegister (R_SP), LONG); -+ * setRegister (R_SP, (getRegister (R_SP) + 4)); -+ * @dest = new_dest; -+ * } -+ */ -+ -+int -+arc_gen_POP(DisasCtxt *ctx, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv new_dest = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ getRegister(temp_3, R_SP); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ getMemory(temp_1, temp_2, LONG); -+ tcg_gen_mov_tl(new_dest, temp_1); -+ getRegister(temp_6, R_SP); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_addi_tl(temp_4, temp_5, 4); -+ setRegister(R_SP, temp_4); -+ tcg_gen_mov_tl(dest, new_dest); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(new_dest); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * PUSH -+ * Variables: @src -+ * Functions: setMemory, getRegister, setRegister -+ * --- code --- -+ * { -+ * local_src = @src; -+ * setMemory ((getRegister (R_SP) - 4), LONG, local_src); -+ * setRegister (R_SP, (getRegister (R_SP) - 4)); -+ * } -+ */ -+ -+int -+arc_gen_PUSH(DisasCtxt *ctx, TCGv src) -+{ -+ int ret = DISAS_NEXT; -+ TCGv local_src = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(local_src, src); -+ getRegister(temp_3, R_SP); -+ tcg_gen_mov_tl(temp_2, temp_3); -+ tcg_gen_subi_tl(temp_1, temp_2, 4); -+ setMemory(temp_1, LONG, local_src); -+ getRegister(temp_6, R_SP); -+ tcg_gen_mov_tl(temp_5, temp_6); -+ tcg_gen_subi_tl(temp_4, temp_5, 4); -+ setRegister(R_SP, temp_4); -+ tcg_temp_free(local_src); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ -+ return ret; -+} -+ -+ -+/* -+ * LP -+ * Variables: @rd -+ * Functions: getCCFlag, getRegIndex, writeAuxReg, nextInsnAddress, getPCL, -+ * setPC -+ * --- code --- -+ * { -+ * if((getCCFlag () == true)) -+ * { -+ * lp_start_index = getRegIndex (LP_START); -+ * lp_end_index = getRegIndex (LP_END); -+ * writeAuxReg (lp_start_index, nextInsnAddress ()); -+ * writeAuxReg (lp_end_index, (getPCL () + @rd)); -+ * } -+ * else -+ * { -+ * setPC ((getPCL () + @rd)); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_LP(DisasCtxt *ctx, TCGv rd) -+{ -+ int ret = DISAS_NEXT; -+ TCGv temp_3 = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv lp_start_index = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv lp_end_index = tcg_temp_local_new(); -+ TCGv temp_7 = tcg_temp_local_new(); -+ TCGv temp_6 = tcg_temp_local_new(); -+ TCGv temp_10 = tcg_temp_local_new(); -+ TCGv temp_9 = tcg_temp_local_new(); -+ TCGv temp_8 = tcg_temp_local_new(); -+ TCGv temp_13 = tcg_temp_local_new(); -+ TCGv temp_12 = tcg_temp_local_new(); -+ TCGv temp_11 = tcg_temp_local_new(); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ getCCFlag(temp_3); -+ tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, temp_3, arc_true); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ getRegIndex(temp_4, LP_START); -+ tcg_gen_mov_tl(lp_start_index, temp_4); -+ getRegIndex(temp_5, LP_END); -+ tcg_gen_mov_tl(lp_end_index, temp_5); -+ nextInsnAddress(temp_7); -+ tcg_gen_mov_tl(temp_6, temp_7); -+ writeAuxReg(lp_start_index, temp_6); -+ getPCL(temp_10); -+ tcg_gen_mov_tl(temp_9, temp_10); -+ tcg_gen_add_tl(temp_8, temp_9, rd); -+ writeAuxReg(lp_end_index, temp_8); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ getPCL(temp_13); -+ tcg_gen_mov_tl(temp_12, temp_13); -+ tcg_gen_add_tl(temp_11, temp_12, rd); -+ setPC(temp_11); -+ gen_set_label(done_1); -+ tcg_temp_free(temp_3); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(lp_start_index); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(lp_end_index); -+ tcg_temp_free(temp_7); -+ tcg_temp_free(temp_6); -+ tcg_temp_free(temp_10); -+ tcg_temp_free(temp_9); -+ tcg_temp_free(temp_8); -+ tcg_temp_free(temp_13); -+ tcg_temp_free(temp_12); -+ tcg_temp_free(temp_11); -+ -+ return ret; -+} -+ -+ -+/* -+ * NORM -+ * Variables: @src, @dest -+ * Functions: CRLSB, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = @src; -+ * @dest = CRLSB (psrc); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_NORM(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ tcg_gen_mov_tl(psrc, src); -+ tcg_gen_clrsb_tl(dest, psrc); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ -+ return ret; -+} -+ -+ -+/* -+ * NORMH -+ * Variables: @src, @dest -+ * Functions: SignExtend16to32, CRLSB, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = (@src & 65535); -+ * psrc = SignExtend16to32 (psrc); -+ * @dest = CRLSB (psrc); -+ * @dest = (@dest - 16); -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_NORMH(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ tcg_gen_andi_tl(psrc, src, 65535); -+ tcg_gen_ext16s_tl(psrc, psrc); -+ tcg_gen_clrsb_tl(dest, psrc); -+ tcg_gen_subi_tl(dest, dest, 16); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ -+ return ret; -+} -+ -+ -+/* -+ * FLS -+ * Variables: @src, @dest -+ * Functions: CLZ, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = @src; -+ * if((psrc == 0)) -+ * { -+ * @dest = 0; -+ * } -+ * else -+ * { -+ * @dest = 31 - CLZ (psrc, 32); -+ * }; -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_FLS(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_5 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(psrc, src); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, psrc, 0); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_movi_tl(dest, 0); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_movi_tl(temp_5, 32); -+ tcg_gen_clz_tl(temp_4, psrc, temp_5); -+ tcg_gen_mov_tl(temp_3, temp_4); -+ tcg_gen_subfi_tl(dest, 31, temp_3); -+ gen_set_label(done_1); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_5); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ -+ return ret; -+} -+ -+ -+/* -+ * FFS -+ * Variables: @src, @dest -+ * Functions: CTZ, getFFlag, setZFlag, setNFlag -+ * --- code --- -+ * { -+ * psrc = @src; -+ * if((psrc == 0)) -+ * { -+ * @dest = 31; -+ * } -+ * else -+ * { -+ * @dest = CTZ (psrc, 32); -+ * }; -+ * if((getFFlag () == true)) -+ * { -+ * setZFlag (psrc); -+ * setNFlag (psrc); -+ * }; -+ * } -+ */ -+ -+int -+arc_gen_FFS(DisasCtxt *ctx, TCGv src, TCGv dest) -+{ -+ int ret = DISAS_NEXT; -+ TCGv psrc = tcg_temp_local_new(); -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_2 = tcg_temp_local_new(); -+ TCGv temp_4 = tcg_temp_local_new(); -+ TCGv temp_3 = tcg_temp_local_new(); -+ tcg_gen_mov_tl(psrc, src); -+ TCGLabel *else_1 = gen_new_label(); -+ TCGLabel *done_1 = gen_new_label(); -+ tcg_gen_setcondi_tl(TCG_COND_EQ, temp_1, psrc, 0); -+ tcg_gen_xori_tl(temp_2, temp_1, 1); -+ tcg_gen_andi_tl(temp_2, temp_2, 1); -+ tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, else_1); -+ tcg_gen_movi_tl(dest, 31); -+ tcg_gen_br(done_1); -+ gen_set_label(else_1); -+ tcg_gen_movi_tl(temp_4, 32); -+ tcg_gen_ctz_tl(temp_3, psrc, temp_4); -+ tcg_gen_mov_tl(dest, temp_3); -+ gen_set_label(done_1); -+ if ((getFFlag () == true)) { -+ setZFlag(psrc); -+ setNFlag(psrc); -+ } -+ tcg_temp_free(psrc); -+ tcg_temp_free(temp_1); -+ tcg_temp_free(temp_2); -+ tcg_temp_free(temp_4); -+ tcg_temp_free(temp_3); -+ -+ return ret; -+} -+ -+ -diff --git a/target/arc/semfunc.h b/target/arc/semfunc.h -new file mode 100644 -index 0000000000..4b12f97285 ---- /dev/null -+++ b/target/arc/semfunc.h -@@ -0,0 +1,63 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * Contributed by Cupertino Miranda -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef __ARC_SEMFUNC_H__ -+#define __ARC_SEMFUNC_H__ -+ -+#include "translate.h" -+#include "semfunc-helper.h" -+ -+/* TODO (issue #62): these must be removed */ -+#define arc_false (ctx->zero) -+#define arc_true (ctx->one) -+ -+#define LONG 0 -+#define BYTE 1 -+#define WORD 2 -+ -+#define SEMANTIC_FUNCTION_PROTOTYPE_0(NAME) \ -+ int arc_gen_##NAME(DisasCtxt *); -+#define SEMANTIC_FUNCTION_PROTOTYPE_1(NAME) \ -+ int arc_gen_##NAME(DisasCtxt *, TCGv); -+#define SEMANTIC_FUNCTION_PROTOTYPE_2(NAME) \ -+ int arc_gen_##NAME(DisasCtxt *, TCGv, TCGv); -+#define SEMANTIC_FUNCTION_PROTOTYPE_3(NAME) \ -+ int arc_gen_##NAME(DisasCtxt *, TCGv, TCGv, TCGv); -+#define SEMANTIC_FUNCTION_PROTOTYPE_4(NAME) \ -+ int arc_gen_##NAME(DisasCtxt *, TCGv, TCGv, TCGv, TCGv); -+ -+#define MAPPING(MNEMONIC, NAME, NOPS, ...) -+#define CONSTANT(...) -+#define SEMANTIC_FUNCTION(NAME, NOPS) \ -+ SEMANTIC_FUNCTION_PROTOTYPE_##NOPS(NAME) -+ -+#include "target/arc/semfunc_mapping.def" -+#include "target/arc/extra_mapping.def" -+ -+#undef MAPPING -+#undef CONSTANT -+#undef SEMANTIC_FUNCTION_PROTOTYPE_0 -+#undef SEMANTIC_FUNCTION_PROTOTYPE_1 -+#undef SEMANTIC_FUNCTION_PROTOTYPE_2 -+#undef SEMANTIC_FUNCTION_PROTOTYPE_3 -+#undef SEMANTIC_FUNCTION -+ -+#endif /* __ARC_SEMFUNC_H__ */ -diff --git a/target/arc/semfunc_generator/Gemfile b/target/arc/semfunc_generator/Gemfile -new file mode 100644 -index 0000000000..ad695b4d11 ---- /dev/null -+++ b/target/arc/semfunc_generator/Gemfile -@@ -0,0 +1,3 @@ -+source 'http://rubygems.org' -+ -+gem 'racc' -diff --git a/target/arc/semfunc_generator/README b/target/arc/semfunc_generator/README -new file mode 100644 -index 0000000000..965e79b894 ---- /dev/null -+++ b/target/arc/semfunc_generator/README -@@ -0,0 +1,35 @@ -+Helper file for ARC instruction traslation functions. -+ -+The code generator was implemented using ruby language. -+In order to change the content of semfunc.c file these scripts should be used. -+ -+Ruby instalation process: -+ -+The recommended way to obtain a compatible ruby is to install it in a user -+local directory using RVM. -+Instructions to install RVM can be found in https://rvm.io/. -+ -+Using RVM one can install Ruby interpreter executing the following -+steps/commands. -+ -+Install Ruby version 2.6: -+ # rvm install ruby-2.6 -+Set ruby version 2.6 as current in use. -+ # rvm use 2.6 -+Create an isolated environment for the required ruby dependencies. -+ # rvm gemset create arc_generator -+Install bundler tool -+ # gem install bundler -+Bundle tool reads the Gemfile file and installs project dependencies. -+ # cd ${QEMU_SOURCE}/target/arc/semfunc_generator & bundle install -+ -+ -+In order to regenerate the semfunc.c file, please execute the following command. -+ # ruby regenerate_semfunc.rb > ../semfunc.c -+ -+By default the tool reads the semfunc.c file and prints the new content for -+the same file. -+The information of what is generated is presented as comment in the file. -+In order to change the functionality of those functions one should change the -+"pseudo code" in the comments, which is what is used to generate the -+semantically similar TCG code. -diff --git a/target/arc/semfunc_generator/classes/CreateInternalVars.rb b/target/arc/semfunc_generator/classes/CreateInternalVars.rb -new file mode 100644 -index 0000000000..05b2eac7ab ---- /dev/null -+++ b/target/arc/semfunc_generator/classes/CreateInternalVars.rb -@@ -0,0 +1,117 @@ -+class CreateInternalVars -+ private -+ -+ # extend SemanticFunctionASTFactory -+ include Pass -+ include ConstantTables -+ extend TranslatorAST -+ -+ -+ -+ def self.translation_rules -+ ret = {} -+ -+ create_var = Proc.new { |stmt, repl, mappings, to_do| -+ -+ var = stmt.object[:lhs] -+ rhs = stmt.object[:rhs] -+ if(@@vars[var.object[:name]].nil? && var.object[:name] !~ /@.+/) -+ # puts "VAR = #{var.object[:name]}" -+ if(var.hasAttr?(:static)) -+ defVar = SemanticFunctionAST.function("defStaticVariable", stmt.getAttr(:static), stmt.object[:lhs]) -+ else -+ #puts "NAME = #{rhs.object.inspect}" -+ #puts "L = #{LIST_OF_FUNCTIONS.index(rhs.object[:name])}" -+ -+ -+ defVar = SemanticFunctionAST.function("defVariable", stmt.object[:lhs]) -+ #if(rhs.object[:type] == :func && !TEMP_CREATING_FUNCTIONS.index(rhs.object[:name]).nil?) -+ # #puts " IN HERE" -+ # stmt.object[:lhs].setAttr(:reference, true) -+ # defVar = SemanticFunctionAST.function("defReference", stmt.object[:lhs]) -+ #else -+ # defVar = SemanticFunctionAST.function("defVariable", stmt.object[:lhs]) -+ -+ -+ -+ #end -+ end -+ # to_do[:pre_pend].push(defVar) -+ @@vars[var.object[:name]] = defVar -+ # @@vars1[var.object[:name]] = { -+ # defVar: defVar, -+ # stmt: stmt, -+ # block: stmt.find_parent_node_with_type(:block) -+ # } -+ # elsif(@@vars[var.object[:name]].nil? && var.object[:name] =~ /@.+/) -+ end -+ } -+ -+ match = SemanticFunctionAST.new(type: :assign, -+ lhs: SemanticFunctionAST.var("a"), -+ rhs: SemanticFunctionAST.var("_")) -+ ret[match] = create_var -+ -+ match = Proc.new { |ast| -+ ret = { result: false, mappings: {} } -+ ret = { result: true, mappings: {} } if(ast.object[:type] == :if) -+ ret -+ } -+ ret[match] = Proc.new { |stmt_ast, repl, mappings, to_do| -+ generate(stmt_ast.object[:then]) -+ generate(stmt_ast.object[:else]) -+ nil -+ } -+ -+ return ret -+ end -+ -+ -+ public -+ def self.task(ast) -+ @@vars = {} -+ # @@vars1 = {} -+ self.generate(ast) -+ # puts "AST = #{ast.class}" -+ # puts ast.debug -+ -+ # NOTE: Add free variables to end of semfunc. -+ new_stmt_list = SemanticFunctionAST.createStmtListFromArray(@@vars.values) -+ new_stmt_list.append_in_stmt_list(ast) -+ ast = new_stmt_list -+ -+ list = [] -+ @@vars.each_pair do |var_name, func| -+ -+ # puts "VAR: #{var_name}" -+ # puts "STMT: #{@@vars1[var_name][:stmt]}" -+ # puts "BLOCK:\n#{@@vars1[var_name][:block].class}" -+ -+ # list.push(var_name) if func.object[:type] == :func && -+ # (func.object[:name] == "defVariable" || -+ # func.object[:name] == "defReference") -+ -+ if(func.object[:type] == :func) -+ if(func.object[:name] == "defVariable") -+ list.push(SemanticFunctionAST.function("freeVariable", SemanticFunctionAST.var(var_name))) -+ elsif(func.object[:name] == "defReference") -+ list.push(SemanticFunctionAST.function("freeReference", SemanticFunctionAST.var(var_name))) -+ end -+ end -+ end -+ # list = list.map do |var_name| -+ # SemanticFunctionAST.function("freeVariable", SemanticFunctionAST.var(var_name)) -+ # end -+ stmt_list = SemanticFunctionAST.createStmtListFromArray(list) -+ ast.append_in_stmt_list(stmt_list) -+ -+ # @@vars.each_pair do |k, v| -+ # puts "FREE: #{k} : #{v.pp}" -+ # ast.prepend_in_stmt_list(SemanticFunctionAST.function("freeVariable", SemanticFunctionAST.createVar(k))) -+ # end -+ -+ # puts ast.pp -+ -+ return ast -+ end -+end -diff --git a/target/arc/semfunc_generator/classes/DecomposeExpressions.rb b/target/arc/semfunc_generator/classes/DecomposeExpressions.rb -new file mode 100644 -index 0000000000..c353cc90bb ---- /dev/null -+++ b/target/arc/semfunc_generator/classes/DecomposeExpressions.rb -@@ -0,0 +1,45 @@ -+class DecomposeExpressions -+ private -+ -+ extend SemanticFunctionASTFactory -+ include Pass -+ -+ def self.traverse(ast) -+ end -+ -+ def self.expandConditions(ast) -+ object = ast.object -+ case(object[:type]) -+ when :var -+ else -+ return ast -+ end -+ return ret -+ end -+ -+ public -+ def self.task(ast) -+ # reset_counters -+ tmp_vars_for_nodes = {} -+ current_stmt = nil -+ -+ ast.traverse_LR_TB() do |ast, to_do| -+ object = ast.object -+ case(object[:type]) -+ when :func -+ if(object[:name] == "IF") -+ to_do[:pre_pend] += ast.object[:args][0].create_stmts_for_expression() -+ -+ var = to_do[:pre_pend][-1].object[:lhs] -+ -+ ast.object[:args][0] = SemanticFunctionAST.new(type: :bincond, name: "==", lhs: var, rhs: createVar("true")) -+ end -+ else -+ -+ end -+ true -+ end -+ -+ return ast -+ end -+end -diff --git a/target/arc/semfunc_generator/classes/IdentifyQEmuStaticInferedParts.rb b/target/arc/semfunc_generator/classes/IdentifyQEmuStaticInferedParts.rb -new file mode 100644 -index 0000000000..536f9fdd49 ---- /dev/null -+++ b/target/arc/semfunc_generator/classes/IdentifyQEmuStaticInferedParts.rb -@@ -0,0 +1,91 @@ -+class IdentifyQEmuStaticInferedParts -+ private -+ -+ # extend SemanticFunctionASTFactory -+ include Pass -+ extend Translator -+ -+ public -+ -+ rules = {} -+ def self.translation_rules -+ ret = {} -+ functions = { -+ "shouldExecuteDelaySlot" => "bool", -+ "getAAFlag" => "int", -+ "getZZFlag" => "int", -+ "getFFlag" => "int", -+ "getFlagX" => "bool", -+ "nextReg" => "TCGvPtr", -+ "instructionHasRegisterOperandIn" => "bool", -+ "targetHasOption" => "bool", -+ "Ext64" => "TCGv_i64", -+ "SignExt64" => "TCGv_i64", -+ "SignExtend" => "TCGv", -+ "getNFlag" => "TCGv", -+ "Zero" => "TCGv", -+ }.each_pair do |name, type| -+ ret[SemanticFunctionAST.function(name)] = SemanticFunctionAST.var(type) -+ end -+ # ret[SemanticFunctionAST.function("shouldExecuteDelaySlot")] = SemanticFunctionAST.var("bool") -+ # ret[SemanticFunctionAST.function("getAAFlag")] = SemanticFunctionAST.var("int") -+ # ret[SemanticFunctionAST.function("getZZFlag")] = SemanticFunctionAST.var("int") -+ return ret; -+ end -+ def self.task(ast) -+ static_variables = {} -+ -+ ast.traverse_LR_BT do |ast| -+ -+ rules = { -+ } -+ -+ match = self.find_matching_rule(ast) -+ if(match) -+ if(match[:replacement]) -+ ast.setAttr(:static, match[:replacement]) -+ end -+ else -+ case(ast.object[:type]) -+ when :var -+ name = ast.object[:name] -+ ast.setAttr(:static, static_variables[name]) if static_variables[name] != nil && ast.object[:name] !~ /@.+/ -+ when :assign -+ name = ast.object[:lhs].object[:name] -+ if(ast.object[:rhs].hasAttr?(:static)) -+ ast.object[:lhs].setAttr(:static, ast.object[:rhs].getAttr(:static)) -+ ast.setAttr(:static, ast.object[:rhs].getAttr(:static)) -+ static_variables[name] = ast.object[:rhs].getAttr(:static) if static_variables[name].nil? -+ end -+ when :if -+ ast.setAttr(:static, ast.object[:cond].getAttr(:static)) if(ast.object[:cond].hasAttr?(:static)) -+ when :unicond -+ ast.setAttr(:static, ast.object[:rhs].getAttr(:static)) if(ast.object[:rhs].hasAttr?(:static)) -+ when :bincond -+ if(ast.object[:lhs].hasAttr?(:static) && ast.object[:rhs].hasAttr?(:static)) -+ # TODO: Static elements might not have same type. Create a warning -+ ast.setAttr(:static, ast.object[:lhs].getAttr(:static)) -+ -+ elsif(ast.object[:lhs].hasAttr?(:static)) -+ tmp = ast.object[:rhs] -+ if(tmp.object[:type] == :number || tmp.object[:type] == :var ) -+ tmp.setAttr(:static, ast.object[:lhs].getAttr(:static)) -+ ast.setAttr(:static, ast.object[:lhs].getAttr(:static)) -+ end -+ -+ # TODO: Verify if other conditions are possible as well. -+ # For example, verify if bincond for static and non static conjunctions. -+ # Currently no validation is being performed. -+ elsif(ast.object[:rhs].hasAttr?(:static)) -+ tmp = ast.object[:lhs] -+ if(tmp.object[:type] == :number || tmp.object[:type] == :var ) -+ tmp.setAttr(:static, ast.object[:rhs].getAttr(:static)) -+ ast.setAttr(:static, ast.object[:rhs].getAttr(:static)) -+ end -+ end -+ end -+ end -+ false -+ end -+ end -+end -diff --git a/target/arc/semfunc_generator/classes/QEmuCompiler.rb b/target/arc/semfunc_generator/classes/QEmuCompiler.rb -new file mode 100644 -index 0000000000..9860d878bc ---- /dev/null -+++ b/target/arc/semfunc_generator/classes/QEmuCompiler.rb -@@ -0,0 +1,15 @@ -+class QEmuCompiler -+ include Compiler -+ -+ def initialize() -+ @passes = [ -+ IdentifyQEmuStaticInferedParts, -+ SpaghettiCodePass, -+ DecomposeExpressions, -+ UnfoldCode, -+ CreateInternalVars, -+ ] -+ @translator = QEmuTranslator -+ end -+ -+end -diff --git a/target/arc/semfunc_generator/classes/QEmuTranslator.rb b/target/arc/semfunc_generator/classes/QEmuTranslator.rb -new file mode 100644 -index 0000000000..1b739d2614 ---- /dev/null -+++ b/target/arc/semfunc_generator/classes/QEmuTranslator.rb -@@ -0,0 +1,269 @@ -+class QEmuTranslator -+ -+ extend TranslatorFinal -+ include ConstantTables -+ -+ def self.translation_rules -+ ret = { -+ SemanticFunctionAST.function("defLabel", SemanticFunctionAST.var("name")) => -+ "TCGLabel *$name = gen_new_label()", -+ SemanticFunctionAST.function("setLabel", SemanticFunctionAST.var("name")) => -+ "gen_set_label($name)", -+ SemanticFunctionAST.function("createTmpVar", SemanticFunctionAST.var("name")) => -+ "TCGv $name = tcg_temp_new()", -+ SemanticFunctionAST.function("defVariable", SemanticFunctionAST.var("name")) => -+ "TCGv $name = tcg_temp_local_new()", -+ SemanticFunctionAST.function("freeVariable", SemanticFunctionAST.var("name")) => -+ "tcg_temp_free($name)", -+ SemanticFunctionAST.function("freeReference", SemanticFunctionAST.var("name")) => -+ "if($name != NULL) tcg_temp_free($name)", -+ SemanticFunctionAST.function("defReference", SemanticFunctionAST.var("name")) => -+ "TCGv $name = NULL /* REFERENCE */", -+ -+ SemanticFunctionAST.assign( -+ SemanticFunctionAST.var("a"), -+ SemanticFunctionAST.function("HELPER", -+ SemanticFunctionAST.var("helper"), -+ SemanticFunctionAST.var("..."))) => -+ "ARC_HELPER($helper, $a, $varargs_)", -+ SemanticFunctionAST.function("HELPER", -+ SemanticFunctionAST.var("helper"), -+ SemanticFunctionAST.var("...")) => -+ "ARC_HELPER($helper, NULL, $varargs_)", -+ -+ SemanticFunctionAST.function("goto", SemanticFunctionAST.var("label")) => "tcg_gen_br($label)", -+ -+ # SemanticFunctionAST.function("_func", SemanticFunctionAST.var("a")) => "$func($a)", -+ # SemanticFunctionAST.function("_func", SemanticFunctionAST.number("1")) => "$func($1)", -+ -+ SemanticFunctionAST.parse_stmt("a = b") => "tcg_gen_mov_tl($a, $b)", -+ SemanticFunctionAST.parse_stmt("a = 1") => "tcg_gen_movi_tl($a, $1)", -+ } -+ -+ match = SemanticFunctionAST.function("defStaticVariable", SemanticFunctionAST.var("type"), SemanticFunctionAST.var("name")) -+ ret[match] = Proc.new { |stmt_ast, repl, mappings, to_do| -+ ret = "#{mappings["type"]} #{mappings["name"]}" -+ if mappings["type"] == "TCGvPtr" -+ ret = "TCGv #{mappings["name"]} = NULL" -+ end -+ if mappings["type"] == "TCGv" -+ ret = "TCGv #{mappings["name"]} = tcg_temp_local_new()" -+ end -+ ret -+ } -+ -+ match = Proc.new { |ast| -+ ret = { result: false, mappings: {} } -+ ret = { result: true, mappings: {} } if(ast.object[:type] == :if) -+ ret -+ } -+ ret[match] = Proc.new { |stmt_ast, repl, mappings, to_do| -+ tmp = " if (#{stmt_ast.object[:cond].pp}) {\n" -+ tmp += @translator.generate(stmt_ast.object[:then], false) -+ tmp += " }\n" -+ if(stmt_ast.object[:else].valid?) -+ tmp += " else {\n" -+ tmp += @translator.generate(stmt_ast.object[:else], false) -+ tmp += " }\n" -+ end -+ return tmp -+ } -+ -+ # Any other static statement. -+ match = Proc.new { |ast| -+ ret = { result: false, mappings: {} } -+ ret = { result: true, mappings: {} } if(ast.hasAttr?(:static)) -+ ret -+ } -+ ret[match] = Proc.new { |stmt_ast, repl, mappings, to_do| -+ tmp = stmt_ast.pp -+ tmp -+ } -+ -+ -+ { -+ "+": "add", -+ "-": "sub", -+ "*": "mul", -+ "/": "div", -+ "&": "and", -+ "|": "or", -+ "^": "xor", -+ "<<": "shl", -+ ">>": "shr", -+ -+ }.each_pair do |k, v| -+ ret[SemanticFunctionAST.parse_stmt("a = b #{k} c")] = "tcg_gen_#{v}_tl($a, $b, $c)" -+ ret[SemanticFunctionAST.parse_stmt("a = b #{k} 1")] = "tcg_gen_#{v}i_tl($a, $b, $1)" -+ ret[SemanticFunctionAST.parse_stmt("a = 2 #{k} c")] = "tcg_gen_#{v}fi_tl($a, $2, $c)" -+ end -+ -+ -+ options1 = { -+ SemanticFunctionAST.var("b") => "$b", -+ SemanticFunctionAST.number("1") => "$1", -+ SemanticFunctionAST.function("_func1", SemanticFunctionAST.var("...")) => "$func1($varargs_func1)" -+ } -+ options2 = { -+ SemanticFunctionAST.var("c") => "$c", -+ SemanticFunctionAST.number("2") => "$2", -+ SemanticFunctionAST.function("_func2", SemanticFunctionAST.var("...")) => "$func2($varargs_func2)" -+ } -+ -+ -+ # Combinations of options -+ options1.each_pair do |m1, r1| -+ options2.each_pair do |m2, r2| -+ next if m1.object[:type] == :number && m2.object[:type] == :number -+ -+ reverted_immediate = false -+ #Revert immediate value and condition -+ if(m1.object[:type] == :number) -+ tmp = [m1, r1] -+ m1 = m2; r2 = r1 -+ reverted_immediate = true -+ m2 = tmp[0]; r2 = tmp[1] -+ end -+ type = "i" if(m2.object[:type] == :number) -+ -+ { -+ "&&": "and", -+ "||": "or", -+ "^^": "xor", -+ }.each_pair do |k, v| -+ op = v -+ -+ # A = B && C (for example) -+ rhs = SemanticFunctionAST.new(type: :bincond, name: k.to_s, lhs: m1.clone, rhs: m2.clone) -+ match = SemanticFunctionAST.new(type: :assign, lhs: SemanticFunctionAST.var("a"), rhs: rhs) -+ ret[match] = "tcg_gen_#{op}_tl($a, #{r1}, #{r2})" -+ -+ end -+ -+ { -+ "==": "TCG_COND_EQ", -+ "!=": "TCG_COND_NE", -+ "<": "TCG_COND_LT", -+ ">": "TCG_COND_GT", -+ "<=": "TCG_COND_LE", -+ ">=": "TCG_COND_GE", -+ }.each_pair do |k, v| -+ -+ op = v -+ if(reverted_immediate == true) -+ case (k) -+ when "<" -+ op = "TCG_COND_GE" -+ when ">" -+ op = "TCG_COND_LE" -+ when "<=" -+ op = "TCG_COND_GT" -+ when ">=" -+ op = "TCG_COND_LT" -+ end -+ end -+ -+ # A = B == C (for example) -+ rhs = SemanticFunctionAST.new(type: :bincond, name: k.to_s, lhs: m1.clone, rhs: m2.clone) -+ match = SemanticFunctionAST.new(type: :assign, lhs: SemanticFunctionAST.var("a"), rhs: rhs) -+ ret[match] = "tcg_gen_setcond#{type}_tl(#{op}, $a, #{r1}, #{r2})" -+ -+ # IF(cond, label1, label2) # TODO: Label2 is expected to be equal to label1 -+ cond = SemanticFunctionAST.new(type: :bincond, name: k.to_s, lhs: m1.clone, rhs: m2.clone) -+ ifcond_match = SemanticFunctionAST.function("IF", cond, -+ SemanticFunctionAST.var("label1"), -+ SemanticFunctionAST.var("label2") -+ ) -+ ret[ifcond_match] = "tcg_gen_brcond#{type}_tl(#{op}, #{r1}, #{r2}, $label1)" -+ # Proc.new { |stmt_ast, repl, mappings, to_do| -+ # mappings.each_pair do |k, v| -+ # mappings[k] = "arc_#{v}" if (v =~ /^(true|false)$/) -+ # end -+ # } -+ end -+ end -+ end -+ -+ { -+ "!": nil, -+ }.each_pair do |k, v| -+ [:unicond, :uniop].each do |type| -+ rhs = SemanticFunctionAST.new(type: type, name: k.to_s, rhs: SemanticFunctionAST.var("b")) -+ match = SemanticFunctionAST.new(type: :assign, lhs: SemanticFunctionAST.var("a"), rhs: rhs) -+ ret[match] = "tcg_gen_xori_tl($a, $b, 1);\ntcg_gen_andi_tl($a, $a, 1)" -+ -+ rhs1 = SemanticFunctionAST.new(type: type, name: k.to_s, rhs: SemanticFunctionAST.function("_func", SemanticFunctionAST.var("..."))) -+ match1 = SemanticFunctionAST.new(type: :assign, lhs: SemanticFunctionAST.var("a"), rhs: rhs1) -+ ret[match1] = "tcg_gen_xori_tl($a, $func($varargs_func), 1);\ntcg_gen_andi_tl($a, $a, 1)" -+ end -+ end -+ -+ { -+ "~": "not", -+ }.each_pair do |k, v| -+ [:unicond, :uniop].each do |type| -+ rhs = SemanticFunctionAST.new(type: type, name: k.to_s, rhs: SemanticFunctionAST.var("b")) -+ match = SemanticFunctionAST.new(type: :assign, lhs: SemanticFunctionAST.var("a"), rhs: rhs) -+ ret[match] = "tcg_gen_#{v}_tl($a, $b)" -+ -+ rhs1 = SemanticFunctionAST.new(type: type, name: k.to_s, rhs: SemanticFunctionAST.function("_func", SemanticFunctionAST.var("..."))) -+ match1 = SemanticFunctionAST.new(type: :assign, lhs: SemanticFunctionAST.var("a"), rhs: rhs1) -+ ret[match1] = "tcg_gen_#{v}_tl($a, $func($varargs_func))" -+ end -+ end -+ -+ DIRECT_TCG_FUNC_TRANSLATIONS.each_pair do |f1, f2| -+ #ret[SemanticFunctionAST.assign(SemanticFunctionAST.var("a"), SemanticFunctionAST.function(f, SemanticFunctionAST.var("...")))] = "#{f}($a, $varargs_)" -+ match = SemanticFunctionAST.assign(SemanticFunctionAST.var("a"), SemanticFunctionAST.function(f1, SemanticFunctionAST.var("..."))) -+ ret[match] = Proc.new { |stmt_ast, repl, mappings, to_do| -+ ret = "" -+ if(mappings["varargs_"].class == Array) -+ mappings["varargs_"] = mappings["varargs_"].map { |a| a.debug() }.join(", ") -+ end -+ if(mappings["varargs_"] =~ /^$/) -+ ret = "#{f2}($a)" -+ else -+ ret = "#{f2}($a, $varargs_)" -+ end -+ ret -+ } -+ end -+ -+ TEMP_CREATING_FUNCTIONS.each do |f| -+ #ret[SemanticFunctionAST.assign(SemanticFunctionAST.var("a"), SemanticFunctionAST.function(f, SemanticFunctionAST.var("...")))] = "#{f}($a, $varargs_)" -+ match = SemanticFunctionAST.assign(SemanticFunctionAST.var("a"), SemanticFunctionAST.function(f, SemanticFunctionAST.var("..."))) -+ ret[match] = Proc.new { |stmt_ast, repl, mappings, to_do| -+ ret = "" -+ if(mappings["varargs_"].class == Array) -+ mappings["varargs_"] = mappings["varargs_"].map { |a| a.debug() }.join(", ") -+ end -+ if(mappings["varargs_"] =~ /^$/) -+ ret = "#{f}($a)" -+ else -+ ret = "#{f}($a, $varargs_)" -+ end -+ ret -+ } -+ end -+ -+ ret[SemanticFunctionAST.assign(SemanticFunctionAST.var("a"), SemanticFunctionAST.function("_func", SemanticFunctionAST.var("...")))] = -+ "tcg_gen_mov_tl($a, $func($varargs_func))" -+ -+ # "$a = $func($varargs_func)" -+ #ret[SemanticFunctionAST.assign(SemanticFunctionAST.var("a"), SemanticFunctionAST.function("_func", SemanticFunctionAST.var("...")))] = Proc.new { |stmt_ast, repl, mappings, to_do| -+ # lhs = stmt_ast.object[:lhs] -+ # if(lhs.hasAttr?(:reference)) -+ # tmp = stmt_ast.pp -+ # else -+ # tmp = "tcg_gen_mov_tl()" -+ # end -+ # tmp = "tcg_gen_mov_tl()" -+ # tmp -+ #} -+ ret[SemanticFunctionAST.function("_func", SemanticFunctionAST.var("..."))] = "$func($varargs_func)" -+ -+ -+ -+ return ret -+ end -+end -diff --git a/target/arc/semfunc_generator/classes/SemanticFunctionAST.rb b/target/arc/semfunc_generator/classes/SemanticFunctionAST.rb -new file mode 100644 -index 0000000000..b617bb7093 ---- /dev/null -+++ b/target/arc/semfunc_generator/classes/SemanticFunctionAST.rb -@@ -0,0 +1,466 @@ -+class SemanticFunctionAST -+ -+ include Enumerable -+ extend SemanticFunctionASTFactory -+ include SemanticFunctionASTBlockOperators -+ -+ def each(&block) -+ yield self -+ @object.each_pair do |k, e| -+ if(e.class == SemanticFunctionAST) -+ e.each(&block) -+ end -+ end -+ end -+ -+ def find_parent_node_with_type(type, parents = {}) -+ if(self.object[:type] == type) -+ return self -+ else -+ if(parents[self] != nil) -+ parents[self].find_parent_node_with_type(type, parents) -+ else -+ return nil -+ end -+ end -+ end -+ -+ -+ def initialize(params) -+ @object = params -+ end -+ -+ def clone -+ new_elem = SemanticFunctionAST.new({}) -+ self.object.each_pair do |k, v| -+ if(v.class == SemanticFunctionAST) -+ new_elem.object[k] = v.clone -+ elsif v.class == Array -+ new_elem.object[k] = Array.new -+ v.each_with_index do |e, i| -+ new_elem.object[k][i] = e.clone -+ end -+ else -+ begin -+ new_elem.object[k] = v.clone -+ rescue -+ new_elem.object[k] = v -+ end -+ end -+ end -+ return new_elem -+ end -+ -+ def self.error(string) -+ SemanticFunctionAST.new({ type: 'error', message: string }) -+ end -+ -+ def self.nothing -+ SemanticFunctionAST.new({ type: :nothing }) -+ end -+ -+ def self.var(name) -+ SemanticFunctionAST.new({ type: :var, name: name }) -+ end -+ -+ def self.number(number) -+ SemanticFunctionAST.new({ type: :number, number: number }) -+ end -+ -+ def self.assign(lhs, rhs) -+ return SemanticFunctionAST.new({ type: :assign, lhs: lhs, rhs: rhs }) -+ end -+ -+ def self.function(name, *args) -+ return SemanticFunctionAST.new({ type: :func, name: name, args: args || [] }) -+ end -+ -+ def self.bincond(name, lhs, rhs) -+ return SemanticFunctionAST.new({ type: :bincond, name: name, lhs: lhs, rhs: rhs }) -+ end -+ -+ def self.unicond(name, rhs) -+ return SemanticFunctionAST.new({ type: :unicond, name: name, rhs: rhs }) -+ end -+ -+ def self.parse(string) -+ #puts "Parsing: #{string}" -+ SemanticFunctionParser.new.parse(string) -+ end -+ def self.parse_stmt(str) -+ ast = self.parse(str) -+ return ast.object[:list].object[:head] -+ end -+ -+ def getAttr(name) -+ return nil if(object[:attrs] == nil || object[:attrs][name] == nil) -+ return object[:attrs][name] -+ end -+ def hasAttr?(name) -+ getAttr(name) != nil -+ end -+ def setAttr(name, value) -+ object[:attrs] = object[:attrs] || {} -+ object[:attrs][name] = value -+ end -+ -+ def valid? -+ @object[:type] != :nothing -+ end -+ def shouldSeparate? -+ # return true -+ return (@object[:type] != :block) -+ end -+ -+ def object -+ return @object -+ end -+ -+ def traverse(data, &block) -+ cont = yield @object, data -+ if(cont) -+ @object.each_pair do |k,v| -+ v.traverse(data, &block) if v.class == SemanticFunctionAST -+ v.each { |v1| v1.traverse(data, &block) } if v.class == Array -+ end -+ end -+ end -+ -+ def graphviz(filename = "/tmp/tmp.png", g = nil, parent = nil) -+ first_call = false -+ if(g == nil) -+ first_call = true -+ g = GraphViz.new( :G, :type => :digraph ) -+ end -+ -+ label = [] -+ -+ node = g.add_nodes("n#{g.node_count}") -+ @object.each_pair do |k,v| -+ if v.class == SemanticFunctionAST -+ v.graphviz(filename, g, node) -+ elsif v.class == Array -+ v.each do |v1| -+ v1.graphviz(filename, g, node) -+ end -+ else -+ label.push("#{k}: #{v}") -+ end -+ end -+ node[:label] = label.join("\n") -+ g.add_edges(parent, node) if(parent != nil) -+ -+ if(first_call) -+ g.output(:png => filename) -+ end -+ end -+ -+ def traverseASTWithMethodName(data, method_name) -+ cont = self.send(method_name, data) -+ if(cont) -+ @object.each_pair do |k,v| -+ v.traverseASTWithMethodName(data, method_name) if v.class == SemanticFunctionAST -+ end -+ end -+ end -+ -+ def SemanticFunctionAST.IF(cond, ifthen, ifelse) -+ ifthen = ifthen || SemanticFunctionAST.nothing -+ ifelse = ifelse || SemanticFunctionAST.nothing -+ return SemanticFunctionAST.new(type: :function, name: "IF", args: [cond, ifthen, ifelse]) -+ end -+ -+ def constructDefinitions(data = {}) -+ #puts " -- #{ object[:type] } ------------------------ " -+ data.each_pair do |k, v| -+ #puts k -+ #puts (v == nil) ? "NIL" : v.debug -+ end -+ -+ case object[:type] -+ when :assign -+ # #puts " =========> #{self.debug}" -+ new_data = object[:rhs].constructDefinitions(data) -+ data[object[:lhs].object[:name]] = new_data["_"] -+ #puts "================== #{object[:lhs].object[:name]} => #{new_data["_"].inspect}" -+ return data -+ when :var -+ if data[object[:name]] -+ #puts " VAR NAME = #{object[:name]} = #{data[object[:name]].debug}" -+ data["_"] = data[object[:name]].clone -+ else -+ data["_"] = self.clone -+ end -+ return data -+ when :func -+ new_func = self.object.clone -+ -+ new_func[:args].map! do |arg| -+ if(arg.valid?) -+ new_data = arg.constructDefinitions(data.clone) -+ arg = new_data["_"] -+ end -+ arg -+ end -+ data[object[:name]] = SemanticFunctionAST.new(new_func) -+ data["_"] = data[object[:name]] -+ -+ -+ return data -+ when :if -+ # One function IF(COND, THEN, ELSE) -+ cond_data = object[:cond].constructDefinitions(data.clone) -+ then_data = object[:then].constructDefinitions(data.clone) -+ else_data = object[:else].constructDefinitions(data.clone) -+ -+ elems = (then_data.keys + else_data.keys).uniq -+ -+ elems.each do |k| -+ td = then_data[k] || SemanticFunctionAST.nothing -+ ed = else_data[k] || SemanticFunctionAST.nothing -+ -+ if(data[k] != then_data[k] || data[k] != else_data[k] || data[k]) -+ #puts "SAME #{k}" -+ #puts "SAME1 #{then_data[k].debug}" if then_data[k] -+ #puts "SAME2 #{else_data[k].debug}" if else_data[k] -+ data[k] = SemanticFunctionAST.IF(cond_data["_"], td, ed) -+ else -+ #puts "DIFFERENT #{k}" -+ #puts "DIFFERENT1 #{then_data[k].debug}" if then_data[k] -+ #puts "DIFFERENT2 #{else_data[k].debug}" if else_data[k] -+ end -+ end -+ -+ cond_data.each_pair do |k, v| -+ data[k] = v if (data[k] != v) -+ end -+ -+ # puts " == #{SemanticFunctionAST.new(object).debug(false) } ==" -+ # data.each_pair do |k, v| -+ # puts " #{k} : #{v.debug(false)}" -+ # end -+ -+ data["_"] = SemanticFunctionAST.nothing -+ return {} -+ -+ # when :while -+ # cond_data = object[:cond].constructDefinitions(data.clone) -+ # loop_data = object[:loop].constructDefinitions(data.clone) -+ # -+ # loop_dat.each { |k| data[k] = SemanticFunctionAST.new(type: :function, name: "WHILE", args: [cond_data["_"], loop_data[k]]) } -+ # data["_"] = SemanticFunctionAST.nothing -+ else -+ # puts self.inspect -+ # puts self.object[:type] -+ elems = {} #Pre-fill semantic function table -+ -+ object.clone.each_pair do |k, v| -+ if (v.class == SemanticFunctionAST) -+ data.merge!(v.constructDefinitions(data)) -+ elems[k] = data["_"] || SemanticFunctionAST.nothing -+ elsif (v.class == Array) -+ v = v.map do |v1| -+ v1.constructDefinitions(data) -+ data["_"] || SemanticFunctionAST.nothing -+ end -+ elems[k] = v -+ else -+ elems[k] = v -+ end -+ # v.traverseASTWithMethodName(data, :constructDefinitions) if(v.class == SemanticFunctionAST) -+ end -+ data["_"] = SemanticFunctionAST.new(elems) -+ end -+ -+ return data -+ end -+ -+ def debug(pn = false) -+ begin -+ case @object[:type] -+ when /error/ -+ return "--- ERROR: #{@object[:message]} ---" -+ when /block/ -+ return "{ #{@object[:list].debug(pn)} }" -+ when /stmt_list/ -+ return "#{@object[:head].debug(pn)}; #{@object[:tail].debug(pn)}" -+ when /if/ -+ ret = "if(#{@object[:cond].debug(pn)}) #{@object[:then].debug(pn)}" -+ ret += " else #{@object[:else].debug(pn)}" if @object[:else].valid? -+ return ret -+ when /while/ -+ return "while(#{@object[:cond].debug(pn)}) #{@object[:loop].debug(pn)}" -+ when /bincond/ -+ return "#{@object[:lhs].debug(pn)} #{@object[:name]} #{@object[:rhs].debug(pn)}" -+ when /unicond/ -+ return "#{@object[:name]} #{@object[:rhs].debug(pn)}" -+ when /cond/ -+ return @object[:value].debug(pn) -+ when /func/ -+ return "#{@object[:name]} (#{@object[:args].map{|a| a.debug(pn)}.join(", ")})" -+ when /expr_block/ -+ return "(#{@object[:value].debug(pn)})" -+ when /assign/ -+ return "#{@object[:lhs].debug(pn)} = #{@object[:rhs].debug(pn)}" -+ when /binop/ -+ return "#{@object[:lhs].debug(pn)}#{@object[:name]}#{@object[:rhs].debug(pn)}" -+ when /uniop/ -+ return "#{@object[:name]}#{@object[:rhs].debug(pn)}" -+ when /var/ -+ return "#{@object[:name]}" -+ when /number/ -+ return "#{@object[:number]}" -+ when /nothing/ -+ return "NOTHING" if(pn == true) -+ else -+ puts @object.inspect -+ raise "Object type is invalid" -+ end -+ rescue Exception => e -+ return "FAILED TO _DEBUG\n#{self.inspect}\nException at: #{e.backtrace}" -+ end -+ end -+ -+ def debug_encoded() -+ ret = debug(false) -+ begin -+ ret = ret.gsub("+","%2B") -+ ret = ret.gsub(";","%3B") -+ ret = URI.encode(ret) -+ rescue -+ ret = "ERROR" -+ end -+ return ret -+ end -+ -+ def pp(ind = 0) -+ ss = " " * ind -+ -+ begin -+ case @object[:type] -+ when /error/ -+ return "--- ERROR: #{@object[:message]} ---" -+ when /block/ -+ ret = "#{ss}{\n" -+ ret+= "#{@object[:list].pp(ind + 2)}" -+ ret+= "#{ss}}" -+ return ret -+ when /stmt_list/ -+ ret = "" -+ if(object[:head].is_a?(SemanticFunctionAST)) -+ ret += "#{ss}#{@object[:head].pp(ind)}" if @object[:head].valid? -+ ret += ";" if @object[:head].shouldSeparate? -+ else -+ ret += "// INVALID (#{object[:head].inspect})" -+ end -+ ret += " (static)" if @object[:head].hasAttr?(:static) -+ # ret += " (#{@object[:head].object[:attrs].inspect})" -+ ret += "\n" -+ # ret += "#{ss}" if @object[:tail][:type] != "stmt_list" -+ if(object[:tail].is_a?(SemanticFunctionAST)) -+ ret += "#{@object[:tail].pp(ind)}" if @object[:tail].valid? -+ else -+ ret += "// INVALID (#{object[:tail].inspect})" -+ end -+ # puts " --- \n#{ret}" -+ return ret -+ when /if/ -+ ret = "if(#{@object[:cond].pp(ind)})\n" -+ ret += "#{@object[:then].pp(ind+2)}" -+ if @object[:else].valid? -+ ret += "\n" -+ ret += "#{ss}else\n" -+ ret += "#{@object[:else].pp(ind+2)}" -+ end -+ return ret -+ when /while/ -+ return "#{ss}while(#{@object[:cond].pp(ind)})\n#{@object[:loop].pp(ind )}" -+ when /bincond/ -+ ret = "" -+ ret += "(#{@object[:lhs].pp(ind)} #{@object[:name]} #{@object[:rhs].pp(ind)})" -+ return ret -+ when /unicond/ -+ return "#{@object[:name]}#{@object[:rhs].pp(ind)}" -+ when /cond/ -+ return @object[:value].pp(ind) -+ when /func/ -+ ret = "" -+ ret += "#{@object[:name]} (#{@object[:args].map{|a| a.pp(ind)}.join(", ")})" -+ when /expr_block/ -+ return "(#{@object[:value].pp(ind)})" -+ when /assign/ -+ return "#{@object[:lhs].pp(ind)} = #{@object[:rhs].pp(ind)}" -+ when /binop/ -+ return "(#{@object[:lhs].pp(ind)} #{@object[:name]} #{@object[:rhs].pp(ind)})" -+ when /uniop/ -+ return "#{@object[:name]}#{@object[:rhs].pp(ind)}" -+ when /var/ -+ return "#{@object[:name]}" -+ when /number/ -+ return "#{@object[:number]}" -+ when /nothing/ -+ return "" -+ else -+ raise "Object type is invalid" -+ end -+ rescue -+ raise "Failed pretty printing #{stmt.inspect}" -+ end -+ end -+ -+ def ppf(ind = 0) -+ ss = " " * ind -+ -+ case @object[:type] -+ when /error/ -+ return "--- ERROR: #{@object[:message]} ---" -+ when /bincond/ -+ return "#{@object[:lhs].ppf(ind)} #{@object[:name]} #{@object[:rhs].ppf(ind)}" -+ when /unicond/ -+ return "#{@object[:name]} #{@object[:rhs].ppf(ind)}" -+ when /cond/ -+ return @object[:value].ppf(ind) -+ when /func/ -+ return "#{@object[:name]} (\n#{ss} #{@object[:args].map{ |a| a.ppf(ind+2) }.join(",\n#{ss} ")})" -+ when /expr_block/ -+ return "(#{@object[:value].ppf(ind)})" -+ when /assign/ -+ return "#{@object[:lhs].ppf(ind)} = #{@object[:rhs].ppf(ind)}" -+ when /binop/ -+ return "#{@object[:lhs].ppf(ind)}#{@object[:name]}#{@object[:rhs].ppf(ind)}" -+ when /uniop/ -+ return "#{@object[:name]}#{@object[:rhs].ppf(ind)}" -+ when /var/ -+ return "#{@object[:name]}" -+ when /number/ -+ return "#{@object[:number]}" -+ when /nothing/ -+ return "NOTHING" -+ return "" -+ else -+ raise "Object type is invalid" -+ end -+ end -+ -+ -+ def to_c(r={}) -+ case @object[:type] -+ when /binop/ -+ return "( #{@object[:lhs].to_c(r)} #{@object[:name]} #{@object[:rhs].to_c(r)} )" -+ when /uniop/ -+ return "( #{@object[:name]}#{@object[:rhs].to_c(r)} )" -+ when /func/ -+ return "( #{@object[:name]} ( #{@object[:param].map {|p| p.to_c(r) }.join(",") } ) )" -+ when /var/ -+ var_name = @object[:var].to_sym -+ #puts "VAR_NAME= #{var_name}" -+ return r[var_name] if r[var_name] != nil -+ return @object[:var] -+ when /number/ -+ return "#{@object[:number]}" -+ else -+ raise "Object type is invalid #{self}" -+ end -+ -+ end -+end -diff --git a/target/arc/semfunc_generator/classes/SpaghettiCodePass.rb b/target/arc/semfunc_generator/classes/SpaghettiCodePass.rb -new file mode 100644 -index 0000000000..0c9ff3e013 ---- /dev/null -+++ b/target/arc/semfunc_generator/classes/SpaghettiCodePass.rb -@@ -0,0 +1,55 @@ -+class SpaghettiCodePass -+ private -+ -+ # extend SemanticFunctionASTFactory -+ include Pass -+ -+ def self.spaghetify(ast) -+ ret = [] -+ object = ast.object -+ -+ case(object[:type]) -+ when :block -+ ret += spaghetify(object[:list]) -+ when :stmt_list -+ ret += spaghetify(object[:head]) -+ ret += spaghetify(object[:tail]) -+ when :if -+ -+ cond = ast.object[:cond] -+ -+ if(cond.hasAttr?(:static)) -+ ast.object[:then] = SemanticFunctionAST.block(SemanticFunctionAST.createStmtListFromArray(spaghetify(ast.object[:then]))) -+ ast.object[:else] = SemanticFunctionAST.block(SemanticFunctionAST.createStmtListFromArray(spaghetify(ast.object[:else]))) -+ ret.push(ast) -+ else -+ done_label = SemanticFunctionAST.createTmpVar("done") -+ else_label = SemanticFunctionAST.createTmpVar("else") -+ else_label = done_label unless object[:else].valid? -+ -+ ret.push(SemanticFunctionAST.defLabel(else_label)) if object[:else].valid? -+ ret.push(SemanticFunctionAST.defLabel(done_label)) -+ -+ ret.push(SemanticFunctionAST.function("IF", SemanticFunctionAST.notCond(object[:cond].clone), else_label, done_label)) -+ -+ ret += spaghetify(object[:then]) -+ if object[:else].valid? -+ ret.push(SemanticFunctionAST.function("goto", done_label)) -+ ret.push(SemanticFunctionAST.setLabel(else_label)) -+ ret += spaghetify(object[:else]) -+ end -+ ret.push(SemanticFunctionAST.setLabel(done_label)) -+ end -+ else -+ ret.push(ast) if ast.valid? -+ end -+ -+ return ret -+ end -+ -+ public -+ def self.task(ast) -+ # reset_counters -+ return SemanticFunctionAST.createStmtListFromArray(spaghetify(ast)) -+ end -+end -diff --git a/target/arc/semfunc_generator/classes/SpaghettiCodePass1.rb b/target/arc/semfunc_generator/classes/SpaghettiCodePass1.rb -new file mode 100644 -index 0000000000..c38b279c48 ---- /dev/null -+++ b/target/arc/semfunc_generator/classes/SpaghettiCodePass1.rb -@@ -0,0 +1,66 @@ -+class SpaghettiCodePass1 -+ private -+ -+ # extend SemanticFunctionASTFactory -+ include Pass -+ extend Translator -+ -+ def self.translation_rules -+ ret = {} -+ -+ match = SemanticFunctionAST.new(type: :if, name: "_") -+ ret[match] = -+ Proc.new { |stmt, repl, mappings, to_do| -+ -+ binop_lhs = stmt.object[:rhs].object[:lhs] -+ binop_rhs = stmt.object[:rhs].object[:rhs] -+ changed_lhs = false -+ changed_rhs = false -+ -+ if(binop_lhs.object[:type] != :var && binop_lhs.object[:type] != :number) -+ # puts "IN 1 #{binop_lhs.inspect}" -+ var = SemanticFunctionAST.createTmpVar("temp") -+ tmp = [ -+ # SemanticFunctionAST.function("createTmpVar", var), -+ ] -+ to_do[:pre_pend] = tmp + to_do[:pre_pend] -+ assign = SemanticFunctionAST.new(type: :assign, lhs: var, rhs: binop_lhs) -+ self.replace(assign, to_do) -+ binop_lhs = var -+ changed_lhs = true -+ end -+ -+ if(binop_rhs.object[:type] != :var && binop_rhs.object[:type] != :number) -+ # puts "IN 2 #{binop_rhs.inspect}" -+ var = SemanticFunctionAST.createTmpVar("temp") -+ tmp = [ -+ # SemanticFunctionAST.function("createTmpVar", var), -+ assign = SemanticFunctionAST.new(type: :assign, lhs: var, rhs: binop_rhs) -+ ] -+ to_do[:pre_pend] = tmp + to_do[:pre_pend] -+ self.replace(assign, to_do) -+ binop_rhs = var -+ changed_rhs = true -+ end -+ -+ if(changed_lhs == true || changed_rhs == true) -+ new_stmt = stmt.clone -+ new_stmt.object[:rhs].object[:lhs] = binop_lhs -+ new_stmt.object[:rhs].object[:rhs] = binop_rhs -+ to_do[:pre_pend].push(new_stmt) -+ # to_do[:remove] = true -+ stmt.object[:type] = :nothing -+ end -+ } -+ -+ return ret -+ end -+ -+ public -+ def self.task(ast) -+ self.generate(ast) -+ # puts "AST = #{ast.class}" -+ # puts ast.debug -+ return ast -+ end -+end -diff --git a/target/arc/semfunc_generator/classes/UnfoldCode.rb b/target/arc/semfunc_generator/classes/UnfoldCode.rb -new file mode 100644 -index 0000000000..0146407a96 ---- /dev/null -+++ b/target/arc/semfunc_generator/classes/UnfoldCode.rb -@@ -0,0 +1,305 @@ -+class UnfoldCode -+ private -+ -+ # extend SemanticFunctionASTFactory -+ include Pass -+ include ConstantTables -+ extend TranslatorAST -+ -+ def self.translation_rules -+ ret = {} -+ -+ match = Proc.new { |ast| -+ ret = { result: false, mappings: {} } -+ # ret = { result: true, mappings: {} } if(ast.hasAttr?(static)) -+ ret = { result: true, mappings: {} } if(ast.object[:type] == :if) -+ ret -+ } -+ ret[match] = Proc.new { |stmt_ast, repl, mappings, to_do| -+ case(stmt_ast.object[:type]) -+ when :if -+ self.generate(stmt_ast.object[:then]) -+ self.generate(stmt_ast.object[:else]) -+ end -+ } -+ -+ # match = Proc.new { |ast| -+ # ret = { result: false, mappings: {} } -+ # ret = {result: true, mappings: {} } if (ast.object[:type] == :variable && ast.object[:name] =~ /^(true|false)$/ && !ast.hasAttr?(:static)) -+ # } -+ # ret[match] = Proc.new { |ast| -+ # return SemanticFunctionAST.variable("arc_#{ast.object[:name]}") -+ # } -+ -+ match = SemanticFunctionAST.new(type: :assign, -+ lhs: SemanticFunctionAST.var("a"), -+ rhs: SemanticFunctionAST.new(type: :binop, name: "_")) -+ -+ # match = Proc.new { |ast| -+ # ret = { result: false, mappings: {} } -+ # # ret = { result: true, mappings: {} } if(ast.hasAttr?(static)) -+ # if(ast.object[:type] == :assign && -+ # ast.object[:rhs].object[:type] != :func && -+ # ast.object[:rhs].object[:type] != :var && -+ # ast.object[:rhs].object[:type] != :number) -+ # ret = { result: true, mappings: {} } -+ # end -+ # ret -+ # } -+ -+ -+ def self.binOpProcess(stmt, repl, mappings, to_do) -+ # puts "STMT = #{stmt.debug}" -+ -+ binop_lhs = stmt.object[:rhs].object[:lhs] -+ binop_rhs = stmt.object[:rhs].object[:rhs] -+ changed_lhs = false -+ changed_rhs = false -+ -+ if(binop_lhs.object[:type] != :var && binop_lhs.object[:type] != :number) -+ # puts "IN 1 #{binop_lhs.inspect}" -+ var = SemanticFunctionAST.createTmpVar("temp") -+ tmp = [ -+ # SemanticFunctionAST.function("createTmpVar", var), -+ assign = SemanticFunctionAST.new(type: :assign, lhs: var, rhs: binop_lhs) -+ ] -+ to_do[:pre_pend] = tmp + to_do[:pre_pend] -+ self.replace(assign, to_do) -+ binop_lhs = var -+ changed_lhs = true -+ end -+ -+ if(binop_rhs.object[:type] != :var && binop_rhs.object[:type] != :number) -+ # puts "IN 2 #{binop_rhs.inspect}" -+ var = SemanticFunctionAST.createTmpVar("temp") -+ tmp = [ -+ # SemanticFunctionAST.function("createTmpVar", var), -+ assign = SemanticFunctionAST.new(type: :assign, lhs: var, rhs: binop_rhs) -+ ] -+ to_do[:pre_pend] = tmp + to_do[:pre_pend] -+ self.replace(assign, to_do) -+ binop_rhs = var -+ changed_rhs = true -+ end -+ -+ if(changed_lhs == true || changed_rhs == true) -+ new_stmt = stmt.clone -+ new_stmt.object[:rhs].object[:lhs] = binop_lhs -+ new_stmt.object[:rhs].object[:rhs] = binop_rhs -+ to_do[:pre_pend].push(new_stmt) -+ # to_do[:remove] = true -+ stmt.object[:type] = :nothing -+ end -+ end -+ # puts "IAMHERE" -+ ret[match] = -+ Proc.new { |stmt, repl, mappings, to_do| -+ self.binOpProcess(stmt, repl, mappings, to_do) -+ } -+ -+ -+ # Do not convert special IF function -+ func_match = -+ Proc.new { |stmt, repl, mappings, to_do| -+ changed = false -+ new_stmt = nil -+ # puts "BLA => #{stmt.debug}" -+ args = stmt.object[:args] -+ new_args = [] -+ args.each_with_index do |arg, i| -+ new_args[i] = arg -+ -+ if(arg.object[:type] != :var) # && arg.object[:type] != :number) -+ var = SemanticFunctionAST.createTmpVar("temp") -+ # arg_var = self.replace(arg.clone, to_do) -+ # puts arg_var.inspect -+ tmp = [ -+ # SemanticFunctionAST.function("createTmpVar", var), -+ assign = SemanticFunctionAST.new(type: :assign, lhs: var, rhs: arg) -+ ] -+ to_do[:pre_pend] = tmp + to_do[:pre_pend] -+ self.replace(assign, to_do) -+ arg = var -+ new_args[i] = var -+ changed = true -+ end -+ end -+ -+ if(changed) -+ new_stmt = SemanticFunctionAST.function(stmt.object[:name], *new_args) -+ to_do[:pre_pend].push(new_stmt) -+ stmt.object[:type] = :nothing -+ end -+ -+ new_stmt -+ } -+ -+ assign_func_match = -+ Proc.new { |stmt, repl, mappings, to_do| -+ # puts "FUNC_MATCH" -+ lhs = stmt.object[:lhs] -+ rhs = stmt.object[:rhs] -+ -+ if(lhs.object[:type] == :var && -+ rhs.object[:type] == :func && TEMP_CREATING_FUNCTIONS.index(rhs.object[:name])) -+ # puts "INSIDE" -+ var = SemanticFunctionAST.createTmpVar("temp") -+ assign = SemanticFunctionAST.assign(var, rhs) -+ new_stmt = func_match.call(rhs, repl, mappings, to_do) -+ if(new_stmt != nil) -+ assign = SemanticFunctionAST.assign(var, to_do[:pre_pend].pop) -+ end -+ to_do[:pre_pend].push(assign) -+ assign = SemanticFunctionAST.assign(lhs, var) -+ to_do[:pre_pend].push(assign) -+ -+ stmt.object[:type] = :nothing -+ else -+ new_stmt = func_match.call(stmt.object[:rhs], repl, mappings, to_do) -+ if(new_stmt != nil) -+ new_stmt = SemanticFunctionAST.assign(stmt.object[:lhs], to_do[:pre_pend].pop) -+ to_do[:pre_pend].push(new_stmt) -+ stmt.object[:type] = :nothing -+ end -+ end -+ } -+ -+ -+ ret[SemanticFunctionAST.function("IF", SemanticFunctionAST.var("..."))] = nil -+ ret[SemanticFunctionAST.function("_", SemanticFunctionAST.var("..."))] = func_match -+ -+ match = Proc.new { |ast| -+ ret = { result: false, mappings: {} } -+ # ret = { result: true, mappings: {} } if(ast.hasAttr?(static)) -+ if(ast.object[:type] == :assign && ast.object[:rhs].object[:type] == :func) -+ ret = { result: true, mappings: {} } -+ end -+ ret -+ } -+ ret[match] = assign_func_match -+ -+ -+ assign_cond_match = -+ Proc.new { |stmt, repl, mappings, to_do| -+ # puts " BINCOND = #{stmt.pp}" -+ -+ cond = stmt.object[:rhs] -+ changed = false -+ -+ if(cond.object[:type] == :bincond) -+ elems = { lhs: cond.object[:lhs], rhs: cond.object[:rhs] } -+ elsif(cond.object[:type] == :unicond) -+ elems = { rhs: cond.object[:rhs] } -+ end -+ -+ elems.clone.each_pair do |k, v| -+ if(v.object[:type] == :func && TEMP_CREATING_FUNCTIONS.index(v.object[:name])) -+ var = SemanticFunctionAST.createTmpVar("temp") -+ assign = SemanticFunctionAST.assign(var, v) -+ new_stmt = func_match.call(v, repl, mappings, to_do) -+ if(new_stmt != nil) -+ assign = SemanticFunctionAST.assign(var, to_do[:pre_pend].pop) -+ end -+ to_do[:pre_pend].push(assign) -+ elems[k] = var -+ changed = true -+ end -+ end -+ -+ if(changed == true) -+ if(cond.object[:type] == :bincond) -+ new_cond = SemanticFunctionAST.bincond(cond.object[:name], elems[:lhs], elems[:rhs]) -+ new_stmt = SemanticFunctionAST.assign(stmt.object[:lhs], new_cond) -+ elsif(cond.object[:type] == :unicond) -+ new_cond = SemanticFunctionAST.unicond(cond.object[:name], elems[:rhs]) -+ new_stmt = SemanticFunctionAST.assign(stmt.object[:lhs], new_cond) -+ end -+ to_do[:pre_pend].push(new_stmt) -+ stmt.object[:type] = :nothing -+ end -+ } -+ match = Proc.new { |ast| -+ ret = { result: false, mappings: {} } -+ # ret = { result: true, mappings: {} } if(ast.hasAttr?(static)) -+ if(ast.object[:type] == :assign && ast.object[:rhs].object[:type] == :bincond) -+ ret = { result: true, mappings: {} } -+ end -+ if(ast.object[:type] == :assign && ast.object[:rhs].object[:type] == :unicond) -+ ret = { result: true, mappings: {} } -+ end -+ ret -+ } -+ ret[match] = assign_cond_match -+ -+ -+ if_cond_match = -+ Proc.new { |stmt, repl, mappings, to_do| -+ # puts " BINCOND = #{stmt.pp}" -+ cond = stmt.object[:cond] -+ -+ changed = false -+ elems = { cond: bincond.object[:cond] } -+ -+ elems.clone.each_pair do |k, v| -+ if(v.object[:type] == :func && TEMP_CREATING_FUNCTIONS.index(v.object[:name])) -+ var = SemanticFunctionAST.createTmpVar("temp") -+ assign = SemanticFunctionAST.assign(var, v) -+ new_stmt = func_match.call(v, repl, mappings, to_do) -+ if(new_stmt != nil) -+ assign = SemanticFunctionAST.assign(var, to_do[:pre_pend].pop) -+ end -+ to_do[:pre_pend].push(assign) -+ elems[k] = var -+ changed = true -+ end -+ end -+ -+ if(changed == true) -+ new_bincond = SemanticFunctionAST.bincond(bincond.object[:name], elems[:lhs], elems[:rhs]) -+ new_stmt = SemanticFunctionAST.assign(stmt.object[:lhs], new_bincond) -+ to_do[:pre_pend].push(new_stmt) -+ stmt.object[:type] = :nothing -+ end -+ } -+ match = Proc.new { |ast| -+ ret = { result: false, mappings: {} } -+ # ret = { result: true, mappings: {} } if(ast.hasAttr?(static)) -+ if(ast.object[:type] == :if) -+ ret = { result: true, mappings: {} } -+ end -+ ret -+ } -+ ret[match] = if_cond_match -+ -+ -+ # match = SemanticFunctionAST.new(type: :assign, -+ # lhs: SemanticFunctionAST.var("a"), -+ # rhs: SemanticFunctionAST.function("_", SemanticFunctionAST.var("..."))) -+ # ret[match] = Proc.new { |stmt, repl, mappings, to_do| -+ # # puts "BLA -------------" -+ # # puts stmt.debug -+ # # puts " ------------- " -+ # -+ # new_func = func_match.call(stmt.object[:rhs], repl, mappings, to_do) -+ # -+ # if(new_func != nil) -+ # new_stmt = SemanticFunctionAST.assign(stmt.object[:lhs], new_func) -+ # to_do[:pre_pend].push(new_stmt) -+ # stmt.object[:type] = :nothing -+ # end -+ # } -+ -+ return ret -+ -+ end -+ -+ -+ public -+ def self.task(ast) -+ # SemanticFunctionAST.reset_counters() -+ self.generate(ast) -+ # puts "AST = #{ast.class}" -+ # puts ast.debug -+ return ast -+ end -+end -diff --git a/target/arc/semfunc_generator/init.rb b/target/arc/semfunc_generator/init.rb -new file mode 100644 -index 0000000000..20a51a9fbf ---- /dev/null -+++ b/target/arc/semfunc_generator/init.rb -@@ -0,0 +1,15 @@ -+require 'rubygems' -+#require 'graphviz' -+ -+project_root = File.dirname(File.absolute_path(__FILE__)) -+Dir.glob(project_root + "/parsers/*.rb").each do |file| -+ require file -+end -+ -+Dir.glob(project_root + "/modules/*.rb").each do |file| -+ require file -+end -+ -+Dir.glob(project_root + "/classes/*.rb").each do |file| -+ require file -+end -diff --git a/target/arc/semfunc_generator/modules/Compiler.rb b/target/arc/semfunc_generator/modules/Compiler.rb -new file mode 100644 -index 0000000000..c63f55c1ff ---- /dev/null -+++ b/target/arc/semfunc_generator/modules/Compiler.rb -@@ -0,0 +1,42 @@ -+module Compiler -+ def optimize(ast, log = [], debug = false) -+ log.push({ name: 'start', ast: ast }) -+ SemanticFunctionAST.reset_counters() -+ @passes.each do |pass| -+ ast = ast.clone -+ ast = pass.task(ast) -+ log.push({ name: pass.name, ast: ast }) -+ # puts " -- #{pass.name} --" -+ # puts ast.pp -+ end -+ if(debug == true) -+ log.each do |v| -+ puts v[:name] + ":" -+ puts " => #{v[:ast].pp}" -+ end -+ end -+ return ast -+ end -+ -+ def getAST(input) -+ if(input.class == String) -+ input = SemanticFunctionAST.parse(input) -+ elsif(input.class != SemanticFunctionAST) -+ abort() -+ end -+ return input -+ end -+ -+ def generate(input, log = [], debug = false) -+ ast = getAST(input) -+ ast = self.optimize(ast, log, debug) -+ # puts ast.class -+ return @translator.generate(ast, debug) -+ end -+ -+ def compile(code, log = [], debug = false) -+ ast = getAST(code) -+ ast = optimize(ast, log, debug) -+ return ast -+ end -+end -diff --git a/target/arc/semfunc_generator/modules/ConstantTables.rb b/target/arc/semfunc_generator/modules/ConstantTables.rb -new file mode 100644 -index 0000000000..047665c4ab ---- /dev/null -+++ b/target/arc/semfunc_generator/modules/ConstantTables.rb -@@ -0,0 +1,57 @@ -+module ConstantTables -+ -+ TEMP_CREATING_FUNCTIONS = [ -+ "CarryADD", -+ "CarrySUB", -+ "OverflowADD", -+ "OverflowSUB", -+ "getCCFlag", -+ -+ "Carry", -+ -+ "getCFlag", -+ "getMemory", -+ # "SignExtend", -+ # "getNFlag", -+ "getPC", -+ "nextInsnAddressAfterDelaySlot", -+ "nextInsnAddress", -+ "getPCL", -+ "unsignedLT", -+ "unsignedGE", -+ "logicalShiftRight", -+ "logicalShiftLeft", -+ "arithmeticShiftRight", -+ "rotateLeft", -+ "rotateRight", -+ "getBit", -+ "getRegIndex", -+ "readAuxReg", -+ "extractBits", -+ "getRegister", -+ "ARC_HELPER", -+ # "nextReg", -+ "CLZ", -+ "CTZ", -+ -+ "MAC", -+ "MACU", -+ -+ "divSigned", -+ "divUnsigned", -+ "divRemainingSigned", -+ "divRemainingUnsigned", -+ "getLF", -+ "setLF", -+ "hasInterrupts", -+ "NoFurtherLoadsPending" -+ ] -+ -+ -+ DIRECT_TCG_FUNC_TRANSLATIONS = { -+ "CLZ" => "tcg_gen_clz_tl", -+ "CTZ" => "tcg_gen_ctz_tl", -+ "CRLSB" => "tcg_gen_clrsb_tl", -+ "SignExtend16to32" => "tcg_gen_ext16s_tl" -+ } -+end -diff --git a/target/arc/semfunc_generator/modules/Pass.rb b/target/arc/semfunc_generator/modules/Pass.rb -new file mode 100644 -index 0000000000..b4f0382d6a ---- /dev/null -+++ b/target/arc/semfunc_generator/modules/Pass.rb -@@ -0,0 +1,11 @@ -+module Pass -+ -+ def name -+ return self.class -+ end -+ -+ def execute(ast) -+ return task(ast) -+ end -+ -+end -diff --git a/target/arc/semfunc_generator/modules/SemanticFunctionASTBlockOperators.rb b/target/arc/semfunc_generator/modules/SemanticFunctionASTBlockOperators.rb -new file mode 100644 -index 0000000000..774c43dcc8 ---- /dev/null -+++ b/target/arc/semfunc_generator/modules/SemanticFunctionASTBlockOperators.rb -@@ -0,0 +1,145 @@ -+module SemanticFunctionASTBlockOperators -+ -+ def prepend_in_stmt_list(elem, parents = {}) -+ parent = parents[self] -+ # puts self -+ # parent = parents[parent] if parent.object[:type] != :stmt_list && parent.object[:type] != :block -+ -+ if(parent != nil) -+ new_stmt_list = SemanticFunctionAST.new(type: :stmt_list, head: elem, tail: self) -+ parents[new_stmt_list] = parent -+ parents[self] = new_stmt_list -+ -+ parent.object.each_pair do |k, v| -+ parent.object[k] = new_stmt_list if(v == self) -+ end -+ end -+ end -+ -+ def append_in_stmt_list(stmt_list, parents = {}) -+ return stmt_list if self.object[:type] == :nothing -+ raise "self is not of type :stmt_list\n#{self.inspect}" if self.object[:type] != :stmt_list -+ -+ if(self.object[:tail].object[:type] == :nothing) -+ self.object[:tail] = stmt_list -+ else -+ self.object[:tail].append_in_stmt_list(stmt_list, parents) -+ end -+ end -+ -+ def remove_from_stmt_list(parents = {}) -+ elem = self.find_parent_node_with_type(:stmt_list, parents) -+ # puts parents.inspect -+ parent = parents[elem] -+ puts "BLING => #{parent.debug}" -+ parents.each_pair do |k, v| -+ puts "#{k.debug} => #{v.debug}" -+ end -+ puts parent -+ parent.object.each_pair do |k, v| -+ if(v == elem) -+ parent.object[k] = elem.object[:tail] -+ parents[parent.object[k]] = parent -+ end -+ end -+ end -+ -+ def create_stmts_for_expression(tmp_vars = {}) -+ ret = [] -+ self.object.each_pair do |k, v| -+ if(v.class == SemanticFunctionAST && v.valid?) -+ ret += v.create_stmts_for_expression(tmp_vars) -+ end -+ end -+ -+ case(object[:type]) -+ when :binop -+ when :bincond -+ var = SemanticFunctionAST.createTmpVar("temp") -+ rhs = SemanticFunctionAST.new(type: object[:type], name: object[:name], lhs: tmp_vars[object[:lhs]], rhs: tmp_vars[object[:rhs]]) -+ ret += [ -+ # SemanticFunctionAST.function("createTmpVar", var), -+ SemanticFunctionAST.new(type: :assign, lhs: var, rhs: rhs) -+ ] -+ tmp_vars[self] = var -+ when :uniop -+ when :unicond -+ var = SemanticFunctionAST.createTmpVar("temp") -+ rhs = SemanticFunctionAST.new(type: object[:type], name: object[:name], rhs: tmp_vars[object[:rhs]]) -+ ret += [ -+ # SemanticFunctionAST.function("createTmpVar", var), -+ SemanticFunctionAST.new(type: :assign, lhs: var, rhs: rhs) -+ ] -+ tmp_vars[self] = var -+ else -+ tmp_vars[self] = self -+ end -+ return ret -+ end -+ -+ -+ def traverse_LR_TB(to_do = {}, parents = {}, &block) -+ to_do[self] ||= { pre_pend: [], post_pend: [], remove: false } -+ -+ do_childs = yield self, to_do[self] -+ -+ if(do_childs == true) -+ @object.each_pair do |k, e| -+ if(e.class == SemanticFunctionAST) -+ if(self.object[:type] == :stmt_list || self.object[:type] == :block) -+ parents[e] = self -+ else -+ parents[e] = parents[self] -+ end -+ e.traverse_LR_TB(to_do, parents, &block) -+ end -+ end -+ end -+ -+ # If it is back to the head of the recursion -+ if(parents[self] == nil) -+ to_do.each_pair do |elem, to_do| -+ to_do[:pre_pend].each do |elem1| -+ elem.prepend_in_stmt_list(elem1, parents) -+ end -+ -+ if(to_do[:remove] == true) -+ elem.remove_from_stmt_list(parents) -+ end -+ end -+ end -+ return self -+ end -+ -+ def traverse_LR_BT(to_do = {}, parents = {}, &block) -+ to_do[self] ||= { pre_pend: [], post_pend: [], remove: false } -+ -+ @object.each_pair do |k, e| -+ if(e.class == SemanticFunctionAST) -+ if(self.object[:type] == :stmt_list || self.object[:type] == :block) -+ parents[e] = self -+ else -+ parents[e] = parents[self] -+ end -+ e.traverse_LR_BT(to_do, parents, &block) -+ end -+ end -+ -+ yield self, to_do[self] -+ -+ # If it is back to the head of the recursion -+ if(parents[self] == nil) -+ to_do.each_pair do |elem, to_do| -+ to_do[:pre_pend].each do |elem1| -+ elem.prepend_in_stmt_list(elem1, parents) -+ end -+ -+ if(to_do[:remove] == true) -+ elem.remove_from_stmt_list(parents) -+ end -+ end -+ end -+ return self -+ end -+ -+end -diff --git a/target/arc/semfunc_generator/modules/SemanticFunctionASTFactory.rb b/target/arc/semfunc_generator/modules/SemanticFunctionASTFactory.rb -new file mode 100644 -index 0000000000..14df3bcd67 ---- /dev/null -+++ b/target/arc/semfunc_generator/modules/SemanticFunctionASTFactory.rb -@@ -0,0 +1,55 @@ -+module SemanticFunctionASTFactory -+ -+ def createIf(cond, else_label, done_label) -+ return SemanticFunctionAST.function("IF", cond.clone, -+ SemanticFunctionAST.function("goto", else_label), -+ SemanticFunctionAST.function("goto", done_label)) -+ return SemanticFunctionAST.new(type: :func, name: "IF", args: [ -+ cond.clone, -+ SemanticFunctionAST.new(type: :func, name: "goto", args: [ else_label ]), -+ SemanticFunctionAST.new(type: :func, name: "goto", args: [ done_label ]) -+ ]) -+ end -+ -+ def createVar(varname) -+ return SemanticFunctionAST.new(type: :var, name: varname) -+ end -+ -+ def notCond(cond) -+ return SemanticFunctionAST.new(type: :unicond, name: "!", rhs: cond) -+ end -+ -+ def defLabel(label) -+ return SemanticFunctionAST.new(type: :func, name: "defLabel", args: [ label ]) -+ end -+ -+ def setLabel(label) -+ return SemanticFunctionAST.new(type: :func, name: "setLabel", args: [ label ]) -+ end -+ -+ def block(stmt_list) -+ return SemanticFunctionAST.new(type: :block, list: stmt_list) -+ end -+ -+ def reset_counters -+ @__Label_counts = {} -+ end -+ def createTmpVar(label_prefix) -+ @__Label_counts ||= {} -+ @__Label_counts[label_prefix] ||= 0 -+ @__Label_counts[label_prefix] += 1 -+ count = @__Label_counts[label_prefix] -+ ret = createVar("#{label_prefix}_#{count}") -+ # puts ret.inspect -+ return ret -+ end -+ -+ def createStmtListFromArray(array) -+ if(array.count > 0) -+ return SemanticFunctionAST.new(type: :stmt_list, head: array.shift, tail: createStmtListFromArray(array)) -+ else -+ return SemanticFunctionAST.nothing -+ end -+ end -+ -+end -diff --git a/target/arc/semfunc_generator/modules/Translator.rb b/target/arc/semfunc_generator/modules/Translator.rb -new file mode 100644 -index 0000000000..d532e96363 ---- /dev/null -+++ b/target/arc/semfunc_generator/modules/Translator.rb -@@ -0,0 +1,102 @@ -+module Translator -+ -+ # def map_for_variable -+ # if(rule_pattern.object[:name] =~ /^_(.*)$/) -+ # name = $1 -+ # if name == "" -+ # name = "unname#{unname}" -+ # unname += 1 -+ # end -+ # return name -+ # end -+ -+ # Function that verifies is AST is compatible with AST Pattern -+ # The function results a hash of the mapping of variables and number elements -+ # the rule pattern -+ def is_a_match(ast, rule_pattern, unname = 1) -+ ret = { result: true, mappings: {} } -+ -+ if(rule_pattern.class == Proc) -+ -+ return rule_pattern.call(ast) -+ end -+ -+ return ret if(rule_pattern.class == TrueClass) -+ ret[:result] &= false if(rule_pattern == nil || ast == nil) -+ -+ if(ret[:result] == false) -+ return ret -+ end -+ -+ if(rule_pattern.object[:name] =~ /^_(.*)$/) -+ name = $1 -+ if name == "" -+ name = "unname#{unname}" -+ unname += 1 -+ end -+ -+ ret[:result] &= false if(ast.object[:type] != rule_pattern.object[:type]) if(rule_pattern.object[:type] != :var) -+ ret[:mappings][name] = ast.object[:name] -+ else -+ ret[:result] &= false if(ast.object[:type] != rule_pattern.object[:type]) -+ -+ # if(ast.object[:type] == :func) -+ if(ast.object[:name].class == String && ast.object[:type] != :var) -+ # puts "NOW THIS" -+ # puts ast.debug -+ # puts rule_pattern.inspect -+ ret[:result] = false if (ast.object[:name] != rule_pattern.object[:name]) -+ end -+ -+ if(ast.object[:type] == :var) -+ ret[:mappings][rule_pattern.object[:name]] = ast.object[:name] -+ elsif(ast.object[:type] == :number) -+ ret[:mappings][rule_pattern.object[:number]] = ast.object[:number].to_s -+ end -+ end -+ -+ # puts "RULE = #{rule_pattern.debug}" -+ # puts "AST = #{ast.debug}" -+ -+ if(ret[:result] == true) -+ -+ if(rule_pattern.object[:type] == :func) -+ rule_pattern.object[:args].each_with_index do |arg_rule, i| -+ if(arg_rule.object[:type] == :var && arg_rule.object[:name] == "...") -+ # puts ast.inspect -+ ret[:mappings]["varargs_#{name}"] = ast.object[:args][i..-1] || [] -+ elsif(ast.object[:args][i]) -+ tmp = is_a_match(ast.object[:args][i], arg_rule, unname) -+ ret[:result] &= tmp[:result] -+ ret[:mappings].merge!(tmp[:mappings]) -+ else -+ ret[:result] &= false -+ end -+ end -+ end -+ -+ rule_pattern.object.each_pair do |k, v| -+ if(v.class == SemanticFunctionAST) -+ tmp = is_a_match(ast.object[k], v, unname) -+ ret[:result] &= tmp[:result] -+ ret[:mappings].merge!(tmp[:mappings]) -+ end -+ end -+ end -+ -+ return ret -+ end -+ -+ def find_matching_rule(ast) -+ rules = self.translation_rules -+ -+ rules.each_pair do |k, v| -+ tmp = is_a_match(ast, k) -+ if(tmp[:result] == true) -+ return { replacement: v, mappings: tmp[:mappings], index: rules.keys.index(k) } -+ end -+ end -+ return nil -+ end -+ -+end -diff --git a/target/arc/semfunc_generator/modules/TranslatorAST.rb b/target/arc/semfunc_generator/modules/TranslatorAST.rb -new file mode 100644 -index 0000000000..595b9437e6 ---- /dev/null -+++ b/target/arc/semfunc_generator/modules/TranslatorAST.rb -@@ -0,0 +1,80 @@ -+require_relative "Translator.rb" -+ -+module TranslatorAST -+ -+ include Translator -+ -+ def replace_variable(str, variable, replace) -+ return str.gsub(/(\$#{variable})([^$a-zA-Z_])/, "#{replace}\\2") -+ end -+ -+ def replace(stmt_ast, to_do = {}) -+ match = find_matching_rule(stmt_ast) -+ if(match) -+ repl = match[:replacement] -+ mappings = match[:mappings] -+ -+ if(repl.class == SemanticFunctionAST) -+ repl.traverse_LR_TB do |ast| -+ ast.object.each_pair do |ok1, ov1| -+ if(ov1.class == String && ov1 =~ /^\$(.+)$/) -+ repl.object[ok1] = mappings[$1] -+ end -+ end -+ end -+ -+ # mappings.each_pair do |k, v| -+ # if(v.class == String) -+ # # repl = repl.gsub(/(\$#{k})([^a-zA-Z_]+)/, "#{v}\\2") -+ # repl = replace_variable(repl, k, v) -+ # elsif(v.class == Array) -+ # tmp = v.map { |e| e.debug }.join(", ") -+ # repl = replace_variable(repl, k, tmp) -+ # end -+ # end -+ return repl -+ elsif(repl.class == Proc) -+ repl.call(stmt_ast, repl, mappings, to_do) -+ elsif(repl == nil) -+ # Do nothing -+ else -+ return "CAN'T REPLACE ELEMENT OF CLASS #{repl.class}" -+ end -+ else -+ ret = "/*\n" -+ ret += "FAILED TO MATCH { #{stmt_ast.debug }}\n" -+ ret += " -----------------------\n" -+ ret += stmt_ast.inspect -+ ret += "\n -----------------------\n" -+ ret += "*/" -+ return ret -+ end -+ end -+ -+ def generate_for_stmt(ast, to_do) -+ object = ast.object -+ case(object[:type]) -+ when :assign, :func, :if -+ # puts ast.inspect -+ # puts "HERE at #{object[:type]} (#{ast.debug})" -+ tmp = replace(ast, to_do) -+ ret = false -+ when :stmt_list, :block -+ ret = true -+ else -+ # puts "Stopping at #{object[:type]}" -+ ret = false -+ end -+ return ret -+ end -+ -+ def generate(full_ast) -+ result = "" -+ full_ast.traverse_LR_TB do |ast, to_do| -+ ret = generate_for_stmt(ast, to_do) -+ ret -+ end -+ return result -+ end -+ -+end -diff --git a/target/arc/semfunc_generator/modules/TranslatorFinal.rb b/target/arc/semfunc_generator/modules/TranslatorFinal.rb -new file mode 100644 -index 0000000000..9ca9e080b5 ---- /dev/null -+++ b/target/arc/semfunc_generator/modules/TranslatorFinal.rb -@@ -0,0 +1,103 @@ -+require_relative 'Translator.rb' -+ -+module TranslatorFinal -+ -+ include Translator -+ -+ def replace_variable(str, variable, replace) -+ # puts "REPLACE #{str}. #{variable}, #{replace}" -+ replace = replace.gsub("@", "") -+ # = $1 if replace =~ /\@(.+)/ -+ return str.gsub(/(\$#{variable})([^$a-zA-Z_])?/, "#{replace}\\2") -+ end -+ -+ def replace(stmt_ast, to_do = {}, debug = true) -+ ret = "" -+ match = find_matching_rule(stmt_ast) -+ if(match) -+ repl = match[:replacement] -+ mappings = match[:mappings] -+ -+ ret += " // Rule with index #{match[:index]}\n" if debug == true -+ -+ if(repl.class == String) -+ mappings.each_pair do |k, v| -+ -+ if(v.class == String) -+ # puts v.inspect -+ # puts "TRUE" if(v =~ /(true|false)/) -+ -+ # repl = repl.gsub(/(\$#{k})([^a-zA-Z_]+)/, "#{v}\\2") -+ # if(!stmt_ast.hasAttr?(:static)) -+ v = "arc_#{v}" if (v =~ /(true|false)/) -+ # end -+ repl = replace_variable(repl, k, v) -+ -+ elsif(v.class == Array) -+ # puts "STMT_AST = #{stmt_ast.pp}" -+ tmp = v.map { |e| e.debug }.join(", ") -+ repl = replace_variable(repl, k, tmp) -+ end -+ end -+ return ret + repl -+ elsif(repl.class == Proc) -+ repl = repl.call(stmt_ast, repl, mappings, to_do) -+ if(repl.class == String) -+ if(!stmt_ast.hasAttr?(:static)) -+ v = "arc_#{v}" if (v =~ /(true|false)/) -+ end -+ mappings.each_pair { |k, v| repl = replace_variable(repl, k, v) } -+ ret += repl -+ else -+ ret += "RESULT SHOULD BE A String ELEMENT." -+ end -+ return ret -+ else -+ return "CAN'T REPLACE ELEMENT OF CLASS #{repl.class}" -+ end -+ else -+ ret = "/*\n" -+ ret += "FAILED TO MATCH { #{stmt_ast.debug }}\n" -+ ret += " -----------------------\n" -+ ret += stmt_ast.inspect -+ ret += "\n -----------------------\n" -+ ret += "*/" -+ return ret -+ end -+ end -+ -+ def generate(full_ast, debug = false) -+ result = "" -+ full_ast.traverse_LR_TB do |ast, to_do| -+ ret = true -+ object = ast.object -+ case(object[:type]) -+ when :if -+ result += " if (#{object[:cond].pp}) {\n" -+ tmp = generate(object[:then], debug) -+ result += " #{tmp};\n" -+ result += " }\n" -+ if(object[:else].valid?) -+ result += " else {\n" -+ tmp = generate(object[:else], debug) -+ result += " #{tmp};\n" -+ result += " }\n" -+ end -+ ret = false -+ when :assign, :func -+ # puts "HERE at #{object[:type]} (#{ast.debug})" -+ tmp = replace(ast, to_do, debug) -+ result += " #{tmp};\n" -+ ret = false -+ when :stmt_list, :block -+ ret = true -+ else -+ # puts "Stopping at #{object[:type]}" -+ ret = false -+ end -+ ret -+ end -+ return result -+ end -+ -+end -diff --git a/target/arc/semfunc_generator/parsers/SemanticFunctionParser.tab.rb b/target/arc/semfunc_generator/parsers/SemanticFunctionParser.tab.rb -new file mode 100644 -index 0000000000..e0634d5a33 ---- /dev/null -+++ b/target/arc/semfunc_generator/parsers/SemanticFunctionParser.tab.rb -@@ -0,0 +1,553 @@ -+# -+# DO NOT MODIFY!!!! -+# This file is automatically generated by Racc 1.4.12 -+# from Racc grammer file "". -+# -+ -+require 'racc/parser.rb' -+class SemanticFunctionParser < Racc::Parser -+ -+module_eval(<<'...end SemanticFunctionParser.y/module_eval...', 'SemanticFunctionParser.y', 66) -+ -+def parse(str) -+ orig_str = str -+ str = str.gsub(" ", "").gsub("\n", "").gsub("\r", "") -+ @yydebug = true -+ @q = [] -+ until str.empty? -+ append = "" -+ case str -+ when /\A(if)/ -+ @q.push [:IF, $1] -+ when /\A(else)/ -+ @q.push [:ELSE, $1] -+ when /\A(while)/ -+ @q.push [:WHILE, $1] -+ when /\A(&&|\|\||\^\^)/ -+ @q.push [:BINCOND, $1] -+ when /\A(&|\||\^|<<|>>|-|\+|\/|\*)/ -+ @q.push [:BINOP, $1] -+ when /\A(==|!=|<=|<|>=|>)/ -+ @q.push [:BINCOMP, $1] -+ when /\A([\~!])/ -+ @q.push [:UNIOP, $1] -+ when /\A(a)\]/ -+ @q.push [:STRING, $1] -+ append = "]" -+ when /\A(^[a-zA-Z][a-zA-Z0-9]*)\(/ -+ @q.push [:FUNC, $1] -+ append = '(' -+ when /\A(@?[a-zA-Z_][a-zA-Z0-9_]*)/ -+ @q.push [:VAR, $1] -+ when /\A0x([0-9a-fA-F])+/ -+ @q.push [:HEX_NUMBER, $&.to_i(16)] -+ when /\A\d+/ -+ @q.push [:NUMBER, $&.to_i] -+ when /\A.|\n/o -+ s = $& -+ @q.push [s, s] -+# # when /\A([\+\-\*\/]|<<|>>|&)/ -+# # @q.push [:BINOP, $1] -+ end -+ str = append + $' -+ end -+ @q.push [false, '$end'] -+# begin -+ do_parse -+# rescue -+# return SemanticFunctionAST.error("Error parsing: --#{orig_str}--") -+# end -+end -+ -+ def next_token -+ @q.shift -+ end -+ -+ def on_error(t, val, vstack) -+ raise ParseError, sprintf("\nparse error on value %s (%s)", -+ val.inspect, token_to_str(t) || '?') -+ end -+ -+...end SemanticFunctionParser.y/module_eval... -+##### State transition tables begin ### -+ -+racc_action_table = [ -+ 7, 7, 8, 8, 53, 52, 2, 2, 12, 11, -+ 51, 9, 9, 7, 7, 8, 8, 7, 17, 8, -+ 10, 10, 18, 2, 9, 9, 53, 52, 9, 7, -+ 7, 8, 8, 10, 10, 2, 2, 10, 19, 47, -+ 9, 9, 29, 20, 9, 28, 62, 21, 33, 10, -+ 10, 34, 35, 10, 39, 47, 9, 37, 53, 52, -+ 33, 22, 62, 34, 35, 10, 39, 23, 9, 37, -+ 24, 24, 33, 53, 52, 34, 35, 10, 39, 58, -+ 9, 37, 47, 50, 33, 53, 52, 34, 35, 10, -+ 29, 67, 9, 28, 47, 59, 33, 60, 47, 34, -+ 35, 10, 29, 63, 9, 28, 47, 70, 33, 53, -+ nil, 34, 35, 10, 39, nil, 9, 37, nil, nil, -+ 33, nil, nil, 34, 35, 10, 39, nil, 9, 37, -+ nil, nil, 33, nil, nil, 34, 35, 10, 29, nil, -+ 9, 28, nil, nil, 33, nil, nil, 34, 35, 10, -+ 39, nil, 9, 37, nil, nil, 33, nil, nil, 34, -+ 35, 10, 39, nil, 9, 37, nil, nil, 33, nil, -+ nil, 34, 35, 10, 39, nil, 9, 37, nil, nil, -+ 33, nil, nil, 34, 35, 10, 47, -26, -26 ] -+ -+racc_action_check = [ -+ 0, 2, 0, 2, 36, 36, 0, 2, 2, 1, -+ 36, 0, 2, 16, 24, 16, 24, 51, 5, 51, -+ 0, 2, 7, 51, 16, 24, 44, 44, 51, 58, -+ 70, 58, 70, 16, 24, 58, 70, 51, 8, 49, -+ 58, 70, 17, 9, 17, 17, 49, 11, 17, 58, -+ 70, 17, 17, 17, 18, 56, 18, 18, 55, 55, -+ 18, 13, 56, 18, 18, 18, 19, 14, 19, 19, -+ 15, 25, 19, 41, 41, 19, 19, 19, 20, 41, -+ 20, 20, 27, 33, 20, 57, 57, 20, 20, 20, -+ 28, 57, 28, 28, 38, 42, 28, 45, 48, 28, -+ 28, 28, 29, 50, 29, 29, 54, 64, 29, 65, -+ nil, 29, 29, 29, 37, nil, 37, 37, nil, nil, -+ 37, nil, nil, 37, 37, 37, 39, nil, 39, 39, -+ nil, nil, 39, nil, nil, 39, 39, 39, 47, nil, -+ 47, 47, nil, nil, 47, nil, nil, 47, 47, 47, -+ 52, nil, 52, 52, nil, nil, 52, nil, nil, 52, -+ 52, 52, 53, nil, 53, 53, nil, nil, 53, nil, -+ nil, 53, 53, 53, 60, nil, 60, 60, nil, nil, -+ 60, nil, nil, 60, 60, 60, 43, 43, 43 ] -+ -+racc_action_pointer = [ -+ -3, 9, -2, nil, nil, 7, nil, 10, 26, 31, -+ nil, 47, nil, 51, 57, 53, 10, 30, 42, 54, -+ 66, nil, nil, nil, 11, 54, nil, 76, 78, 90, -+ nil, nil, nil, 64, nil, nil, -3, 102, 88, 114, -+ nil, 66, 82, 180, 19, 81, nil, 126, 92, 33, -+ 83, 14, 138, 150, 100, 51, 49, 78, 26, nil, -+ 162, nil, nil, nil, 103, 102, nil, nil, nil, nil, -+ 27, nil ] -+ -+racc_action_default = [ -+ -37, -37, -37, -4, -5, -37, -7, -37, -37, -37, -+ -36, -37, -1, -37, -37, -4, -5, -37, -37, -37, -+ -21, 72, -2, -3, -30, -31, -29, -6, -37, -37, -+ -15, -16, -32, -37, -34, -35, -37, -37, -26, -37, -+ -16, -37, -37, -17, -18, -20, -28, -37, -12, -37, -+ -37, -37, -37, -37, -12, -25, -26, -37, -37, -11, -+ -21, -13, -14, -33, -9, -23, -24, -22, -10, -19, -+ -37, -8 ] -+ -+racc_goto_table = [ -+ 1, 5, 13, 5, 6, 42, 6, 27, nil, nil, -+ 43, 31, 36, 41, nil, nil, 14, 5, 48, 49, -+ 6, 15, 31, 31, nil, 5, 16, 54, 6, 56, -+ 26, 55, nil, 57, nil, 25, nil, 61, 46, nil, -+ 16, 31, nil, 25, nil, 69, 65, 66, 16, nil, -+ 43, 64, 5, nil, nil, 6, nil, nil, 68, 5, -+ nil, nil, 6, nil, nil, nil, nil, nil, nil, nil, -+ 71, 5, nil, nil, 6 ] -+ -+racc_goto_check = [ -+ 1, 5, 1, 5, 7, 9, 7, 6, nil, nil, -+ 6, 10, 8, 8, nil, nil, 2, 5, 6, 6, -+ 7, 3, 10, 10, nil, 5, 4, 6, 7, 6, -+ 2, 8, nil, 8, nil, 3, nil, 6, 2, nil, -+ 4, 10, nil, 3, nil, 9, 8, 8, 4, nil, -+ 6, 1, 5, nil, nil, 7, nil, nil, 1, 5, -+ nil, nil, 7, nil, nil, nil, nil, nil, nil, nil, -+ 1, 5, nil, nil, 7 ] -+ -+racc_goto_pointer = [ -+ nil, 0, 14, 19, 24, 1, -10, 4, -6, -15, -+ -6, nil ] -+ -+racc_goto_default = [ -+ nil, nil, nil, 3, 4, 32, 38, 30, 44, nil, -+ 40, 45 ] -+ -+racc_reduce_table = [ -+ 0, 0, :racc_error, -+ 2, 25, :_reduce_1, -+ 3, 25, :_reduce_2, -+ 3, 25, :_reduce_3, -+ 1, 25, :_reduce_4, -+ 1, 27, :_reduce_5, -+ 3, 27, :_reduce_6, -+ 1, 27, :_reduce_7, -+ 7, 28, :_reduce_8, -+ 5, 28, :_reduce_9, -+ 5, 28, :_reduce_10, -+ 4, 31, :_reduce_11, -+ 2, 30, :_reduce_12, -+ 3, 30, :_reduce_13, -+ 3, 30, :_reduce_14, -+ 1, 30, :_reduce_15, -+ 1, 30, :_reduce_16, -+ 1, 35, :_reduce_17, -+ 1, 35, :_reduce_18, -+ 3, 33, :_reduce_19, -+ 1, 33, :_reduce_20, -+ 0, 33, :_reduce_21, -+ 3, 32, :_reduce_22, -+ 3, 32, :_reduce_23, -+ 3, 32, :_reduce_24, -+ 2, 32, :_reduce_25, -+ 1, 32, :_reduce_26, -+ 1, 32, :_reduce_27, -+ 3, 26, :_reduce_28, -+ 2, 26, :_reduce_29, -+ 2, 26, :_reduce_30, -+ 1, 26, :_reduce_31, -+ 1, 34, :_reduce_32, -+ 3, 34, :_reduce_33, -+ 1, 34, :_reduce_34, -+ 1, 34, :_reduce_35, -+ 1, 29, :_reduce_36 ] -+ -+racc_reduce_n = 37 -+ -+racc_shift_n = 72 -+ -+racc_token_table = { -+ false => 0, -+ :error => 1, -+ :UMINUS => 2, -+ :IF => 3, -+ :ELSE => 4, -+ :WHILE => 5, -+ :BINOP => 6, -+ :BINCOMP => 7, -+ :BINCOND => 8, -+ "{" => 9, -+ "}" => 10, -+ "=" => 11, -+ "(" => 12, -+ ")" => 13, -+ :FUNC => 14, -+ :UNIOP => 15, -+ "," => 16, -+ ";" => 17, -+ "[" => 18, -+ :STRING => 19, -+ "]" => 20, -+ :NUMBER => 21, -+ :HEX_NUMBER => 22, -+ :VAR => 23 } -+ -+racc_nt_base = 24 -+ -+racc_use_result_var = true -+ -+Racc_arg = [ -+ racc_action_table, -+ racc_action_check, -+ racc_action_default, -+ racc_action_pointer, -+ racc_goto_table, -+ racc_goto_check, -+ racc_goto_default, -+ racc_goto_pointer, -+ racc_nt_base, -+ racc_reduce_table, -+ racc_token_table, -+ racc_shift_n, -+ racc_reduce_n, -+ racc_use_result_var ] -+ -+Racc_token_to_s_table = [ -+ "$end", -+ "error", -+ "UMINUS", -+ "IF", -+ "ELSE", -+ "WHILE", -+ "BINOP", -+ "BINCOMP", -+ "BINCOND", -+ "\"{\"", -+ "\"}\"", -+ "\"=\"", -+ "\"(\"", -+ "\")\"", -+ "FUNC", -+ "UNIOP", -+ "\",\"", -+ "\";\"", -+ "\"[\"", -+ "STRING", -+ "\"]\"", -+ "NUMBER", -+ "HEX_NUMBER", -+ "VAR", -+ "$start", -+ "block", -+ "stmt_list", -+ "stmt", -+ "block_stmt", -+ "var", -+ "expr", -+ "func", -+ "cond", -+ "func_args", -+ "leaf", -+ "arg" ] -+ -+Racc_debug_parser = false -+ -+##### State transition tables end ##### -+ -+# reduce 0 omitted -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 12) -+ def _reduce_1(val, _values, result) -+ return SemanticFunctionAST.new({ type: :block, list: SemanticFunctionAST.nothing }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 13) -+ def _reduce_2(val, _values, result) -+ return val[1] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 14) -+ def _reduce_3(val, _values, result) -+ return SemanticFunctionAST.new({ type: :block, list: val[1] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 15) -+ def _reduce_4(val, _values, result) -+ return SemanticFunctionAST.new({ type: :block, list: SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: SemanticFunctionAST.nothing }) }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 17) -+ def _reduce_5(val, _values, result) -+ return val[0] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 18) -+ def _reduce_6(val, _values, result) -+ return SemanticFunctionAST.new({ type: :assign, lhs: val[0], rhs: val[2] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 19) -+ def _reduce_7(val, _values, result) -+ return val[0] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 21) -+ def _reduce_8(val, _values, result) -+ return SemanticFunctionAST.new({ type: :if, cond: val[2], then: val[4], else: val[6] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 22) -+ def _reduce_9(val, _values, result) -+ return SemanticFunctionAST.new({ type: :if, cond: val[2], then: val[4], else: SemanticFunctionAST.nothing }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 23) -+ def _reduce_10(val, _values, result) -+ return SemanticFunctionAST.new({ type: :while, cond: val[2], loop: val[4] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 25) -+ def _reduce_11(val, _values, result) -+ return SemanticFunctionAST.new({ type: :func, name: val[0], args: val[2] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 27) -+ def _reduce_12(val, _values, result) -+ return SemanticFunctionAST.new({ type: :uniop, name: val[0], rhs: val[1] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 28) -+ def _reduce_13(val, _values, result) -+ return SemanticFunctionAST.new({ type: :binop, name: val[1], lhs: val[0], rhs: val[2] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 29) -+ def _reduce_14(val, _values, result) -+ return val[1] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 30) -+ def _reduce_15(val, _values, result) -+ return val[0] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 31) -+ def _reduce_16(val, _values, result) -+ return val[0] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 33) -+ def _reduce_17(val, _values, result) -+ val[0] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 34) -+ def _reduce_18(val, _values, result) -+ val[0] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 37) -+ def _reduce_19(val, _values, result) -+ return [val[0]] + val[2] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 38) -+ def _reduce_20(val, _values, result) -+ return [val[0]] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 39) -+ def _reduce_21(val, _values, result) -+ return [] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 41) -+ def _reduce_22(val, _values, result) -+ return val[1] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 42) -+ def _reduce_23(val, _values, result) -+ return SemanticFunctionAST.new({ type: :bincond, name: val[1], lhs: val[0], rhs: val[2] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 43) -+ def _reduce_24(val, _values, result) -+ return SemanticFunctionAST.new({ type: :bincond, name: val[1], lhs: val[0], rhs: val[2] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 44) -+ def _reduce_25(val, _values, result) -+ return SemanticFunctionAST.new({ type: :unicond, name: val[0], rhs: val[1] }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 45) -+ def _reduce_26(val, _values, result) -+ val[0] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 46) -+ def _reduce_27(val, _values, result) -+ val[0] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 50) -+ def _reduce_28(val, _values, result) -+ return SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: val[2]}) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 51) -+ def _reduce_29(val, _values, result) -+ return SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: val[1]}) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 52) -+ def _reduce_30(val, _values, result) -+ return SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: SemanticFunctionAST.nothing }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 53) -+ def _reduce_31(val, _values, result) -+ return SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: SemanticFunctionAST.nothing }) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 55) -+ def _reduce_32(val, _values, result) -+ return val[0] -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 56) -+ def _reduce_33(val, _values, result) -+ return SemanticFunctionAST.new(type: :string, value: val[0]) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 57) -+ def _reduce_34(val, _values, result) -+ return SemanticFunctionAST.new(type: :number, number: val[0]) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 58) -+ def _reduce_35(val, _values, result) -+ return SemanticFunctionAST.new(type: :number, number: val[0]) -+ result -+ end -+.,., -+ -+module_eval(<<'.,.,', 'SemanticFunctionParser.y', 60) -+ def _reduce_36(val, _values, result) -+ return SemanticFunctionAST.new(type: :var, name: val[0]) -+ result -+ end -+.,., -+ -+def _reduce_none(val, _values, result) -+ val[0] -+end -+ -+end # class SemanticFunctionParser -diff --git a/target/arc/semfunc_generator/parsers/SemanticFunctionParser.y b/target/arc/semfunc_generator/parsers/SemanticFunctionParser.y -new file mode 100644 -index 0000000000..31cec1734c ---- /dev/null -+++ b/target/arc/semfunc_generator/parsers/SemanticFunctionParser.y -@@ -0,0 +1,126 @@ -+class SemanticFunctionParser -+ -+prechigh -+ nonassoc UMINUS IF ELSE WHILE -+# left '*' '/' -+# left '+' '-' -+ left BINOP BINCOMP -+ left BINCOND -+preclow -+ -+rule -+ -+ block: '{' '}' { return SemanticFunctionAST.new({ type: :block, list: SemanticFunctionAST.nothing }) } -+ block: '{' block '}' { return val[1] } -+ | '{' stmt_list '}' { return SemanticFunctionAST.new({ type: :block, list: val[1] }) } -+ | stmt { return SemanticFunctionAST.new({ type: :block, list: SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: SemanticFunctionAST.nothing }) }) } -+ -+ stmt: block_stmt { return val[0] } -+ | var '=' expr { return SemanticFunctionAST.new({ type: :assign, lhs: val[0], rhs: val[2] }) } -+ | func { return val[0] } -+ -+ block_stmt: IF '(' cond ')' block ELSE block { return SemanticFunctionAST.new({ type: :if, cond: val[2], then: val[4], else: val[6] }) } -+ | IF '(' cond ')' block { return SemanticFunctionAST.new({ type: :if, cond: val[2], then: val[4], else: SemanticFunctionAST.nothing }) } -+ | WHILE '(' cond ')' block { return SemanticFunctionAST.new({ type: :while, cond: val[2], loop: val[4] }) } -+ -+ func: FUNC '(' func_args ')' { return SemanticFunctionAST.new({ type: :func, name: val[0], args: val[2] }) } -+ -+ expr: UNIOP expr { return SemanticFunctionAST.new({ type: :uniop, name: val[0], rhs: val[1] }) } -+ | expr BINOP expr { return SemanticFunctionAST.new({ type: :binop, name: val[1], lhs: val[0], rhs: val[2] }) } -+ | '(' expr ')' { return val[1] } -+ | func { return val[0] } -+ | leaf { return val[0] } -+ -+ arg: expr {val[0]} -+ | cond {val[0]} -+# | '{' stmt_list '}' { return SemanticFunctionAST.new({ type: :block, list: val[1] }) } -+ -+ func_args: arg ',' func_args { return [val[0]] + val[2] } -+ | arg { return [val[0]] } -+ | { return [] } -+ -+ cond: '(' cond ')' { return val[1] } -+ | cond BINCOND cond { return SemanticFunctionAST.new({ type: :bincond, name: val[1], lhs: val[0], rhs: val[2] }) } -+ | cond BINCOMP cond { return SemanticFunctionAST.new({ type: :bincond, name: val[1], lhs: val[0], rhs: val[2] }) } -+ | UNIOP cond { return SemanticFunctionAST.new({ type: :unicond, name: val[0], rhs: val[1] }) } -+ | expr { val[0] } -+ | leaf { val[0] } -+# | expr { return SemanticFunctionAST.new({ type: :cond, value: val[0] }) } -+# | leaf { return SemanticFunctionAST.new({ type: :cond, value: val[0] }) } -+ -+ stmt_list: stmt ';' stmt_list { return SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: val[2]}) } -+ | block_stmt stmt_list { return SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: val[1]}) } -+ | stmt ';' { return SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: SemanticFunctionAST.nothing }) } -+ | stmt { return SemanticFunctionAST.new({ type: :stmt_list, head: val[0], tail: SemanticFunctionAST.nothing }) } -+ -+ leaf: var { return val[0] } -+ | '[' STRING ']' { return SemanticFunctionAST.new(type: :string, value: val[0]) } -+ | NUMBER { return SemanticFunctionAST.new(type: :number, number: val[0]) } -+ | HEX_NUMBER { return SemanticFunctionAST.new(type: :number, number: val[0]) } -+ -+ var: VAR { return SemanticFunctionAST.new(type: :var, name: val[0]) } -+ -+end -+ -+---- inner -+ -+def parse(str) -+ orig_str = str -+ str = str.gsub(" ", "").gsub("\n", "").gsub("\r", "") -+ @yydebug = true -+ @q = [] -+ until str.empty? -+ append = "" -+ case str -+ when /\A(if)/ -+ @q.push [:IF, $1] -+ when /\A(else)/ -+ @q.push [:ELSE, $1] -+ when /\A(while)/ -+ @q.push [:WHILE, $1] -+ when /\A(&&|\|\||\^\^)/ -+ @q.push [:BINCOND, $1] -+ when /\A(&|\||\^|<<|>>|-|\+|\/|\*)/ -+ @q.push [:BINOP, $1] -+ when /\A(==|!=|<=|<|>=|>)/ -+ @q.push [:BINCOMP, $1] -+ when /\A([\~!])/ -+ @q.push [:UNIOP, $1] -+ when /\A(a)\]/ -+ @q.push [:STRING, $1] -+ append = "]" -+ when /\A(^[a-zA-Z][a-zA-Z0-9]*)\(/ -+ @q.push [:FUNC, $1] -+ append = '(' -+ when /\A(@?[a-zA-Z_][a-zA-Z0-9_]*)/ -+ @q.push [:VAR, $1] -+ when /\A0x([0-9a-fA-F])+/ -+ @q.push [:HEX_NUMBER, $&.to_i(16)] -+ when /\A\d+/ -+ @q.push [:NUMBER, $&.to_i] -+ when /\A.|\n/o -+ s = $& -+ @q.push [s, s] -+# # when /\A([\+\-\*\/]|<<|>>|&)/ -+# # @q.push [:BINOP, $1] -+ end -+ str = append + $' -+ end -+ @q.push [false, '$end'] -+# begin -+ do_parse -+# rescue -+# return SemanticFunctionAST.error("Error parsing: --#{orig_str}--") -+# end -+end -+ -+ def next_token -+ @q.shift -+ end -+ -+ def on_error(t, val, vstack) -+ raise ParseError, sprintf("\nparse error on value %s (%s)", -+ val.inspect, token_to_str(t) || '?') -+ end -+ -+---- footer -diff --git a/target/arc/semfunc_generator/regenerate_semfunc.rb b/target/arc/semfunc_generator/regenerate_semfunc.rb -new file mode 100644 -index 0000000000..61936f9d7c ---- /dev/null -+++ b/target/arc/semfunc_generator/regenerate_semfunc.rb -@@ -0,0 +1,245 @@ -+#!/usr/bin/env ruby -+ -+require 'erb' -+require_relative 'init.rb' -+ -+HEADER = < -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "translate.h" -+#include "target/arc/semfunc.h" -+ -+EOF -+ -+ERB_TEMPLATE = < -+<%= print_lists(" Variables", @variables) %> -+<%= print_lists(" Functions", @functions) %> -+ * --- code --- -+<%= @pretty_code %> -+ */ -+ -+int -+arc_gen_<%= @name %>(DisasCtxt *ctx<%= @tcg_variables %>) -+{ -+ int ret = DISAS_NEXT; -+<%= @tcg_code %> -+ return ret; -+} -+ -+ -+EOF -+ -+def print_lists(name, elems, max_length = 80, prefix: " * ") -+ ret = "" -+ to_print = prefix + name + ": " -+ -+ elems.each_with_index do |e, i| -+ if(to_print.length + e.length + 2 > max_length) -+ ret += to_print.gsub(/ $/, "") + "\n" -+ to_print = prefix + (" " * (name.length + 2)) -+ end -+ -+ to_print += e -+ to_print += ", " if i + 1 != elems.length -+ end -+ -+ ret += to_print -+ return ret.split("\n").map { |a| a.gsub(/[ \t]+$/, "") }.join("\n") -+end -+ -+ -+def error(line_num, message) -+ puts "Error at semfunc.c:#{line_num} -- #{message}" -+ exit(-1) -+end -+ -+EMPTY_ENTRY = { -+ name: "invalid", -+ code: "" -+} -+ -+funcs = {} -+funcs_in_order = [] -+ -+current_func = nil -+func_name = nil -+in_comment = false -+in_code = false -+in_field_read = nil -+line_num = 1; -+File.read("../semfunc.c").each_line do |l| -+ if(l =~ /^\/[*]/) -+ # puts "ENTERED IN COMMENT at line #{line_num}" -+ in_comment = true -+ elsif (in_comment == true && l =~ /\*\/[ \t]*$/) -+ in_comment = false -+ if(in_code == true) -+ # puts "END_COMMENT at line #{line_num}" -+ # puts current_func[:code] -+ current_func[:ast] = SemanticFunctionParser.new.parse(current_func[:code]) -+ funcs[func_name] = current_func -+ funcs_in_order.push(func_name) -+ end -+ in_code = false -+ elsif (in_comment == true) -+ if(l =~ /^ [*][ ]+([A-Z0-9_]+)$/) -+ func_name = $1 -+ current_func = EMPTY_ENTRY.clone() -+ current_func["Variables"] = [] -+ current_func["Functions"] = [] -+ current_func[:name] = func_name -+ current_func[:code] = "" -+ elsif(in_field_read != nil && l =~ /^ [*][ \t]+([@a-zA-Z0-9, ]+)$/) -+ data = $1 -+ data.split(/,[ ]*/).each do |d_entry| -+ current_func[in_field_read].push(d_entry) -+ end -+ elsif(l =~ /^ [*][ \t]+([a-zA-Z]+): ([@a-zA-Z0-9, ]+)$/) -+ field = $1 -+ data = $2 -+ if(current_func[field].nil?) -+ error(line_num, "Field '#{field}' not valid.") -+ end -+ data.split(/,[ ]*/).each do |d_entry| -+ #puts "#{field} = #{d_entry}" -+ current_func[field].push(d_entry) -+ end -+ in_field_read = field -+ elsif(l =~ /^ [*] --- code ---$/) -+ in_field_read = nil -+ in_code = true -+ elsif(in_code) -+ current_func[:code] = "#{current_func[:code]}#{l[3..-1]}" -+ end -+ end -+ line_num += 1 -+end -+ -+def fix_indentation_tcg_code(code) -+ -+ ret = "" -+ in_comment = false -+ indent = 0 -+ #puts code -+ -+ code.split("\n").each_with_index do |line, idx| -+ -+ if(in_comment == false) -+ if(line =~ /^[ \t]+$/) -+ #ret += "1: " -+ ret += "\n" -+ elsif(line =~ /^[ \t;]+$/) -+ #ret += "2: \n" -+ ret += "" -+ else -+ indent -= (line.scan(/}/).size - 1) * 4 -+ -+ #ret += "9: " -+ line =~ /^[ \t]*(.+)$/ -+ code = $1 -+ ret += "#{" "*indent}#{$1}\n" -+ -+ indent += (line.scan(/{/).size - 1) * 4 -+ end -+ end -+ -+ end -+ -+ ret1 = "" -+ in_else = nil -+ else_content = "" -+ perhaps_else = false; -+ ret.split("\n").each_with_index do |line, i| -+ if(line.index("else {") != nil) -+ #puts "1- #{line}" -+ in_else = i -+ else_content = " else {\n" -+ elsif(line.index("}") != nil && in_else != nil) -+ if(in_else + 1 != i) -+ #puts "2- #{line}" -+ else_content += line -+ ret1 += else_content + "\n" -+ end -+ else_content = "" -+ in_else = nil -+ elsif(line.index("}") != nil && in_else == nil) -+ ret1 += line -+ else_content += line -+ perhaps_else = true -+ else -+ if(in_else != nil) -+ perhaps_else = false -+ #puts "3- #{line}" -+ else_content += line + "\n" -+ else -+ #puts "4- #{line}" -+ ret1 += "\n" if(perhaps_else == true) -+ ret1 += "#{line}\n" -+ perhaps_else = false -+ end -+ end -+ end -+ return ret1 -+end -+ -+ -+class FuncBinding -+ def initialize(data, opts) -+ @name = data[:name] -+ @functions = data["Functions"] -+ @variables = data["Variables"] -+ @code = data[:code].gsub(/\t/, '') -+ @pretty_code = data[:code].split("\n").map { |l| " * #{l}" }.join("\n") -+ @ast = SemanticFunctionParser.new.parse(@code) -+ tcg_code = QEmuCompiler.new.generate(@ast, [], opts[:debug]) -+ @tcg_code = fix_indentation_tcg_code(tcg_code) -+ @tcg_variables = @variables.map { |a| "TCGv #{a.gsub("@", "")}"}.unshift("").join(", ") -+ end -+end -+ -+ -+# Options parsing -+opts = { debug: false } -+while(ARGV.count > 0) -+ opt = ARGV.shift -+ if(opt == '-f' && (tmp = ARGV.shift) != nil) -+ opts[:filter] = tmp -+ elsif(opt == '-d') -+ puts "HERE" -+ opts[:debug] = true -+ end -+end -+ -+puts HEADER -+funcs_in_order.each do |name| -+ next if(opts[:filter] && opts[:filter] != name) -+ data = funcs[name] -+ #puts name -+ next if data[:code].nil? -+ erb = ERB.new(ERB_TEMPLATE) -+ MyClass = erb.def_class(FuncBinding, 'render()') -+ puts MyClass.new(data, opts).render() -+ self.class.send(:remove_const, :MyClass) -+end -diff --git a/target/arc/semfunc_mapping.def b/target/arc/semfunc_mapping.def -new file mode 100644 -index 0000000000..746339d9e6 ---- /dev/null -+++ b/target/arc/semfunc_mapping.def -@@ -0,0 +1,25 @@ -+/* -+ * QEMU ARC SEMANTIC MAPPING. -+ * -+ * Copyright (c) 2020 Synopsys, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#ifdef TARGET_ARCV2 -+#include "semfunc-v2_mapping.def" -+#endif -+ -+#ifdef TARGET_ARCV3 -+#include "semfunc-v3_mapping.def" -+#endif -diff --git a/target/arc/timer.c b/target/arc/timer.c -new file mode 100644 -index 0000000000..43caf3b5a1 ---- /dev/null -+++ b/target/arc/timer.c -@@ -0,0 +1,459 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "qemu/timer.h" -+#include "cpu.h" -+#include "exec/exec-all.h" -+#include "hw/irq.h" -+#include "hw/arc/cpudevs.h" -+#include "timer.h" -+#include "qemu/main-loop.h" -+ -+#define TIMER_PERIOD(hz) (1000000000LL / (hz)) -+#define TIMEOUT_LIMIT 1000000 -+ -+#define FREQ_HZ (env_archcpu(env)->freq_hz) -+#define T_PERIOD (TIMER_PERIOD(FREQ_HZ)) -+#define T_COUNT(T) \ -+ ((uint32_t) ((qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - \ -+ env->timer[T].last_clk) / T_PERIOD)) -+ -+/* Update the next timeout time as difference between Count and Limit */ -+static void cpu_arc_timer_update(CPUARCState *env, uint32_t timer) -+{ -+ uint32_t delta; -+ uint32_t t_count = T_COUNT(timer); -+ uint64_t now = -+ (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) * T_PERIOD; -+ uint32_t period = T_PERIOD; -+ -+ delta = env->timer[timer].T_Limit - t_count - 1; -+ -+ /* -+ * Artificially limit timeout rate to something achievable under -+ * QEMU. Otherwise, QEMU spends all its time generating timer -+ * interrupts, and there is no forward progress. About ten -+ * microseconds is the fastest that really works on the current -+ * generation of host machines. -+ */ -+ if ((delta * period) < TIMEOUT_LIMIT) { -+ delta = TIMEOUT_LIMIT / period; -+ } -+ -+ timer_mod(env->cpu_timer[timer], now + ((uint64_t)delta * period)); -+ -+ qemu_log_mask(LOG_UNIMP, -+ "[TMR%d] Timer update in 0x" TARGET_FMT_lx -+ " - 0x%08x = 0x%08x (ctrl:0x" TARGET_FMT_lx -+ " @ %d Hz)\n", -+ timer, env->timer[timer].T_Limit, -+ t_count, delta, env->timer[timer].T_Cntrl, FREQ_HZ); -+} -+ -+/* Expire the timer function. Rise an interrupt if required. */ -+ -+static void cpu_arc_timer_expire(CPUARCState *env, uint32_t timer) -+{ -+ assert(timer == 1 || timer == 0); -+ qemu_log_mask(LOG_UNIMP, "[TMR%d] Timer expired\n", timer); -+ -+ uint32_t overflow = env->timer[timer].T_Cntrl & TMR_IP; -+ /* Set the IP bit. */ -+ -+ bool unlocked = !qemu_mutex_iothread_locked(); -+ if (unlocked) { -+ qemu_mutex_lock_iothread(); -+ } -+ env->timer[timer].T_Cntrl |= TMR_IP; -+ env->timer[timer].last_clk = -+ (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) * T_PERIOD; -+ if (unlocked) { -+ qemu_mutex_unlock_iothread(); -+ } -+ -+ /* Raise an interrupt if enabled. */ -+ if ((env->timer[timer].T_Cntrl & TMR_IE) && !overflow) { -+ qemu_log_mask(CPU_LOG_INT, "[TMR%d] Rising IRQ\n", timer); -+ qemu_irq_raise(env->irq[TIMER0_IRQ + (timer & 0x01)]); -+ } -+} -+ -+/* -+ * This callback should occur when the counter is exactly equal to the -+ * limit value. Offset the count by one to avoid immediately -+ * retriggering the callback before any virtual time has passed. -+ */ -+ -+static void arc_timer0_cb(void *opaque) -+{ -+ CPUARCState *env = (CPUARCState *) opaque; -+ -+ if (!(env_archcpu(env)->timer_build & TB_T0)) { -+ return; -+ } -+ -+ cpu_arc_timer_expire(env, 0); -+ cpu_arc_timer_update(env, 0); -+} -+ -+/* Like the above function but for TIMER1. */ -+static void arc_timer1_cb(void *opaque) -+{ -+ CPUARCState *env = (CPUARCState *) opaque; -+ -+ if (!(env_archcpu(env)->timer_build & TB_T1)) { -+ return; -+ } -+ -+ cpu_arc_timer_expire(env, 1); -+ cpu_arc_timer_update(env, 1); -+} -+ -+/* RTC counter update. */ -+static void cpu_rtc_count_update(CPUARCState *env) -+{ -+ uint64_t now; -+ uint64_t llreg; -+ -+ assert((env_archcpu(env)->timer_build & TB_RTC) && env->cpu_rtc); -+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); -+ -+ if (!(env->aux_rtc_ctrl & 0x01)) { -+ return; -+ } -+ -+ llreg = ((now - env->last_clk_rtc) / TIMER_PERIOD(FREQ_HZ)); -+ llreg += env->aux_rtc_low + ((uint64_t)env->aux_rtc_high << 32); -+ env->aux_rtc_high = llreg >> 32; -+ env->aux_rtc_low = (uint32_t) llreg; -+ -+ env->last_clk_rtc = now; -+ qemu_log_mask(LOG_UNIMP, "[RTC] RTC count-regs update\n"); -+} -+ -+/* Update the next timeout time as difference between Count and Limit */ -+static void cpu_rtc_update(CPUARCState *env) -+{ -+ uint64_t wait = 0; -+ uint64_t now, next, period; -+ -+ assert(env->cpu_rtc); -+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); -+ -+ if (!(env->aux_rtc_ctrl & 0x01)) { -+ return; -+ } -+ -+ period = TIMER_PERIOD(FREQ_HZ); -+ wait = UINT64_MAX - ((((uint64_t) env->aux_rtc_high) << 32) -+ + env->aux_rtc_low); -+ wait -= (now - env->last_clk_rtc) / period; -+ -+ /* Limit timeout rate. */ -+ if ((wait * period) < TIMEOUT_LIMIT) { -+ period = TIMEOUT_LIMIT / wait; -+ } -+ -+ next = now + (uint64_t) wait * period; -+ timer_mod(env->cpu_rtc, next); -+ qemu_log_mask(LOG_UNIMP, "[RTC] RTC update\n"); -+} -+ -+/* RTC call back routine. */ -+static void arc_rtc_cb(void *opaque) -+{ -+ CPUARCState *env = (CPUARCState *) opaque; -+ -+ if (!(env_archcpu(env)->timer_build & TB_RTC)) { -+ return; -+ } -+ -+ qemu_log_mask(LOG_UNIMP, "[RTC] RTC expired\n"); -+ -+ env->aux_rtc_high = 0; -+ env->aux_rtc_low = 0; -+ env->last_clk_rtc = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); -+ cpu_rtc_update(env); -+} -+ -+/* Helper used when resetting the system. */ -+static void cpu_arc_count_reset(CPUARCState *env, uint32_t timer) -+{ -+ assert(timer == 0 || timer == 1); -+ env->timer[timer].T_Cntrl = 0; -+ env->timer[timer].T_Limit = 0x00ffffff; -+} -+ -+/* Get the counter value. */ -+static uint32_t cpu_arc_count_get(CPUARCState *env, uint32_t timer) -+{ -+ uint32_t count = T_COUNT(timer); -+ qemu_log_mask(LOG_UNIMP, "[TMR%d] Timer count %d.\n", timer, count); -+ return count; -+} -+ -+/* Set the counter value. */ -+static void cpu_arc_count_set(CPUARCState *env, uint32_t timer, uint32_t val) -+{ -+ assert(timer == 0 || timer == 1); -+ bool unlocked = !qemu_mutex_iothread_locked(); -+ if (unlocked) { -+ qemu_mutex_lock_iothread(); -+ } -+ env->timer[timer].last_clk = -+ ((qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) + val) * T_PERIOD; -+ cpu_arc_timer_update(env, timer); -+ if (unlocked) { -+ qemu_mutex_unlock_iothread(); -+ } -+} -+ -+/* Store the counter limit. */ -+static void cpu_arc_store_limit(CPUARCState *env, -+ uint32_t timer, uint32_t value) -+{ -+ switch (timer) { -+ case 0: -+ if (!(env_archcpu(env)->timer_build & TB_T0)) { -+ return; -+ } -+ break; -+ case 1: -+ if (!(env_archcpu(env)->timer_build & TB_T1)) { -+ return; -+ } -+ break; -+ default: -+ break; -+ } -+ env->timer[timer].T_Limit = value; -+ cpu_arc_timer_update(env, timer); -+} -+ -+/* Set the timer control bits. */ -+static void cpu_arc_control_set(CPUARCState *env, -+ uint32_t timer, uint32_t value) -+{ -+ assert(timer == 1 || timer == 0); -+ bool unlocked = !qemu_mutex_iothread_locked(); -+ if (unlocked) { -+ qemu_mutex_lock_iothread(); -+ } -+ if ((env->timer[timer].T_Cntrl & TMR_IP) && !(value & TMR_IP)) { -+ qemu_irq_lower(env->irq[TIMER0_IRQ + (timer)]); -+ } -+ env->timer[timer].T_Cntrl = value & 0x1f; -+ if (unlocked) { -+ qemu_mutex_unlock_iothread(); -+ } -+} -+ -+/* Get The RTC count value. */ -+static uint32_t arc_rtc_count_get(CPUARCState *env, bool lower) -+{ -+ cpu_rtc_count_update(env); -+ return lower ? env->aux_rtc_low : env->aux_rtc_high; -+} -+ -+/* Set the RTC control bits. */ -+static void arc_rtc_ctrl_set(CPUARCState *env, uint32_t val) -+{ -+ assert(GET_STATUS_BIT(env->stat, Uf) == 0); -+ -+ if (val & 0x02) { -+ env->aux_rtc_low = 0; -+ env->aux_rtc_high = 0; -+ env->last_clk_rtc = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); -+ } -+ if (!(val & 0x01)) { -+ timer_del(env->cpu_rtc); -+ } -+ -+ /* Restart RTC, update last clock. */ -+ if ((env->aux_rtc_ctrl & 0x01) == 0 && (val & 0x01)) { -+ env->last_clk_rtc = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); -+ } -+ -+ env->aux_rtc_ctrl = 0xc0000000 | (val & 0x01); -+ cpu_rtc_update(env); -+} -+ -+/* Init procedure, called in platform. */ -+ -+void -+cpu_arc_clock_init(ARCCPU *cpu) -+{ -+ CPUARCState *env = &cpu->env; -+ -+ if (env_archcpu(env)->timer_build & TB_T0) { -+ env->cpu_timer[0] = -+ timer_new_ns(QEMU_CLOCK_VIRTUAL, &arc_timer0_cb, env); -+ } -+ -+ if (env_archcpu(env)->timer_build & TB_T1) { -+ env->cpu_timer[1] = -+ timer_new_ns(QEMU_CLOCK_VIRTUAL, &arc_timer1_cb, env); -+ } -+ -+ if (env_archcpu(env)->timer_build & TB_RTC) { -+ env->cpu_rtc = -+ timer_new_ns(QEMU_CLOCK_VIRTUAL, &arc_rtc_cb, env); -+ } -+ -+ env->timer[0].last_clk = -+ (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) * T_PERIOD; -+ env->timer[1].last_clk = -+ (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) * T_PERIOD; -+} -+ -+void -+arc_initializeTIMER(ARCCPU *cpu) -+{ -+ CPUARCState *env = &cpu->env; -+ -+ /* FIXME! add default timer priorities. */ -+ env_archcpu(env)->timer_build = 0x04 | (cpu->cfg.has_timer_0 ? TB_T0 : 0) | -+ (cpu->cfg.has_timer_1 ? TB_T1 : 0) | -+ (cpu->cfg.rtc_option ? TB_RTC : 0); -+} -+ -+void -+arc_resetTIMER(ARCCPU *cpu) -+{ -+ CPUARCState *env = &cpu->env; -+ -+ if (env_archcpu(env)->timer_build & TB_T0) { -+ cpu_arc_count_reset(env, 0); -+ } -+ -+ if (env_archcpu(env)->timer_build & TB_T1) { -+ cpu_arc_count_reset(env, 1); -+ } -+} -+ -+/* Function implementation for reading/writing aux regs. */ -+target_ulong -+aux_timer_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ -+ switch (aux_reg_detail->id) { -+ case AUX_ID_control0: -+ return env->timer[0].T_Cntrl; -+ break; -+ -+ case AUX_ID_control1: -+ return env->timer[1].T_Cntrl; -+ break; -+ -+ case AUX_ID_count0: -+ return cpu_arc_count_get(env, 0); -+ break; -+ -+ case AUX_ID_count1: -+ return cpu_arc_count_get(env, 1); -+ break; -+ -+ case AUX_ID_limit0: -+ return env->timer[0].T_Limit; -+ break; -+ -+ case AUX_ID_limit1: -+ return env->timer[1].T_Limit; -+ break; -+ -+ case AUX_ID_timer_build: -+ return env_archcpu(env)->timer_build; -+ break; -+ -+ case AUX_ID_aux_rtc_low: -+ return arc_rtc_count_get(env, true); -+ break; -+ -+ case AUX_ID_aux_rtc_high: -+ return arc_rtc_count_get(env, false); -+ break; -+ -+ case AUX_ID_aux_rtc_ctrl: -+ return env->aux_rtc_ctrl; -+ break; -+ -+ default: -+ break; -+ } -+ return 0; -+} -+ -+void aux_timer_set(const struct arc_aux_reg_detail *aux_reg_detail, -+ target_ulong val, void *data) -+{ -+ CPUARCState *env = (CPUARCState *) data; -+ -+ qemu_log_mask(LOG_UNIMP, "[TMRx] AUX[%s] <= 0x" TARGET_FMT_lx "\n", -+ aux_reg_detail->name, val); -+ -+ qemu_mutex_lock_iothread(); -+ switch (aux_reg_detail->id) { -+ case AUX_ID_control0: -+ if (env_archcpu(env)->timer_build & TB_T0) { -+ cpu_arc_control_set(env, 0, val); -+ } -+ break; -+ -+ case AUX_ID_control1: -+ if (env_archcpu(env)->timer_build & TB_T1) { -+ cpu_arc_control_set(env, 1, val); -+ } -+ break; -+ -+ case AUX_ID_count0: -+ if (env_archcpu(env)->timer_build & TB_T0) { -+ cpu_arc_count_set(env, 0, val); -+ } -+ break; -+ -+ case AUX_ID_count1: -+ if (env_archcpu(env)->timer_build & TB_T1) { -+ cpu_arc_count_set(env, 1, val); -+ } -+ break; -+ -+ case AUX_ID_limit0: -+ cpu_arc_store_limit(env, 0, val); -+ break; -+ -+ case AUX_ID_limit1: -+ cpu_arc_store_limit(env, 1, val); -+ break; -+ -+ case AUX_ID_aux_rtc_ctrl: -+ arc_rtc_ctrl_set(env, val); -+ break; -+ -+ default: -+ break; -+ } -+ qemu_mutex_unlock_iothread(); -+} -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/timer.h b/target/arc/timer.h -new file mode 100644 -index 0000000000..01baf73d37 ---- /dev/null -+++ b/target/arc/timer.h -@@ -0,0 +1,27 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef __ARC_TIMER_H__ -+#define __ARC_TIMER_H__ -+ -+void arc_initializeTIMER(ARCCPU *); -+void arc_resetTIMER(ARCCPU *); -+ -+#endif -diff --git a/target/arc/translate.c b/target/arc/translate.c -new file mode 100644 -index 0000000000..c81d284a7c ---- /dev/null -+++ b/target/arc/translate.c -@@ -0,0 +1,1716 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#include "qemu/osdep.h" -+#include "translate.h" -+#include "qemu/qemu-print.h" -+#include "tcg/tcg-op-gvec.h" -+#include "target/arc/semfunc.h" -+#include "target/arc/arc-common.h" -+ -+/* Globals */ -+TCGv cpu_S1f; -+TCGv cpu_S2f; -+TCGv cpu_CSf; -+ -+TCGv cpu_Ef; -+TCGv cpu_IEf; -+TCGv cpu_Vf; -+TCGv cpu_Cf; -+TCGv cpu_Nf; -+TCGv cpu_Zf; -+TCGv cpu_DEf; -+ -+TCGv cpu_is_delay_slot_instruction; -+ -+TCGv cpu_l1_Ef; -+TCGv cpu_l1_Vf; -+TCGv cpu_l1_Cf; -+TCGv cpu_l1_Nf; -+TCGv cpu_l1_Zf; -+TCGv cpu_l1_DEf; -+ -+TCGv cpu_l2_Ef; -+TCGv cpu_l2_Vf; -+TCGv cpu_l2_Cf; -+TCGv cpu_l2_Nf; -+TCGv cpu_l2_Zf; -+TCGv cpu_l2_DEf; -+ -+TCGv cpu_er_Ef; -+TCGv cpu_er_Vf; -+TCGv cpu_er_Cf; -+TCGv cpu_er_Nf; -+TCGv cpu_er_Zf; -+TCGv cpu_er_DEf; -+ -+TCGv cpu_eret; -+TCGv cpu_erbta; -+TCGv cpu_ecr; -+TCGv cpu_efa; -+ -+TCGv cpu_bta; -+TCGv cpu_bta_l1; -+TCGv cpu_bta_l2; -+ -+TCGv cpu_pc; -+/* replaced by AUX_REG array */ -+TCGv cpu_lps; -+TCGv cpu_lpe; -+ -+TCGv cpu_r[64]; -+ -+TCGv cpu_intvec; -+ -+TCGv cpu_lock_lf_var; -+ -+/* NOTE: Pseudo register required for comparison with lp_end */ -+TCGv cpu_npc; -+ -+/* Macros */ -+ -+#include "exec/gen-icount.h" -+#define REG(x) (cpu_r[x]) -+ -+/* macro used to fix middle-endianess. */ -+#define ARRANGE_ENDIAN(endianess, buf) \ -+ ((endianess) ? ror32(buf, 16) : bswap32(buf)) -+ -+static inline bool use_goto_tb(const DisasContext *dc, target_ulong dest) -+{ -+ if (unlikely(dc->base.singlestep_enabled)) { -+ return false; -+ } -+#ifndef CONFIG_USER_ONLY -+ return (dc->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); -+#else -+ return true; -+#endif -+} -+ -+void gen_goto_tb(const DisasContext *ctx, int n, TCGv dest) -+{ -+ tcg_gen_mov_tl(cpu_pc, dest); -+ tcg_gen_andi_tl(cpu_pcl, dest, ~((target_ulong) 3)); -+ if (ctx->base.singlestep_enabled) { -+ gen_helper_debug(cpu_env); -+ } else { -+ tcg_gen_exit_tb(NULL, 0); -+ } -+} -+ -+static void gen_gotoi_tb(const DisasContext *ctx, int n, target_ulong dest) -+{ -+ if (use_goto_tb(ctx, dest)) { -+ tcg_gen_goto_tb(n); -+ tcg_gen_movi_tl(cpu_pc, dest); -+ tcg_gen_movi_tl(cpu_pcl, dest & (~((target_ulong) 3))); -+ tcg_gen_exit_tb(ctx->base.tb, n); -+ } else { -+ tcg_gen_movi_tl(cpu_pc, dest); -+ tcg_gen_movi_tl(cpu_pcl, dest & (~((target_ulong) 3))); -+ if (ctx->base.singlestep_enabled) { -+ gen_helper_debug(cpu_env); -+ } -+ tcg_gen_exit_tb(NULL, 0); -+ } -+} -+ -+void arc_translate_init(void) -+{ -+ int i; -+#define ARC_REG_OFFS(x) offsetof(CPUARCState, x) -+ -+#define NEW_ARC_REG(TCGV, FIELD) \ -+ { &TCGV, offsetof(CPUARCState, FIELD), #FIELD }, -+ -+ static const struct { TCGv *ptr; int off; const char *name; } r32[] = { -+ NEW_ARC_REG(cpu_S1f, macmod.S1) -+ NEW_ARC_REG(cpu_S2f, macmod.S2) -+ NEW_ARC_REG(cpu_CSf, macmod.CS) -+ -+ NEW_ARC_REG(cpu_Zf, stat.Zf) -+ NEW_ARC_REG(cpu_Nf, stat.Nf) -+ NEW_ARC_REG(cpu_Cf, stat.Cf) -+ NEW_ARC_REG(cpu_Vf, stat.Vf) -+ NEW_ARC_REG(cpu_DEf, stat.DEf) -+ NEW_ARC_REG(cpu_Ef, stat.Ef) -+ NEW_ARC_REG(cpu_IEf, stat.IEf) -+ -+ NEW_ARC_REG(cpu_l1_Zf, stat_l1.Zf) -+ NEW_ARC_REG(cpu_l1_Nf, stat_l1.Nf) -+ NEW_ARC_REG(cpu_l1_Cf, stat_l1.Cf) -+ NEW_ARC_REG(cpu_l1_Vf, stat_l1.Vf) -+ NEW_ARC_REG(cpu_l1_DEf, stat_l1.DEf) -+ -+ NEW_ARC_REG(cpu_er_Zf, stat_er.Zf) -+ NEW_ARC_REG(cpu_er_Nf, stat_er.Nf) -+ NEW_ARC_REG(cpu_er_Cf, stat_er.Cf) -+ NEW_ARC_REG(cpu_er_Vf, stat_er.Vf) -+ NEW_ARC_REG(cpu_er_DEf, stat_er.DEf) -+ -+ NEW_ARC_REG(cpu_eret, eret) -+ NEW_ARC_REG(cpu_erbta, erbta) -+ NEW_ARC_REG(cpu_ecr, ecr) -+ NEW_ARC_REG(cpu_efa, efa) -+ NEW_ARC_REG(cpu_bta, bta) -+ NEW_ARC_REG(cpu_lps, lps) -+ NEW_ARC_REG(cpu_lpe, lpe) -+ NEW_ARC_REG(cpu_pc , pc) -+ NEW_ARC_REG(cpu_npc, npc) -+ -+ NEW_ARC_REG(cpu_bta_l1, bta_l1) -+ NEW_ARC_REG(cpu_bta_l2, bta_l2) -+ -+ NEW_ARC_REG(cpu_intvec, intvec) -+ -+ NEW_ARC_REG(cpu_is_delay_slot_instruction, -+ stat.is_delay_slot_instruction) -+ -+ NEW_ARC_REG(cpu_lock_lf_var, lock_lf_var) -+ }; -+ -+ -+ for (i = 0; i < ARRAY_SIZE(r32); ++i) { -+ *r32[i].ptr = tcg_global_mem_new(cpu_env, r32[i].off, r32[i].name); -+ } -+ -+ -+ for (i = 0; i < 64; i++) { -+ char name[16]; -+ -+ sprintf(name, "r[%d]", i); -+ cpu_r[i] = tcg_global_mem_new(cpu_env, -+ ARC_REG_OFFS(r[i]), -+ strdup(name)); -+ } -+ -+#undef ARC_REG_OFFS -+#undef NEW_ARC_REG -+} -+ -+static void arc_tr_init_disas_context(DisasContextBase *dcbase, -+ CPUState *cs) -+{ -+ DisasContext *dc = container_of(dcbase, DisasContext, base); -+ -+ dc->base.is_jmp = DISAS_NEXT; -+ dc->mem_idx = dc->base.tb->flags & 1; -+ dc->in_delay_slot = false; -+} -+static void arc_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) -+{ -+ /* place holder for now */ -+} -+ -+static void arc_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) -+{ -+ DisasContext *dc = container_of(dcbase, DisasContext, base); -+ -+ -+ tcg_gen_insn_start(dc->base.pc_next); -+ dc->cpc = dc->base.pc_next; -+ -+ if (dc->base.num_insns == dc->base.max_insns && -+ (dc->base.tb->cflags & CF_LAST_IO)) { -+ gen_io_start(); -+ } -+} -+ -+static bool arc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, -+ const CPUBreakpoint *bp) -+{ -+ DisasContext *dc = container_of(dcbase, DisasContext, base); -+ -+ tcg_gen_movi_tl(cpu_pc, dc->cpc); -+ dc->base.is_jmp = DISAS_NORETURN; -+ gen_helper_debug(cpu_env); -+ dc->base.pc_next += 2; -+ return true; -+} -+ -+static int arc_gen_INVALID(const DisasContext *ctx) -+{ -+ qemu_log_mask(LOG_UNIMP, -+ "invalid inst @:%08x\n", ctx->cpc); -+ return DISAS_NEXT; -+} -+ -+/* -+ * Giving a CTX, decode it into an valid OPCODE_P if it -+ * exists. Returns TRUE if successfully. -+ */ -+static bool read_and_decode_context(DisasContext *ctx, -+ const struct arc_opcode **opcode_p) -+{ -+ uint16_t buffer[2]; -+ uint8_t length; -+ uint64_t insn; -+ ARCCPU *cpu = env_archcpu(ctx->env); -+ -+ /* Read the first 16 bits, figure it out what kind of instruction it is. */ -+ buffer[0] = cpu_lduw_code(ctx->env, ctx->cpc); -+ length = arc_insn_length(buffer[0], cpu->family); -+ -+ switch (length) { -+ case 2: -+ /* 16-bit instructions. */ -+ insn = (uint64_t) buffer[0]; -+ break; -+ case 4: -+ /* 32-bit instructions. */ -+ buffer[1] = cpu_lduw_code(ctx->env, ctx->cpc + 2); -+ uint32_t buf = (buffer[0] << 16) | buffer[1]; -+ insn = buf; -+ break; -+ default: -+ g_assert_not_reached(); -+ } -+ -+ /* -+ * Now, we have read the entire opcode, decode it and place the -+ * relevant info into opcode and ctx->insn. -+ */ -+ *opcode_p = arc_find_format(&ctx->insn, insn, length, cpu->family); -+ -+ if (*opcode_p == NULL) { -+ return false; -+ } -+ -+ /* -+ * If the instruction requires long immediate, read the extra 4 -+ * bytes and initialize the relevant fields. -+ */ -+ if (ctx->insn.limm_p) { -+ ctx->insn.limm = ARRANGE_ENDIAN(true, -+ cpu_ldl_code(ctx->env, -+ ctx->cpc + length)); -+ length += 4; -+#ifdef TARGET_ARCV3 -+ } else if(ctx->insn.signed_limm_p) { -+ ctx->insn.limm = ARRANGE_ENDIAN(true, -+ cpu_ldl_code (ctx->env, -+ ctx->cpc + length)); -+ if(ctx->insn.limm & 0x80000000) -+ ctx->insn.limm += 0xffffffff00000000; -+ length += 4; -+#endif -+ } else { -+ ctx->insn.limm = 0; -+ } -+ -+ /* Update context. */ -+ ctx->insn.len = length; -+ ctx->npc = ctx->cpc + length; -+ ctx->pcl = ctx->cpc & (~((target_ulong) 3)); -+ -+ return true; -+} -+ -+/* Check if OPR is a register _and_ an odd numbered one. */ -+static inline bool is_odd_numbered_register(const operand_t opr) -+{ -+ return (opr.type & ARC_OPERAND_IR) && (opr.value & 1); -+} -+ -+enum arc_opcode_map { -+ MAP_NONE = -1, -+#define SEMANTIC_FUNCTION(...) -+#define CONSTANT(...) -+#define MAPPING(MNEMONIC, NAME, NOPS, ...) MAP_##MNEMONIC##_##NAME, -+#include "target/arc/semfunc_mapping.def" -+#include "target/arc/extra_mapping.def" -+#undef MAPPING -+#undef CONSTANT -+#undef SEMANTIC_FUNCTION -+ /* Add some include to generated files */ -+ MAP_LAST -+}; -+ -+const char number_of_ops_semfunc[MAP_LAST + 1] = { -+#define SEMANTIC_FUNCTION(...) -+#define CONSTANT(...) -+#define MAPPING(MNEMONIC, NAME, NOPS, ...) NOPS, -+#include "target/arc/semfunc_mapping.def" -+#include "target/arc/extra_mapping.def" -+#undef MAPPING -+#undef CONSTANT -+#undef SEMANTIC_FUNCTION -+ 2 -+}; -+ -+static enum arc_opcode_map arc_map_opcode(const struct arc_opcode *opcode) -+{ -+#define SEMANTIC_FUNCTION(...) -+#define CONSTANT(...) -+#define MAPPING(MNEMONIC, NAME, ...) \ -+ if (strcmp(opcode->name, #MNEMONIC) == 0) \ -+ return MAP_##MNEMONIC##_##NAME; -+#include "target/arc/semfunc_mapping.def" -+#include "target/arc/extra_mapping.def" -+#undef MAPPING -+#undef CONSTANT -+#undef SEMANTIC_FUNCTION -+ -+ return MAP_NONE; -+} -+ -+/* Code support for constant values coming from semantic function mapping. */ -+struct constant_operands { -+ uint8_t operand_number; -+ uint32_t default_value; -+ struct constant_operands *next; -+}; -+ -+struct constant_operands *map_constant_operands[MAP_LAST]; -+ -+static void add_constant_operand(enum arc_opcode_map mapping, -+ uint8_t operand_number, -+ uint32_t value) -+{ -+ struct constant_operands **t = &(map_constant_operands[mapping]); -+ while (*t != NULL) { -+ t = &((*t)->next); -+ } -+ *t = (struct constant_operands *) g_new(struct constant_operands, 1); -+ -+ (*t)->operand_number = operand_number; -+ (*t)->default_value = value; -+ (*t)->next = NULL; -+} -+ -+static struct constant_operands * -+constant_entry_for(enum arc_opcode_map mapping, -+ uint8_t operand_number) -+{ -+ struct constant_operands *t = map_constant_operands[mapping]; -+ while (t != NULL) { -+ if (t->operand_number == operand_number) { -+ return t; -+ } -+ t = t->next; -+ } -+ return NULL; -+} -+ -+static void init_constants(void) -+{ -+#define SEMANTIC_FUNCTION(...) -+#define MAPPING(...) -+#define CONSTANT(NAME, MNEMONIC, OP_NUM, VALUE) \ -+ add_constant_operand(MAP_##MNEMONIC##_##NAME, OP_NUM, VALUE); -+#include "target/arc/semfunc_mapping.def" -+#include "target/arc/extra_mapping.def" -+#undef MAPPING -+#undef CONSTANT -+#undef SEMANTIC_FUNCTION -+} -+ -+static void arc_debug_opcode(const struct arc_opcode *opcode, -+ DisasContext *ctx, -+ const char *msg) -+{ -+ qemu_log_mask(LOG_UNIMP, -+ "%s for %s at pc=0x%08x\n", -+ msg, opcode->name, ctx->cpc); -+} -+ -+static TCGv arc_decode_operand(const struct arc_opcode *opcode, -+ DisasContext *ctx, -+ unsigned char nop, -+ enum arc_opcode_map mapping) -+{ -+ TCGv ret; -+ -+ if (nop >= ctx->insn.n_ops) { -+ struct constant_operands *co = constant_entry_for(mapping, nop); -+ assert(co != NULL); -+ ret = tcg_const_local_tl(co->default_value); -+ return ret; -+ } else { -+ operand_t operand = ctx->insn.operands[nop]; -+ -+ if (operand.type & ARC_OPERAND_IR) { -+ ret = cpu_r[operand.value]; -+ if (operand.value == 63) { -+ tcg_gen_movi_tl(cpu_pcl, ctx->pcl); -+ } -+ } else { -+ int64_t limm = operand.value; -+ if (operand.type & ARC_OPERAND_LIMM) { -+ limm = ctx->insn.limm; -+ tcg_gen_movi_tl(cpu_limm, limm); -+ ret = cpu_r[62]; -+ } else { -+ ret = tcg_const_local_tl(limm); -+ } -+ } -+ } -+ -+ return ret; -+} -+ -+/* See translate.h. */ -+void arc_gen_excp(const DisasCtxt *ctx, -+ uint32_t index, -+ uint32_t causecode, -+ uint32_t param) -+{ -+ TCGv tcg_index = tcg_const_tl(index); -+ TCGv tcg_cause = tcg_const_tl(causecode); -+ TCGv tcg_param = tcg_const_tl(param); -+ -+ tcg_gen_movi_tl(cpu_pc, ctx->cpc); -+ tcg_gen_movi_tl(cpu_eret, ctx->cpc); -+ tcg_gen_movi_tl(cpu_erbta, ctx->npc); -+ -+ gen_helper_raise_exception(cpu_env, tcg_index, tcg_cause, tcg_param); -+ -+ tcg_temp_free(tcg_index); -+ tcg_temp_free(tcg_cause); -+ tcg_temp_free(tcg_param); -+} -+ -+/* Wrapper around tcg_gen_exit_tb that handles single stepping */ -+static void exit_tb(const DisasContext *ctx) -+{ -+ if (ctx->base.singlestep_enabled) { -+ gen_helper_debug(cpu_env); -+ } else { -+ tcg_gen_exit_tb(NULL, 0); -+ } -+} -+ -+/* -+ * throw "illegal instruction" exception if more than available -+ * registers are asked to be saved/restore. -+ */ -+static bool check_enter_leave_nr_regs(const DisasCtxt *ctx, -+ uint8_t regs) -+{ -+ const uint8_t rgf_num_regs = env_archcpu(ctx->env)->cfg.rgf_num_regs; -+ if ((rgf_num_regs == 32 && regs > 14) || -+ (rgf_num_regs == 16 && regs > 3)) { -+ -+ TCGv tcg_index = tcg_const_tl(EXCP_INST_ERROR); -+ TCGv tcg_cause = tcg_const_tl(0); -+ TCGv tcg_param = tcg_const_tl(0); -+ -+ tcg_gen_movi_tl(cpu_eret, ctx->cpc); -+ tcg_gen_movi_tl(cpu_erbta, ctx->npc); -+ -+ gen_helper_raise_exception(cpu_env, tcg_index, tcg_cause, tcg_param); -+ -+ tcg_temp_free(tcg_index); -+ tcg_temp_free(tcg_cause); -+ tcg_temp_free(tcg_param); -+ return false; -+ } -+ return true; -+} -+ -+/* -+ * throw "illegal instruction sequence" exception if we are in a -+ * delay/execution slot. -+ */ -+static bool check_delay_or_execution_slot(const DisasCtxt *ctx) -+{ -+ if (ctx->in_delay_slot) { -+ TCGv tcg_index = tcg_const_tl(EXCP_INST_ERROR); -+ TCGv tcg_cause = tcg_const_tl(0x1); -+ TCGv tcg_param = tcg_const_tl(0x0); -+ -+ tcg_gen_mov_tl(cpu_eret, cpu_pc); -+ tcg_gen_mov_tl(cpu_erbta, cpu_bta); -+ -+ gen_helper_raise_exception(cpu_env, tcg_index, tcg_cause, tcg_param); -+ -+ tcg_temp_free(tcg_index); -+ tcg_temp_free(tcg_cause); -+ tcg_temp_free(tcg_param); -+ return false; -+ } -+ return true; -+} -+ -+/* -+ * Throw "misaligned" exception if 'addr' is not 32-bit aligned. -+ * This check is done irrelevant of status32.AD bit. -+ */ -+static void check_addr_is_word_aligned(const DisasCtxt *ctx, -+ TCGv addr) -+{ -+ TCGLabel *l1 = gen_new_label(); -+ TCGv tmp = tcg_temp_local_new(); -+ -+ tcg_gen_andi_tl(tmp, addr, 0x3); -+ tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, l1); -+ -+ tcg_gen_mov_tl(cpu_efa, addr); -+ tcg_gen_movi_tl(cpu_eret, ctx->cpc); -+ tcg_gen_mov_tl(cpu_erbta, cpu_bta); -+ -+ TCGv tcg_index = tcg_const_tl(EXCP_MISALIGNED); -+ TCGv tcg_cause = tcg_const_tl(0x0); -+ TCGv tcg_param = tcg_const_tl(0x0); -+ -+ gen_helper_raise_exception(cpu_env, tcg_index, tcg_cause, tcg_param); -+ -+ gen_set_label(l1); -+ -+ tcg_temp_free(tcg_index); -+ tcg_temp_free(tcg_cause); -+ tcg_temp_free(tcg_param); -+ tcg_temp_free(tmp); -+} -+ -+ -+ -+/* -+ * enter_s instruction. -+ * after we are done, stack layout would be: -+ * ,- top -. -+ * | blink | -+ * | r13 | -+ * | r14 | -+ * | ... | -+ * | r26 | -+ * | fp | -+ * `-------' -+ */ -+int arc_gen_ENTER(DisasContext *ctx) -+{ -+ int ret = DISAS_NEXT; -+ uint32_t u6 = ctx->insn.operands[0].value; -+ -+ if (!u6) { -+ return ret; -+ } -+ -+ uint8_t regs = u6 & 0x0f; /* u[3:0] determines registers to save */ -+ bool save_fp = u6 & 0x10; /* u[4] indicates if fp must be saved */ -+ bool save_blink = u6 & 0x20; /* u[5] indicates saving of blink */ -+ uint8_t stack_size = 4 * (regs + save_fp + save_blink); -+ -+ /* number of regs to be saved must be sane */ -+ if (!check_enter_leave_nr_regs(ctx, regs)) { -+ return ret; -+ } -+ -+ /* this cannot be executed in a delay/execution slot */ -+ if (!check_delay_or_execution_slot(ctx)) { -+ return ret; -+ } -+ -+ TCGv temp_1 = tcg_temp_local_new(); -+ TCGv temp_sp = tcg_temp_local_new(); -+ -+ /* stack must be a multiple of 4 (32 bit aligned) */ -+ tcg_gen_subi_tl(temp_1, cpu_sp, stack_size); -+ check_addr_is_word_aligned(ctx, temp_1); -+ -+ /* -+ * Backup SP. SP should only be written in the end of the execution to -+ * allow to correctly recover from exceptions the might happen in the -+ * middle of the instruction execution. -+ */ -+ tcg_gen_mov_tl(temp_sp, cpu_sp); -+ -+ if (save_fp) { -+ tcg_gen_subi_tl(temp_sp, temp_sp, 4); -+ tcg_gen_qemu_st_tl(cpu_fp, temp_sp, ctx->mem_idx, MO_UL); -+ } -+ -+ for (uint8_t gpr = regs; gpr >= 1; --gpr) { -+ tcg_gen_subi_tl(temp_sp, temp_sp, 4); -+ tcg_gen_qemu_st_tl(cpu_r[13 + gpr - 1], temp_sp, ctx->mem_idx, MO_UL); -+ } -+ -+ if (save_blink) { -+ tcg_gen_subi_tl(temp_sp, temp_sp, 4); -+ tcg_gen_qemu_st_tl(cpu_blink, temp_sp, ctx->mem_idx, MO_UL); -+ } -+ -+ tcg_gen_mov_tl(cpu_sp, temp_sp); -+ -+ /* now that sp has been allocated, shall we write it to fp? */ -+ if (save_fp) { -+ tcg_gen_mov_tl(cpu_fp, cpu_sp); -+ } -+ -+ tcg_temp_free(temp_sp); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+/* -+ * helper for leave_s instruction. -+ * a stack layout of below is assumed: -+ * ,- top -. -+ * | blink | -+ * | r13 | -+ * | r14 | -+ * | ... | -+ * | r26 | -+ * | fp | -+ * `-------' -+ */ -+int arc_gen_LEAVE(DisasContext *ctx) -+{ -+ int ret = DISAS_NEXT; -+ uint32_t u7 = ctx->insn.operands[0].value; -+ -+ /* nothing to do? then bye-bye! */ -+ if (!u7) { -+ return ret; -+ } -+ -+ uint8_t regs = u7 & 0x0f; /* u[3:0] determines registers to save */ -+ bool restore_fp = u7 & 0x10; /* u[4] indicates if fp must be saved */ -+ bool restore_blink = u7 & 0x20; /* u[5] indicates saving of blink */ -+ bool jump_to_blink = u7 & 0x40; /* u[6] should we jump to blink? */ -+ -+ /* number of regs to be saved must be sane */ -+ if (!check_enter_leave_nr_regs(ctx, regs)) { -+ return ret; -+ } -+ -+ /* this cannot be executed in a delay/execution slot */ -+ if (!check_delay_or_execution_slot(ctx)) { -+ return ret; -+ } -+ -+ TCGv temp_1 = tcg_temp_local_new(); -+ /* -+ * stack must be a multiple of 4 (32 bit aligned). we must take into -+ * account if sp is going to use fp's value or not. -+ */ -+ if (restore_fp) { -+ tcg_gen_mov_tl(temp_1, cpu_fp); -+ } else { -+ tcg_gen_mov_tl(temp_1, cpu_sp); -+ } -+ check_addr_is_word_aligned(ctx, temp_1); -+ -+ TCGv temp_sp = tcg_temp_local_new(); -+ /* -+ * if fp is in the picture, then first we have to use the current -+ * fp as the stack pointer for restoring. -+ */ -+ if (restore_fp) { -+ tcg_gen_mov_tl(cpu_sp, cpu_fp); -+ } -+ -+ tcg_gen_mov_tl(temp_sp, cpu_sp); -+ -+ if (restore_blink) { -+ tcg_gen_qemu_ld_tl(cpu_blink, temp_sp, ctx->mem_idx, MO_UL); -+ tcg_gen_addi_tl(temp_sp, temp_sp, 4); -+ } -+ -+ for (uint8_t gpr = 0; gpr < regs; ++gpr) { -+ tcg_gen_qemu_ld_tl(cpu_r[13 + gpr], temp_sp, ctx->mem_idx, MO_UL); -+ tcg_gen_addi_tl(temp_sp, temp_sp, 4); -+ } -+ -+ if (restore_fp) { -+ tcg_gen_qemu_ld_tl(cpu_fp, temp_sp, ctx->mem_idx, MO_UL); -+ tcg_gen_addi_tl(temp_sp, temp_sp, 4); -+ } -+ -+ tcg_gen_mov_tl(cpu_sp, temp_sp); -+ -+ /* now that we are done, should we jump to blink? */ -+ if (jump_to_blink) { -+ gen_goto_tb(ctx, 1, cpu_blink); -+ ret = DISAS_NORETURN; -+ } -+ -+ tcg_temp_free(temp_sp); -+ tcg_temp_free(temp_1); -+ -+ return ret; -+} -+ -+/* SR tcg translator */ -+int -+arc_gen_SR(DisasCtxt *ctx, TCGv src2, TCGv src1) -+{ -+ int ret = DISAS_NEXT; -+ -+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) -+ gen_io_start(); -+ -+#ifdef TARGET_ARCV2 -+ writeAuxReg(src2, src1); -+#elif defined(TARGET_ARCV3) -+ TCGv temp = tcg_temp_local_new(); -+ tcg_gen_andi_tl(temp, src1, 0xffffffff); -+ writeAuxReg(src2, src1); -+ tcg_temp_free(temp); -+#endif -+ return ret; -+} -+int -+arc_gen_SRL(DisasCtxt *ctx, TCGv src2, TCGv src1) -+{ -+ int ret = DISAS_NEXT; -+ -+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) -+ gen_io_start(); -+ -+ writeAuxReg(src2, src1); -+ return ret; -+} -+ -+/* SYNC tcg translator */ -+int -+arc_gen_SYNC(DisasCtxt *ctx) -+{ -+ int ret = DISAS_NEXT; -+ -+ syncReturnDisasUpdate(); -+ return ret; -+} -+ -+ -+#ifdef TARGET_ARCV3 -+/* -+ * The mpyl instruction is a 64x64 signed multipler that produces -+ * a 64-bit product (the lower 64-bit of the actual prodcut). -+ */ -+int -+arc_gen_MPYL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ if ((getFFlag () == true)) { -+ arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); -+ return DISAS_NEXT; -+ } -+ -+ TCGLabel *done = gen_new_label(); -+ -+ if (ctx->insn.cc) { -+ TCGv cc = tcg_temp_local_new(); -+ arc_gen_verifyCCFlag(ctx, cc); -+ tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done); -+ tcg_temp_free(cc); -+ } -+ -+ TCGv_i64 lo = tcg_temp_local_new_i64(); -+ TCGv_i64 hi = tcg_temp_local_new_i64(); -+ -+ tcg_gen_muls2_i64(lo, hi, b, c); -+ tcg_gen_mov_tl(a, lo); -+ -+ tcg_temp_free_i64(hi); -+ tcg_temp_free_i64(lo); -+ gen_set_label(done); -+ -+ return DISAS_NEXT; -+} -+ -+/* -+ * The mpyml instruction is a 64x64 signed multipler that produces -+ * a 64-bit product (the higher 64-bit of the actual prodcut). -+ */ -+int -+arc_gen_MPYML(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ if ((getFFlag () == true)) { -+ arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); -+ return DISAS_NEXT; -+ } -+ -+ TCGLabel *done = gen_new_label(); -+ -+ if (ctx->insn.cc) { -+ TCGv cc = tcg_temp_local_new(); -+ arc_gen_verifyCCFlag(ctx, cc); -+ tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done); -+ tcg_temp_free(cc); -+ } -+ -+ TCGv lo = tcg_temp_local_new(); -+ TCGv hi = tcg_temp_local_new(); -+ tcg_gen_muls2_i64(lo, hi, b, c); -+ tcg_gen_mov_tl(a, hi); -+ -+ tcg_temp_free(hi); -+ tcg_temp_free(lo); -+ gen_set_label(done); -+ -+ return DISAS_NEXT; -+} -+ -+/* -+ * The mpymul instruction is a 64x64 unsigned multipler that produces -+ * a 64-bit product (the higher 64-bit of the actual prodcut). -+ */ -+int -+arc_gen_MPYMUL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ if ((getFFlag () == true)) { -+ arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); -+ return DISAS_NEXT; -+ } -+ -+ TCGLabel *done = gen_new_label(); -+ -+ if (ctx->insn.cc) { -+ TCGv cc = tcg_temp_local_new(); -+ arc_gen_verifyCCFlag(ctx, cc); -+ tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done); -+ tcg_temp_free(cc); -+ } -+ -+ TCGv lo = tcg_temp_local_new(); -+ TCGv hi = tcg_temp_local_new(); -+ -+ tcg_gen_mulu2_i64(lo, hi, b, c); -+ tcg_gen_mov_tl(a, hi); -+ -+ tcg_temp_free(hi); -+ tcg_temp_free(lo); -+ gen_set_label(done); -+ -+ return DISAS_NEXT; -+} -+ -+/* -+ * The mpymsul instruction is a 64x64 signedxunsigned multipler that -+ * produces * a 64-bit product (the higher 64-bit of the actual prodcut). -+ */ -+int -+arc_gen_MPYMSUL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ if ((getFFlag () == true)) { -+ arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); -+ return DISAS_NEXT; -+ } -+ -+ TCGLabel *done = gen_new_label(); -+ -+ if (ctx->insn.cc) { -+ TCGv cc = tcg_temp_local_new(); -+ arc_gen_verifyCCFlag(ctx, cc); -+ tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done); -+ tcg_temp_free(cc); -+ } -+ -+ TCGv lo = tcg_temp_local_new(); -+ TCGv hi = tcg_temp_local_new(); -+ tcg_gen_mulsu2_tl(lo, hi, b, c); -+ tcg_gen_mov_tl(a, hi); -+ -+ tcg_temp_free(hi); -+ tcg_temp_free(lo); -+ gen_set_label(done); -+ -+ return DISAS_NEXT; -+} -+ -+/* -+ * a = b + (c << 32) -+ */ -+int -+arc_gen_ADDHL(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) -+{ -+ TCGLabel *done = gen_new_label(); -+ -+ if (ctx->insn.cc) { -+ TCGv cc = tcg_temp_local_new(); -+ arc_gen_verifyCCFlag(ctx, cc); -+ tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done); -+ tcg_temp_free(cc); -+ } -+ -+ TCGv shifted = tcg_temp_local_new(); -+ tcg_gen_shli_tl(shifted, c, 32); -+ tcg_gen_add_tl(a, b, shifted); -+ -+ tcg_temp_free(shifted); -+ gen_set_label(done); -+ -+ return DISAS_NEXT; -+} -+ -+#endif -+#ifdef TARGET_ARCV2 -+ -+/* -+ * Function to add boiler plate code for conditional execution. -+ * It will add tcg_gen codes only if there is a condition to -+ * be checked (ctx->insn.cc != 0). -+ * Remember to pair it with gen_cc_epilogue(ctx) macro. -+ */ -+static void gen_cc_prologue(DisasCtxt *ctx) -+{ -+ ctx->tmp_reg = tcg_temp_local_new(); -+ ctx->label = gen_new_label(); -+ if (ctx->insn.cc) { -+ arc_gen_verifyCCFlag(ctx, ctx->tmp_reg); -+ tcg_gen_brcondi_tl(TCG_COND_NE, ctx->tmp_reg, 1, ctx->label); -+ } -+} -+ -+/* -+ * The finishing counter part of gen_cc_prologue. This is supposed -+ * to be put at the end of the function using it. -+ */ -+static void gen_cc_epilogue(const DisasCtxt *ctx) -+{ -+ if (ctx->insn.cc) { -+ gen_set_label(ctx->label); -+ } -+ tcg_temp_free(ctx->tmp_reg); -+} -+ -+/* -+ * Verifies if the destination operand (operand 0) is a register -+ * then it is an even numbered one. Else, an exception is put in -+ * the generated code and FALSE is returned. -+ */ -+static bool verify_dest_reg_is_even(const DisasCtxt *ctx) -+{ -+ if (is_odd_numbered_register(ctx->insn.operands[0])) { -+ arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); -+ return false; -+ } -+ return true; -+} -+ -+ -+/* accumulator = b32 * c32 (signed multiplication). */ -+int -+arc_gen_MPYD(DisasCtxt *ctx, TCGv_i32 dest, -+ TCGv_i32 b32, TCGv_i32 c32) -+{ -+ if (verify_dest_reg_is_even(ctx)) { -+ gen_cc_prologue(ctx); -+ tcg_gen_muls2_i32(cpu_acclo, cpu_acchi, b32, c32); -+ if (ctx->insn.operands[0].type & ARC_OPERAND_IR) { -+ tcg_gen_mov_tl(arc_gen_next_reg(ctx, dest), cpu_acchi); -+ tcg_gen_mov_tl(dest, cpu_acclo); -+ } -+ if (ctx->insn.f) { -+ setNFlag(cpu_acchi); -+ tcg_gen_movi_tl(cpu_Vf, 0); -+ } -+ gen_cc_epilogue(ctx); -+ } -+ return DISAS_NEXT; -+} -+ -+/* accumulator = b32 * c32 (unsigned multiplication). */ -+int -+arc_gen_MPYDU(DisasCtxt *ctx, TCGv_i32 dest, -+ TCGv_i32 b32, TCGv_i32 c32) -+{ -+ if (verify_dest_reg_is_even(ctx)) { -+ gen_cc_prologue(ctx); -+ tcg_gen_mulu2_i32(cpu_acclo, cpu_acchi, b32, c32); -+ if (ctx->insn.operands[0].type & ARC_OPERAND_IR) { -+ tcg_gen_mov_tl(arc_gen_next_reg(ctx, dest), cpu_acchi); -+ tcg_gen_mov_tl(dest, cpu_acclo); -+ } -+ if (ctx->insn.f) { -+ tcg_gen_movi_tl(cpu_Vf, 0); -+ } -+ gen_cc_epilogue(ctx); -+ } -+ return DISAS_NEXT; -+} -+ -+/* -+ * Populates a 64-bit vector with register pair: -+ * vec64=(REGn+1,REGn)=(REGn+1_hi,REGn+1_lo,REGn_hi,REGn_lo) -+ * REG must be refering to an even numbered register. -+ * Do not forget to free the returned TCGv_i64 when done! -+ */ -+static TCGv_i64 pair_reg_to_i64(const DisasCtxt *ctx, TCGv_i32 reg) -+{ -+ TCGv_i64 vec64 = tcg_temp_new_i64(); -+ tcg_gen_concat_i32_i64(vec64, reg, arc_gen_next_reg(ctx, reg)); -+ return vec64; -+} -+ -+/* -+ * Populates a 32-bit vector with repeating SHIMM: -+ * vec32=(0000000000u6,0000000000u6) -+ * vec32=(sssss12,sssss12) -+ * It's crucial that the s12 part of an encoding is in signed -+ * integer form while passed along in SHIMM, e.g: -+ * s12 = -125 (0xf803) --> 0xfffff803 -+ * Do not forget to free the returned TCGv_i32 when done! -+ */ -+static TCGv_i32 dup_shimm_to_i32(int16_t shimm) -+{ -+ TCGv_i32 vec32 = tcg_temp_new_i32(); -+ int32_t val = shimm; -+ val = ((val << 16) & 0xffff0000) | (val & 0xffff); -+ tcg_gen_movi_i32(vec32, val); -+ return vec32; -+} -+ -+/* -+ * Populates a 64-bit vector with repeating LIMM: -+ * vec64=(limm,limm)=(limm_hi,limm_lo,limm_hi,limm_lo) -+ * Do not forget to free the returned TCGv_i64 when done! -+ */ -+static TCGv_i64 dup_limm_to_i64(int32_t limm) -+{ -+ TCGv_i64 vec64 = tcg_temp_new_i64(); -+ int64_t val = limm; -+ val = (val << 32) | (val & 0xffffffff); -+ tcg_gen_movi_i64(vec64, val); -+ return vec64; -+} -+ -+/* -+ * Populates a 64-bit vector with four SHIMM (u6 or s12): -+ * vec64=(0000000000u6,0000000000u6,0000000000u6,0000000000u6) -+ * vec64=(sssss12,sssss12,sssss12,sssss12) -+ * It's crucial that the s12 part of an encoding is in signed -+ * integer form while passed along in SHIMM, e.g: -+ * s12 = -125 (0xf803) --> 0xfffff803 -+ * Do not forget to free the returned TCGv_i64 when done! -+ */ -+static TCGv_i64 quad_shimm_to_i64(int16_t shimm) -+{ -+ TCGv_i64 vec64 = tcg_temp_new_i64(); -+ int64_t val = shimm; -+ val = (val << 48) | ((val << 32) & 0x0000ffff00000000) | -+ ((val << 16) & 0x00000000ffff0000) | (val & 0xffff); -+ tcg_gen_movi_i64(vec64, val); -+ return vec64; -+} -+ -+/* -+ * gen_vec_op2 emits instructions to perform the desired operation, -+ * defined by OP, on the inputs (B32 and C32) and returns the -+ * result in DEST. -+ * -+ * vector size: 64-bit -+ * vector elements: 2 -+ * element size: 32-bit -+ * -+ * (A1, A0) = (B1, B0) op (C1, C0) -+ */ -+static void gen_vec_op2(const DisasCtxt *ctx, -+ void (*OP)(TCGv_i64, TCGv_i64, TCGv_i64), -+ TCGv_i32 dest, -+ TCGv_i32 b32, -+ TCGv_i32 c32) -+{ -+ TCGv_i64 d64, b64, c64; -+ -+ /* If no real register for result, then this a nop. Bail out! */ -+ if (!(ctx->insn.operands[0].type & ARC_OPERAND_IR)) { -+ return; -+ } -+ -+ /* Extend B32 to B64 based on its type: {reg, limm}. */ -+ if (ctx->insn.operands[1].type & ARC_OPERAND_IR) { -+ b64 = pair_reg_to_i64(ctx, b32); -+ } else if (ctx->insn.operands[1].type & ARC_OPERAND_LIMM) { -+ b64 = dup_limm_to_i64(ctx->insn.limm); -+ } else { -+ g_assert_not_reached(); -+ } -+ /* Extend C32 to C64 based on its type: {reg, limm, shimm}. */ -+ if (ctx->insn.operands[2].type & ARC_OPERAND_IR) { -+ c64 = pair_reg_to_i64(ctx, c32); -+ } else if (ctx->insn.operands[2].type & ARC_OPERAND_LIMM) { -+ c64 = dup_limm_to_i64(ctx->insn.limm); -+ } else if (ctx->insn.operands[2].type & ARC_OPERAND_SHIMM) { -+ /* At this point SHIMM is extended like LIMM. */ -+ c64 = dup_limm_to_i64(ctx->insn.operands[2].value); -+ } else { -+ g_assert_not_reached(); -+ } -+ d64 = tcg_temp_new_i64(); -+ -+ (*OP)(d64, b64, c64); -+ tcg_gen_extrl_i64_i32(dest, d64); -+ tcg_gen_extrh_i64_i32(arc_gen_next_reg(ctx, dest), d64); -+ -+ tcg_temp_free_i64(d64); -+ tcg_temp_free_i64(c64); -+ tcg_temp_free_i64(b64); -+ return; -+} -+ -+/* -+ * gen_vec_op2h emits instructions to perform the desired operation, -+ * defined by OP, on the inputs (B32 and C32) and returns the -+ * result in DEST. -+ * -+ * vector size: 32-bit -+ * vector elements: 2 -+ * element size: 16-bit -+ * -+ * (a1, a0) = (b1, b0) op (c1, c0) -+ */ -+static void gen_vec_op2h(const DisasCtxt *ctx, -+ void (*OP)(TCGv, TCGv, TCGv), -+ TCGv_i32 dest, -+ TCGv_i32 b32, -+ TCGv_i32 c32) -+{ -+ TCGv_i32 t0, t1; -+ -+ /* If no real register for result, then this a nop. Bail out! */ -+ if (!(ctx->insn.operands[0].type & ARC_OPERAND_IR)) { -+ return; -+ } -+ -+ t0 = tcg_temp_new(); -+ tcg_gen_mov_i32(t0, b32); -+ /* -+ * If the last operand is a u6/s12, say 63, there is no "HI" in it. -+ * Instead, it must be duplicated to form a pair; e.g.: (63, 63). -+ */ -+ if (ctx->insn.operands[2].type & ARC_OPERAND_SHIMM) { -+ t1 = dup_shimm_to_i32(ctx->insn.operands[2].value); -+ } else { -+ t1 = tcg_temp_new(); -+ tcg_gen_mov_i32(t1, c32); -+ } -+ -+ (*OP)(dest, t0, t1); -+ -+ tcg_temp_free(t1); -+ tcg_temp_free(t0); -+} -+ -+ -+/* -+ * gen_vec_op4h emits instructions to perform the desired operation, -+ * defined by OP, on the inputs (B32 and C32) and returns the -+ * result in DEST. -+ * -+ * vector size: 64-bit -+ * vector elements: 4 -+ * element size: 16-bit -+ * -+ * (a3, a2, a1, a0) = (b3, b2, b1, b0) op (c3, c2, c1, c0) -+ */ -+static void gen_vec_op4h(const DisasCtxt *ctx, -+ void (*op)(TCGv_i64, TCGv_i64, TCGv_i64), -+ TCGv_i32 dest, -+ TCGv_i32 b32, -+ TCGv_i32 c32) -+{ -+ TCGv_i64 d64, b64, c64; -+ -+ /* If no real register for result, then this a nop. Bail out! */ -+ if (!(ctx->insn.operands[0].type & ARC_OPERAND_IR)) { -+ return; -+ } -+ -+ /* Extend B32 to B64 based on its type: {reg, limm}. */ -+ if (ctx->insn.operands[1].type & ARC_OPERAND_IR) { -+ b64 = pair_reg_to_i64(ctx, b32); -+ } else if (ctx->insn.operands[1].type & ARC_OPERAND_LIMM) { -+ b64 = dup_limm_to_i64(ctx->insn.limm); -+ } else { -+ g_assert_not_reached(); -+ } -+ /* Extend C32 to C64 based on its type: {reg, limm, shimm}. */ -+ if (ctx->insn.operands[2].type & ARC_OPERAND_IR) { -+ c64 = pair_reg_to_i64(ctx, c32); -+ } else if (ctx->insn.operands[2].type & ARC_OPERAND_LIMM) { -+ c64 = dup_limm_to_i64(ctx->insn.limm); -+ } else if (ctx->insn.operands[2].type & ARC_OPERAND_SHIMM) { -+ c64 = quad_shimm_to_i64(ctx->insn.operands[2].value); -+ } else { -+ g_assert_not_reached(); -+ } -+ d64 = tcg_temp_new_i64(); -+ -+ (*op)(d64, b64, c64); -+ tcg_gen_extrl_i64_i32(dest, d64); -+ tcg_gen_extrh_i64_i32(arc_gen_next_reg(ctx, dest), d64); -+ -+ tcg_temp_free_i64(d64); -+ tcg_temp_free_i64(c64); -+ tcg_temp_free_i64(b64); -+ return; -+} -+ -+/* -+ * To use a 32-bit adder to sum two 16-bit numbers: -+ * 1) Mask out the 16th bit in both operands to cause no carry. -+ * 2) Add the numbers. -+ * 3) Put back the 16th bit sum: T0[15] ^ T1[15] ^ CARRY[14] -+ * (ignoring the possible carry generated) -+ * T0 and T1 values will change. Use temporary ones. -+ */ -+static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) -+{ -+ TCGv_i32 tmp = tcg_temp_new_i32(); -+ tcg_gen_xor_i32(tmp, t0, t1); -+ tcg_gen_andi_i32(tmp, tmp, 0x8000); -+ tcg_gen_andi_i32(t0, t0, ~0x8000); -+ tcg_gen_andi_i32(t1, t1, ~0x8000); -+ tcg_gen_add_i32(t0, t0, t1); -+ tcg_gen_xor_i32(dest, t0, tmp); -+ tcg_temp_free_i32(tmp); -+} -+ -+/* -+ * To use a 32-bit subtracter to subtract two 16-bit numbers: -+ * 0) Record how T0[15]-T1[15] would result without other bits. -+ * 1) Make the 16th bit for the first operand 1 and the second -+ * operand 0. This combination of (1 - 0) will absorb any -+ * possible borrow that may come from the 15th bit. -+ * 2) Subtract the numbers. -+ * 3) Correct the 16th bit result (1 - 0 - B): -+ * If the 16th bit is 1 --> no borrow was asked. -+ * If the 16th bit is 0 --> a borrow was asked. -+ * and if a borrow was asked, the result of step 0 must be -+ * inverted (0 -> 1 and 1 -> 0). If not, the result of step -+ * 0 can be used readily: -+ * STEP2[15] | T0[15]-T1[15] | DEST[15] -+ * ----------+---------------+--------- -+ * 0 | 0 | 1 -+ * 0 | 1 | 0 -+ * 1 | 0 | 0 -+ * 1 | 1 | 1 -+ * This is a truth table for XNOR(a,b): -+ * NOT(XOR(a,b))=XOR(XOR(a,b),1) -+ * This approach might seem pedantic, but it generates one less -+ * instruction than the obvious mask-and-sub approach and requires -+ * two less TCG variables. -+ * T0 and T1 values will change. Use temporary ones. -+ */ -+static void gen_sub16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) -+{ -+ TCGv_i32 tmp = tcg_temp_new_i32(); -+ tcg_gen_xor_i32(tmp, t0, t1); /* step 0 */ -+ tcg_gen_andi_i32(tmp, tmp, 0x8000); /* step 0 */ -+ tcg_gen_ori_i32(t0, t0, 0x8000); /* step 1 */ -+ tcg_gen_andi_i32(t1, t1, ~0x8000); /* step 1 */ -+ tcg_gen_sub_i32(t0, t0, t1); /* step 2 */ -+ tcg_gen_xor_i32(dest, t0, tmp); /* step 3 */ -+ tcg_gen_xori_i32(dest, dest, 0x8000); /* step 3 */ -+ tcg_temp_free_i32(tmp); -+} -+ -+/* -+ * Going through every operand, if any of those is a register -+ * it is verified to be an even numbered register. Else, an -+ * exception is put in the generated code and FALSE is returned. -+ */ -+static bool verify_all_regs_are_even(const DisasCtxt *ctx) -+{ -+ for (int nop = 0; nop < ctx->insn.n_ops; ++nop) { -+ if (is_odd_numbered_register(ctx->insn.operands[nop])) { -+ arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); -+ return false; -+ } -+ } -+ return true; -+} -+ -+ -+int -+arc_gen_VADD2(DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) -+{ -+ if (verify_all_regs_are_even(ctx)) { -+ gen_cc_prologue(ctx); -+ gen_vec_op2(ctx, tcg_gen_vec_add32_i64, dest, b, c); -+ gen_cc_epilogue(ctx); -+ } -+ return DISAS_NEXT; -+} -+ -+int -+arc_gen_VADD2H(DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) -+{ -+ gen_cc_prologue(ctx); -+ gen_vec_op2h(ctx, gen_add16, dest, b, c); -+ gen_cc_epilogue(ctx); -+ return DISAS_NEXT; -+} -+ -+int -+arc_gen_VADD4H(DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) -+{ -+ if (verify_all_regs_are_even(ctx)) { -+ gen_cc_prologue(ctx); -+ gen_vec_op4h(ctx, tcg_gen_vec_add16_i64, dest, b, c); -+ gen_cc_epilogue(ctx); -+ } -+ return DISAS_NEXT; -+} -+ -+int -+arc_gen_VSUB2(DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) -+{ -+ if (verify_all_regs_are_even(ctx)) { -+ gen_cc_prologue(ctx); -+ gen_vec_op2(ctx, tcg_gen_vec_sub32_i64, dest, b, c); -+ gen_cc_epilogue(ctx); -+ } -+ return DISAS_NEXT; -+} -+ -+int -+arc_gen_VSUB2H(DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) -+{ -+ gen_cc_prologue(ctx); -+ gen_vec_op2h(ctx, gen_sub16, dest, b, c); -+ gen_cc_epilogue(ctx); -+ return DISAS_NEXT; -+} -+ -+int -+arc_gen_VSUB4H(DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) -+{ -+ if (verify_all_regs_are_even(ctx)) { -+ gen_cc_prologue(ctx); -+ gen_vec_op4h(ctx, tcg_gen_vec_sub16_i64, dest, b, c); -+ gen_cc_epilogue(ctx); -+ } -+ return DISAS_NEXT; -+} -+#endif -+ -+int -+arc_gen_SWI(DisasCtxt *ctx, TCGv a) -+{ -+ TCGv tcg_index = tcg_const_tl(EXCP_SWI); -+ TCGv tcg_cause = tcg_const_tl(0); -+ -+ tcg_gen_movi_tl(cpu_pc, ctx->cpc); -+ tcg_gen_movi_tl(cpu_eret, ctx->cpc); -+ tcg_gen_movi_tl(cpu_erbta, ctx->npc); -+ -+ gen_helper_raise_exception(cpu_env, tcg_index, tcg_cause, a); -+ -+ tcg_temp_free(tcg_index); -+ tcg_temp_free(tcg_cause); -+ return DISAS_NEXT; -+} -+int -+arc_gen_TRAP(DisasCtxt *ctx, TCGv a) -+{ -+ TCGv tcg_index = tcg_const_tl(EXCP_TRAP); -+ TCGv tcg_cause = tcg_const_tl(0); -+ -+ tcg_gen_movi_tl(cpu_pc, ctx->cpc); -+ tcg_gen_movi_tl(cpu_eret, ctx->npc); -+ tcg_gen_mov_tl(cpu_erbta, cpu_bta); -+ -+ gen_helper_raise_exception(cpu_env, tcg_index, tcg_cause, a); -+ -+ tcg_temp_free(tcg_index); -+ tcg_temp_free(tcg_cause); -+ -+ return DISAS_NORETURN; -+} -+int -+arc_gen_RTIE(DisasCtxt *ctx) -+{ -+ tcg_gen_movi_tl(cpu_pc, ctx->cpc); -+ gen_helper_rtie(cpu_env); -+ tcg_gen_mov_tl(cpu_pc, cpu_pcl); -+ exit_tb(ctx); /* no chaining */ -+ return DISAS_NORETURN; -+} -+ -+/* Generate sleep insn. */ -+int -+arc_gen_SLEEP(DisasCtxt *ctx, TCGv a) -+{ -+ uint32_t param = 0; -+ -+ if (ctx->insn.operands[0].type & ARC_OPERAND_IR) { -+ TCGv tmp3 = tcg_temp_local_new(); -+ TCGLabel *done_L = gen_new_label(); -+ -+ tcg_gen_andi_tl(tmp3, a, 0x10); -+ tcg_gen_brcondi_tl(TCG_COND_NE, tmp3, 0x10, done_L); -+ tcg_gen_andi_tl(cpu_Ef, a, 0x0f); -+ tcg_gen_movi_tl(cpu_IEf, 1); -+ gen_set_label(done_L); -+ -+ tcg_temp_free(tmp3); -+ } else { -+ param = ctx->insn.operands[0].value; -+ if (param & 0x10) { -+ tcg_gen_movi_tl(cpu_IEf, 1); -+ tcg_gen_movi_tl(cpu_Ef, param & 0x0f); -+ } -+ } -+ /* FIXME: setup debug registers as well. */ -+ -+ TCGv npc = tcg_temp_local_new(); -+ tcg_gen_movi_tl(npc, ctx->npc); -+ gen_helper_halt(cpu_env, npc); -+ tcg_temp_free(npc); -+ return DISAS_NEXT; -+} -+ -+/* Given a CTX, generate the relevant TCG code for the given opcode. */ -+static int arc_decode(DisasContext *ctx, const struct arc_opcode *opcode) -+{ -+ int ret = DISAS_NEXT; -+ enum arc_opcode_map mapping; -+ static bool initialized; -+ -+ if (initialized == false) { -+ init_constants(); -+ initialized = true; -+ } -+ -+ /* Do the mapping. */ -+ mapping = arc_map_opcode(opcode); -+ if (mapping != MAP_NONE) { -+ TCGv ops[10]; -+ int i; -+ for (i = 0; i < number_of_ops_semfunc[mapping]; i++) { -+ ops[i] = arc_decode_operand(opcode, ctx, i, mapping); -+ } -+ -+ /* -+ * Store some elements statically to implement less dynamic -+ * features of instructions. Started by the need to keep a -+ * static reference to LP_START and LP_END. -+ */ -+ -+#define SEMANTIC_FUNCTION_CALL_0(NAME, A) \ -+ arc_gen_##NAME(ctx); -+#define SEMANTIC_FUNCTION_CALL_1(NAME, A) \ -+ arc_gen_##NAME(ctx, ops[A]); -+#define SEMANTIC_FUNCTION_CALL_2(NAME, A, B) \ -+ arc_gen_##NAME(ctx, ops[A], ops[B]); -+#define SEMANTIC_FUNCTION_CALL_3(NAME, A, B, C) \ -+ arc_gen_##NAME(ctx, ops[A], ops[B], ops[C]); -+#define SEMANTIC_FUNCTION_CALL_4(NAME, A, B, C, D) \ -+ arc_gen_##NAME(ctx, ops[A], ops[B], ops[C], ops[D]); -+ -+#define SEMANTIC_FUNCTION(...) -+#define CONSTANT(...) -+#define MAPPING(MNEMONIC, NAME, NOPS, ...) \ -+ case MAP_##MNEMONIC##_##NAME: \ -+ ret = SEMANTIC_FUNCTION_CALL_##NOPS(NAME, __VA_ARGS__); \ -+ break; -+ switch (mapping) { -+#include "target/arc/semfunc_mapping.def" -+#include "target/arc/extra_mapping.def" -+ -+ default: -+ arc_debug_opcode(opcode, ctx, "No handle for map opcode"); -+ arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); -+ } -+#undef MAPPING -+#undef CONSTANT -+#undef SEMANTIC_FUNCTION -+#undef SEMANTIC_FUNCTION_CALL_0 -+#undef SEMANTIC_FUNCTION_CALL_1 -+#undef SEMANTIC_FUNCTION_CALL_2 -+#undef SEMANTIC_FUNCTION_CALL_3 -+ -+ for (i = 0; i < number_of_ops_semfunc[mapping]; i++) { -+ operand_t operand = ctx->insn.operands[i]; -+ if (!(operand.type & ARC_OPERAND_LIMM) && -+ !(operand.type & ARC_OPERAND_IR)) { -+ tcg_temp_free(ops[i]); -+ } -+ } -+ -+ } else { -+ arc_debug_opcode(opcode, ctx, "No mapping for opcode"); -+ arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); -+ } -+ -+ return ret; -+} -+ -+void decode_opc(CPUARCState *env, DisasContext *ctx) -+{ -+ ctx->env = env; -+ -+ env->enabled_interrupts = false; -+ -+ const struct arc_opcode *opcode = NULL; -+ if (!read_and_decode_context(ctx, &opcode)) { -+ ctx->base.is_jmp = arc_gen_INVALID(ctx); -+ return; -+ } -+ -+ ctx->base.is_jmp = arc_decode(ctx, opcode); -+ -+ TCGv npc = tcg_const_local_tl(ctx->npc); -+ gen_helper_zol_verify(cpu_env, npc); -+ tcg_temp_free(npc); -+ -+ env->enabled_interrupts = true; -+} -+ -+static void arc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) -+{ -+ bool in_a_delayslot_instruction = false; -+ DisasContext *dc = container_of(dcbase, DisasContext, base); -+ CPUARCState *env = cpu->env_ptr; -+ -+ /* TODO (issue #62): these must be removed */ -+ dc->zero = tcg_const_local_tl(0); -+ dc->one = tcg_const_local_tl(1); -+ -+ if (env->stat.is_delay_slot_instruction == 1) { -+ in_a_delayslot_instruction = true; -+ } -+ -+ dc->cpc = dc->base.pc_next; -+ decode_opc(env, dc); -+ -+ dc->base.pc_next = dc->npc; -+ tcg_gen_movi_tl(cpu_npc, dc->npc); -+ -+ if (in_a_delayslot_instruction == true) { -+ dc->base.is_jmp = DISAS_NORETURN; -+ -+ /* Post execution delayslot logic. */ -+ TCGLabel *DEf_not_set_label1 = gen_new_label(); -+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_DEf, 1, DEf_not_set_label1); -+ tcg_gen_movi_tl(cpu_DEf, 0); -+ gen_goto_tb(dc, 1, cpu_bta); -+ gen_set_label(DEf_not_set_label1); -+ env->stat.is_delay_slot_instruction = 0; -+ } -+ -+ if (dc->base.is_jmp == DISAS_NORETURN) { -+ gen_gotoi_tb(dc, 0, dc->npc); -+ } else if (dc->base.is_jmp == DISAS_NEXT) { -+ target_ulong page_start; -+ -+ page_start = dc->base.pc_first & TARGET_PAGE_MASK; -+ if (dc->base.pc_next - page_start >= TARGET_PAGE_SIZE) { -+ dc->base.is_jmp = DISAS_TOO_MANY; -+ } -+ } -+ -+ /* TODO (issue #62): these must be removed. */ -+ tcg_temp_free(dc->zero); -+ tcg_temp_free(dc->one); -+ -+ /* verify if there is any TCG temporaries leakge */ -+ translator_loop_temp_check(dcbase); -+} -+ -+static void arc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) -+{ -+ DisasContext *dc = container_of(dcbase, DisasContext, base); -+ -+ switch (dc->base.is_jmp) { -+ case DISAS_TOO_MANY: -+ case DISAS_UPDATE: -+ gen_gotoi_tb(dc, 0, dc->base.pc_next); -+ break; -+ case DISAS_BRANCH_IN_DELAYSLOT: -+ case DISAS_NORETURN: -+ break; -+ default: -+ g_assert_not_reached(); -+ } -+ -+ if (dc->base.num_insns == dc->base.max_insns && -+ (dc->base.tb->cflags & CF_LAST_IO)) { -+ gen_io_end(); -+ } -+} -+ -+static void arc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) -+{ -+ DisasContext *dc = container_of(dcbase, DisasContext, base); -+ -+ qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); -+ log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size); -+} -+ -+ -+static const TranslatorOps arc_translator_ops = { -+ .init_disas_context = arc_tr_init_disas_context, -+ .tb_start = arc_tr_tb_start, -+ .insn_start = arc_tr_insn_start, -+ .breakpoint_check = arc_tr_breakpoint_check, -+ .translate_insn = arc_tr_translate_insn, -+ .tb_stop = arc_tr_tb_stop, -+ .disas_log = arc_tr_disas_log, -+}; -+ -+/* generate intermediate code for basic block 'tb'. */ -+void gen_intermediate_code(CPUState *cpu, -+ TranslationBlock *tb, -+ int max_insns) -+{ -+ DisasContext dc; -+ const TranslatorOps *ops = &arc_translator_ops; -+ translator_loop(ops, &dc.base, cpu, tb, max_insns); -+} -+ -+void restore_state_to_opc(CPUARCState *env, -+ TranslationBlock *tb, -+ target_ulong *data) -+{ -+ env->pc = data[0]; -+} -+ -+void arc_cpu_dump_state(CPUState *cs, FILE *f, int flags) -+{ -+ ARCCPU *cpu = ARC_CPU(cs); -+ CPUARCState *env = &cpu->env; -+ int i; -+ -+ -+ qemu_fprintf(f, -+ "STATUS: [ %c %c %c %c %c %c %s %s %s %s %s %s %c]\n", -+ GET_STATUS_BIT(env->stat, Lf) ? 'L' : '-', -+ env->stat.Zf ? 'Z' : '-', -+ env->stat.Nf ? 'N' : '-', -+ env->stat.Cf ? 'C' : '-', -+ env->stat.Vf ? 'V' : '-', -+ GET_STATUS_BIT(env->stat, Uf) ? 'U' : '-', -+ env->stat.DEf ? "DE" : "--", -+ GET_STATUS_BIT(env->stat, AEf) ? "AE" : "--", -+ env->stat.Ef ? "E" : "--", -+ GET_STATUS_BIT(env->stat, DZf) ? "DZ" : "--", -+ GET_STATUS_BIT(env->stat, SCf) ? "SC" : "--", -+ env->stat.IEf ? "IE" : "--", -+ GET_STATUS_BIT(env->stat, Hf) ? 'H' : '-' -+ ); -+ -+ qemu_fprintf(f, "\n"); -+ for (i = 0; i < ARRAY_SIZE(env->r); i++) { -+ qemu_fprintf(f, "R[%02d]: " TARGET_FMT_lx " ", i, env->r[i]); -+ -+ if ((i % 8) == 7) { -+ qemu_fprintf(f, "\n"); -+ } -+ } -+} -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/arc/translate.h b/target/arc/translate.h -new file mode 100644 -index 0000000000..3986c2298e ---- /dev/null -+++ b/target/arc/translate.h -@@ -0,0 +1,168 @@ -+/* -+ * QEMU ARC CPU -+ * -+ * Copyright (c) 2020 Synppsys Inc. -+ * -+ * This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU Lesser General Public -+ * License as published by the Free Software Foundation; either -+ * version 2.1 of the License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * Lesser General Public License for more details. -+ * -+ * You should have received a copy of the GNU Lesser General Public -+ * License along with this library; if not, see -+ * http://www.gnu.org/licenses/lgpl-2.1.html -+ */ -+ -+#ifndef ARC_TRANSLATE_H_ -+#define ARC_TRANSLATE_H_ -+ -+ -+#include "arc-common.h" -+ -+#include "tcg/tcg.h" -+#include "cpu.h" -+#include "exec/exec-all.h" -+#include "disas/disas.h" -+#include "tcg/tcg-op.h" -+#include "exec/cpu_ldst.h" -+ -+#include "exec/helper-proto.h" -+#include "exec/helper-gen.h" -+#include "exec/log.h" -+ -+#include "exec/translator.h" -+ -+/* signaling the end of translation block */ -+#define DISAS_UPDATE DISAS_TARGET_0 -+#define DISAS_BRANCH_IN_DELAYSLOT DISAS_TARGET_1 -+ -+typedef struct DisasContext { -+ DisasContextBase base; -+ -+ uint32_t cpc; /* current pc */ -+ uint32_t npc; /* next pc */ -+ uint32_t dpc; /* next next pc */ -+ uint32_t pcl; -+ uint32_t lpe; -+ uint32_t lps; -+ -+ unsigned ds; /* we are within ds*/ -+ -+ /* TODO (issue #62): these must be removed */ -+ TCGv zero; /* 0x00000000 */ -+ TCGv one; /* 0x00000001 */ -+ -+ insn_t insn; -+ -+ CPUARCState *env; -+ -+ uint16_t buffer[2]; -+ uint8_t mem_idx; -+ -+ bool in_delay_slot; -+ -+ TCGv tmp_reg; -+ TCGLabel *label; -+ -+} DisasContext; -+ -+ -+#define cpu_gp (cpu_r[26]) -+#define cpu_fp (cpu_r[27]) -+#define cpu_sp (cpu_r[28]) -+#define cpu_ilink1 (cpu_r[29]) -+#define cpu_ilink2 (cpu_r[30]) -+#define cpu_blink (cpu_r[31]) -+#define cpu_acclo (cpu_r[58]) -+#define cpu_acchi (cpu_r[59]) -+#define cpu_lpc (cpu_r[60]) -+#define cpu_pcl (cpu_r[63]) -+#define cpu_limm (cpu_r[62]) -+ -+extern TCGv cpu_S1f; -+extern TCGv cpu_S2f; -+extern TCGv cpu_CSf; -+ -+extern TCGv cpu_Ef; -+extern TCGv cpu_IEf; -+extern TCGv cpu_Vf; -+extern TCGv cpu_Cf; -+extern TCGv cpu_Nf; -+extern TCGv cpu_Zf; -+extern TCGv cpu_DEf; -+ -+extern TCGv cpu_is_delay_slot_instruction; -+ -+extern TCGv cpu_l1_Ef; -+extern TCGv cpu_l1_Vf; -+extern TCGv cpu_l1_Cf; -+extern TCGv cpu_l1_Nf; -+extern TCGv cpu_l1_Zf; -+extern TCGv cpu_l1_DEf; -+ -+extern TCGv cpu_l2_Ef; -+extern TCGv cpu_l2_Vf; -+extern TCGv cpu_l2_Cf; -+extern TCGv cpu_l2_Nf; -+extern TCGv cpu_l2_Zf; -+extern TCGv cpu_l2_DEf; -+ -+extern TCGv cpu_er_Ef; -+extern TCGv cpu_er_Vf; -+extern TCGv cpu_er_Cf; -+extern TCGv cpu_er_Nf; -+extern TCGv cpu_er_Zf; -+extern TCGv cpu_er_DEf; -+ -+extern TCGv cpu_eret; -+extern TCGv cpu_erbta; -+extern TCGv cpu_ecr; -+extern TCGv cpu_efa; -+ -+extern TCGv cpu_pc; -+extern TCGv cpu_lps; -+extern TCGv cpu_lpe; -+ -+extern TCGv cpu_npc; -+ -+extern TCGv cpu_bta; -+extern TCGv cpu_bta_l1; -+extern TCGv cpu_bta_l2; -+ -+extern TCGv cpu_r[64]; -+ -+extern TCGv cpu_intvec; -+ -+extern TCGv cpu_lock_lf_var; -+ -+extern TCGv cpu_exception_delay_slot_address; -+ -+ -+/* TODO: Remove DisasCtxt. */ -+typedef struct DisasContext DisasCtxt; -+ -+void gen_goto_tb(const DisasContext *ctx, int n, TCGv dest); -+ -+void decode_opc(CPUARCState *env, DisasContext *ctx); -+ -+/* -+ * Helper function to glue "rasing an exception" in the generated TCGs. -+ * -+ * ctx: Disassembling context -+ * index: ECR's index field -+ * causecode: ECR's cause code filed -+ * param: ECR's parameter field -+ */ -+void arc_gen_excp(const DisasCtxt *ctx, uint32_t index, -+ uint32_t causecode, uint32_t param); -+ -+#endif -+ -+ -+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ -+/* vim: set ts=4 sw=4 et: */ -diff --git a/target/meson.build b/target/meson.build -index 0e2c4b69cb..c3d94ae1dd 100644 ---- a/target/meson.build -+++ b/target/meson.build -@@ -1,4 +1,5 @@ - subdir('alpha') -+subdir('arc') - subdir('arm') - subdir('avr') - subdir('cris') -diff --git a/tests/Makefile.include b/tests/Makefile.include -index 8f220e15d1..407b1e4472 100644 ---- a/tests/Makefile.include -+++ b/tests/Makefile.include -@@ -56,6 +56,7 @@ $(BUILD_TCG_TARGET_RULES): build-tcg-tests-%: $(if $(CONFIG_PLUGIN),test-plugins - $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) \ - -f $(SRC_PATH)/tests/tcg/Makefile.qemu \ - SRC_PATH=$(SRC_PATH) \ -+ BUILD_DIR=$(BUILD_DIR) \ - V="$(V)" TARGET="$*" guest-tests, \ - "BUILD", "TCG tests for $*") - -diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py -index 1ca32ecf25..b5a781b6b4 100644 ---- a/tests/acceptance/boot_linux_console.py -+++ b/tests/acceptance/boot_linux_console.py -@@ -138,6 +138,26 @@ def test_mips_malta(self): - console_pattern = 'Kernel command line: %s' % kernel_command_line - self.wait_for_console_pattern(console_pattern) - -+ def test_mips_malta(self): -+ """ -+ :avocado: tags=arch:arc -+ """ -+ deb_url = ('http://snapshot.debian.org/archive/debian/' -+ '20130217T032700Z/pool/main/l/linux-2.6/' -+ 'linux-image-2.6.32-5-4kc-malta_2.6.32-48_mips.deb') -+ deb_hash = 'a8cfc28ad8f45f54811fc6cf74fc43ffcfe0ba04' -+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) -+ kernel_path = self.extract_from_deb(deb_path, -+ '/boot/vmlinux-archs') -+ -+ self.vm.set_console() -+ kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=ttyS0' -+ self.vm.add_args('-kernel', kernel_path, -+ '-append', kernel_command_line) -+ self.vm.launch() -+ console_pattern = 'Kernel command line: %s' % kernel_command_line -+ self.wait_for_console_pattern(console_pattern) -+ - def test_mips64el_malta(self): - """ - This test requires the ar tool to extract "data.tar.gz" from -@@ -966,6 +986,17 @@ def test_alpha_clipper(self): - console_pattern = 'Kernel command line: %s' % kernel_command_line - self.wait_for_console_pattern(console_pattern) - -+ def do_test_arc(self, kernel_name, console=0): -+ tar_url = ('https://github.com/cupertinomiranda/arc-qemu-resources/archive/master.tar.gz') -+ file_path = self.fetch_asset(tar_url) -+ archive.extract(file_path, self.workdir) -+ -+ self.vm.set_console(console_index=console) -+ self.vm.add_args('-kernel', -+ self.workdir + '/' + kernel_name) -+ self.vm.launch() -+ self.wait_for_console_pattern('QEMU advent calendar') -+ - def test_m68k_q800(self): - """ - :avocado: tags=arch:m68k -@@ -1086,3 +1117,27 @@ def test_xtensa_lx60(self): - tar_hash = '49e88d9933742f0164b60839886c9739cb7a0d34' - self.vm.add_args('-cpu', 'dc233c') - self.do_test_advcal_2018('02', tar_hash, 'santas-sleigh-ride.elf') -+ -+ timeout = 240 -+ def test_arc_virt(self): -+ """ -+ :avocado: tags=arch:arc -+ :avocado: tags=machine:virt -+ """ -+ -+ tar_url = ('https://github.com/cupertinomiranda/' -+ 'arc-qemu-resources/archive/master.tar.gz') -+ file_path = self.fetch_asset(tar_url) -+ archive.extract(file_path, self.workdir) -+ -+ kernel_path = self.workdir + '/arc-qemu-resources-master/vmlinux_archs' -+ -+ self.vm.set_console() -+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE) -+ self.vm.add_args('-kernel', kernel_path) -+ self.vm.add_args('-device', 'virtio-net-device,netdev=net0') -+ self.vm.add_args('-netdev', 'user,id=net0,hostfwd=tcp::5558-:21,hostfwd=tcp::5557-:23') -+ self.vm.launch() -+ -+ console_pattern = 'Welcome to Buildroot' -+ self.wait_for_console_pattern(console_pattern) -diff --git a/tests/tcg/arc/Makefile b/tests/tcg/arc/Makefile -new file mode 100644 -index 0000000000..81226d294e ---- /dev/null -+++ b/tests/tcg/arc/Makefile -@@ -0,0 +1,114 @@ -+-include ../../../config-host.mak -+ -+CROSS = arc-elf32- -+#CROSS = arc-snps-linux-uclibc- -+ -+SIM = ../../../arc-softmmu/qemu-system-arc -+SIM_FLAGS = -M arc-sim -m 3G -nographic -no-reboot -monitor none \ -+ -serial stdio -global cpu.mpu-numreg=8 -kernel -+#SIM_FLAGS=-cpu archs -+TST_PATH = $(SRC_PATH)/tests/tcg/arc -+ -+CC = $(CROSS)gcc -+LD = $(CROSS)ld -+AS = $(CROSS)as -+CFLAGS = -mcpu=archs -O2 --specs=qemu.specs -+ASFLAGS = -mcpu=archs -+ -+TESTCASES = check_add.tst -+TESTCASES += check_lp.tst -+TESTCASES += check_lp02.tst -+TESTCASES += check_lp03.tst -+TESTCASES += check_lp04.tst -+TESTCASES += check_lp05.tst -+TESTCASES += check_lp06.tst -+TESTCASES += check_addx.tst -+TESTCASES += check_andx.tst -+TESTCASES += check_aslx.tst -+TESTCASES += check_asrx.tst -+TESTCASES += check_orx.tst -+TESTCASES += check_rolx.tst -+TESTCASES += check_rorx.tst -+TESTCASES += check_subx.tst -+TESTCASES += check_xorx.tst -+TESTCASES += check_beqx.tst -+TESTCASES += check_bnex.tst -+TESTCASES += check_brhsx.tst -+TESTCASES += check_brlox.tst -+TESTCASES += check_breqx.tst -+TESTCASES += check_brnex.tst -+TESTCASES += check_brltx.tst -+TESTCASES += check_brgex.tst -+TESTCASES += check_ldstx.tst -+TESTCASES += check_stld.tst -+TESTCASES += check_lsrx.tst -+TESTCASES += check_beq.tst -+TESTCASES += check_carry.tst -+TESTCASES += check_flags.tst -+TESTCASES += check_t01.tst -+TESTCASES += check_t02.tst -+TESTCASES += check_basic1.tst -+TESTCASES += check_basic2.tst -+TESTCASES += check_norm.tst -+TESTCASES += check_excp.tst -+TESTCASES += check_excp_1.ctst -+TESTCASES += check_mmu.tst -+TESTCASES += check_excp_mmu.tst -+TESTCASES += check_excp_jumpdl_mmu.tst -+TESTCASES += check_timer0.tst -+TESTCASES += check_timer0_loop.tst -+TESTCASES += check_timer0_loop3.tst -+TESTCASES += check_timer0_retrig.tst -+TESTCASES += check_timer0_sleep.tst -+TESTCASES += check_timerX_freq.tst -+TESTCASES += check_swi.tst -+TESTCASES += check_swirq.tst -+TESTCASES += check_swirq1.tst -+TESTCASES += check_swirq3.tst -+TESTCASES += check_mpyw.tst -+TESTCASES += check_subf.tst -+TESTCASES += check_prefetch.tst -+TESTCASES += check_mac.tst -+TESTCASES += check_ldaw_mmu.tst -+TESTCASES += check_manip_4_mmu.tst -+TESTCASES += check_manip_5_mmu.tst -+TESTCASES += check_manip_10_mmu.tst -+TESTCASES += check_manip_mmu.tst -+TESTCASES += check_rtie_user.tst -+TESTCASES += check_rtc.tst -+TESTCASES += check_mpu.tst -+TESTCASES += check_big_tb.tst -+TESTCASES += check_enter_leave.tst -+TESTCASES += check_bta.tst -+TESTCASES += check_vadd.tst -+TESTCASES += check_vsub.tst -+TESTCASES += check_mpyd.tst -+TESTCASES += check_bi.tst -+TESTCASES += check_bih.tst -+ -+all: $(TESTCASES) -+OBJECTS = ivt.o -+ -+%.o: $(SRC_PATH)/tests/tcg/arc/%.S -+ echo "Running: $(CC) $(ASFLAGS) -c $< -o $@ -I$(TST_PATH)"; \ -+ $(CC) $(ASFLAGS) -c $< -o $@ -I$(TST_PATH) -+ -+%_mmu.tst: %_mmu.o ${OBJECTS} $(SRC_PATH)/tests/tcg/arc/macros.inc $(SRC_PATH)/tests/tcg/arc/mmu.inc -+ echo "Running: $(LD) -T $(TST_PATH)/tarc_mmu.ld ${OBJECTS} $< -o $@"; \ -+ $(LD) -T $(TST_PATH)/tarc_mmu.ld ${OBJECTS} $< -o $@ -+ -+%.tst: %.o ${OBJECTS} $(SRC_PATH)/tests/tcg/arc/macros.inc -+ echo "Running: $(LD) -T $(TST_PATH)/tarc.ld ${OBJECTS} $< -o $@"; \ -+ $(LD) -T $(TST_PATH)/tarc.ld ${OBJECTS} $< -o $@ -+ -+%.ctst: $(SRC_PATH)/tests/tcg/arc/%.c -+ $(CC) $(CFLAGS) -Wl,-marcv2elfx -L $(SRC_PATH)/tests/tcg/arc/ $< -o $@ -+ -+check: $(TESTCASES) -+ @for case in $(TESTCASES); do \ -+ echo $(SIM) $(SIM_FLAGS) ./$$case;\ -+ $(SIM) $(SIM_FLAGS) ./$$case; \ -+ done -+ -+clean: -+ $(RM) -rf $(TESTCASES) -diff --git a/tests/tcg/arc/Makefile.softmmu-target b/tests/tcg/arc/Makefile.softmmu-target -new file mode 100644 -index 0000000000..3a0db7ef8c ---- /dev/null -+++ b/tests/tcg/arc/Makefile.softmmu-target -@@ -0,0 +1,43 @@ -+# -+# ARC softmmu tests -+# -+ -+ARC_SRC = $(SRC_PATH)/tests/tcg/arc -+ARC_ALL = $(filter-out $(ARC_SRC)/ivt.S,$(wildcard $(ARC_SRC)/*.S)) -+ARC_TESTS = $(patsubst $(ARC_SRC)/%.S, %, $(ARC_ALL)) -+ -+# Filter out common blobs and broken tests -+ARC_BROKEN_TESTS = check_carry check_excp_jumpdl_mmu -+ARC_USABLE_TESTS = $(filter-out $(ARC_BROKEN_TESTS), $(ARC_TESTS)) -+ -+# add to the list of tests -+TESTS += $(ARC_USABLE_TESTS) -+VPATH += $(ARC_SRC) -+ -+QEMU_OPTS+=-M arc-sim -m 3G -nographic -no-reboot -serial stdio -global cpu.mpu-numreg=8 -kernel -+ -+CROSS = arc-elf32- -+ -+ASFLAGS = -mcpu=archs -+LDFLAGS = --specs=qemu.specs -T $(ARC_SRC)/tarc.ld -nostartfiles -nostdlib -+MMU_LDFLAGS = --specs=qemu.specs -T $(ARC_SRC)/tarc_mmu.ld -nostartfiles -nostdlib -+CRT = ivt.o -+ -+SIM = ../../../qemu-system-arc -+SIM_FLAGS = -M arc-sim -m 3G -nographic -no-reboot -monitor none \ -+ -serial stdio -global cpu.mpu-numreg=8 -kernel -+ -+$(ARC_USABLE_TESTS): $(CRT) Makefile.softmmu-target -+ -+# special rule for common blobs -+%.o: %.S -+ cd ${BUILD_DIR} && \ -+ $(CC) -I$(ARC_SRC) $($*ASFLAGS) $(ASFLAGS) $(EXTRACFLAGS) -c $< -o ./$@ -+ -+%_mmu: %_mmu.o -+ cd ${BUILD_DIR} && \ -+ $(CC) -I$(ARC_SRC) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(MMU_LDFLAGS) $(NOSTDFLAGS) $(CRT) -+ -+%: %.o -+ cd ${BUILD_DIR} && \ -+ $(CC) -I$(ARC_SRC) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(NOSTDFLAGS) $(CRT) -diff --git a/tests/tcg/arc/Makefile.target b/tests/tcg/arc/Makefile.target -new file mode 100644 -index 0000000000..abbf1a7b79 ---- /dev/null -+++ b/tests/tcg/arc/Makefile.target -@@ -0,0 +1,101 @@ -+# -*- Mode: makefile -*- -+# -+# ARC specific tweaks -+ -+ARC_SRC=$(SRC_PATH)/tests/tcg/arc-softmmu -+VPATH+=$(ARC_SRC) -+ -+ARC_TESTS = check_add.tst -+ARC_TESTS += check_lp.tst -+ARC_TESTS += check_lp02.tst -+ARC_TESTS += check_lp03.tst -+ARC_TESTS += check_lp04.tst -+ARC_TESTS += check_lp05.tst -+ARC_TESTS += check_lp06.tst -+ARC_TESTS += check_addx.tst -+ARC_TESTS += check_andx.tst -+ARC_TESTS += check_aslx.tst -+ARC_TESTS += check_asrx.tst -+ARC_TESTS += check_orx.tst -+ARC_TESTS += check_rolx.tst -+ARC_TESTS += check_rorx.tst -+ARC_TESTS += check_subx.tst -+ARC_TESTS += check_xorx.tst -+ARC_TESTS += check_beqx.tst -+ARC_TESTS += check_bnex.tst -+ARC_TESTS += check_brhsx.tst -+ARC_TESTS += check_brlox.tst -+ARC_TESTS += check_breqx.tst -+ARC_TESTS += check_brnex.tst -+ARC_TESTS += check_brltx.tst -+ARC_TESTS += check_brgex.tst -+ARC_TESTS += check_ldstx.tst -+ARC_TESTS += check_stld.tst -+ARC_TESTS += check_lsrx.tst -+ARC_TESTS += check_beq.tst -+ARC_TESTS += check_carry.tst -+ARC_TESTS += check_flags.tst -+ARC_TESTS += check_t01.tst -+ARC_TESTS += check_t02.tst -+ARC_TESTS += check_basic1.tst -+ARC_TESTS += check_basic2.tst -+ARC_TESTS += check_norm.tst -+ARC_TESTS += check_excp.tst -+ARC_TESTS += check_excp_1.ctst -+ARC_TESTS += check_mmu.tst -+ARC_TESTS += check_excp_mmu.tst -+ARC_TESTS += check_excp_jumpdl_mmu.tst -+ARC_TESTS += check_timer0.tst -+ARC_TESTS += check_timer0_loop.tst -+ARC_TESTS += check_timer0_loop3.tst -+ARC_TESTS += check_timer0_retrig.tst -+ARC_TESTS += check_timer0_sleep.tst -+ARC_TESTS += check_timerX_freq.tst -+ARC_TESTS += check_swi.tst -+ARC_TESTS += check_swirq.tst -+ARC_TESTS += check_swirq1.tst -+ARC_TESTS += check_swirq3.tst -+ARC_TESTS += check_mpyw.tst -+ARC_TESTS += check_subf.tst -+ARC_TESTS += check_prefetch.tst -+ARC_TESTS += check_mac.tst -+ARC_TESTS += check_ldaw_mmu.tst -+ARC_TESTS += check_manip_4_mmu.tst -+ARC_TESTS += check_manip_5_mmu.tst -+ARC_TESTS += check_manip_10_mmu.tst -+ARC_TESTS += check_manip_mmu.tst -+ARC_TESTS += check_rtie_user.tst -+ARC_TESTS += check_rtc.tst -+ARC_TESTS += check_mpu.tst -+ARC_TESTS += check_big_tb.tst -+ARC_TESTS += check_enter_leave.tst -+ARC_TESTS += check_bta.tst -+ARC_TESTS += check_vadd.tst -+ARC_TESTS += check_vsub.tst -+ARC_TESTS += check_mpyd.tst -+ -+TESTS+=$(ARC_TESTS) -+ -+%.o: $(ARC_SRC)/%.S -+ echo "Running: $(CC) $(ASFLAGS) -c $< -o $@ -I$(TST_PATH)"; \ -+ $(CC) $(ASFLAGS) -c $< -o $@ -I$(TST_PATH) -+ -+%_mmu.tst: %_mmu.o ${OBJECTS} $(ARC_SRC)/macros.inc $(ARC_SRC)/mmu.inc -+ echo "Running: $(LD) -T $(TST_PATH)/tarc_mmu.ld ${OBJECTS} $< -o $@"; \ -+ $(LD) -T $(TST_PATH)/tarc_mmu.ld ${OBJECTS} $< -o $@ -+ -+%.tst: %.o ${OBJECTS} $(ARC_SRC)/macros.inc -+ echo "Running: $(LD) -T $(TST_PATH)/tarc.ld ${OBJECTS} $< -o $@"; \ -+ $(LD) -T $(TST_PATH)/tarc.ld ${OBJECTS} $< -o $@ -+ -+%.ctst: $(ARC_SRC)/%.c -+ $(CC) $(CFLAGS) -Wl,-marcv2elfx -L $(ARC_SRC)/ $< -o $@ -+ -+#test-cmov: EXTRA_CFLAGS=-DTEST_CMOV -+#test-cmov: test-cond.c -+# $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) -+# -+#run-test-cmov: test-cmov -+# -+## On Alpha Linux only supports 8k pages -+#EXTRA_RUNS+=run-test-mmap-8192 -diff --git a/tests/tcg/arc/check_add.S b/tests/tcg/arc/check_add.S -new file mode 100644 -index 0000000000..be400cf788 ---- /dev/null -+++ b/tests/tcg/arc/check_add.S -@@ -0,0 +1,11 @@ -+.include "macros.inc" -+ -+ start -+ -+ test_name ADD_1 -+ mov r2,0x10ff01ff -+ mov r3,0x10010001 -+ add r2,r2,r3 -+ check_r2 0x21000200 -+ -+ end -diff --git a/tests/tcg/arc/check_addx.S b/tests/tcg/arc/check_addx.S -new file mode 100644 -index 0000000000..467679823f ---- /dev/null -+++ b/tests/tcg/arc/check_addx.S -@@ -0,0 +1,71 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# add.S -+#----------------------------------------------------------------------------- -+# -+# Test add instruction. -+# -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Arithmetic tests -+ #------------------------------------------------------------- -+ -+ TEST_IMM_OP( 2, add, 0x00000000, 0x00000000, 0x000 ) -+ TEST_IMM_OP( 3, add, 0x00000002, 0x00000001, 0x001 ) -+ TEST_IMM_OP( 4, add, 0x0000000a, 0x00000003, 0x007 ) -+ -+ TEST_IMM_OP( 5, add, 0xfffffffffffff800, 0x0000000000000000, 0x800 ) -+ TEST_IMM_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x000 ) -+ TEST_IMM_OP( 7, add, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 ) -+ -+ TEST_IMM_OP( 8, add, 0x00000000000007ff, 0x00000000, 0x7ff ) -+ TEST_IMM_OP( 9, add, 0x000000007fffffff, 0x7fffffff, 0x000 ) -+ TEST_IMM_OP( 10, add, 0x00000000800007fe, 0x7fffffff, 0x7ff ) -+ -+ TEST_IMM_OP( 11, add, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff ) -+ TEST_IMM_OP( 12, add, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 ) -+ -+ TEST_IMM_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xfff ) -+ TEST_IMM_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x001 ) -+ TEST_IMM_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff ) -+ -+ TEST_IMM_OP( 16, add, 0x0000000080000000, 0x7fffffff, 0x001 ) -+ -+ TEST_RR_3OP( 17, add, 0x00000000, 0x00000000, 0x00000000 ) -+ TEST_RR_3OP( 18, add, 0x00000002, 0x00000001, 0x00000001 ) -+ TEST_RR_3OP( 19, add, 0x0000000a, 0x00000003, 0x00000007 ) -+ -+ TEST_RR_3OP( 20, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ) -+ TEST_RR_3OP( 21, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 ) -+ TEST_RR_3OP( 22, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ) -+ -+ TEST_RR_3OP( 23, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ) -+ TEST_RR_3OP( 24, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ) -+ TEST_RR_3OP( 25, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ) -+ -+ TEST_RR_3OP( 26, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff ) -+ TEST_RR_3OP( 27, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ) -+ -+ TEST_RR_3OP( 28, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ) -+ TEST_RR_3OP( 29, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 ) -+ TEST_RR_3OP( 30, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff ) -+ -+ TEST_RR_3OP( 31, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ) -+ -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ -+ TEST_IMM_SRC1_EQ_DEST( 32, add, 24, 13, 11 ) -+ -+ TEST_RR_SRC1_EQ_DEST( 33, add, 24, 13, 11 ) -+ TEST_RR_SRC2_EQ_DEST( 34, add, 25, 14, 11 ) -+ TEST_RR_SRC12_EQ_DEST( 35, add, 26, 13 ) -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_andx.S b/tests/tcg/arc/check_andx.S -new file mode 100644 -index 0000000000..efdec10ae3 ---- /dev/null -+++ b/tests/tcg/arc/check_andx.S -@@ -0,0 +1,36 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# and.S -+#----------------------------------------------------------------------------- -+# -+# Test and instruction. -+# -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ -+ TEST_IMM_OP( 2, and, 0xff00ff00, 0xff00ff00, 0xf0f ); -+ TEST_IMM_OP( 3, and, 0x000000f0, 0x0ff00ff0, 0x0f0 ); -+ TEST_IMM_OP( 4, and, 0x0000000f, 0x00ff00ff, 0x70f ); -+ TEST_IMM_OP( 5, and, 0x00000000, 0xf00ff00f, 0x0f0 ); -+ TEST_RR_3OP( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); -+ TEST_RR_3OP( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); -+ TEST_RR_3OP( 8, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); -+ TEST_RR_3OP( 9, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 ); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ -+ TEST_IMM_SRC1_EQ_DEST( 10, and, 0x00000000, 0xff00ff00, 0x0f0 ); -+ TEST_RR_SRC1_EQ_DEST( 11, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); -+ TEST_RR_SRC2_EQ_DEST( 12, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); -+ TEST_RR_SRC12_EQ_DEST( 13, and, 0xff00ff00, 0xff00ff00 ); -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_aslx.S b/tests/tcg/arc/check_aslx.S -new file mode 100644 -index 0000000000..77eb3c65cc ---- /dev/null -+++ b/tests/tcg/arc/check_aslx.S -@@ -0,0 +1,57 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# check_aslx.S -+#----------------------------------------------------------------------------- -+# -+# Test or instruction. -+# -+# .--------------.----------.--------------. -+# | instruction | check CC | update flags | -+# |--------------+----------+--------------| -+# | asl | no | Z, N, C, V | -+# | asl multiple | yes | Z, N, C | -+# `--------------^----------^--------------' -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ TEST_RR_3OP(2, asl, 0x12345678, 0x12345678, 0); -+ TEST_RR_3OP(3, asl, 0x23456780, 0x12345678, 4); -+ TEST_RR_3OP(4, asl, 0x80000000, 0x12345671, 31); -+ -+ TEST_RR_2OP(5, asl, 0x00000002, 0x00000001); -+ TEST_RR_2OP(6, asl, 0x00000000, 0x80000000); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ TEST_RR_SRC1_EQ_DEST (7, asl, 0xf7780000, 0xdeedbeef, 0x00000013); -+ TEST_RR_2OP_SRC1_EQ_DEST(8, asl, 0x000804ca, 0x80040265); -+ -+ #------------------------------------------------------------- -+ # Flag tests -+ #------------------------------------------------------------- -+ TEST_2OP_CARRY ( 9, asl, 0, 0x10000000, 0x02); -+ TEST_2OP_CARRY (10, asl, 1, 0x80000000, 0x01); -+ TEST_2OP_CARRY (11, asl, 0, 0xffffffff, 0x00); -+ TEST_2OP_ZERO (12, asl, 1, 0x12345670, 0xbf); -+ TEST_2OP_NEGATIVE(13, asl, 1, 0x1F345678, 0x04); -+ # no overflow flag update in "asl multiple" -+ TEST_2OP_OVERFLOW(14, asl, 0, 0x80000000, 0x01); -+ -+ TEST_1OP_CARRY (15, asl, 0, 0x40000000); -+ TEST_1OP_CARRY (16, asl, 1, 0x80000000); -+ TEST_1OP_ZERO (17, asl, 0, 0x00001000); -+ TEST_1OP_ZERO (18, asl, 1, 0x80000000); -+ TEST_1OP_NEGATIVE(19, asl, 0, 0x20000000); -+ TEST_1OP_NEGATIVE(20, asl, 1, 0x40000000); -+ TEST_1OP_OVERFLOW(21, asl, 1, 0x80000000); -+ TEST_1OP_OVERFLOW(22, asl, 0, 0xffffffff); -+ TEST_1OP_OVERFLOW(23, asl, 1, 0x40000000); -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_asrx.S b/tests/tcg/arc/check_asrx.S -new file mode 100644 -index 0000000000..6729f0c42b ---- /dev/null -+++ b/tests/tcg/arc/check_asrx.S -@@ -0,0 +1,86 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# check_asrx.S -+#----------------------------------------------------------------------------- -+# -+# Test or instruction. -+# -+# .--------------.----------.--------------. -+# | instruction | check CC | update flags | -+# |--------------+----------+--------------| -+# | asr | no | Z, N, C | -+# | asr multiple | yes | Z, N, C | -+# | asr8 | no | Z, N | -+# | asr16 | no | Z, N | -+# `--------------^----------^--------------' -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ TEST_RR_3OP( 2, asr , 0x12345678, 0x12345678, 0); -+ TEST_RR_3OP( 3, asr , 0x01234567, 0x12345678, 4); -+ TEST_RR_3OP( 4, asr , 0xFF234567, 0xF2345678, 4); -+ TEST_RR_3OP( 5, asr , 0xffffffff, 0x8fffffff, 31); -+ TEST_RR_3OP( 6, asr , 0x00000001, 0x7fffffff, 30); -+ -+ TEST_RR_2OP( 7, asr , 0x00000009, 0x00000012); -+ TEST_RR_2OP( 8, asr , 0xc0000000, 0x80000000); -+ TEST_RR_2OP( 9, asr , 0x20000000, 0x40000000); -+ -+ TEST_RR_2OP(10, asr8 , 0x00000100, 0x00010000); -+ TEST_RR_2OP(11, asr8 , 0xffff0000, 0xff000000); -+ TEST_RR_2OP(12, asr8 , 0xff800000, 0x80000000); -+ TEST_RR_2OP(13, asr8 , 0x007f0000, 0x7f000000); -+ TEST_RR_2OP(14, asr8 , 0x00000000, 0x000000ff); -+ -+ TEST_RR_2OP(15, asr16, 0x00000001, 0x00010000); -+ TEST_RR_2OP(16, asr16, 0xffffffff, 0xffff0000); -+ TEST_RR_2OP(17, asr16, 0xffff8000, 0x80000000); -+ TEST_RR_2OP(18, asr16, 0x00007fff, 0x7fff0000); -+ TEST_RR_2OP(19, asr16, 0x00000000, 0x0000ff00); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ TEST_RR_SRC1_EQ_DEST (20, asr , 0xfffffbdd, 0xdeedbeef, 0x00000013); -+ TEST_RR_2OP_SRC1_EQ_DEST(21, asr , 0xc0020132, 0x80040265); -+ TEST_RR_2OP_SRC1_EQ_DEST(22, asr8 , 0xff800402, 0x80040265); -+ TEST_RR_2OP_SRC1_EQ_DEST(23, asr16, 0xffff8004, 0x80040265); -+ -+ #------------------------------------------------------------- -+ # Flag tests -+ #------------------------------------------------------------- -+ TEST_2OP_CARRY (24, asr , 0, 0x00000001, 0x02); -+ TEST_2OP_CARRY (25, asr , 1, 0x00000001, 0x01); -+ TEST_2OP_ZERO (26, asr , 0, 0x00000004, 0x02); -+ TEST_2OP_ZERO (27, asr , 1, 0x12345678, 0xbf); -+ TEST_2OP_NEGATIVE(28, asr , 1, 0xFF345678, 0x04); -+ TEST_2OP_NEGATIVE(29, asr , 0, 0x7F345678, 0x04); -+ -+ TEST_1OP_CARRY (30, asr , 0, 0x00000002); -+ TEST_1OP_CARRY (31, asr , 1, 0x00000001); -+ TEST_1OP_ZERO (32, asr , 0, 0x00000002); -+ TEST_1OP_ZERO (33, asr , 1, 0x00000001); -+ TEST_1OP_NEGATIVE(34, asr , 1, 0x80000000); -+ TEST_1OP_NEGATIVE(35, asr , 0, 0x7fffffff); -+ -+ TEST_1OP_CARRY (36, asr8 , 0, 0x0000007f); -+ TEST_1OP_CARRY (37, asr8 , 0, 0xffffffff); -+ TEST_1OP_ZERO (38, asr8 , 0, 0x00000100); -+ TEST_1OP_ZERO (39, asr8 , 1, 0x000000ff); -+ TEST_1OP_NEGATIVE(40, asr8 , 1, 0x80000000); -+ TEST_1OP_NEGATIVE(41, asr8 , 0, 0x7fffffff); -+ -+ TEST_1OP_CARRY (42, asr16, 0, 0x00007fff); -+ TEST_1OP_CARRY (43, asr16, 0, 0xffffffff); -+ TEST_1OP_ZERO (44, asr16, 0, 0x00010000); -+ TEST_1OP_ZERO (45, asr16, 1, 0x0000ffff); -+ TEST_1OP_NEGATIVE(46, asr16, 1, 0x80000000); -+ TEST_1OP_NEGATIVE(47, asr16, 0, 0x7fffffff); -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_basic1.S b/tests/tcg/arc/check_basic1.S -new file mode 100644 -index 0000000000..b26c548bc2 ---- /dev/null -+++ b/tests/tcg/arc/check_basic1.S -@@ -0,0 +1,30 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# ror.S -+#----------------------------------------------------------------------------- -+# -+# Test or instruction. -+# -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ TEST_RR_3OP( 2, ror, 0xca000804, 0x000804ca, 0xfff80008); -+ TEST_RR_3OP( 3, add1, 0x00000096, 0x00000002, 0x0000004a); -+ TEST_RR_3OP( 4, add2, 0x0000025a, 0x00000002, 0x00000096); -+ TEST_RR_3OP( 5, asr, 0x000007da, 0x00000fb5, 0xfff00001); -+ TEST_RR_3OP( 6, bic, 0x01010101, 0x29292909, 0x2a2a2a0a); -+ TEST_RR_3OP( 7, rsub, 0x00000011, 0x50005134, 0x50005145); -+ TEST_RR_3OP( 8, sub1, 0xfffff720, 0x0000046e, 0x000006a7); -+ TEST_RR_3OP( 9, sub3, 0xfffff9e4, 0x000008ac, 0x000001d9); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_basic2.S b/tests/tcg/arc/check_basic2.S -new file mode 100644 -index 0000000000..31de81a2e4 ---- /dev/null -+++ b/tests/tcg/arc/check_basic2.S -@@ -0,0 +1,26 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# ror.S -+#----------------------------------------------------------------------------- -+# -+# Test or instruction. -+# -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ TEST_RR_3OP( 2, bmsk, 0x010101FF, 0x010101FF, 0x800289bf); -+ TEST_RR_3OP( 3, bmsk, 0x00000001, 0x01010101, 0x89000007); -+ TEST_RR_3OP( 4, min, 0xffffff00, 0xffffff00, 0x000000ff); -+ TEST_RR_3OP( 5, lsr, 0x658403fd, 0xcb0807fb, 0x89000001); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_beq.S b/tests/tcg/arc/check_beq.S -new file mode 100644 -index 0000000000..841f4c6760 ---- /dev/null -+++ b/tests/tcg/arc/check_beq.S -@@ -0,0 +1,14 @@ -+.include "macros.inc" -+ -+ start -+ test_name BEQ_1 -+ mov.f r2,0 -+ beq 1f -+ check_r2 0x01 -+1: -+ beq.d 2f -+ mov r2,0x01 -+ check_r2 0x00 -+2: -+ check_r2 0x01 -+ end -diff --git a/tests/tcg/arc/check_beqx.S b/tests/tcg/arc/check_beqx.S -new file mode 100644 -index 0000000000..2c246da2ce ---- /dev/null -+++ b/tests/tcg/arc/check_beqx.S -@@ -0,0 +1,26 @@ -+#***************************************************************************** -+# beq.S -+#----------------------------------------------------------------------------- -+# -+# Test beq instruction. -+# -+ -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ #------------------------------------------------------------- -+ # Branch tests -+ #------------------------------------------------------------- -+ -+ # Each test checks both forward and backward branches -+ -+ TEST_BR2_OP_TAKEN( 2, beq, 0, 0 ); -+ TEST_BR2_OP_TAKEN( 3, beq, 1, 1 ); -+ TEST_BR2_OP_TAKEN( 4, beq, -1, -1 ); -+ -+ TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 ); -+ TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 ); -+ TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 ); -+ TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_bi.S b/tests/tcg/arc/check_bi.S -new file mode 100644 -index 0000000000..f71748a346 ---- /dev/null -+++ b/tests/tcg/arc/check_bi.S -@@ -0,0 +1,32 @@ -+ .include "macros.inc" -+ -+ start -+ test_name BI -+ mov_s r0,0 -+.Lloop: -+ bi [r0] -+ b @.L1 -+ b @.L2 -+ b @.L3 -+ b @.L4 -+ b @.Lfail -+ b @.Lfail -+ b @.Lfail -+.L1: -+ add r0,r0,1 -+ print "[PASS] BI:jmp0\n" -+ b @.Lloop -+.L2: -+ add r0,r0,1 -+ print "[PASS] BI:jmp1\n" -+ b @.Lloop -+.L3: -+ add r0,r0,1 -+ print "[PASS] BI:jmp2\n" -+ b @.Lloop -+.L4: -+ print "[PASS] BI\n" -+ end -+.Lfail: -+ print "[FAIL] BI\n" -+ end -diff --git a/tests/tcg/arc/check_big_tb.S b/tests/tcg/arc/check_big_tb.S -new file mode 100644 -index 0000000000..1c22b811ae ---- /dev/null -+++ b/tests/tcg/arc/check_big_tb.S -@@ -0,0 +1,173 @@ -+.equ POWER_DEVICE, 0xF0000008 ; power management device -+ -+.text -+.global main -+.align 4 -+main: -+ -+add3 r6,sp,0x38 -+mov_s r7,0x152f8 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x34 -+mov_s r7,0x152d8 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x30 -+mov_s r7,0x152b8 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x2c -+mov_s r7,0x15298 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x28 -+mov_s r7,0x15278 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x24 -+mov_s r7,0x15258 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x20 -+mov_s r7,0x15238 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x1c -+mov_s r7,0x15218 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x18 -+mov_s r7,0x151f8 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x14 -+mov_s r7,0x151d8 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x10 -+mov_s r7,0x151b8 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0xc -+mov_s r7,0x15198 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add3 r6,sp,0x8 -+mov_s r7,0x15178 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+add r6,sp,0x20 -+mov_s r7,0x15158 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+mov_s r6,sp -+mov_s r7,0x15138 -+ldd r4r5,[r7] -+ldd r2r3,[r7,8] -+std r4r5,[r6] -+ldd r4r5,[r7,16] -+std r2r3,[r6,8] -+ldd r2r3,[r7,24] -+std r4r5,[r6,16] -+std r2r3,[r6,24] -+ld r0,[0x15118] -+ld r1,[0x1511c] -+ld r2,[0x15120] -+ld r3,[0x15124] -+ld r4,[0x15128] -+ld r5,[0x1512c] -+ld r6,[0x15130] -+ld r7,[0x15134] -+bl @fin -+ -+nop_s -+nop_s -+.align 4 -+ -+fin: -+st 1, [POWER_DEVICE] -diff --git a/tests/tcg/arc/check_bih.S b/tests/tcg/arc/check_bih.S -new file mode 100644 -index 0000000000..c099d72b96 ---- /dev/null -+++ b/tests/tcg/arc/check_bih.S -@@ -0,0 +1,29 @@ -+ .include "macros.inc" -+ -+ start -+ test_name BIH -+ mov_s r0,0 -+.Lloop: -+ bih [r0] -+ b_s @.L1 -+ b_s @.L2 -+ b_s @.L3 -+ b_s @.L4 -+ b_s @.Lfail -+ b_s @.Lfail -+ b_s @.Lfail -+.L1: -+ add r0,r0,1 -+ b @.Lloop -+.L2: -+ add r0,r0,1 -+ b @.Lloop -+.L3: -+ add r0,r0,1 -+ b @.Lloop -+.L4: -+ print "[PASS] BIH\n" -+ end -+.Lfail: -+ print "[FAIL] BIH\n" -+ end -diff --git a/tests/tcg/arc/check_bnex.S b/tests/tcg/arc/check_bnex.S -new file mode 100644 -index 0000000000..4b7c0cfed9 ---- /dev/null -+++ b/tests/tcg/arc/check_bnex.S -@@ -0,0 +1,26 @@ -+#***************************************************************************** -+# bne.S -+#----------------------------------------------------------------------------- -+# -+# Test bne instruction. -+# -+ -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ #------------------------------------------------------------- -+ # Branch tests -+ #------------------------------------------------------------- -+ -+ # Each test checks both forward and backward branches -+ -+ TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); -+ TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); -+ TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); -+ TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); -+ -+ TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); -+ TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); -+ TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_breqx.S b/tests/tcg/arc/check_breqx.S -new file mode 100644 -index 0000000000..a3a3dd1160 ---- /dev/null -+++ b/tests/tcg/arc/check_breqx.S -@@ -0,0 +1,26 @@ -+#***************************************************************************** -+# breq.S -+#----------------------------------------------------------------------------- -+# -+# Test breq instruction. -+# -+ -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ #------------------------------------------------------------- -+ # Branch tests -+ #------------------------------------------------------------- -+ -+ # Each test checks both forward and backward branches -+ -+ TEST_BR_OP_TAKEN( 2, breq, 0, 0 ); -+ TEST_BR_OP_TAKEN( 3, breq, 1, 1 ); -+ TEST_BR_OP_TAKEN( 4, breq, -1, -1 ); -+ -+ TEST_BR_OP_NOTTAKEN( 5, breq, 0, 1 ); -+ TEST_BR_OP_NOTTAKEN( 6, breq, 1, 0 ); -+ TEST_BR_OP_NOTTAKEN( 7, breq, -1, 1 ); -+ TEST_BR_OP_NOTTAKEN( 8, breq, 1, -1 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_brgex.S b/tests/tcg/arc/check_brgex.S -new file mode 100644 -index 0000000000..ddd6003b7c ---- /dev/null -+++ b/tests/tcg/arc/check_brgex.S -@@ -0,0 +1,26 @@ -+#***************************************************************************** -+# brge.S -+#----------------------------------------------------------------------------- -+# -+# Test brge instruction. -+# -+ -+#defirge ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ #------------------------------------------------------------- -+ # Branch tests -+ #------------------------------------------------------------- -+ -+ # Each test checks both forward and backward branches -+ -+ TEST_BR_OP_NOTTAKEN( 2, brge, 0, 1 ); -+ TEST_BR_OP_TAKEN( 3, brge, 1, 0 ); -+ TEST_BR_OP_NOTTAKEN( 4, brge, -1, 1 ); -+ TEST_BR_OP_TAKEN( 5, brge, 1, -1 ); -+ -+ TEST_BR_OP_TAKEN( 6, brge, 0, 0 ); -+ TEST_BR_OP_TAKEN( 7, brge, 1, 1 ); -+ TEST_BR_OP_TAKEN( 8, brge, -1, -1 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_brhsx.S b/tests/tcg/arc/check_brhsx.S -new file mode 100644 -index 0000000000..6a05b53f8e ---- /dev/null -+++ b/tests/tcg/arc/check_brhsx.S -@@ -0,0 +1,27 @@ -+#***************************************************************************** -+# brhs.S -+#----------------------------------------------------------------------------- -+# -+# Test brhs instruction. -+# -+ -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ #------------------------------------------------------------- -+ # Branch tests -+ #------------------------------------------------------------- -+ -+ # Each test checks both forward and backward branches -+ -+ TEST_BR_OP_TAKEN( 2, brhs, 0, 0 ); -+ TEST_BR_OP_TAKEN( 3, brhs, 1, 1 ); -+ TEST_BR_OP_TAKEN( 4, brhs, -1, -1 ); -+ TEST_BR_OP_TAKEN( 5, brhs, -1, 1 ); -+ -+ TEST_BR_OP_NOTTAKEN( 6, brhs, 0, 1 ); -+ TEST_BR_OP_NOTTAKEN( 7, brhs, 1, -1 ); -+ TEST_BR_OP_NOTTAKEN( 8, brhs, 33, 0x2aaaaaab ); -+ TEST_BR_OP_NOTTAKEN( 9, brhs, 123, 124 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_brlox.S b/tests/tcg/arc/check_brlox.S -new file mode 100644 -index 0000000000..53a15b27d1 ---- /dev/null -+++ b/tests/tcg/arc/check_brlox.S -@@ -0,0 +1,26 @@ -+#***************************************************************************** -+# brlo.S -+#----------------------------------------------------------------------------- -+# -+# Test brlo instruction. -+# -+ -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ #------------------------------------------------------------- -+ # Branch tests -+ #------------------------------------------------------------- -+ -+ # Each test checks both forward and backward branches -+ -+ TEST_BR_OP_NOTTAKEN( 2, brlo, 0, 0 ); -+ TEST_BR_OP_NOTTAKEN( 3, brlo, 1, 1 ); -+ TEST_BR_OP_NOTTAKEN( 4, brlo, -1, -1 ); -+ TEST_BR_OP_NOTTAKEN( 5, brlo, -1, 1 ); -+ -+ TEST_BR_OP_TAKEN( 6, brlo, 0, 1 ); -+ TEST_BR_OP_TAKEN( 7, brlo, 1, -1 ); -+ TEST_BR_OP_TAKEN( 8, brlo, 33, 0x2aaaaaab ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_brltx.S b/tests/tcg/arc/check_brltx.S -new file mode 100644 -index 0000000000..475d3ddf1c ---- /dev/null -+++ b/tests/tcg/arc/check_brltx.S -@@ -0,0 +1,26 @@ -+#***************************************************************************** -+# brlt.S -+#----------------------------------------------------------------------------- -+# -+# Test brlt instruction. -+# -+ -+#defirlt ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ #------------------------------------------------------------- -+ # Branch tests -+ #------------------------------------------------------------- -+ -+ # Each test checks both forward and backward branches -+ -+ TEST_BR_OP_TAKEN( 2, brlt, 0, 1 ); -+ TEST_BR_OP_NOTTAKEN( 3, brlt, 1, 0 ); -+ TEST_BR_OP_TAKEN( 4, brlt, -1, 1 ); -+ TEST_BR_OP_NOTTAKEN( 5, brlt, 1, -1 ); -+ -+ TEST_BR_OP_NOTTAKEN( 6, brlt, 0, 0 ); -+ TEST_BR_OP_NOTTAKEN( 7, brlt, 1, 1 ); -+ TEST_BR_OP_NOTTAKEN( 8, brlt, -1, -1 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_brnex.S b/tests/tcg/arc/check_brnex.S -new file mode 100644 -index 0000000000..6f37c33930 ---- /dev/null -+++ b/tests/tcg/arc/check_brnex.S -@@ -0,0 +1,26 @@ -+#***************************************************************************** -+# brne.S -+#----------------------------------------------------------------------------- -+# -+# Test brne instruction. -+# -+ -+#defirne ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ #------------------------------------------------------------- -+ # Branch tests -+ #------------------------------------------------------------- -+ -+ # Each test checks both forward and backward branches -+ -+ TEST_BR_OP_TAKEN( 2, brne, 0, 1 ); -+ TEST_BR_OP_TAKEN( 3, brne, 1, 0 ); -+ TEST_BR_OP_TAKEN( 4, brne, -1, 1 ); -+ TEST_BR_OP_TAKEN( 5, brne, 1, -1 ); -+ -+ TEST_BR_OP_NOTTAKEN( 6, brne, 0, 0 ); -+ TEST_BR_OP_NOTTAKEN( 7, brne, 1, 1 ); -+ TEST_BR_OP_NOTTAKEN( 8, brne, -1, -1 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_bta.S b/tests/tcg/arc/check_bta.S -new file mode 100644 -index 0000000000..abef1a33fc ---- /dev/null -+++ b/tests/tcg/arc/check_bta.S -@@ -0,0 +1,294 @@ -+; check_bta.S -+; Tests for setting Branch Target Address register. -+; The BTA register is updated if and only if the -+; branch is going to be taken (cc = true) AND there -+; is a delay slot: -+; ,-----------.-----------. -+; | not taken | taken | -+; ,---------------|-----------+-----------| -+; | no delay slot | - | - | -+; |---------------|-----------+-----------| -+; | delay slot | - | UPDATE | -+; `---------------^-----------^-----------' -+; In other words, BTA is updated only when STATUS32.DE is set. -+; -+; TODO: Add test cases for Bcc, JL, JLcc, BBITn -+; TODO: the following test cases fail in QEMU: 3, 9 -+; the condition of the tests are (not taken, delay slot) -+; and yet QEMU insists on updating the BTA. -+ -+ .include "macros.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+.data -+; Test case counter -+test_nr: -+ .word 0x0 -+; Saved BTA -+saved_bta: -+ .word 0x0 -+ -+; Increment the test counter -+.macro prep_test_case -+ ld r13, [test_nr] -+ add_s r13, r13, 1 ; Increase test case counter -+ st r13, [test_nr] -+ lr r13, [bta] -+ st r13, [saved_bta] ; Some tests need this to check if BTA changed. -+.endm -+ -+; Compares the current BTA with the value saved at the start of a -+; test by PREP_TEST_CASE. If not the same, the test will fail. -+.macro check_bta_remained_intact -+ ld r13, [saved_bta] -+ lr r12, [bta] -+ cmp r13, r12 -+ bne @fail -+.endm -+ -+; Checks the BTA against the EXPECTED_BTA. -+; If they're not the same, the test will fail. -+.macro check_bta expected_bta -+ mov r13, \expected_bta -+ lr r12, [bta] -+ cmp r13, r12 -+ bne @fail -+.endm -+ -+; Checks if the given REGs are equal. Fails, if not. -+.macro check_equal reg, expected_reg -+ cmp \expected_reg, \reg -+ bne @fail -+.endm -+ -+; Checks if REG is one number bigger than ORIG_REG. -+.macro check_one_above reg, orig_reg -+ mov r13, \orig_reg -+ add_s r13, r13, 1 -+ cmp r13, \reg -+ bne @fail -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Conditonal branches ;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+start -+ -+; Test case 1 -+; Conditional branch is not taken and there is no delay slot. -+; BTA mustn't be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ add r1, r0, 1 -+ breq r0, r1, @test_01_target -+ check_bta_remained_intact -+ b @test_01_end -+test_01_target: -+ b @fail -+test_01_end: -+ ; Fall through -+ -+; Test case 2 -+; Conditional branch is taken but there is no delay slot. -+; BTA mustn't be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ mov r1, r0 -+ breq r0, r1, @test_02_target -+ b @fail -+test_02_target: -+ check_bta_remained_intact -+ -+; Test case 3 -+; Conditional branch is not taken but there is a delay slot. -+; BTA mustn't be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ add r1, r0, 1 -+ breq.d r0, r1, @test_03_target -+ add_s r0, r0, 1 -+ check_bta_remained_intact -+ check_equal r0, r1 -+ b @test_03_end -+test_03_target: -+ b @fail -+test_03_end: -+ ; Fall through -+ -+; Test case 4 -+; Conditional branch is taken AND there is a delay slot. -+; BTA must be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ mov r1, r0 -+ breq.d r0, r1, @test_04_target -+ add_s r0, r0, 1 -+ b @fail -+test_04_target: -+ check_bta @test_04_target -+ check_one_above r0, r1 -+ -+;;;;;;;;;;;;;;;;;;;;;;;; Unconditonal branches ;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case 5 -+; Branch unconditionally but there is no delay slot. -+; BTA mustn't be updated. -+ prep_test_case -+ b @test_05_target -+ b @fail -+test_05_target: -+ check_bta_remained_intact -+ -+; Test case 6 -+; Branch unconditionally AND there is a delay slot. -+; BTA must be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ mov r1, r0 -+ b.d @test_06_target -+ add_s r0, r0, 1 -+ b @fail -+test_06_target: -+ check_bta @test_06_target -+ check_one_above r0, r1 -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;; Conditonal jumps ;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case 7 -+; Conditional jump is not taken and there is no delay slot. -+; BTA mustn't be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ add r1, r0, 1 -+ cmp r0, r1 -+ jz @test_07_target -+ check_bta_remained_intact -+ b @test_07_end -+test_07_target: -+ b @fail -+test_07_end: -+ ; Fall through -+ -+; Test case 8 -+; Conditional jump is taken but there is no delay slot. -+; BTA mustn't be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ mov r1, r0 -+ cmp r0, r1 -+ jz @test_08_target -+ add_s r0, r0, 1 -+ -+ b @fail -+test_08_target: -+ check_bta_remained_intact -+ -+; Test case 9 -+; Conditional jump is not taken but there is a delay slot. -+; BTA mustn't be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ add r1, r0, 1 -+ mov r2, @test_09_target -+ cmp r0, r1 -+ jz.d [r2] -+ add_s r0, r0, 1 -+ check_bta_remained_intact -+ check_equal r0, r1 -+ b @test_09_end -+test_09_target: -+ b @fail -+test_09_end: -+ ; Fall through -+ -+; Test case 10 -+; Conditional jump is taken AND there is a delay slot. -+; BTA must be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ mov r1, r0 -+ mov r2, @test_10_target -+ cmp r0, r1 -+ jz.d [r2] -+ add_s r0, r0, 1 -+ b @fail -+test_10_target: -+ check_bta @test_10_target -+ check_one_above r0, r1 -+ -+;;;;;;;;;;;;;;;;;;;;;;; Conditonal short jumps ;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case 11 -+; Conditional short jump is not taken (there can't be a delay slot). -+; BTA mustn't be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ add r1, r0, 1 -+ mov blink, @test_11_target -+ cmp r0, r1 -+ jeq_s [blink] -+ check_bta_remained_intact -+ check_one_above r1, r0 -+ b @test_11_end -+test_11_target: -+ b @fail -+test_11_end: -+ ; Fall through -+ -+; Test case 12 -+; Conditional short jump is taken (there can't be a delay slot). -+; BTA mustn't be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ add r1, r0, 1 -+ mov blink, @test_12_target -+ cmp r0, r1 -+ jne_s [blink] -+ add_s r0, r0, 1 -+ b @fail -+test_12_target: -+ check_bta_remained_intact -+ check_one_above r1, r0 -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Unconditonal jumps ;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case 13 -+; Jump unconditionally but there is no delay slot. -+; BTA mustn't be updated. -+ prep_test_case -+ j @test_13_target -+ b @fail -+test_13_target: -+ check_bta_remained_intact -+ -+; Test case 14 -+; Jump unconditionally AND there is a delay slot. -+; BTA must be updated. -+ prep_test_case -+ ld r0, [test_nr] -+ mov r1, r0 -+ mov r2, @test_14_target -+ j.d [r2] -+ add_s r0, r0, 1 -+ b @fail -+test_14_target: -+ check_bta @test_14_target -+ check_one_above r0, r1 -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [test_nr] -+ ;print_number r0 -+ print "[FAIL]" -+1: -+ print " BTA register (implicit) writing\n" -+ end -diff --git a/tests/tcg/arc/check_carry.S b/tests/tcg/arc/check_carry.S -new file mode 100644 -index 0000000000..5928897911 ---- /dev/null -+++ b/tests/tcg/arc/check_carry.S -@@ -0,0 +1,15 @@ -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ ARCTEST_BEGIN -+ -+test_2: -+ mov r0, 10 -+ mov r1, 12 -+ cmp r0,r1 ;Carry is set here -+ mov.lo.f 0, 0x0 -+ mov.hs.f 0, 0x1 -+ -+ bne @fail -+ -+ ARCTEST_END -diff --git a/tests/tcg/arc/check_enter_leave.S b/tests/tcg/arc/check_enter_leave.S -new file mode 100644 -index 0000000000..9bb8180b29 ---- /dev/null -+++ b/tests/tcg/arc/check_enter_leave.S -@@ -0,0 +1,715 @@ -+;; These are the tests cases for verifying the functionality of -+;; enter_s and leave_s. It is assumed that there are 32 general -+;; purpose registers available (r0 ... r31). It is also good to -+;; remark the aliases for some of the registers: -+;; r27: fp -+;; r28: sp -+;; r31: blink -+ -+ .include "macros.inc" -+ -+;;;;;;;;;;;;;;;;;;; / Exception Verification Helpers \ ;;;;;;;;;;;;;;;;;;;;;; -+; these are the parameters that the exception routine uses as reference -+ .data -+ .align 4 -+ecr_ref : .word 0x0 -+eret_ref : .word 0x0 -+efa_ref : .word 0x0 -+erbta_ref : .word 0x0 -+cont_addr : .word 0x0 -+test_number: .word 0x0 -+ .text -+ .align 4 -+ -+; macro: set_excep_params -+; regs used: r11 -+; -+; this macro writes the provided parameters to a temporary place holder -+; that later will be used by ProtV exception above to verify as reference -+.macro set_excep_params ecr, eret, efa, erbta, continue, test_num -+ mov r11, \ecr -+ st r11, [ecr_ref] -+ mov r11, \efa -+ st r11, [efa_ref] -+ mov r11, \eret -+ st r11, [eret_ref] -+ mov r11, \erbta -+ st r11, [erbta_ref] -+ mov r11, \continue -+ st r11, [cont_addr] -+ mov r11, \test_num -+ st r11, [test_number] -+.endm -+ -+; exception verification routine -+; regs used: r11, r12 -+; -+; this is a parameterized exception that will check the followings: -+; ecr == ecr_ref -+; efa == efa_ref -+; eret == eret_ref -+; if everything passes, it will jump to 'cont_addr' parameter. it will clear -+; the user bit before the jump, ie if an exception is raised in user mode, -+; the continuation after exception will be in kernel mode. -+; the parameters must be set beforehand using 'set_except_params' macro. -+; last but not least, this requires ivt.S file to be compiled and linked. -+ .align 4 -+ .global instruction_error -+ .global EV_Misaligned -+ .type instruction_error, @function -+ .type EV_Misaligned, @function -+instruction_error: -+EV_Misaligned: -+ ld r11, [ecr_ref] -+ lr r12, [ecr] -+ brne r12, r11, @exc_fail -+ ld r11, [eret_ref] -+ lr r12, [eret] -+ brne r12, r11, @exc_fail -+ ld r11, [efa_ref] -+ lr r12, [efa] -+ brne r12, r11, @exc_fail -+ ld r11, [erbta_ref] -+ lr r12, [erbta] -+ brne r12, r11, @exc_fail -+ ; do not pursue the branch target anymore -+ lr r11, [erstatus] -+ and r11, r11, ~0x8040 ; clear ES and DE bit -+ sr r11, [erstatus] -+ ; going back to given address -+ ld r11, [cont_addr] -+ sr r11, [eret] -+ rtie -+exc_fail: -+ ld r11, [test_number] -+ print_number r11 -+ print "[FAIL] :exception is not sane:" -+ b @endtest -+;;;;;;;;;;;;;;;;;;; \ Exception Verification Helpers / ;;;;;;;;;;;;;;;;;;;;;; -+ -+ start -+ mov sp , 0x1000 ; let's set sp to 0x100 for all the tests -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; u6=0 leads to doing nothing -+test00: -+ mov r10, sp -+ enter_s 0 ; enter_s [] -+ brne sp, r10, @test00_fail -+ j @test01 -+ -+test00_fail: -+ print "[FAIL] :test00:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; saving first 3 general purpose registers -+test01: -+ mov r10, sp ; ,-- top ---. -+ mov r13, 13 ; | r13 = 13 | -+ mov r14, 14 ; | r14 = 14 | -+ mov r15, 15 ; | r15 = 15 | -+ enter_s [r13-r15] ; `- bottom -' -+ pop r3 -+ pop r4 -+ pop r5 -+ brne r3, 13, @test01_fail -+ brne r4, 14, @test01_fail -+ brne r5, 15, @test01_fail -+ brne sp, r10, @test01_fail -+ j @test02 -+ -+test01_fail: -+ print "[FAIL] :test01:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; saving blink register -+test02: -+ mov r10, sp -+ mov blink, 0x123 -+ enter_s [blink] -+ pop r1 -+ brne r1, 0x123, @test02_fail -+ brne sp, r10, @test02_fail -+ j @test03 -+ -+test02_fail: -+ print "[FAIL] :test02:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; saving fp register -+test03: -+ mov r10, sp -+ mov fp, 0x321 -+ -+ enter_s [fp] -+ mov r9, sp ; save current sp before poping -+ pop r1 -+ brne r1, 0x321, @test03_fail -+ brne fp, r9, @test03_fail -+ brne sp, r10, @test03_fail -+ j @test04 -+ -+test03_fail: -+ print "[FAIL] :test03:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; saving all registers -+ .data -+ .align 4 -+sp_orig: .word 0x0 -+ .text -+test04: -+ st sp , [sp_orig] ; ,----- top -----. -+ mov blink, 0x456 ; | blink = 0x456 | -+ mov r13 , 13 ; | r13 = 13 | -+ mov r14 , 14 ; | r14 = 14 | -+ mov r15 , 15 ; | r15 = 15 | -+ mov r16 , 16 ; | r16 = 16 | -+ mov r17 , 17 ; | r17 = 17 | -+ mov r18 , 18 ; | r18 = 18 | -+ mov r19 , 19 ; | r19 = 19 | -+ mov r20 , 20 ; | r20 = 20 | -+ mov r21 , 21 ; | r21 = 21 | -+ mov r22 , 22 ; | r22 = 22 | -+ mov r23 , 23 ; | r23 = 23 | -+ mov r24 , 24 ; | r24 = 24 | -+ mov r25 , 25 ; | r25 = 25 | -+ mov r26 , 26 ; | r26 = 26 | -+ mov fp , 0x789 ; | fp = 0x789 | -+ enter_s [r13-r26, fp, blink] ; `--- bottom ----' -+ mov r0, sp ; save current sp before poping -+ pop r1 ; blink -+ pop r3 ; r13 -+ pop r4 ; r14 -+ pop r5 ; r15 -+ pop r6 ; r16 -+ pop r7 ; r17 -+ pop r8 ; r18 -+ pop r9 ; r19 -+ pop r10 ; r20 -+ pop r11 ; r21 -+ pop r12 ; r22 -+ pop r13 ; r23 -+ pop r14 ; r24 -+ pop r15 ; r25 -+ pop r16 ; r26 -+ pop r2 ; fp -+ brne fp, r0, @test04_fail ; sp value before all the pops -+ brne r1, 0x456, @test04_fail ; blink value during save -+ brne r2, 0x789, @test04_fail ; frame pointer value during save -+ brne r3, 13, @test04_fail ; stored r13 value -+ brne r4, 14, @test04_fail ; stored r14 value -+ brne r5, 15, @test04_fail ; stored r15 value -+ brne r6, 16, @test04_fail ; stored r16 value -+ brne r7, 17, @test04_fail ; stored r17 value -+ brne r8, 18, @test04_fail ; stored r18 value -+ brne r9, 19, @test04_fail ; stored r19 value -+ brne r10, 20, @test04_fail ; stored r20 value -+ brne r11, 21, @test04_fail ; stored r21 value -+ brne r12, 22, @test04_fail ; stored r22 value -+ brne r13, 23, @test04_fail ; stored r23 value -+ brne r14, 24, @test04_fail ; stored r24 value -+ brne r15, 25, @test04_fail ; stored r25 value -+ brne r16, 26, @test04_fail ; stored r26 value -+ ld r10, [sp_orig] ; original sp value spilled -+ brne sp, r10, @test04_fail ; original sp value -+ j @test05 -+ -+test04_fail: -+ print "[FAIL] :test04:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; sp's value is not 32-bit aligned --> misaligned exception -+; this happens irrelevant of status32.AD bit -+test05: -+ .equ TEST05_SP , 0x111 ; an address which is not 32-bit aligned -+ .equ TEST05_STACK_SIZE, 60 ; saving r13-r26 (14x4) + fp (4) -+ .equ TEST05_EFA , TEST05_SP - TEST05_STACK_SIZE -+ lr r1, [status32] -+ or r1, r1, 0x80000 ; set AD bit -+ mov r2, @test05_excep_prep -+ sr r1, [erstatus] ; enable AD bit -+ sr r2, [eret] ; continue with the test -+ rtie -+ -+test05_excep_prep: -+ lr r7, [erbta] ; don't care for erbta -+ set_excep_params ecr=MISALIGNED_DATA_ACCESS, \ -+ eret=@test05_enter , \ -+ efa=TEST05_EFA , \ -+ erbta=r7 , \ -+ continue=@test05_wrapup , \ -+ test_num=5 -+ mov r10, sp ; backup sp to restore later -+ mov sp, TEST05_SP ; an address which is not 32-bit aligned -+test05_enter: -+ enter_s [r13-r26, fp] ; just being flamboyant -+ print "[FAIL] :test05:" ; this code must not fall through -+ b @endtest -+ -+test05_wrapup: -+ mov sp, r10 -+ lr r1, [status32] -+ and r1, r1, ~0x80000 ; clear AD bit -+ mov r2, @test06 ; go to next test -+ sr r1, [erstatus] ; disable AD bit -+ sr r2, [eret] ; continue with next test -+ rtie -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; a delay slot instruction --> illegal instruction sequence exception -+; the tricky thing in this test is that gas does not allow us to put -+; an "enter_s" in a delay slot (good job there!). however, we work -+; around it by writing the opcode at runtime. -+test06: -+ set_excep_params ecr=ILLEGAL_INSTRUCTION_SEQUENCE, \ -+ eret=@test06_delay , \ -+ efa=@test06_delay , \ -+ erbta=@test06_fail , \ -+ continue=@test07 , \ -+ test_num=6 -+ mov r1, 0xc0e2 ; opcode for enter_s [r13] -+ sth r1, [test06_delay] -+ b @test06_dummy_tb ; by having 'b' here, it is end of this tb. -+test06_dummy_tb: ; so this one will be decoded after mutation. -+ b.d @test06_fail -+test06_delay: -+ nop_s -+ nop_s -+ -+test06_fail: -+ print "[FAIL] :test06:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; an execution slot instruction --> illegal instruction sequence exception -+; TODO (issue #73): enable this after EI_S has been implemented. -+test07: -+; mov r1, @test07_ei_table -+; sr r1, [ei_base] -+; j @test07_begin -+; -+; .align 4 -+;test07_ei_table: -+; enter_s [r13] -+; -+;test07_begin: -+; set_excep_params ecr=ILLEGAL_INSTRUCTION_SEQUENCE, \ -+; eret=@test07_ei_table , \ -+; efa=@test07_ei_table , \ -+; erbta=@test07_fail , \ -+; continue=@test08 , \ -+; test_num=7 -+; ei_s 0 -+; -+;test07_fail: -+; print "failed: test07\n" -+; end -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; it is allowed to have "enter_s 0" in delay/execution slot because it is -+; like a nop then and is not a multi-cycle instruction. -+; TODO (issue #73): enable the ei_check part after EI_S has been done. -+test08: -+ mov r1, 0xc0e0 ; opcode for enter_s [] -+ sth r1, [test08_delay] -+ b @test08_dummy_tb ; by having 'b' here, it is end of this tb. -+test08_dummy_tb: ; so this one will be decoded after mutation. -+ b.d @test08_ei_check -+test08_delay: -+ nop_s ; at runtime this is enter_s [] and is ok -+ nop_s -+ -+ .align 4 -+test08_ei_table: -+ enter_s 0 -+ -+test08_ei_check: -+ ; TODO (issue #73): enable after EI_S is implemented. -+ ;mov r1, @test08_ei_table -+ ;sr r1, [ei_base] -+ ;ei_s 0 -+ ; fall through to the next test -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; 32 general registers configured AND u[3:0] > 14 (r13-r26) -+; OR -+; 16 general registers configured AND u[3:0] > 3 (r13-r15) -+; --> illegal instruction exception -+; TODO (issue #52): this test case must be executed with -+; -global cpu.num-regs=16. -+test09: -+; lr r7, [bta] ; don't care for erbta (use current bta) -+; set_excep_params ecr=ILLEGAL_INSTRUCTION, \ -+; eret=@test09_big_u3 , \ -+; efa=@test09_big_u3 , \ -+; erbta=r7 , \ -+; continue=@test10 , \ -+; test_num=9 -+;test09_big_u3: ; enter_s encoding : 1100 00UU 111u uuu0 -+; enter_s 4 -+; -+;test09_fail: -+; print "failed: test09\n" -+; end -+;;;;;;;;;;;;;;;;;;;;;;;;;;;; \ Enter Tests / ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;; / Leave Tests \ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; u7=0 leads to doing nothing -+test10: -+ mov r10, sp -+ leave_s 0 -+ brne sp, r10, @test10_fail -+ j @test11 -+ -+test10_fail: -+ print "[FAIL] :test10:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; restoring first 3 general purpose registers -+test11: -+ mov r10, sp ; ,--- top ---. -+ mov r3, 113 ; | r13 = 113 | -+ mov r4, 114 ; | r14 = 114 | -+ mov r5, 115 ; | r15 = 115 | -+ push r5 ; `-- bottom -' -+ push r4 -+ push r3 -+ leave_s [r13-r15] -+ brne r13, 113, @test11_fail -+ brne r14, 114, @test11_fail -+ brne r15, 115, @test11_fail -+ brne sp , r10, @test11_fail -+ j @test12 -+ -+test11_fail: -+ print "[FAIL] :test11:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; restoring blink register -+test12: -+ mov r10, sp -+ mov r1, 0x10123 -+ push r1 -+ leave_s [blink] -+ brne blink, 0x10123, @test12_fail -+ brne sp , r10, @test12_fail -+ j @test13 -+ -+test12_fail: -+ print "[FAIL] :test12:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; restoring fp register -+test13: -+ mov r10, sp -+ mov r1, 0x11321 -+ push r1 -+ mov fp, sp ; fp is pointing current frame now -+ mov sp, 0x4009 ; botch sp -+ leave_s [fp] ; 'leave_s' must look into fp for restoring -+ brne fp, 0x11321, @test13_fail -+ brne sp, r10, @test13_fail -+ j @test14 -+ -+test13_fail: -+ print "[FAIL] :test13" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; jumping to what blink holds -+test14: -+ mov r10, sp -+ mov blink, @test14_cont -+ leave_s [pcl] ; jump to whatever blink points to -+ j @test14_fail ; this should not be reached -+test14_cont: -+ brne sp, r10, @test14_fail -+ j @test15 -+ -+test14_fail: -+ print "[FAIL] :test14:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; restoring first 3 general purpose registers -+test15: -+ mov r0 , sp ; ,--------- top ----------. -+ mov r1 , @test15_return ; | blink = @test15_return | -+ mov r3 , 213 ; | r3 = 213 | -+ mov r4 , 214 ; | r4 = 214 | -+ mov r5 , 215 ; | r5 = 215 | -+ mov r6 , 216 ; | r6 = 216 | -+ mov r7 , 217 ; | r7 = 217 | -+ mov r8 , 218 ; | r8 = 218 | -+ mov r9 , 219 ; | r9 = 219 | -+ mov r10, 220 ; | r10 = 220 | -+ mov r11, 221 ; | r11 = 221 | -+ mov r12, 222 ; | r12 = 222 | -+ mov r13, 223 ; | r13 = 223 | -+ mov r14, 224 ; | r14 = 224 | -+ mov r15, 225 ; | r15 = 225 | -+ mov r16, 226 ; | r16 = 226 | -+ mov r2, 0x14456 ; | fp = 0x14456 | -+ push r2 ; `-------- bottom --------' -+ push r16 -+ push r15 -+ push r14 -+ push r13 -+ push r12 -+ push r11 -+ push r10 -+ push r9 -+ push r8 -+ push r7 -+ push r6 -+ push r5 -+ push r4 -+ push r3 -+ push r1 -+ mov fp, sp -+ mov sp, 0x1337 ; both sp again -+ leave_s [r13-r26, fp, blink, pcl] ; restore and do everything -+ j @test15_fail -+test15_return: -+ brne sp , r0, @test15_fail -+ brne blink, @test15_return, @test15_fail -+ brne r13 , 213, @test15_fail -+ brne r14 , 214, @test15_fail -+ brne r15 , 215, @test15_fail -+ brne r16 , 216, @test15_fail -+ brne r17 , 217, @test15_fail -+ brne r18 , 218, @test15_fail -+ brne r19 , 219, @test15_fail -+ brne r20 , 220, @test15_fail -+ brne r21 , 221, @test15_fail -+ brne r22 , 222, @test15_fail -+ brne r23 , 223, @test15_fail -+ brne r24 , 224, @test15_fail -+ brne r25 , 225, @test15_fail -+ brne r26 , 226, @test15_fail -+ brne fp , 0x14456, @test15_fail -+ j @test16 -+ -+test15_fail: -+ print "[FAIL] :test15:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; sp's value is not 32-bit aligned --> misaligned exception -+; this happens irrelevant of status32.AD bit -+test16: -+ .equ TEST16_FP, 0x777 ; an address which is not 32-bit aligned -+ lr r1, [status32] -+ or r1, r1, 0x80000 ; set AD bit -+ mov r2, @test16_excep_prep -+ sr r1, [erstatus] ; enable AD bit -+ sr r2, [eret] ; continue with the test -+ rtie -+ -+test16_excep_prep: -+ lr r7, [erbta] ; don't care for erbta -+ set_excep_params ecr=MISALIGNED_DATA_ACCESS, \ -+ eret=@test16_enter , \ -+ efa=TEST16_FP , \ -+ erbta=r7 , \ -+ continue=@test16_wrapup , \ -+ test_num=16 -+ mov r10, sp ; backup sp to restore later -+ mov fp, TEST16_FP ; an address which is not 32-bit aligned -+test16_enter: -+ leave_s [r13-r26, fp] ; first fp's value is put into sp -+ print "[FAIL] :test16:" ; this code must not fall through -+ b @endtest -+ -+test16_wrapup: -+ mov sp, r10 -+ lr r1, [status32] -+ and r1, r1, ~0x80000 ; clear AD bit -+ mov r2, @test17 ; go to next test -+ sr r1, [erstatus] ; disable AD bit -+ sr r2, [eret] ; continue with next test -+ rtie -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; a delay slot instruction --> illegal instruction sequence exception -+; the tricky thing in this test is that gas does not allow us to put -+; an "leave_s" in a delay slot (good job there!). however, we work -+; around it by writing the opcode at runtime. -+test17: -+ set_excep_params ecr=ILLEGAL_INSTRUCTION_SEQUENCE, \ -+ eret=@test17_delay , \ -+ efa=@test17_delay , \ -+ erbta=@test17_fail , \ -+ continue=@test18 , \ -+ test_num=17 -+ mov r1, 0xc0c2 ; opcode for leave_s [13] -+ sth r1, [test17_delay] -+ b @test17_dummy_tb ; by having 'b' here, it is end of this tb. -+test17_dummy_tb: ; so this one will be decoded after mutation. -+ b.d @test17_fail -+test17_delay: -+ nop_s -+ nop_s -+ -+test17_fail: -+ print "[FAIL] :test17:" -+ b @endtest -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; an execution slot instruction --> illegal instruction sequence exception -+; TODO (issue #73): enable this after EI_S has been implemented. -+test18: -+; mov r1, @test18_ei_table -+; sr r1, [ei_base] -+; j @test18_begin -+; -+; .align 4 -+;test18_ei_table: -+; leave_s [r13] -+; -+;test18_begin: -+; set_excep_params ecr=ILLEGAL_INSTRUCTION_SEQUENCE, \ -+; eret=@test18_ei_table , \ -+; efa=@test18_ei_table , \ -+; erbta=@test18_fail , \ -+; continue=@test19 , \ -+; test_num=18 -+; ei_s 0 -+; -+;test18_fail: -+; print "[FAIL] : test18\n" -+; end -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; it is allowed to have "leave_s 0" in delay/execution slot because it is -+; like a nop then and is not a multi-cycle instruction. -+; TODO (issue #73): enable the ei_check part after EI_S has been done. -+test19: -+ mov r1, 0xc0c0 ; opcode for leave_s [] -+ sth r1, [test19_delay] -+ b @test19_dummy_tb ; by having 'b' here, it is end of this tb. -+test19_dummy_tb: ; so this one will be decoded after mutation. -+ b.d @test19_ei_check -+test19_delay: -+ nop_s ; at runtime this is leave_s [] and is ok -+ nop_s -+ -+ .align 4 -+test19_ei_table: -+ leave_s 0 -+ -+test19_ei_check: -+ ; TODO (issue #73): enable after EI_S is implemented. -+ ;mov r1, @test19_ei_table -+ ;sr r1, [ei_base] -+ ;ei_s 0 -+ ; fall through to the next test -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; 32 general registers configured AND u[3:0] > 14 (r13-r26) -+; OR -+; 16 general registers configured AND u[3:0] > 3 (r13-r15) -+; --> illegal instruction exception -+; TODO (issue #52): this test case must be executed with -+; -global cpu.num-regs=16. -+test20: -+; lr r7, [bta] ; don't care for erbta (use current bta) -+; set_excep_params ecr=ILLEGAL_INSTRUCTION, \ -+; eret=@test20_big_u3 , \ -+; efa=@test20_big_u3 , \ -+; erbta=r7 , \ -+; continue=@test21 , \ -+; test_num=20 -+;test20_big_u3: ; leave_s encoding : 1100 0UUU 110u uuu0 -+; leave_s 4 -+; -+;test20_fail: -+; print "[FAIL] : test20\n" -+; b @endtest -+;;;;;;;;;;;;;;;;;;;;;;;;;;;; \ Leave Tests / ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; / Enter/Leave Test \ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; testing enter_s/leave_s together full fledged. -+test21: -+ mov r0 , sp ; original sp -+ mov r13, 0x80000013 -+ mov r14, 0x80000014 -+ mov r15, 0x80000015 -+ mov r16, 0x80000016 -+ mov r17, 0x80000017 -+ mov r18, 0x80000018 -+ mov r19, 0x80000019 -+ mov r20, 0x8000001a -+ mov r21, 0x8000001b -+ mov r22, 0x8000001c -+ mov r23, 0x8000001d -+ mov r24, 0x8000001e -+ mov r25, 0x8000001f -+ mov r26, 0x80000020 -+ mov r27, 0x88888888 ; fp -+ mov r31, @test21_verify ; blink -+ -+ enter_s [r13-r26, fp, blink] -+ ; botching all except for fp. it's already changed to current sp. -+ breq r28, 0x88888888, @test21_fail ; sanity check that fp changed -+ mov r1 , 0xdeadbeef -+ mov r13, r1 -+ mov r14, r1 -+ mov r15, r1 -+ mov r16, r1 -+ mov r17, r1 -+ mov r18, r1 -+ mov r19, r1 -+ mov r20, r1 -+ mov r21, r1 -+ mov r22, r1 -+ mov r23, r1 -+ mov r24, r1 -+ mov r25, r1 -+ mov r26, r1 -+ mov r28, r1 ; botch sp -+ mov r31, r1 ; botch blink -+ leave_s [r13-r26, fp, blink, pcl] -+ j @test21_fail -+ -+test21_verify: -+ brne r13, 0x80000013, @test21_fail -+ brne r14, 0x80000014, @test21_fail -+ brne r15, 0x80000015, @test21_fail -+ brne r16, 0x80000016, @test21_fail -+ brne r17, 0x80000017, @test21_fail -+ brne r18, 0x80000018, @test21_fail -+ brne r19, 0x80000019, @test21_fail -+ brne r20, 0x8000001a, @test21_fail -+ brne r21, 0x8000001b, @test21_fail -+ brne r22, 0x8000001c, @test21_fail -+ brne r23, 0x8000001d, @test21_fail -+ brne r24, 0x8000001e, @test21_fail -+ brne r25, 0x8000001f, @test21_fail -+ brne r26, 0x80000020, @test21_fail -+ brne r27, 0x88888888, @test21_fail -+ brne r28, r0, @test21_fail -+ breq r31, @test21_verify, @valhalla -+ -+test21_fail: -+ print "[FAIL] :test20:" -+ b @endtest -+;;;;;;;;;;;;;;;;;;;;;;;;; \ Enter/Leave Test / ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+endtest: -+ print " enter/leave\n" -+ end -+ -+ -+; vim: set syntax=asm ts=2 sw=2 et: -diff --git a/tests/tcg/arc/check_excp.S b/tests/tcg/arc/check_excp.S -new file mode 100644 -index 0000000000..18b436dec7 ---- /dev/null -+++ b/tests/tcg/arc/check_excp.S -@@ -0,0 +1,17 @@ -+ .include "macros.inc" -+ -+ start -+ -+ test_name TRAP_1 -+ trap_s 0 -+ print "[PASS] TRAP_1:1\n" -+ trap_s 1 -+ print "[PASS] TRAP_1:2\n" -+ end -+ -+ .align 4 -+ .global EV_Trap -+ .type EV_Trap, @function -+EV_SWI: -+EV_Trap: -+ rtie -diff --git a/tests/tcg/arc/check_excp_1.c b/tests/tcg/arc/check_excp_1.c -new file mode 100644 -index 0000000000..f06720c119 ---- /dev/null -+++ b/tests/tcg/arc/check_excp_1.c -@@ -0,0 +1,15 @@ -+#include -+ -+void main (void) -+{ -+ __builtin_arc_trap_s (0); -+ printf ("[PASS] TRAPC:1\n"); -+ __builtin_arc_trap_s (1); -+ printf ("[PASS] TRAPC:2\n"); -+} -+ -+void __attribute__ ((interrupt("ilink"))) -+EV_Trap (void) -+{ -+ printf ("[PASS] TRAPC:IRQ\n"); -+} -diff --git a/tests/tcg/arc/check_excp_jumpdl_mmu.S b/tests/tcg/arc/check_excp_jumpdl_mmu.S -new file mode 100644 -index 0000000000..a98229eba2 ---- /dev/null -+++ b/tests/tcg/arc/check_excp_jumpdl_mmu.S -@@ -0,0 +1,44 @@ -+.include "macros.inc" -+ -+.equ PHYSICAL_ADDRESS_START, 0x80000000 -+.equ MMU_ENABLE_FLAG , 0x80000000 -+ -+start -+ -+; use physical address range for handling exceptions (ivt) -+mov r0, PHYSICAL_ADDRESS_START -+sr r0, [int_vector_base] -+ -+# enable mmu -+mov r3, MMU_ENABLE_FLAG -+sr r3, [pid] -+xor_s r3, r3, r3 -+ -+; write to some virtual address range in a delay slot -+mov r2, 0x1000 -+mov r1, @check -+j_s.d [r1] # let's enjoy the code after delay slot is executed. -+st r0, [r2] # oh, oh: exception! -+ -+# this line should not be executed -+add_s r3, r3, 1 -+ -+check: -+brgt r3, 0, @fail -+print "[ OK]" -+b @rest -+fail: -+print "[NOK]" -+ -+rest: -+print " Exception in a delay slot.\n" -+ -+end -+ -+ .align 4 -+ .global EV_TLBMissD -+ .type EV_TLBMissD, @function -+EV_TLBMissD: -+ # disable mmu -+ sr r3, [pid] -+ rtie -diff --git a/tests/tcg/arc/check_excp_mmu.S b/tests/tcg/arc/check_excp_mmu.S -new file mode 100644 -index 0000000000..8d1cf83445 ---- /dev/null -+++ b/tests/tcg/arc/check_excp_mmu.S -@@ -0,0 +1,69 @@ -+.include "macros.inc" -+.include "mmu.inc" -+ -+; courtesy of macros.inc and mmu.inc -+.extern REG_IVT_BASE -+.extern PAGE_NUMBER_MSK -+.extern REG_PD0_GLOBAL -+.extern REG_PD0_VALID -+.extern REG_PD1_KRNL_W -+ -+; test data -+; making an entry for the TLB -+; -+; ,------------------------------------. -+; | VPN(VA), G=1, V=1 | PPN(PHY), Wk=1 | -+; `------------------------------------' -+; where: -+; VPN(VA) is the virtual page number of logical address -+; G is the global bit -+; V is the validity bit -+; PPN(PHY) is the physical page number -+; Wk is the write permission in kernel mode -+ -+; obviously, the offsets in both addresses must be the same -+.equ VIRT_ADR , 0x13371334 ; the virtual address; word aligned -+.equ PHYS_ADR , 0x73311334 ; the physical address > 0x7FFFFFFF -+.equ MAGICDATA, 0x00BADB07 ; the test value to write and verify -+.equ PD0_VPN , (VIRT_ADR & PAGE_NUMBER_MSK) -+.equ PD1_PPN , (PHYS_ADR & PAGE_NUMBER_MSK) -+.equ PD0_BITS , (PD0_VPN | REG_PD0_GLOBAL | REG_PD0_VALID) -+.equ PD1_BITS , (PD1_PPN | REG_PD1_KRNL_W) -+.equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT -+ -+start -+ -+; use physicall address range for handling exceptions (ivt) -+mov r0, INT_VECT_ADDRESS -+sr r0, [REG_IVT_BASE] -+ -+mmu_enable -+ -+; write to the mapped virtual address -+mov r0, MAGICDATA -+st r0, [VIRT_ADR] -+ -+mmu_disable -+ -+; with mmu disabled, read from physical address and -+; verify that it is the same as the value written -+; to the mapped virtual address earlier -+ld r1, [PHYS_ADR] -+cmp r0, r1 ; r0 contains the MAGICDATA -+beq @goodboy -+ -+print "nope, still no MMU!\n" -+j @adios -+ -+goodboy: -+print "Yay, you got the MMU right :)\n" -+ -+adios: -+end -+ -+ .align 4 -+ .global EV_TLBMissD -+ .type EV_TLBMissD, @function -+EV_TLBMissD: -+ mmu_tlb_insert PD0_BITS, PD1_BITS -+ rtie -diff --git a/tests/tcg/arc/check_flags.S b/tests/tcg/arc/check_flags.S -new file mode 100644 -index 0000000000..92faf18c15 ---- /dev/null -+++ b/tests/tcg/arc/check_flags.S -@@ -0,0 +1,23 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# flags.S -+#----------------------------------------------------------------------------- -+# -+# Test or instruction. -+# -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ TEST_2OP_CARRY (2, sub, 0, 0x00000000, 0x0000000) ; -+ TEST_2OP_CARRY (3, sub, 1, 0x00000000, 0x0000001) ; -+ TEST_2OP_ZERO (4, sub, 0, 0x00000001, 0x0000000) ; -+ TEST_2OP_ZERO (5, sub, 1, 0x00000001, 0x0000001) ; -+ TEST_2OP_NEGATIVE (6, sub, 0, 0x00000000, 0x00000000) ; -+ TEST_2OP_NEGATIVE (7, sub, 1, 0x00000000, 0x00000001) ; -+ TEST_2OP_OVERFLOW (8, sub, 0, 0x00000000, 0x00000000) ; -+ TEST_2OP_OVERFLOW (9, sub, 1, 0x00000000, 0x80000000) ; -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_ldaw_mmu.S b/tests/tcg/arc/check_ldaw_mmu.S -new file mode 100644 -index 0000000000..a503c607b9 ---- /dev/null -+++ b/tests/tcg/arc/check_ldaw_mmu.S -@@ -0,0 +1,71 @@ -+.include "macros.inc" -+.include "mmu.inc" -+ -+; courtesy of mmu.inc -+.extern PAGE_NUMBER_MSK -+.extern REG_PD0_GLOBAL -+.extern REG_PD0_VALID -+.extern REG_PD1_KRNL_W -+ -+; test data -+; making an entry for the TLB -+; -+; ,------------------------------------. -+; | VPN(VA), G=1, V=1 | PPN(PHY), Wk=1 | -+; `------------------------------------' -+; where: -+; VPN(VA) is the virtual page number of logical address -+; G is the global bit -+; V is the validity bit -+; PPN(PHY) is the physical page number -+; Wk is the write permission in kernel mode -+ -+; obviously, the offsets in both addresses must be the same -+.equ VIRT_ADR , 0x13371334 ; the virtual address; word aligned -+.equ PHYS_ADR , 0x73311334 ; the physical address > 0x7FFFFFFF -+.equ MAGICDATA, 0x00BADB07 ; the test value to write and verify -+.equ PD0_VPN , (VIRT_ADR & PAGE_NUMBER_MSK) -+.equ PD1_PPN , (PHYS_ADR & PAGE_NUMBER_MSK) -+.equ PD0_BITS , (PD0_VPN | REG_PD0_GLOBAL | REG_PD0_VALID) -+.equ PD1_BITS , (PD1_PPN | REG_PD1_KRNL_R) -+.equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT -+ -+start -+ -+; use physicall address range for handling exceptions (ivt) -+mov r0, INT_VECT_ADDRESS -+sr r0, [REG_IVT_BASE] -+ -+; initialize the data in physical address -+mov r0, MAGICDATA -+st r0, [PHYS_ADR] -+ -+mmu_enable -+ -+; read from the mapped virtual address -+mov r2, 0 -+ld.aw r1, [r2, VIRT_ADR] -+ -+mmu_disable -+ -+; with mmu disabled, read from physical address and -+; verify that it is the same as the value written -+; to the mapped virtual address earlier -+cmp r0, r1 ; r0 contains the MAGICDATA -+beq @goodboy -+ -+print "nope, still no MMU!\n" -+j @adios -+ -+goodboy: -+print "Yay, you got the MMU right :)\n" -+ -+adios: -+end -+ -+.align 4 -+.global EV_TLBMissD -+.type EV_TLBMissD, @function -+EV_TLBMissD: -+mmu_tlb_insert PD0_BITS, PD1_BITS -+rtie -diff --git a/tests/tcg/arc/check_ldstx.S b/tests/tcg/arc/check_ldstx.S -new file mode 100644 -index 0000000000..ac181d9a51 ---- /dev/null -+++ b/tests/tcg/arc/check_ldstx.S -@@ -0,0 +1,37 @@ -+#***************************************************************************** -+# ldst.S -+#----------------------------------------------------------------------------- -+# -+# This test verifies that ld, ldb, ldw work as expected. -+# -+ -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ TEST_CASE(2, r0, 0x40000000, "ld:2", ld r1,[@tdat]` ld r0,[r1,@tdat]) -+ TEST_CASE(3, r0, 0xbeef, "ld:3", mov r1, 16` ldw r0,[r1, @tdat]) -+ TEST_CASE(4, r0, 0xbe, "ld:4", mov r1, 20` ldb r0,[r1, @tdat]) -+ TEST_CASE(5, r0, 0xffffbeef, "ld:5", mov r1, 16` ldw.x r0,[r1, @tdat]) -+ TEST_CASE(6, r0, 0xffffffbe, "ld:6", mov r1, 20` ldb.x r0,[r1, @tdat]) -+ -+ TEST_CASE(7, r0, 0xbeef, "ld:7", mov r1, @tdat` ldw.as r0,[r1,8]) -+ TEST_CASE(8, r0, 0xcafebabe, "ld:8", mov r1, @tdat` ld.as r0,[r1, 5]) -+ TEST_CASE(9, r0, 0xcafebabe, "ld:9", mov r2, 5` mov r1, @tdat` ld_s.as r0,[r1, r2]) -+ TEST_CASE(10, r0, 0x40400000, "ld:10", ldd.as r0,[@tdat,2]) -+ TEST_CASE(11, r1, 0xc0800000, "ld:11", ldd.as r0,[@tdat,2]) -+ -+ -+ARCTEST_END -+# TEST_DATA -+ -+tdat: -+.word 0x00000004 -+.word 0x40000000 -+.word 0x40400000 -+.word 0xc0800000 -+.word 0xdeadbeef -+.word 0xcafebabe -+.word 0xabad1dea -+.word 0x1337d00d -diff --git a/tests/tcg/arc/check_lp.S b/tests/tcg/arc/check_lp.S -new file mode 100644 -index 0000000000..4074cfa1e5 ---- /dev/null -+++ b/tests/tcg/arc/check_lp.S -@@ -0,0 +1,12 @@ -+.include "macros.inc" -+ -+ start -+ mov_s r2,0x28cc -+ sub r3,0x28d8,r2 -+ mov lp_count,0x00fffff0 -+ lpne bla -+ st.ab r3,[r2,4] -+ mov 0,0 -+bla: -+ print "[PASS] LP: simple\n" -+ end -diff --git a/tests/tcg/arc/check_lp02.S b/tests/tcg/arc/check_lp02.S -new file mode 100644 -index 0000000000..866fa01f36 ---- /dev/null -+++ b/tests/tcg/arc/check_lp02.S -@@ -0,0 +1,72 @@ -+.include "macros.inc" -+ -+ start -+ mov r3,0 -+ mov r2, 0x2e10 -+ mov.f lp_count,0x10 -+ lpne 2f -+ st.ab r3,[r2,4] -+2: -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ mov r2,0x1000 -+ mov_s r3,0xa -+ and.f lp_count,r3, 0x1f -+ lpnz 2f -+ add r2,r2,r2 -+2: # end single insn loop -+ -+ print "[PASS] LP01\n" -+ end -diff --git a/tests/tcg/arc/check_lp03.S b/tests/tcg/arc/check_lp03.S -new file mode 100644 -index 0000000000..76e70958f0 ---- /dev/null -+++ b/tests/tcg/arc/check_lp03.S -@@ -0,0 +1,49 @@ -+ .include "macros.inc" -+ -+ start -+ test_name ZOLvsIRQ -+ ;; Program the Timer such that we get fast interrupts -+ sr 0x01,[control0] -+ sr 0x1ff,[limit0] -+ sr 0,[count0] -+ mov r0,0 -+ mov sp,0x1000 -+ ;; enable global interrupts -+ seti -+ ;; Make a short ZOL -+ mov lp_count,0x1ffff -+ lp 1f -+ nop -+1: -+ clri -+ stb.ab 0,[sp,1] -+2: -+ rem r2,r0,10 -+ add r2,r2,0x30 -+ stb.ab r2,[sp,1] -+ div.f r0,r0,10 -+ bne 2b -+3: -+ ld.aw r2,[sp,-1] -+ breq r2,0,4f -+ ;; stb r2,[OUTPUT_DEVICE] -+ brne r2,0,3b -+4: -+ print "[PASS] " -+ printl r30 -+ end -+ -+ ;; Timer ISR -+ .align 4 -+ .global IRQ_Timer0 -+ .type IRQ_Timer0, @function -+IRQ_Timer0: -+ clri -+ ;; reset the pending interrupt and reneable it. -+ sr 0x01,[control0] -+ sr 0,[count0] -+ add r0,r0,1 -+ rtie -+ print "[FAIL] " -+ printl r30 -+ end -diff --git a/tests/tcg/arc/check_lp04.S b/tests/tcg/arc/check_lp04.S -new file mode 100644 -index 0000000000..8a2ca6e432 ---- /dev/null -+++ b/tests/tcg/arc/check_lp04.S -@@ -0,0 +1,48 @@ -+.include "macros.inc" -+ -+ start -+ -+ ; memset params -+ mov r0, data ; address to write -+ mov r1, 0 ; data to write -+ mov r2, 0x13 ; size of memory to clear -+ -+ ; align the address -+ and r4, r0, 3 -+ rsub.f lp_count, r4, 4 -+ lpne @main_clear -+ stb.ab r1, [r0, 1] -+ sub r2, r2, 1 -+ -+main_clear: -+ ; main setting to zero -+ and.f lp_count, r2, 0x1f -+ lpne @verify -+ stb.ab r1, [r0, 1] -+ -+verify: -+ ld r1, [data, 0x12] -+ cmp r1, 0x66665500 -+ beq @good -+ print "[FAIL] " -+ j @the_end -+good: -+ print "[PASS] " -+the_end: -+ print "LP04\n" -+ end -+ -+.align 4 -+make_unaligned: -+ .2byte 0xffff -+data: -+ .4byte 0x11111111 -+ .4byte 0x22222222 -+ .4byte 0x33333333 -+ .4byte 0x44444444 -+ .4byte 0x55555555 -+ .4byte 0x66666666 -+ .4byte 0x77777777 -+ .4byte 0x88888888 -+ .4byte 0x99999999 -+ .4byte 0xAAAAAAAA -diff --git a/tests/tcg/arc/check_lp05.S b/tests/tcg/arc/check_lp05.S -new file mode 100644 -index 0000000000..2fc9e40b97 ---- /dev/null -+++ b/tests/tcg/arc/check_lp05.S -@@ -0,0 +1,23 @@ -+ .include "macros.inc" -+;;; Test what is happening when we have a trap_s at the end of a zol -+ start -+ mov r0,0 -+ mov lp_count, 0x1f -+ lp 1f -+ trap_s 0 -+1: -+ breq r0,0x1f,1f -+ print "[FAIL]" -+ b 2f -+1: -+ print "[PASS]" -+2: -+ print " LP05\n" -+ end -+ -+ .align 4 -+ .global EV_Trap -+ .type EV_Trap, @function -+EV_Trap: -+ add r0,r0,1 -+ rtie -diff --git a/tests/tcg/arc/check_lp06.S b/tests/tcg/arc/check_lp06.S -new file mode 100644 -index 0000000000..60e7a66309 ---- /dev/null -+++ b/tests/tcg/arc/check_lp06.S -@@ -0,0 +1,163 @@ -+; check_lp06.S -+; -+; Tests for Zero overhead loop: interrupting the loop -+; If the test fails, check the end of this file for how to troubleshoot. -+ -+ .include "macros.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case counter -+.data -+test_nr: -+ .word 0x0 -+ -+; Increment the test counter. -+.macro prep_test_case -+ ld r13, [test_nr] -+ add_s r13, r13, 1 ; increase test case counter -+ st r13, [test_nr] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Handler of the day. -+ .align 4 -+handler : .word 0x0 -+ -+; An exception handler routine that merely jumps to whatever address -+; it was told to by the test. See set_except_handler macro. This -+; requires ivt.S file to be compiled and linked. -+ .align 4 -+ .global EV_Trap -+ .global EV_SWI -+ .type EV_Trap, @function -+ .type EV_SWI, @function -+EV_SWI: -+EV_Trap: -+ ld r11, [handler] -+ j [r11] -+ -+; macro: set_except_handler -+; regs used: r11 -+; -+; This macro writes the provided ADDR to a temporary place holder -+; that later the exception handler routine will jump to. -+.macro set_except_handler addr -+ mov r11, \addr -+ st r11, [handler] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ZOL ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Let the tests begin -+ start -+ -+; Test case 1 -+; Having a 'trap_s' at the end of a loop body. The exception handler -+; must return to the _next instruction_ after the trap which is the -+; LOOP_END. Consequently, it should end up in the LOOP_START if the -+; LP_COUNT != 1. To cut a long story short: -+; next instruction(trap) = loop_start and all iterations should finish -+; before getting out of the loop. -+ prep_test_case -+ set_except_handler @test_1_except_handler -+ mov r0, 0 -+ mov lp_count, 0x1f -+ lp @test_1_loop_end -+ trap_s 0 -+test_1_loop_end: -+ cmp r0, 0x1f ; has the loop finished completely? -+ bne @fail -+ b @test_1_end ; success -+test_1_except_handler: -+ add r0, r0, 1 -+ rtie -+test_1_end: -+ ; Fall through -+ -+; Test case 2 -+; Having a 'swi' at the end of a loop body. The exception handler -+; must return to the _last instruction_ of the loop body and the -+; whole loop must finish completely. -+; Going back to 'swi' is tricky because it keeps triggering the -+; exception. So, after the first trigger, we change it to NOPs. -+ prep_test_case -+ set_except_handler @test_2_except_handler -+ mov r0, 0 ; exception trigger mark -+ mov r1, 0 ; loop counting -+ mov lp_count, 0x1f -+ lp @test_2_loop_end -+ add r1, r1, 1 -+test_2_last_insn_loop: -+ swi -+test_2_loop_end: -+ cmp r1, 0x1f ; has the loop finished completely? -+ bne @fail -+ cmp r0, 1 ; exception triggered? -+ bne @fail -+ b @test_2_end ; success -+test_2_except_handler: -+ add r0, r0, 1 -+ mov r11, @test_2_last_insn_loop -+ mov r12, 0x78e0 ; NOP_S opcode -+ sth.ab r12, [r11,2] ; write two NOP_S instead of one NOP -+ sth r12, [r11] ; to avoid misaligned exception. -+ rtie -+test_2_end: -+ ; Fall through -+ -+; Test case 3 -+; Check if _any_ fetch of instruction at address LOOP_END trigger -+; going back to the loop start if the LP_COUNT is not 1. To test -+; that: -+; Jump out of the loop prematurely. -+; Then outside the loop jump back inside the lopp. -+; This should trigger going back to the loop, but do not jump out -+; prematurely anymore. -+ prep_test_case -+ mov r0, 0 ; loop counter -+ mov r2, 0 ; indicator if we jumped to LOOP_END before -+ mov lp_count, 17 -+ lp @test_3_loop_end -+ cmp r2, 1 -+ bne @test_3_outside_loop -+test_3_last_insn_loop: -+ add r0, r0, 1 -+test_3_loop_end: -+ add r3, r2, r0 ; r3 = 1 + 17 -+test_3_outside_loop: -+ add r2, r2, 1 -+ cmp r2, 1 -+ beq @test_3_last_insn_loop -+ cmp r0, 17 ; sanity checks begin -+ bne @fail -+ cmp r2, 2 ; once we jumped there, once fall through. -+ bne @fail -+ cmp r3, 18 -+ bne @fail -+ -+; Next test cases -+; Timer interrupt and a single insn ZOL. We need to check if indeed we get multiple interrupts, while in ZOL. -+; Timer interrupt and CLRI/SETI body ZOL. The same as above, 2 tests with seti/clri and clri/seti instruction order. -+; Last instruction of a ZOL gets a MMU TLBI miss. -+; Last instruction of a ZOL gets a MMU TLBD miss (load/store). -+; Last instruction of a ZOL gets a MMU TLBI fallowed by a MMU TLBD miss. -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [test_nr] -+ ;print_number r0 -+ print "[FAIL]" -+1: -+ print " Zero overhead loop: interrupting the loop\n" -+ end -diff --git a/tests/tcg/arc/check_lsrx.S b/tests/tcg/arc/check_lsrx.S -new file mode 100644 -index 0000000000..9f72e84eb5 ---- /dev/null -+++ b/tests/tcg/arc/check_lsrx.S -@@ -0,0 +1,33 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# lsr.S -+#----------------------------------------------------------------------------- -+# -+# Test or instruction. -+# -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ TEST_RR_3OP ( 2, lsr, 0x00000000, 0x00000000, 0); -+ TEST_RR_3OP ( 3, lsr, 0x12345678, 0x12345678, 0); -+ TEST_RR_3OP ( 4, lsr, 0x01234567, 0x12345678, 4); -+ TEST_RR_3OP ( 5, lsr, 0x0ABCDEF4, 0xABCDEF45, 4); -+ TEST_RR_3OP ( 6, lsr, 0x00000000, 0x7FFFFFFF, 31); -+ TEST_RR_3OP ( 7, lsr, 0x00000001, 0xFFFFFFFF, 31); -+ -+ #------------------------------------------------------------- -+ # Flag tests -+ #------------------------------------------------------------- -+ TEST_2OP_CARRY( 9, lsr, 0, 0x00000001, 0x02); -+ TEST_2OP_CARRY(10, lsr, 1, 0x00000001, 0x01); -+ TEST_2OP_ZERO( 11, lsr, 1, 0x00000001, 0x01); -+ TEST_2OP_NEGATIVE( 12, lsr, 1, 0x80000000, 0x00); -+ -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_mac.S b/tests/tcg/arc/check_mac.S -new file mode 100644 -index 0000000000..7e172457ab ---- /dev/null -+++ b/tests/tcg/arc/check_mac.S -@@ -0,0 +1,228 @@ -+.include "macros.inc" -+ -+.equ NOTSET, 47806 -+ -+; conditionally sets the ACC data -+.macro setup_acc acch, accl -+ .if \accl <> NOTSET -+ mov r58, \accl -+ .endif -+ .if \acch <> NOTSET -+ mov r59, \acch -+ .endif -+.endm -+ -+; conditionally checks if ACC holds the given value -+.macro verify_acc racch, raccl, test_num -+ .if \raccl <> NOTSET -+ assert_eq r58, \raccl, \test_num -+ .endif -+ .if \racch <> NOTSET -+ assert_eq r59, \racch, \test_num -+ .endif -+.endm -+ -+; all Z, N, C, V flags are cleared and ACC will become 0 -+.macro clear_flags_and_accu -+ ; clearing the Z N C V flags -+ mov r0, 1 -+ add.f r0, r0, r0 -+ ; clearing the acc -+ mov r58, 0 -+ mov r59, 0 -+.endm -+ -+; checks if Z, N, C, and V flags are set correctly -+.macro verify_flags z=0, n=0, c=0, v=0, test_num -+ assert_flag REG_STAT_Z, \z, \test_num -+ assert_flag REG_STAT_N, \n, \test_num -+ assert_flag REG_STAT_C, \c, \test_num -+ assert_flag REG_STAT_V, \v, \test_num -+.endm -+ -+; macro for testing "MAC" instruction -+.macro mac_test acch=NOTSET, accl=NOTSET, val1, val2, res, racch=NOTSET, raccl=NOTSET, n=0, v=0, test_num -+ ; initializing data -+ setup_acc \acch, \accl -+ mov r0, \val1 -+ mov r1, \val2 -+ ; operation under test -+ mac.f r0, r0, r1 -+ ; checking the results -+ verify_flags n=\n, v=\v, test_num=\test_num -+ assert_eq \res, r0, \test_num -+ verify_acc \racch, \raccl, \test_num -+.endm -+ -+; macro for testing "MACU" instruction -+.macro macu_test acch=NOTSET, accl=NOTSET, val1, val2, res, racch=NOTSET, raccl=NOTSET, v=0, test_num -+ ; initializing data -+ setup_acc \acch, \accl -+ mov r0, \val1 -+ mov r1, \val2 -+ ; operation under test -+ macu.f r0, r0, r1 -+ ; checking the results -+ verify_flags v=\v, test_num=\test_num -+ assert_eq \res, r0, \test_num -+ verify_acc \racch, \raccl, \test_num -+.endm -+ -+ -+; macro for testing "MACD" instruction -+.macro macd_test acch=NOTSET, accl=NOTSET, val1, val2, resh, resl, racch=NOTSET, raccl=NOTSET, n=0, v=0, test_num -+ ; initializing data -+ setup_acc \acch, \accl -+ mov r0, \val1 -+ mov r1, \val2 -+ ; operation under test -+ macd.f r0, r0, r1 -+ ; checking the results -+ verify_flags n=\n, v=\v, test_num=\test_num -+ assert_eq \resl, r0, \test_num -+ assert_eq \resh, r1, \test_num -+ verify_acc \racch, \raccl, \test_num -+.endm -+ -+; macro for testing "MACU" instruction -+.macro macdu_test acch=NOTSET, accl=NOTSET, val1, val2, resh, resl, racch=NOTSET, raccl=NOTSET, v=0, test_num -+ ; initializing data -+ setup_acc \acch, \accl -+ mov r0, \val1 -+ mov r1, \val2 -+ ; operation under test -+ macdu.f r0, r0, r1 -+ ; checking the results -+ verify_flags v=\v, test_num=\test_num -+ assert_eq \resl, r0, \test_num -+ assert_eq \resh, r1, \test_num -+ verify_acc \racch, \raccl, \test_num -+.endm -+ -+ -+start -+ -+;;;;;;;;;;;;;;;;;;;;;; MAC ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; acc = 0 + 4*5 = 20 -+mac_test val1=4, val2=5, res=20, test_num=1 -+; acc = 20 + 5*1 = 25 -+mac_test val1=1, val2=5, res=25, test_num=2 -+; acc = 25 + -1*5 = 20 -+mac_test val1=0xFFFFFFFF, val2=0x5, res=20, racch=0x0, raccl=20, n=0, test_num=3 -+; acc = 20 + -3*9 = -7 -+mac_test val1=0xFFFFFFFD, val2=0x09, res=0xFFFFFFF9, racch=0xFFFFFFFF, raccl=0xFFFFFFF9, n=1, test_num=4 -+; producing a result that sets both acch and accl -+mac_test acch=0, accl=0, val1=0x7FFFFFFF, val2=0x7FFFFFFF, res=1, racch=0x3FFFFFFF, raccl=0x01, n=0, v=0, test_num=5 -+; acc is 0x3FFFFFFF00000001 -+mac_test val1=0x80000000, val2=0x80000000, res=1, racch=0x7FFFFFFF, raccl=0x01, n=0, v=0, test_num=6 -+; acc is 0x7FFFFFFF00000001; going for the kill: N and V will be set -+mac_test val1=0x12344321, val2=0x56788654, res=0xE1C14CD5, racch=0x86262098, raccl=0xE1C14CD5, n=1, v=1, test_num=7 -+; "mac" is not supposed to clear the overflow bit -+mac_test acch=0, accl=0, val1=0, val2=0, res=0, racch=0, raccl=0, n=0, v=1, test_num=8 -+clear_flags_and_accu -+ -+ -+;;;;;;;;;;;;;;;;;;;;;; MACU ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; acc = 0 + 4*5 = 20 -+macu_test val1=4, val2=5, res=20, test_num=9 -+; acc = 20 + 5*1 = 25 -+macu_test val1=1, val2=5, res=25, test_num=10 -+; acc = 25 + 21,474,836,475 = 21,474,836,500 (0x00000005,0x00000014) -+macu_test val1=0xFFFFFFFF, val2=0x5, res=20, racch=5, raccl=20, test_num=11 -+; acc = 21,474,836,500 + 38,654,705,637 = 60,129,542,137 (0x0000000D,0xFFFFFFF9) -+macu_test val1=0xFFFFFFFD, val2=0x09, res=0xFFFFFFF9, racch=0x0D, raccl=0xFFFFFFF9, test_num=12 -+; producing a result that sets both acch and accl -+macu_test acch=0, accl=0, val1=0x7FFFFFFF, val2=0x7FFFFFFF, res=1, racch=0x3FFFFFFF, raccl=0x01, v=0, test_num=13 -+; acc is 0x3FFFFFFF00000001 -+macu_test val1=0x80000000, val2=0x80000000, res=1, racch=0x7FFFFFFF, raccl=0x01, v=0, test_num=14 -+; acc is 0x7FFFFFFF00000001; line below still will not trigger an overflow for MACU -+macu_test val1=0x12344321, val2=0x56788654, res=0xE1C14CD5, racch=0x86262098, raccl=0xE1C14CD5, v=0, test_num=15 -+; cause an overflow -+macu_test acch=0xFFFFFFFF, accl=0xFFFFFFFF, val1=1, val2=1, res=0, racch=0, raccl=0, v=1, test_num=16 -+; "macu" is not supposed to clear the overflow bit -+macu_test acch=0, accl=0, val1=0, val2=0, res=0, racch=0, raccl=0, v=1, test_num=17 -+clear_flags_and_accu -+ -+ -+;;;;;;;;;;;;;;;;;;;;; MACD ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+macd_test val1=4, val2=5, resh=0, resl=20, test_num=18 -+; acc is now 20 -+macd_test val1=1, val2=5, resh=0, resl=25, test_num=19 -+; acc = 25 + -1*5 = 20 -+macd_test val1=0xFFFFFFFF, val2=0x5, resh=0, resl=20, racch=0x0, raccl=20, n=0, test_num=20 -+; acc = 20 + -3*9 = -7 -+macd_test val1=0xFFFFFFFD, val2=0x09, resh = 0xFFFFFFFF, resl=0xFFFFFFF9, racch=0xFFFFFFFF, raccl=0xFFFFFFF9, n=1, test_num=21 -+; producing a result that sets both acch and accl -+macd_test acch=0, accl=0, val1=0x7FFFFFFF, val2=0x7FFFFFFF, resh=0x3FFFFFFF, resl=0x01, racch=0x3FFFFFFF, raccl=0x01, v=0, test_num=22 -+; acc is 0x3FFFFFFF00000001 -+macd_test val1=0x80000000, val2=0x80000000, resh=0x7FFFFFFF, resl=0x01, racch=0x7FFFFFFF, raccl=0x01, v=0, test_num=23 -+; acc is 0x7FFFFFFF00000001; going for the kill: N and V will be set -+macd_test val1=0x12344321, val2=0x56788654, resh=0x86262098, resl=0xE1C14CD5, racch=0x86262098, raccl=0xE1C14CD5, n=1, v=1, test_num=24 -+; "macd" is not supposed to clear the overflow bit -+macd_test acch=0, accl=0, val1=0, val2=0, resh=0, resl=0, racch=0, raccl=0, n=0, v=1, test_num=25 -+clear_flags_and_accu -+ -+ -+;;;;;;;;;;;;;;;;;;;; MACDU ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+macdu_test val1=4, val2=5, resh=0, resl=20, test_num=26 -+; acc is now 20 -+macdu_test val1=1, val2=5, resh=0, resl=25, test_num=27 -+; acc = 25 + 21,474,836,475 = 21,474,836,500 (0x00000005,0x00000014) -+macdu_test val1=0xFFFFFFFF, val2=0x5, resh=5, resl=20, racch=5, raccl=20, test_num=28 -+; acc = 21,474,836,500 + 38,654,705,637 = 60,129,542,137 (0x0000000D,0xFFFFFFF9) -+macdu_test val1=0xFFFFFFFD, val2=0x09, resh=0x0D, resl=0xFFFFFFF9, racch=0x0D, raccl=0xFFFFFFF9, test_num=29 -+; producing a result that sets both acch and accl -+macdu_test acch=0, accl=0, val1=0x7FFFFFFF, val2=0x7FFFFFFF, resh=0x3FFFFFFF, resl=0x01, racch=0x3FFFFFFF, raccl=0x01, v=0, test_num=30 -+; acc is 0x3FFFFFFF00000001 -+macdu_test val1=0x80000000, val2=0x80000000, resh=0x7FFFFFFF, resl=0x01, racch=0x7FFFFFFF, raccl=0x01, v=0, test_num=31 -+; acc is 0x7FFFFFFF00000001; line below still will not trigger an overflow for MACU -+macdu_test val1=0x12344321, val2=0x56788654, resh=0x86262098, resl=0xE1C14CD5, racch=0x86262098, raccl=0xE1C14CD5, v=0, test_num=32 -+; cause an overflow -+macdu_test acch=0xFFFFFFFF, accl=0xFFFFFFFF, val1=1, val2=1, resh=0, resl=0, racch=0, raccl=0, v=1, test_num=33 -+; "macdu" is not supposed to clear the overflow bit -+macdu_test acch=0, accl=0, val1=0, val2=0, resh=0, resl=0, racch=0, raccl=0, v=1, test_num=34 -+clear_flags_and_accu -+ -+ -+;;;;;;;;;;;;;;;;;;; CC anf FF ;;;;;;;;;;;;;;;;;;;;;;;;; -+mov r0, 0xFFFFFFFF -+mov r1, 0x11111111 -+mac.f r2, r0, r1 -+assert_flag REG_STAT_N, 1, test_num=35 -+clear_flags_and_accu -+ -+mov r0, 0xFFFFFFFF -+mov r1, 0x11111111 -+mac r2, r0, r1 -+assert_flag REG_STAT_N, 0, test_num=36 -+clear_flags_and_accu -+ -+setup_acc acch=0xFFFFFFFF, accl=0xFFFFFFFF -+mov r0, 0x01 -+mov r1, 0x01 -+; earlier, this caused an overflow; see test case 25 -+macdu r2, r0, r1 -+assert_flag REG_STAT_V, 0, test_num=37 -+clear_flags_and_accu -+ -+; FIXME: uncomment code below when assmbler starts supporting conditon codes -+; cause an overflow and then execute based on CC -+;mov r0, 42 -+;mov r1, 1 -+;mov r2, 0x1337 -+;;macu.v r2, r1, r0 ; assembler does not support this line -+;assert_eq 0x1337, r2, test_num=38 -+; -+;mov r0, 42 -+;mov r1, 1 -+;; causing the N bit to be set -+;mov r4, 0xFFFFFFFF -+;add.f r4, r4, r4 -+;; conditional execution and update flags -+;macd.N.f r2, r1, r0 ; assembler does not support this line -+;assert_flag REG_STAT_N, 0, test_num=39 -+;assert_eq 42, r2, test_num=39 -+ -+ -+;;;;;;;;;;;;;;;;;;; Finished ;;;;;;;;;;;;;;;;;;;;;;;;;; -+end -diff --git a/tests/tcg/arc/check_manip_10_mmu.S b/tests/tcg/arc/check_manip_10_mmu.S -new file mode 100644 -index 0000000000..be426d89e9 ---- /dev/null -+++ b/tests/tcg/arc/check_manip_10_mmu.S -@@ -0,0 +1,173 @@ -+; check_manip_5_mmu.S -+; -+; Tests for MMU: manipulate MMU table in exception routines. -+; If the test fails, check the end of this file for how to troubleshoot. -+; The running code for this test needs to be in address range >= 0x8000_0000. -+ -+ .include "macros.inc" -+ .include "mmu.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;; Bunch of constants ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+ .equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT -+ .equ STATUS32_AD_BIT , 19 ; Alignment Disable bit -+ ; courtesy of macros.inc and mmu.inc -+ .extern REG_IVT_BASE -+ .extern PAGE_NUMBER_MSK -+ .extern REG_PD0_GLOBAL -+ .extern REG_PD0_VALID -+ .extern REG_PD1_KRNL_W -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Handler of the day. -+ .align 4 -+handler : .word 0x0 -+ -+; An exception handler routine that merely jumps to whatever address -+; it was told to by the test. See set_except_handler macro. This -+; requires ivt.S file to be compiled and linked. -+ .align 4 -+ .global EV_TLBMissI -+ .global EV_TLBMissD -+ .global EV_ProtV -+ .type EV_TLBMissI, @function -+ .type EV_TLBMissD, @function -+ .type EV_ProtV, @function -+EV_TLBMissI: -+EV_TLBMissD: -+EV_ProtV: -+ ld r11, [handler] -+ j [r11] -+ -+; macro: set_except_handler -+; regs used: r11 -+; -+; This macro writes the provided ADDR to a temporary place holder -+; that later the exception handler routine will jump to. -+.macro set_except_handler addr -+ mov r11, \addr -+ st r11, [handler] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Tests ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Let the tests begin -+ start -+ ; use physicall address range for handling exceptions (ivt) -+ mov r0, INT_VECT_ADDRESS -+ sr r0, [REG_IVT_BASE] -+ -+; Test case 5 -+; Like previous test but with a "branch and link". This is even trickier. -+; BL needs to decode the delay instruction to know its length. It uses -+; this information to determine what value should "BLINK" register hold. -+; Below is the pertinent semantic: -+; -+; delay_insn_addr = bl_insn_addr + bl_insn_len -+; delay_insn_len = decode(delay_insn_addr) -+; BLINK = bl_insn_addr + bl_insn_len + delay_insn_len -+; -+; If the "delay slot" instruction is on a missing page, a TLBMissI is -+; raised during "decode(delay_insn_addr)". This all happens while the -+; "BL" instruction is being handled (and not the delay slot): -+; -+; ecr = 0x40000 (TLBMissI) -+; eret = bl_insn_addr --> for previous test, this is delay_insn_addr -+; efa = delay_insn_addr -+; blink = old value (not updated) -+ .equ T5_VIRT_ADDR, 0x00602000 ; virtual page address -+ .equ T5_PHYS_ADDR, 0xA0008000 ; physical page address -+ .equ T5_ADDR_OFS, 0x00001FF8 ; the offset in the page -+ .equ T5_PD0, ((T5_VIRT_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T5_PD1, ((T5_PHYS_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) -+ .equ T5_size, test_10_embedded_code_end - test_10_embedded_code_start -+ -+ mmu_prep_test_case -+ mmu_prep_test_case -+ ; Copy the embedded code into physical page -+ xor_s r3, r3, r3 -+ mov r0, @test_10_embedded_code_start -+ mov r1, @T5_PHYS_ADDR+T5_ADDR_OFS -+test_10_copy: -+ ldb.ab r2, [r0, 1] -+ stb.ab r2, [r1, 1] -+ add_s r3, r3, 1 -+ cmp r3, T5_size -+ blt @test_10_copy -+ ; Add MMU -+ set_except_handler @test_10_except_handler -+ mmu_tlb_insert T5_PD0, T5_PD1 -+ mmu_enable -+ lr r8, [bta] ; remember the old bta value -+ mov r0, 0x80000000 ; will be used by the code to be executed -+ mov r1, T5_VIRT_ADDR+T5_ADDR_OFS ; jump to the copied code -+ ; Have embedded code word-aligned at a place where it will be put. -+ -+ mov r5, 0 -+ mov r4, 1 -+ sub.f 0, r5, r4 -+ j [r1] -+ -+test_10_control: -+ sub r7, r4, r5 ; 1 -+ sub.f 0, r7, r6 ; -+ -+ bne @fail -+ add r5, r5, 1 -+ -+ sub.f 0, r5, 2 -+ beq @test_10_end -+ -+ sub.f 0, r5, r4 -+ j [r1] -+ -+ .align 4 -+test_10_embedded_code_start: -+ mov r6, 1 -+ bne.d @to_jump -+ ld r7, [r0] -+ mov r6, 0 -+to_jump: -+ j @test_10_control -+ nop -+test_10_virt_finish: -+ mov r6, 1 -+ j @test_10_control -+test_10_embedded_code_end: -+; Exception routine that will add entry for the second page -+test_10_except_handler: -+ mmu_prep_test_case_address -+ lr r9, [ecr] -+ cmp r9, 0x40000 ; TLBMissI? -+ bne @fail -+ mmu_prep_test_case_address -+ lr r9, [eret] -+ cmp r9, @T5_VIRT_ADDR+0x2000 ; Beginning of second page? -+ jne @fail -+ mmu_prep_test_case_address -+ lr r9, [efa] -+ cmp r9, @T5_VIRT_ADDR+0x2000 ; Beginning of second page? -+ jne @fail -+ mmu_tlb_insert T5_PD0+0x2000, T5_PD1+0x2000 -+ rtie -+test_10_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [mmu_test_nr] -+ ;print_number r0 -+ print "[FAIL]" -+1: -+ print " MMU: manipulate MMU table in exception routines\n" -+ end -diff --git a/tests/tcg/arc/check_manip_4_mmu.S b/tests/tcg/arc/check_manip_4_mmu.S -new file mode 100644 -index 0000000000..599cd2a95a ---- /dev/null -+++ b/tests/tcg/arc/check_manip_4_mmu.S -@@ -0,0 +1,158 @@ -+; check_manip_4_mmu.S -+; -+; Tests for MMU: manipulate MMU table in exception routines. -+; If the test fails, check the end of this file for how to troubleshoot. -+; The running code for this test needs to be in address range >= 0x8000_0000. -+ -+ .include "macros.inc" -+ .include "mmu.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;; Bunch of constants ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+ .equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT -+ .equ STATUS32_AD_BIT , 19 ; Alignment Disable bit -+ ; courtesy of macros.inc and mmu.inc -+ .extern REG_IVT_BASE -+ .extern PAGE_NUMBER_MSK -+ .extern REG_PD0_GLOBAL -+ .extern REG_PD0_VALID -+ .extern REG_PD1_KRNL_W -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Handler of the day. -+ .align 4 -+handler : .word 0x0 -+ -+; An exception handler routine that merely jumps to whatever address -+; it was told to by the test. See set_except_handler macro. This -+; requires ivt.S file to be compiled and linked. -+ .align 4 -+ .global EV_TLBMissI -+ .global EV_TLBMissD -+ .global EV_ProtV -+ .type EV_TLBMissI, @function -+ .type EV_TLBMissD, @function -+ .type EV_ProtV, @function -+EV_TLBMissI: -+EV_TLBMissD: -+EV_ProtV: -+ ld r11, [handler] -+ j [r11] -+ -+; macro: set_except_handler -+; regs used: r11 -+; -+; This macro writes the provided ADDR to a temporary place holder -+; that later the exception handler routine will jump to. -+.macro set_except_handler addr -+ mov r11, \addr -+ st r11, [handler] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Tests ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Let the tests begin -+ start -+ ; use physicall address range for handling exceptions (ivt) -+ mov r0, INT_VECT_ADDRESS -+ sr r0, [REG_IVT_BASE] -+; Test case 4 -+; Straddle a "branch" and its "delay slot" on two consecutive pages. -+; The first virtual page has an entry in TLB, but the second one (which -+; the delay slot is on) does not. We want to see when fetching the delay -+; slot causes a TLBMissI, things will go back smoothly. -+; -+; first page with TLB entry -+; ,-----. -+; | ... | -+; | nop | -+; | b.d | branch instruction as the last instruction of the page -+; `-----' -+; ,-----. -+; | dly | delay instruction on the next page -+; | ... | -+; | | -+; `-----' -+; second page without TLB entry -+ .equ T4_VIRT_ADDR, 0x00402000 ; virtual page address -+ .equ T4_PHYS_ADDR, 0x90008000 ; physical page address -+ .equ T4_ADDR_OFS, 0x00001FF8 ; the offset in the page -+ .equ T4_PD0, ((T4_VIRT_ADDR+T4_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T4_PD1, ((T4_PHYS_ADDR+T4_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) -+ .equ T4_size, test_4_embedded_code_end - test_4_embedded_code_start -+ -+ mmu_prep_test_case -+ ; Copy the embedded code into physical page -+ xor_s r3, r3, r3 -+ mov r0, @test_4_embedded_code_start -+ mov r1, @T4_PHYS_ADDR+T4_ADDR_OFS -+test_4_copy: -+ ldb.ab r2, [r0, 1] -+ stb.ab r2, [r1, 1] -+ add_s r3, r3, 1 -+ cmp r3, T4_size -+ blt @test_4_copy -+ ; Add MMU -+ set_except_handler @test_4_except_handler -+ mmu_tlb_insert T4_PD0, T4_PD1 -+ mmu_enable -+ mov r0, 0x80000000 ; will be used by the code to be executed -+ mov r1, T4_VIRT_ADDR+T4_ADDR_OFS ; jump to the copied code -+ j [r1] -+ ; Have embedded code word-aligned at a place where it will be put. -+ .align 4 -+test_4_embedded_code_start: -+ nop -+ b.d @test_4_virt_finish -+ ld r1, [r0] -+ nop -+ j @fail -+ nop -+test_4_virt_finish: -+ j @test_4_end -+test_4_embedded_code_end: -+; Exception routine that will add entry for the second page -+test_4_except_handler: -+ mmu_prep_test_case_address -+ lr r9, [ecr] -+ cmp r9, 0x40000 ; TLBMissI? -+ bne @fail -+ mmu_prep_test_case_address -+ lr r9, [eret] -+ cmp r9, @T4_VIRT_ADDR+0x2000 ; Beginning of second page? -+ jne @fail -+ mmu_prep_test_case_address -+ lr r9, [efa] -+ cmp r9, @T4_VIRT_ADDR+0x2000 ; Beginning of second page? -+ jne @fail -+ mmu_prep_test_case_address -+ lr r9, [bta] -+ cmp r9, @T4_VIRT_ADDR+T4_ADDR_OFS+T4_size-8 ; BTA correct? -+ jne @fail -+ mmu_prep_test_case_address -+ lr r9, [erbta] -+ cmp r9, @T4_VIRT_ADDR+T4_ADDR_OFS+T4_size-8 ; ERBTA correct? -+ jne @fail -+ mmu_tlb_insert T4_PD0+0x2000, T4_PD1+0x2000 -+ rtie -+test_4_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [mmu_test_nr] -+ ;print_number r0 -+ print "[FAIL]" -+1: -+ print " MMU: manipulate MMU table in exception routines\n" -+ end -diff --git a/tests/tcg/arc/check_manip_5_mmu.S b/tests/tcg/arc/check_manip_5_mmu.S -new file mode 100644 -index 0000000000..17ea00bfe8 ---- /dev/null -+++ b/tests/tcg/arc/check_manip_5_mmu.S -@@ -0,0 +1,166 @@ -+; check_manip_5_mmu.S -+; -+; Tests for MMU: manipulate MMU table in exception routines. -+; If the test fails, check the end of this file for how to troubleshoot. -+; The running code for this test needs to be in address range >= 0x8000_0000. -+ -+ .include "macros.inc" -+ .include "mmu.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;; Bunch of constants ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+ .equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT -+ .equ STATUS32_AD_BIT , 19 ; Alignment Disable bit -+ ; courtesy of macros.inc and mmu.inc -+ .extern REG_IVT_BASE -+ .extern PAGE_NUMBER_MSK -+ .extern REG_PD0_GLOBAL -+ .extern REG_PD0_VALID -+ .extern REG_PD1_KRNL_W -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Handler of the day. -+ .align 4 -+handler : .word 0x0 -+ -+; An exception handler routine that merely jumps to whatever address -+; it was told to by the test. See set_except_handler macro. This -+; requires ivt.S file to be compiled and linked. -+ .align 4 -+ .global EV_TLBMissI -+ .global EV_TLBMissD -+ .global EV_ProtV -+ .type EV_TLBMissI, @function -+ .type EV_TLBMissD, @function -+ .type EV_ProtV, @function -+EV_TLBMissI: -+EV_TLBMissD: -+EV_ProtV: -+ ld r11, [handler] -+ j [r11] -+ -+; macro: set_except_handler -+; regs used: r11 -+; -+; This macro writes the provided ADDR to a temporary place holder -+; that later the exception handler routine will jump to. -+.macro set_except_handler addr -+ mov r11, \addr -+ st r11, [handler] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Tests ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Let the tests begin -+ start -+ ; use physicall address range for handling exceptions (ivt) -+ mov r0, INT_VECT_ADDRESS -+ sr r0, [REG_IVT_BASE] -+ -+; Test case 5 -+; Like previous test but with a "branch and link". This is even trickier. -+; BL needs to decode the delay instruction to know its length. It uses -+; this information to determine what value should "BLINK" register hold. -+; Below is the pertinent semantic: -+; -+; delay_insn_addr = bl_insn_addr + bl_insn_len -+; delay_insn_len = decode(delay_insn_addr) -+; BLINK = bl_insn_addr + bl_insn_len + delay_insn_len -+; -+; If the "delay slot" instruction is on a missing page, a TLBMissI is -+; raised during "decode(delay_insn_addr)". This all happens while the -+; "BL" instruction is being handled (and not the delay slot): -+; -+; ecr = 0x40000 (TLBMissI) -+; eret = bl_insn_addr --> for previous test, this is delay_insn_addr -+; efa = delay_insn_addr -+; blink = old value (not updated) -+ .equ T5_VIRT_ADDR, 0x00602000 ; virtual page address -+ .equ T5_PHYS_ADDR, 0xA0008000 ; physical page address -+ .equ T5_ADDR_OFS, 0x00001FF8 ; the offset in the page -+ .equ T5_PD0, ((T5_VIRT_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T5_PD1, ((T5_PHYS_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) -+ .equ T5_size, test_5_embedded_code_end - test_5_embedded_code_start -+ -+ mmu_prep_test_case -+ mmu_prep_test_case -+ ; Copy the embedded code into physical page -+ xor_s r3, r3, r3 -+ mov r0, @test_5_embedded_code_start -+ mov r1, @T5_PHYS_ADDR+T5_ADDR_OFS -+test_5_copy: -+ ldb.ab r2, [r0, 1] -+ stb.ab r2, [r1, 1] -+ add_s r3, r3, 1 -+ cmp r3, T5_size -+ blt @test_5_copy -+ ; Add MMU -+ set_except_handler @test_5_except_handler -+ mmu_tlb_insert T5_PD0, T5_PD1 -+ mmu_enable -+ lr r4, [bta] ; remember the old bta value -+ mov r0, 0x80000000 ; will be used by the code to be executed -+ mov r1, T5_VIRT_ADDR+T5_ADDR_OFS ; jump to the copied code -+ j [r1] -+ ; Have embedded code word-aligned at a place where it will be put. -+ .align 4 -+test_5_embedded_code_start: -+ nop -+ bl.d @test_5_virt_finish -+ ld r1, [r0] -+ nop -+ j @fail -+ nop -+test_5_virt_finish: -+ j @test_5_end -+test_5_embedded_code_end: -+; Exception routine that will add entry for the second page -+test_5_except_handler: -+ mmu_prep_test_case_address -+ lr r9, [ecr] -+ print_number_hex r9 -+ cmp r9, 0x40000 ; TLBMissI? -+ bne @fail -+ mmu_prep_test_case_address -+ lr r9, [eret] -+ print_number_hex r9 -+ cmp r9, @T5_VIRT_ADDR+0x2000-4 ; Beginning of second page? -+ jne @fail -+ mmu_prep_test_case_address -+ lr r9, [efa] -+ print_number_hex r9 -+ cmp r9, @T5_VIRT_ADDR+0x2000 ; Beginning of second page? -+ jne @fail -+ mmu_prep_test_case_address -+ lr r9, [bta] -+ print_number_hex r9 -+ cmp r9, r4 ; BTA not updated? (still old?) -+ jne @fail -+ mmu_prep_test_case_address -+ lr r9, [erbta] -+ cmp r9, r4 ; ERBTA same as not updated BTA? -+ jne @fail -+ mmu_tlb_insert T5_PD0+0x2000, T5_PD1+0x2000 -+ rtie -+test_5_end: -+ ; Fall through -+ -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [mmu_test_nr] -+ ;print_number r0 -+ print "[FAIL]" -+1: -+ print " MMU: manipulate MMU table in exception routines\n" -+ end -diff --git a/tests/tcg/arc/check_manip_mmu.S b/tests/tcg/arc/check_manip_mmu.S -new file mode 100644 -index 0000000000..c2bab099f9 ---- /dev/null -+++ b/tests/tcg/arc/check_manip_mmu.S -@@ -0,0 +1,565 @@ -+; check_manip_mmu.S -+; -+; Tests for MMU: manipulate MMU table in exception routines. -+; If the test fails, check the end of this file for how to troubleshoot. -+; The running code for this test needs to be in address range >= 0x8000_0000. -+ -+ .include "macros.inc" -+ .include "mmu.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;; Bunch of constants ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+ .equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT -+ .equ STATUS32_AD_BIT , 19 ; Alignment Disable bit -+ ; courtesy of macros.inc and mmu.inc -+ .extern REG_IVT_BASE -+ .extern PAGE_NUMBER_MSK -+ .extern REG_PD0_GLOBAL -+ .extern REG_PD0_VALID -+ .extern REG_PD1_KRNL_W -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Handler of the day. -+ .align 4 -+handler : .word 0x0 -+ -+; An exception handler routine that merely jumps to whatever address -+; it was told to by the test. See set_except_handler macro. This -+; requires ivt.S file to be compiled and linked. -+ .align 4 -+ .global EV_TLBMissI -+ .global EV_TLBMissD -+ .global EV_ProtV -+ .global instruction_error -+ .type EV_TLBMissI, @function -+ .type EV_TLBMissD, @function -+ .type EV_ProtV, @function -+ .type instruction_error, @function -+EV_TLBMissI: -+EV_TLBMissD: -+EV_ProtV: -+instruction_error: -+ ld r11, [handler] -+ j [r11] -+ -+; macro: set_except_handler -+; regs used: r11 -+; -+; This macro writes the provided ADDR to a temporary place -+; that later the exception handler routine will jump to. -+.macro set_except_handler addr -+ mov r11, \addr -+ st r11, [handler] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Tests ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Let the tests begin -+ start -+ ; use physicall address range for handling exceptions (ivt) -+ mov r0, INT_VECT_ADDRESS -+ sr r0, [REG_IVT_BASE] -+ -+; Test case 1: -+; Reading from a virtual address that has no entry in TLB. This will -+; cause a TLBMissD exception. In return, the exception routine handler -+; will add the corresponding entry: -+; ,-----------------.------------------.----------------------. -+; | virtual address | physical address | (kernel) permissions | -+; |-----------------+------------------+----------------------| -+; | 0x1337_1334 | 0x7331_1334 | R-- | -+; `-----------------^------------------^----------------------' -+; After returning from the exception, the "ld" should go OK. -+; Then there comes a write ("st") that will trigger a ProtV exception. -+; This time, we allow writing as well: -+; ,-----------------.------------------.----------------------. -+; | virtual address | physical address | (kernel) permissions | -+; |-----------------+------------------+----------------------| -+; | 0x1337_1334 | 0x7331_1334 | RW- | -+; `-----------------^------------------^----------------------' -+; the "st" to the same address should go fine. -+ .equ T1_VIRT_ADDR, 0x13371334 ; the virtual address; word aligned -+ .equ T1_PHYS_ADDR, 0x73311334 ; the physical address (same page offset as VA) -+ .equ T1_DATA_1 , 0x00BADB07 ; the test value to read and verify -+ .equ T1_DATA_2 , 0x00B07BAD ; the test value to write and verify -+ .equ T1_PD0 , ((T1_VIRT_ADDR & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T1_PD1_R , ((T1_PHYS_ADDR & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R) -+ .equ T1_PD1_RW, (T1_PD1_R | REG_PD1_KRNL_W) -+ mmu_prep_test_case -+ mov r2, 0 ; exception handler counter -+ mov r1, T1_DATA_1 ; plant the data ... -+ st r1, [T1_PHYS_ADDR] ; ... into the physical address -+ set_except_handler @test_1_except_handler -+ mmu_enable -+test_1_ld: -+ ld r0, [T1_VIRT_ADDR] ; TLBMissD causing instruction -+ cmp r0, T1_DATA_1 -+ bne @fail -+ mov r0, T1_DATA_2 -+test_1_st: -+ st r0, [T1_VIRT_ADDR] ; TLBProtV causing instruction -+ mmu_disable ; MMU bye-bye! -+ ld r1, [T1_PHYS_ADDR] ; Load the final destination of "st" -+ cmp r1, T1_DATA_2 ; was it written successfuly? -+ bne @fail -+ b @test_1_end -+test_1_except_handler: -+ add_s r2, r2, 1 -+ cmp r2, 1 ; TLBMissD while loading? -+ bne @1f -+ lr r11, [ecr] -+ cmp r11, TLB_MISS_D_READ; TLBMissD during a load? -+ bne @fail -+ lr r11, [eret] -+ cmp r11, @test_1_ld ; instruction causing the exception -+ lr r11, [efa] -+ cmp r11, T1_VIRT_ADDR ; faulty address is correct? -+ jne @fail -+ mov r11, 0 -+ sr r11, [efa] ; clearing EFA -+ mmu_tlb_insert T1_PD0, T1_PD1_R -+ rtie -+1: -+ cmp r2, 2 ; ProtV during write? -+ bne @fail -+ lr r11, [ecr] -+ cmp r11, 0x60208 ; ProtV from MMU during a write? -+ bne @fail -+ lr r11, [eret] -+ cmp r11, @test_1_st ; instruction causing the exception -+ lr r11, [efa] -+ cmp r11, T1_VIRT_ADDR ; faulty address is correct? -+ jne @fail -+ mmu_tlb_insert T1_PD0, T1_PD1_RW -+ rtie -+test_1_end: -+ ; Fall through -+ -+; Test case 2 -+; Load a double word data straddled over two consecutive virtual pages: -+; ,-------------------------------.,-----------------------------. -+; | ... x0 x1 x2 x3 || x4 x5 x6 x7 x8 ... | -+; `-------------------------------'`-----------------------------' -+; virt=0x0050_2000..0x0050_4000 virt=0x0050_4000..0x050_6000 -+; -+; Only the first page has an entry in TLB: -+; ,-----------------.------------------.----------------------. -+; | virtual address | physical address | (kernel) permissions | -+; |-----------------+------------------+----------------------| -+; | 0x0050_2000 | 0x3000_8000 | R-- | -+; `-----------------^------------------^----------------------' -+; -+; An "ldd" from the last 4 byte of the first page will span to -+; the second page. This will lead to an exception (TLBMissD). -+ .equ T2_VIRT_ADDR, 0x00502000 ; virtual page address -+ .equ T2_PHYS_ADDR, 0x30008000 ; physical page address -+ .equ T2_ADDR_OFS, 0x00001FFC ; the offset in the page -+ .equ T2_PD0, ((T2_VIRT_ADDR+T2_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T2_PD1, ((T2_PHYS_ADDR & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R) -+ -+ mmu_prep_test_case -+ mov r2, 0 ; exception handler counter -+ set_except_handler @test_2_except_handler -+ mmu_tlb_insert T2_PD0, T2_PD1 -+ mmu_enable -+test_2_ldd: -+ ldd r0, [T2_VIRT_ADDR+T2_ADDR_OFS] -+ cmp r2, 1 -+ bne @fail -+ b @test_2_end ; success! -+test_2_except_handler: -+ add r2, r2, 1 ; increase the counter -+ lr r11, [ecr] -+ cmp r11, 0x50100 ; TLBMissD during a load? -+ bne @fail -+ lr r11, [eret] -+ cmp r11, @test_2_ldd -+ jne @fail -+ lr r11, [efa] -+ cmp r11, T2_VIRT_ADDR+T2_ADDR_OFS+4 ; beginning of next page -+ jne @fail -+ mmu_disable -+ rtie -+test_2_end: -+ ; Fall through -+ -+; Test case 3 -+; Load a data word (0x12345678) straddled over two consecutive -+; virtual pages: -+; ,--------------------.,--------------------. -+; | ... 0x78 || 0x56 0x34 0x12 ... | -+; `--------------------'`--------------------' -+; virt=0x0000...0x2000 virt=0x2000...0x4000 -+; -+; Only the first page has an entry in TLB: -+; ,-----------------.------------------.----------------------. -+; | virtual address | physical address | (kernel) permissions | -+; |-----------------+------------------+----------------------| -+; | 0x0000_0000 | 0x7000_0000 | R-- | -+; `-----------------^------------------^----------------------' -+; -+; An "ld" (word-sized) from the last byte of the first page will -+; span to the first 3 bytes of the second page. This will lead -+; to an exception (TLBMissD). The exception routine will add the -+; entry for the second page: -+; ,-----------------.------------------.----------------------. -+; | virtual address | physical address | (kernel) permissions | -+; |-----------------+------------------+----------------------| -+; | 0x0000_0000 | 0x7000_0000 | R-- | -+; | 0x0000_2000 | 0x6000_2000 | R-- | -+; `-----------------^------------------^----------------------' -+; -+; And in the end, we must have fetched the data (0x12345678). -+; To make the test realistic, the physical page addresses are not -+; consecutive as opposed to their virtual counter parts. -+; The alignment check should be disabled for this test. -+ .equ T3_VIRT_ADDR_1, 0x00000000 ; two virtual page addresses ... -+ .equ T3_VIRT_ADDR_2, 0x00002000 ; ... that are consecutive. -+ .equ T3_PHYS_ADDR_1, 0x70000000 ; two physical page addresses ... -+ .equ T3_PHYS_ADDR_2, 0x60002000 ; ... that are inconsecutive. -+ .equ T3_ADDR_1_OFS, 0x00001FFF ; the offset in the first pages. -+ .equ T3_PD0_ENT1, ((T3_VIRT_ADDR_1+T3_ADDR_1_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T3_PD1_ENT1, ((T3_PHYS_ADDR_1 & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R) -+ .equ T3_PD0_ENT2, ((T3_VIRT_ADDR_2 & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T3_PD1_ENT2, ((T3_PHYS_ADDR_2 & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R) -+ mmu_prep_test_case -+ ; Plant data at the physical addresses -+ mov r1, 0x12345678 -+ stb r1, [T3_PHYS_ADDR_1+T3_ADDR_1_OFS] ; 0x78 at the end of first page -+ lsr8 r1, r1 -+ sth r1, [T3_PHYS_ADDR_2] ; 0x56 0x34 at the beginning of 2nd page -+ lsr16 r1, r1 -+ stb r1, [T3_PHYS_ADDR_2+2] ; 0x12 The 3rd byte on the 2nd page -+ mov r1, 0 ; exception handler counter -+ disable_alignment -+ set_except_handler @test_3_except_handler -+ mmu_tlb_insert T3_PD0_ENT1, T3_PD1_ENT1 -+ mmu_enable -+ ; Exception-causing instruction -+test_3_ld: -+ ld r0, [T3_VIRT_ADDR_1+T3_ADDR_1_OFS] -+ mov r3, 0x12345678 -+ cmp r0, r3 -+ bne @fail -+ cmp r1, 1 -+ bne @fail -+ b @test_3_end ; success! -+test_3_except_handler: -+ add r1, r1, 1 ; increase the counter -+ lr r11, [ecr] -+ cmp r11, 0x50100 ; TLBMissD during a load? -+ bne @fail -+ lr r11, [eret] -+ cmp r11, @test_3_ld -+ jne @fail -+ lr r11, [efa] -+ cmp r11, @T3_VIRT_ADDR_2 -+ jne @fail -+ mmu_tlb_insert T3_PD0_ENT2, T3_PD1_ENT2 -+ rtie -+test_3_end: -+ ; Fall through -+ -+; Test case 4 -+; Straddle a "branch" and its "delay slot" on two consecutive pages. -+; The first virtual page has an entry in TLB, but the second one (which -+; the delay slot is on) does not. We want to see when fetching the delay -+; slot causes a TLBMissI, things will go back smoothly. -+; -+; first page with TLB entry -+; ,-----. -+; | ... | -+; | nop | -+; | b.d | branch instruction as the last instruction of the page -+; `-----' -+; ,-----. -+; | dly | delay instruction on the next page -+; | ... | -+; | | -+; `-----' -+; second page without TLB entry -+ .equ T4_VIRT_ADDR, 0x00402000 ; virtual page address -+ .equ T4_PHYS_ADDR, 0x90008000 ; physical page address -+ .equ T4_ADDR_OFS, 0x00001FF8 ; the offset in the page -+ .equ T4_PD0, ((T4_VIRT_ADDR+T4_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T4_PD1, ((T4_PHYS_ADDR+T4_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) -+ .equ T4_size, test_4_embedded_code_end - test_4_embedded_code_start -+ -+ mmu_prep_test_case -+ ; Copy the embedded code into physical page -+ xor_s r3, r3, r3 -+ mov r0, @test_4_embedded_code_start -+ mov r1, @T4_PHYS_ADDR+T4_ADDR_OFS -+test_4_copy: -+ ldb.ab r2, [r0, 1] -+ stb.ab r2, [r1, 1] -+ add_s r3, r3, 1 -+ cmp r3, T4_size -+ blt @test_4_copy -+ ; Add MMU -+ set_except_handler @test_4_except_handler -+ mmu_tlb_insert T4_PD0, T4_PD1 -+ mmu_enable -+ mov r1, T4_VIRT_ADDR+T4_ADDR_OFS ; jump to the copied code -+ j [r1] -+ ; Have embedded code word-aligned at a place where it will be put. -+ .align 4 -+test_4_embedded_code_start: -+ nop -+ b.d @test_4_virt_finish -+ add r1, r0, r0 -+ nop -+ j @fail -+ nop -+test_4_virt_finish: -+ j @test_4_end -+test_4_embedded_code_end: -+; Exception routine that will add entry for the second page -+test_4_except_handler: -+ lr r11, [ecr] -+ cmp r11, TLB_MISS_I -+ bne @fail -+ lr r11, [eret] -+ cmp r11, @T4_VIRT_ADDR+0x2000 ; Beginning of second page? -+ jne @fail -+ lr r11, [efa] -+ cmp r11, @T4_VIRT_ADDR+0x2000 ; Beginning of second page? -+ jne @fail -+ lr r11, [bta] -+ cmp r11, @T4_VIRT_ADDR+T4_ADDR_OFS+T4_size-8 ; BTA correct? -+ jne @fail -+ lr r11, [erbta] -+ cmp r11, @T4_VIRT_ADDR+T4_ADDR_OFS+T4_size-8 ; ERBTA correct? -+ jne @fail -+ mmu_tlb_insert T4_PD0+0x2000, T4_PD1+0x2000 -+ rtie -+test_4_end: -+ ; Fall through -+ -+; Test case 5 -+; Like previous test but with a "branch and link". This is even trickier. -+; BL needs to decode the delay instruction to know its length. It uses -+; this information to determine what value should "BLINK" register hold. -+; Below is the pertinent semantic: -+; -+; delay_insn_addr = bl_insn_addr + bl_insn_len -+; delay_insn_len = decode(delay_insn_addr) -+; BLINK = bl_insn_addr + bl_insn_len + delay_insn_len -+; -+; If the "delay slot" instruction is on a missing page, a TLBMissI is -+; raised during "decode(delay_insn_addr)". This all happens while the -+; "BL" instruction is being handled (and not the delay slot): -+; -+; ecr = 0x40000 (TLBMissI) -+; eret = bl_insn_addr --> for previous test, this is delay_insn_addr -+; efa = delay_insn_addr -+; bta = old value (not updated) -+; blink = old value (not updated) -+ .equ T5_VIRT_ADDR, 0x00602000 ; virtual page address -+ .equ T5_PHYS_ADDR, 0xA0008000 ; physical page address -+ .equ T5_ADDR_OFS, 0x00001FF8 ; the offset in the page -+ .equ T5_PD0, ((T5_VIRT_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T5_PD1, ((T5_PHYS_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) -+ .equ T5_size, test_5_embedded_code_end - test_5_embedded_code_start -+ -+ mmu_prep_test_case -+ ; Copy the embedded code into physical page -+ xor_s r3, r3, r3 -+ mov r0, @test_5_embedded_code_start -+ mov r1, @T5_PHYS_ADDR+T5_ADDR_OFS -+test_5_copy: -+ ldb.ab r2, [r0, 1] -+ stb.ab r2, [r1, 1] -+ add_s r3, r3, 1 -+ cmp r3, T5_size -+ blt @test_5_copy -+ ; Add MMU -+ set_except_handler @test_5_except_handler -+ mmu_tlb_insert T5_PD0, T5_PD1 -+ mmu_enable -+ lr r4, [bta] ; remember the old bta value -+ mov r5, blink ; remember the old blink value -+ mov r1, T5_VIRT_ADDR+T5_ADDR_OFS ; jump to the copied code -+ j [r1] -+ ; Have embedded code word-aligned at a place where it will be put. -+ .align 4 -+test_5_embedded_code_start: -+ nop -+ bl.d @test_5_virt_finish -+ add r1, r0, r0 -+ nop -+ j @fail -+ nop -+test_5_virt_finish: -+ j @test_5_end -+test_5_embedded_code_end: -+; Exception routine that will add entry for the second page -+test_5_except_handler: -+ lr r11, [ecr] -+ cmp r11, TLB_MISS_I -+ bne @fail -+ lr r11, [eret] -+ cmp r11, @T5_VIRT_ADDR+0x2000-4 ; Last instruction of the first page (bl)? -+ jne @fail -+ lr r11, [efa] -+ cmp r11, @T5_VIRT_ADDR+0x2000 ; Beginning of second page? -+ jne @fail -+ lr r11, [bta] -+ cmp r11, r4 ; BTA not updated? (still old?) -+ jne @fail -+ lr r11, [erbta] -+ cmp r11, r4 ; ERBTA same as not-updated-BTA? -+ mov r11, blink -+ cmp r11, r5 ; BLINK not updated? (still old?) -+ jne @fail -+ mmu_tlb_insert T5_PD0+0x2000, T5_PD1+0x2000 -+ rtie -+test_5_end: -+ ; Fall through -+ -+; Test case 6: BLINK register must be updated immediately after "BL". -+ mmu_prep_test_case -+ bl.d @test_6_branch_taken -+ mov r0, blink -+test_6_after_delay_slot: -+ b @fail -+ .align 4 -+test_6_branch_taken: -+ mov r1, @test_6_after_delay_slot -+ cmp r0, r1 -+ bne @fail -+ -+; Test case 7: BTA register must be updated immediately after "BL". -+ mmu_prep_test_case -+ bl.d @test_7_branch_taken -+ lr r0, [bta] -+ b @fail -+ .align 4 -+test_7_branch_taken: -+ mov r1, @test_7_branch_taken -+ cmp r0, r1 -+ bne @fail -+ -+;; Test case 8: Exceptions other than TLBMissI for the delay slot of BL -+;; In this case, such exceptions are deep in decoding pipeline and should -+;; cause a normal exception like any other instructions, where ERET is -+;; pointing to the delay slot and not the BL instruction, like the previous -+;; tests. -+; mmu_prep_test_case -+; set_except_handler @test_8_except_handler -+; bl.d @test_8_end -+;test_8_delay_slot: -+; lr r0, [blink] ; InstructionError -+; b @fail -+;; Exception routine that will add entry for the second page -+;test_8_except_handler: -+; lr r11, [ecr] -+; cmp r11, ILLEGAL_INSTRUCTION -+; bne @fail -+; lr r11, [eret] -+; cmp r11, @test_8_delay_slot -+; jne @fail -+; lr r11, [efa] -+; cmp r11, @test_8_delay_slot -+; jne @fail -+; lr r11, [erbta] -+; cmp r11, @test_8_end -+; jne @fail -+; lr r11, [bta] -+; cmp r11, @test_8_end -+; jne @fail -+; sr r11, [eret] ; Get out of delay slot by jumping to BTA -+; lr r11, [erstatus] -+; bclr r11, r11, 6 ; Clear delay slot execution flag -+; sr r11, [erstatus] -+; rtie -+; b @fail -+; .align 4 -+;test_8_end: -+; ; Fall through -+ -+; Test case 9 -+; Like test case 5, but the CC is false here. Although, there is no need -+; for the calculation of BLINK and the _early_ decode of delay slot -+; instruction, still TLBMissI exception for the delay slot instruction -+; happens during the execution of "BLne.D". This is how the hardware -+; works. -+; ecr = 0x40000 (TLBMissI) -+; eret = bl_insn_addr -+; efa = delay_insn_addr -+; bta = old value (not updated) -+; blink = old value (not updated) -+ .equ T9_VIRT_ADDR, 0x00606000 ; virtual page address -+ .equ T9_PHYS_ADDR, 0xA000A000 ; physical page address -+ .equ T9_ADDR_OFS, 0x00001FF4 ; the offset in the page -+ .equ T9_PD0, ((T9_VIRT_ADDR+T9_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) -+ .equ T9_PD1, ((T9_PHYS_ADDR+T9_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) -+ .equ T9_size, test_9_embedded_code_end - test_9_embedded_code_start -+ -+ mmu_prep_test_case -+ ; Copy the embedded code into physical page -+ xor_s r3, r3, r3 -+ mov r0, @test_9_embedded_code_start -+ mov r1, @T9_PHYS_ADDR+T9_ADDR_OFS -+test_9_copy: -+ ldb.ab r2, [r0, 1] -+ stb.ab r2, [r1, 1] -+ add_s r3, r3, 1 -+ cmp r3, T9_size -+ blt @test_9_copy -+ ; Add MMU -+ set_except_handler @test_9_except_handler -+ mmu_tlb_insert T9_PD0, T9_PD1 -+ mmu_enable -+ lr r4, [bta] ; remember the old bta value -+ mov r1, T9_VIRT_ADDR+T9_ADDR_OFS ; jump to the copied code -+ j [r1] -+ ; Have embedded code word-aligned at a place where it will be put. -+ .align 4 -+test_9_embedded_code_start: -+ add.f 0, 0, 0 -+ blne.d @fail -+ add r0, r0, r0 -+ j @test_9_end -+test_9_embedded_code_end: -+; Exception routine that will add entry for the second page -+test_9_except_handler: -+ lr r11, [ecr] -+ cmp r11, TLB_MISS_I -+ bne @fail -+ lr r11, [eret] -+ cmp r11, @T9_VIRT_ADDR+0x2000-4 ; Last instruction of the first page (blne.d)? -+ jne @fail -+ lr r11, [efa] -+ cmp r11, @T9_VIRT_ADDR+0x2000 ; Beginning of second page? -+ jne @fail -+ lr r11, [bta] -+ cmp r11, r4 ; BTA not updated? (still old?) -+ jne @fail -+ lr r11, [erbta] -+ cmp r11, r4 ; ERBTA same as not updated BTA? -+ jne @fail -+ mmu_tlb_insert T9_PD0+0x2000, T9_PD1+0x2000 -+ rtie -+test_9_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+.align 4 -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [mmu_test_nr] -+ ;print_number r0 -+ print "[FAIL]" -+1: -+ print " MMU: manipulate MMU table in exception routines\n" -+ end -diff --git a/tests/tcg/arc/check_mmu.S b/tests/tcg/arc/check_mmu.S -new file mode 100644 -index 0000000000..69a38e30d5 ---- /dev/null -+++ b/tests/tcg/arc/check_mmu.S -@@ -0,0 +1,59 @@ -+.include "macros.inc" -+.include "mmu.inc" -+ -+; courtesy of mmu.inc -+.extern PAGE_NUMBER_MSK -+.extern REG_PD0_GLOBAL -+.extern REG_PD0_VALID -+.extern REG_PD1_KRNL_W -+ -+; test data -+; making an entry for the TLB -+; -+; ,------------------------------------. -+; | VPN(VA), G=1, V=1 | PPN(PHY), Wk=1 | -+; `------------------------------------' -+; where: -+; VPN(VA) is the virtual page number of logical address -+; G is the global bit -+; V is the validity bit -+; PPN(PHY) is the physical page number -+; Wk is the write permission in kernel mode -+ -+; obviously, the offsets in both addresses must be the same -+.equ VIRT_ADR , 0x13371334 ; the virtual address; word aligned -+.equ PHYS_ADR , 0x73311334 ; the physical address > 0x7FFFFFFF -+.equ MAGICDATA, 0x00BADB07 ; the test value to write and verify -+.equ PD0_VPN , (VIRT_ADR & PAGE_NUMBER_MSK) -+.equ PD1_PPN , (PHYS_ADR & PAGE_NUMBER_MSK) -+.equ PD0_BITS , (PD0_VPN | REG_PD0_GLOBAL | REG_PD0_VALID) -+.equ PD1_BITS , (PD1_PPN | REG_PD1_KRNL_W) -+ -+start -+ -+mmu_enable -+ -+; insert into table: VA 0x13371337 (Global) --> PHY: 0x73311337 (RW kernel) -+mmu_tlb_insert PD0_BITS, PD1_BITS -+ -+; write to the mapped virtual address -+mov r0, MAGICDATA -+st r0, [VIRT_ADR] -+ -+mmu_disable -+ -+; with mmu disabled, read from physical address and -+; verify that it is the same as the value written -+; to the mapped virtual address earlier -+ld r1, [PHYS_ADR] -+cmp r0, r1 ; r0 contains the MAGICDATA -+beq @goodboy -+ -+print "nope, still no MMU!\n" -+j @adios -+ -+goodboy: -+print "Yay, you got the MMU right :)\n" -+ -+adios: -+end -diff --git a/tests/tcg/arc/check_mpu.S b/tests/tcg/arc/check_mpu.S -new file mode 100644 -index 0000000000..e840b95403 ---- /dev/null -+++ b/tests/tcg/arc/check_mpu.S -@@ -0,0 +1,703 @@ -+; check_mpu.S -+; -+; Tests for MPUv3: Memory protection unit v3. -+; If the test fails, check the end of this file for how to troubleshoot. -+ -+ .include "macros.inc" -+ .include "mpu.inc" -+ .include "mmu.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case counter -+.data -+test_nr: -+ .word 0x0 -+ -+; Increment the test counter and set (Z,N,C,V) to (0,0,0,0). -+.macro prep_test_case -+ ld r13, [test_nr] -+ add_s r13, r13, 1 ; increase test case counter -+ st r13, [test_nr] -+ add.f 0, 0, 1 ; (Z, N, C, V) = (0, 0, 0, 0) -+.endm -+ -+; macro: auxreg_write_read -+; input: reg - the register we are talking about -+; write - value to write -+; read - value expected to be read -+; regs used: r11, r12 -+; example: auxreg_write_read mpuen, 0xffffffff, 0x400001f8 -+; -+; description: -+; Not always, "write" and "read" values are the same. This true about -+; the registers who have reserved bits or read as zero in user mode, -+; etc. -+; Be careful, what is the result of you writing to to "reg". It may -+; have consequences like enabling page protection or so. -+.macro auxreg_write_read reg, write, read -+ mov r11, \write -+ sr r11, [\reg] -+ ; using a different register to reduce the chande of false equality -+ lr r12, [\reg] -+ cmp r12, \read -+ bne @fail -+.endm -+ -+ start -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; check the MPU_BUILD -+test_00: -+ .equ VERSION , 0x03 -+ .equ NR_REGIONS, 0x08 -+ .equ MPU_BCR_REF, (NR_REGIONS << 8) | VERSION -+ lr r0, [mpu_build] -+ cmp r0, MPU_BCR_REF -+ bne @fail -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; All of the registers should be accessible in kernel mode -+; this test (check_mpu) is based on 8 regions. -+test_01: -+ prep_test_case -+ ; mpuen : momentarily enabled with full access -+ ; when read, only relevant bits must be set. -+ auxreg_write_read mpuen , 0xffffffff, 0x400001f8 -+ ; disable mpu at once -+ mpu_disable -+ auxreg_write_read mpurdb0 , 0xffffffff, 0xffffffe1 -+ auxreg_write_read mpurdp0 , 0xffffffff, 0x00000ffb -+ auxreg_write_read mpurdb1 , 0xffffffff, 0xffffffe1 -+ auxreg_write_read mpurdp1 , 0xffffffff, 0x00000ffb -+ auxreg_write_read mpurdb2 , 0xffffffff, 0xffffffe1 -+ auxreg_write_read mpurdp2 , 0xffffffff, 0x00000ffb -+ auxreg_write_read mpurdb3 , 0xffffffff, 0xffffffe1 -+ auxreg_write_read mpurdp3 , 0xffffffff, 0x00000ffb -+ auxreg_write_read mpurdb4 , 0xffffffff, 0xffffffe1 -+ auxreg_write_read mpurdp4 , 0xffffffff, 0x00000ffb -+ auxreg_write_read mpurdb5 , 0xffffffff, 0xffffffe1 -+ auxreg_write_read mpurdp5 , 0xffffffff, 0x00000ffb -+ auxreg_write_read mpurdb6 , 0xffffffff, 0xffffffe1 -+ auxreg_write_read mpurdp6 , 0xffffffff, 0x00000ffb -+ auxreg_write_read mpurdb7 , 0xffffffff, 0xffffffe1 -+ auxreg_write_read mpurdp7 , 0xffffffff, 0x00000ffb -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; None of the registers should be accessible in user mode -+test_02: -+ prep_test_case -+ mpu_reset -+ ; prep the exception for the end -+ lr r0, [mpuic] ; don't care for mpu_ecr value -+ mpu_set_except_params mpu_ecr = r0 , \ -+ ecr = PRIVILEGE_VIOLATION , \ -+ efa = @test_02_user_space+4, \ -+ eret = @test_02_user_space+4, \ -+ continue = @test_02_end -+ enter_user_mode @test_02_user_space -+test_02_user_space: -+ add r0, r0, r0 ; some filler to make a basic block -+ ; accessing MPU registers in user mode is not allowed -+ lr r0, [mpu_build] -+ b @fail ; an exception must have been raised -+test_02_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; Running with -global cpu.has-mpu=false or reading a region register -+; which is higher than the configured number of regions causes an -+; instuction error: ecr=0x020000 -+test_03: -+ prep_test_case -+ mpu_reset -+ ; prep the exception for 'lr'ing a region that does not exist -+ lr r0, [mpuic] ; don't care for mpu_ecr value -+ mpu_set_except_params mpu_ecr = r0 , \ -+ ecr = ILLEGAL_INSTRUCTION , \ -+ efa = @test_03_illegal_lr_rgn, \ -+ eret = @test_03_illegal_lr_rgn, \ -+ continue = @test_03_cont -+test_03_illegal_lr_rgn: -+ lr r1, [mpurdb15] -+ b @fail ; exception must have been raised -+test_03_cont: -+ ; prep the exception for 'sr'ing a region that does not exist -+ lr r0, [mpuic] ; don't care for mpu_ecr value -+ mpu_set_except_params mpu_ecr = r0 , \ -+ ecr = ILLEGAL_INSTRUCTION , \ -+ efa = @test_03_illegal_sr_rgn, \ -+ eret = @test_03_illegal_sr_rgn, \ -+ continue = @test_03_end -+test_03_illegal_sr_rgn: -+ sr r1, [mpurdp8] -+ b @fail ; an exception must have been raised -+test_03_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; Verifying the KR permission for region 1. -+; Checking if "read" is OK and "write" raises an exception. -+test_04: -+ .equ MEM_ADDR04 , 0x16000 -+ .equ DATA04 , 0x1337 -+ .equ MPU_ECR_W_R1, MPU_ECR_WRITE | 1 -+ prep_test_case -+ mpu_reset -+ mpu_add_base mpurdb1, MEM_ADDR04 -+ mpu_add_region mpurdp1, REG_MPU_EN_KR, MPU_SIZE_32B -+ mpu_write_data DATA04, MEM_ADDR04 -+ mpu_enable -+ ; read permission check -+ mpu_verify_data DATA04, MEM_ADDR04 -+ ; write permission check -+ mpu_set_except_params mpu_ecr = MPU_ECR_W_R1 , \ -+ ecr = PROTV_WRITE_MPU , \ -+ efa = MEM_ADDR04 , \ -+ eret = @test_04_illegal_store+4, \ -+ continue = @test_04_end -+test_04_illegal_store: -+ add r0, r0, r0 ; filler; so exception happens in... -+ st r1, [MEM_ADDR04] ; ...the middle of a translation block -+ b @fail ; an exception must have been raised -+test_04_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; Having 2 small regions next to each other: one with write permission -+; and the other with read permission. Check if permissions are respected -+; accordingly. This tests how MPU sets QEmu's internal TLB and if it is -+; able to set the TLB's entry size correctly. -+test_05: -+ .equ MEM_ADDR05, 0x16024 ; 4 bytes above the multiple of 32 -+ .equ DATA05 , 0xbabe -+ prep_test_case -+ mpu_reset -+ mpu_add_base mpurdb0, MEM_ADDR05 ; effective address would be 0x4020 -+ mpu_add_region mpurdp0, REG_MPU_EN_KW, MPU_SIZE_32B -+ mpu_add_base mpurdb1, MEM_ADDR05+32; effective address would be 0x4040 -+ mpu_add_region mpurdp1, REG_MPU_EN_KR, MPU_SIZE_32B -+ mpu_write_data DATA05, MEM_ADDR05+32 ; write to 0x4044 (region1) -+ ; let the fun begin -+ mpu_enable -+ mpu_verify_data DATA05, MEM_ADDR05+32 -+ st r7, [MEM_ADDR05] ; write bogus data (region 0) -+ ; now time for some exception -+ mpu_set_except_params mpu_ecr = MPU_ECR_W_R1 , \ -+ ecr = PROTV_WRITE_MPU , \ -+ efa = MEM_ADDR05+32 , \ -+ eret = @test_05_illegal_store, \ -+ continue = @test_05_end -+test_05_illegal_store: -+ st r7, [MEM_ADDR05+32] ; this shouldn't be allowed -+ b @fail ; an exception must have been raised -+test_05_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; Update a region's permission and size to check if they are taken -+; into account. -+test_06: -+ .equ MEM_ADDR06, 0x30000 -+ .equ MPU_ECR_R_R3, MPU_ECR_READ | 3 -+ prep_test_case -+ mpu_reset -+ mpu_add_base mpurdb3, MEM_ADDR06 -+ mpu_add_region mpurdp3, REG_MPU_EN_KR, MPU_SIZE_64B -+ mpu_enable -+ ld r7, [MEM_ADDR06+32] ; this should be allowed -+ ; changing permission (deliberately mpu is not disabled) -+ mpu_add_region mpurdp3, REG_MPU_EN_KE, MPU_SIZE_64B ; update (KR -> KE) -+ ; prep for exception -+ mpu_set_except_params mpu_ecr = MPU_ECR_R_R3 , \ -+ ecr = PROTV_READ_MPU , \ -+ efa = MEM_ADDR06+32 , \ -+ eret = @test_06_illegal_read, \ -+ continue = @test_06_change_size -+test_06_illegal_read: -+ ld r7, [MEM_ADDR06+32] ; this is not allowed anymore -+ b @fail ; an exception must have been raised -+test_06_change_size: -+ ; changing size (deliberately mpu is not disabled) -+ mpu_add_region mpurdp3, REG_MPU_EN_KE, MPU_SIZE_32B ; update (64 -> 32) -+ mpu_enable -+ ld r7, [MEM_ADDR06+32] ; this is allowed again (+32 is in def. region) -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; Check a permission that has only execute permission. -+; The read should not be possible. -+test_07: -+ .equ NOP_OPCODE, 0x7000264a -+ .equ JR1_OPCODE, 0x00402020 -+ .equ CODE_CAVE07, 0x40000 -+ .equ MPU_ECR_R_R0, MPU_ECR_READ | 0 -+ prep_test_case -+ mpu_reset -+ mpu_add_base mpurdb0, CODE_CAVE07 -+ mpu_add_region mpurdp0, REG_MPU_EN_KE, MPU_SIZE_32B -+ mov r0, NOP_OPCODE -+ mov r1, @test_07_rest -+ mov r2, JR1_OPCODE -+ st r0, [CODE_CAVE07] ; nop -+ st r2, [CODE_CAVE07+4] ; j [r1] -+ st r0, [CODE_CAVE07+8] ; nop -+ mpu_enable -+ ; let's take a leap of faith -+ j CODE_CAVE07 -+ -+test_07_rest: -+ ; wow, if we just came back, let's raise hell -+ mpu_set_except_params mpu_ecr = MPU_ECR_R_R0 , \ -+ ecr = PROTV_READ_MPU , \ -+ efa = CODE_CAVE07+4 , \ -+ eret = @test_07_illegal_read, \ -+ continue = @test_07_end -+test_07_illegal_read: -+ ld r7, [CODE_CAVE07+4] ; this shouldn't be allowed -+ b @fail ; an exception must have been raised -+test_07_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; One region to rule them all -+; 1) We are testing a very big region here. -+; 2) Moreover we change its permission and size in the middle -+test_08: -+ .equ MEM_ADDR08 , 0x00000000 -+ .equ BIG_ADDR08 , 0x7FFFFFE0 -+ .equ MPU_ECR_W_R7 , MPU_ECR_WRITE | 7 -+ .equ MPU_ECR_R_DEF, MPU_ECR_READ | 0xFF -+ .equ DATA08_1 , 0x34fa ; random magic -+ .equ DATA08_2 , 0x987afb ; random magic -+ prep_test_case -+ mpu_reset -+ ; planting the data -+ mpu_write_data DATA08_1, BIG_ADDR08 -+ ; a 4 gigabyte region with read and execute permissions -+ mpu_add_base mpurdb7, MEM_ADDR08 -+ mpu_add_region mpurdp7, REG_MPU_EN_KR | REG_MPU_EN_KE , MPU_SIZE_4G -+ ; prepping exception (must be before enable, otherwise no write access) -+ mpu_set_except_params mpu_ecr = MPU_ECR_W_R7 , \ -+ ecr = PROTV_WRITE_MPU , \ -+ efa = BIG_ADDR08 , \ -+ eret = @test_08_illegal_write , \ -+ continue = @test_08_change_permission, \ -+ ; default region with only write permission -+ mpu_enable REG_MPU_EN_KW -+ ; checking read (BIG_ADDR08) and exec (current instruction) permissions -+ mpu_verify_data DATA08_1, BIG_ADDR08 -+test_08_illegal_write: -+ st r7, [BIG_ADDR08] ; no write is allowed -+ b @fail ; an exception must have been raised -+test_08_change_permission: -+ ; change permission _and_ size -+ mpu_add_region mpurdp7, REG_MPU_EN_FULL_ACCESS , MPU_SIZE_2G -+ ; now there should be no problem in writing either -+ mpu_write_data DATA08_2, BIG_ADDR08 -+ mpu_verify_data DATA08_2, BIG_ADDR08 -+ ; prepping second exception: default region has no read access -+ mpu_set_except_params mpu_ecr = MPU_ECR_R_DEF , \ -+ ecr = PROTV_READ_MPU , \ -+ efa = BIG_ADDR08+0xF0 , \ -+ eret = @test_08_illegal_def_read, \ -+ continue = @test_08_end -+test_08_illegal_def_read: -+ ld r7, [BIG_ADDR08+0xF0] ; this is default region now and not sanctioned -+ b @fail ; an exception must have been raised -+test_08_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; A user cannot have kernel permissions, but a kernel inherits granted -+; user permissions as well. -+test_09: -+ .equ MEM_ADDR09_1, 0x60000 -+ .equ MEM_ADDR09_2, 0x62000 ; 8k after -+ .equ MPU_ECR_W_R6, MPU_ECR_WRITE | 6 -+ .equ DATA09 , 0x89091 ; another random data from beyond -+ prep_test_case -+ mpu_reset -+ ; a region for user to write -+ mpu_add_base mpurdb5, MEM_ADDR09_1 -+ mpu_add_region mpurdp5, REG_MPU_EN_UW, MPU_SIZE_8K -+ ; a region only for kernel -+ mpu_add_base mpurdb6, MEM_ADDR09_2 -+ mpu_add_region mpurdp6, REG_MPU_EN_KR | REG_MPU_EN_KW, MPU_SIZE_8K -+ ; prep the exception for the end -+ mpu_set_except_params mpu_ecr = MPU_ECR_W_R6 , \ -+ ecr = PROTV_WRITE_MPU , \ -+ efa = MEM_ADDR09_2 , \ -+ eret = @test_09_user_space+8 , \ -+ continue = @test_09_rest_kernel_mode -+ ; let's have at it -+ mpu_enable REG_MPU_EN_UE | REG_MPU_EN_KR -+ enter_user_mode @test_09_user_space -+test_09_user_space: -+ st r7, [MEM_ADDR09_2-4] ; write to the end of user region -+ st r7, [MEM_ADDR09_2] ; uh-oh: causing trouble -+ b @fail ; an exception must have been raised -+test_09_rest_kernel_mode: -+ ; a simple write and verify chore in kernel mode -+ mpu_write_data DATA09, MEM_ADDR09_2+64 -+ mpu_verify_data DATA09, MEM_ADDR09_2+64 -+ ; also writing to user region because of implied write access -+ mpu_write_data DATA09, MEM_ADDR09_1+64 -+ mpu_disable ; else we cannot verify (no read access) -+ mpu_verify_data DATA09, MEM_ADDR09_1+64 -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; A region with only user read access should not be fetchable. -+test_10: -+ .equ CODE_CAVE10 , 0x100000 -+ .equ DATA10 , 0x010101 -+ .equ MPU_ECR_E_R4, MPU_ECR_FETCH | 4 -+ prep_test_case -+ mpu_reset -+ mpu_add_base mpurdb4, CODE_CAVE10 -+ mpu_add_region mpurdp4, REG_MPU_EN_UR, MPU_SIZE_64K -+ ; plant the data -+ mpu_write_data DATA10, CODE_CAVE10 -+ ; prep the exception for the region being not executable -+ mpu_set_except_params mpu_ecr = MPU_ECR_E_R4 , \ -+ ecr = PROTV_FETCH_MPU, \ -+ efa = CODE_CAVE10 , \ -+ eret = CODE_CAVE10 , \ -+ continue = @test_10_end -+ mpu_enable -+ enter_user_mode @test_10_user_space -+test_10_user_space: -+ mpu_verify_data DATA10, CODE_CAVE10 ; read must be OK -+ j @CODE_CAVE10 ; this one not -+ b @fail ; an exception must have been raised -+test_10_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; KE must be enough for raising exceptions. -+; The tricky thing about this test is that it is allowing the -+; parameters for the exceptions to be readable. As a result, -+; the test assumes that there is 32 byte region that these -+; parameters fit in AND it does not overlap with the exception -+; routine itself. -+test_11: -+ .equ MEM_ADDR11, 0x900 -+ prep_test_case -+ mpu_reset -+ ; allowing exception parameters to be read -+ mpu_add_base mpurdb0, @mpu_ecr_ref -+ mpu_add_region mpurdp0, REG_MPU_EN_KR, MPU_SIZE_32B -+ ; prep for the exception -+ mpu_set_except_params mpu_ecr = MPU_ECR_R_DEF , \ -+ ecr = PROTV_READ_MPU , \ -+ efa = MEM_ADDR11 , \ -+ eret = @test_11_illegal_read, \ -+ continue = @test_11_end -+ mpu_enable REG_MPU_EN_KE -+ add r0, r0, r0 ; just a random guy making a difference -+test_11_illegal_read: -+ ld r0, [MEM_ADDR11] -+ b @fail ; an exception must have been raised -+test_11_end: -+ mpu_disable -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; Double exception must raise Machine Check with memory management disabled. -+; This test hangs in nSIM if MMU exists. Apparently, nSIM sets the halt flag -+; if a MachineCheck is raised and there is MMU in the system. The presence -+; of MMU is necessary for test 14. -+test_12: -+ .equ MPU_ECR_E_DEF, MPU_ECR_FETCH | 0xFF -+ prep_test_case -+ mpu_reset -+ ; enable MPU with no access whatsoever -+ mpu_enable 0x0 -+test_12_doomed: -+ add r0, r0, r0 -+ lr r0, [mpuen] -+ cmp r0, 0 -+ bne @fail -+ j @test_12_end -+ ; the machine check routine to be executed eventually -+ .global EV_MachineCheck -+ .type EV_MachineCheck, @function -+ .align 4 -+EV_MachineCheck: -+ lr r0, [mpuen] -+ cmp r0, REG_MPU_EN_EN -+ bne @fail -+ lr r0, [mpuic] -+ cmp r0, MPU_ECR_E_DEF -+ bne @fail -+ lr r0, [ecr] -+ cmp r0, MACHINE_CHECK -+ bne @fail -+ lr r0, [eret] -+ cmp r0, @test_12_doomed -+ bne @fail -+ lr r1, [efa] -+ cmp r0, r1 -+ bne @fail -+ mpu_disable ; disable MPU in a civilized way -+ lr r0, [erstatus] ; undo the mess: -+ and r0, r0, ~32 ; clear AE bit -+ sr r0, [erstatus] ; and -+ rtie ; return -+test_12_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; Page size for the default region: best effort 8K, else 1 byte. You need -+; to look into tracing to see if it is doing the right thing. -+test_13: -+ .equ TWO_PAGES_BEFORE , 0x7C000 -+ .equ ONE_PAGE_BEFORE , 0x7E000 -+ .equ MEM_ADDR13_1 , 0x80000 -+ .equ SAME_PAGE_BETWEEN, 0x80050 -+ .equ MEM_ADDR13_2 , 0x80100 -+ .equ SAME_PAGE_AFTER , 0x81000 -+ .equ ONE_PAGE_AFTER , 0x82000 -+ .equ MPU_ECR_R_R1 , MPU_ECR_READ | 1 -+ prep_test_case -+ mpu_reset -+ mpu_add_base mpurdb3, MEM_ADDR13_1 ; \ -+ mpu_add_region mpurdp3, 0x0, MPU_SIZE_32B ; | two black holes -+ mpu_add_base mpurdb1, MEM_ADDR13_2 ; | alike regions -+ mpu_add_region mpurdp1, 0x0, MPU_SIZE_32B ; / -+ ; your exception shall be your salvation -+ mpu_set_except_params mpu_ecr = MPU_ECR_R_R1 , \ -+ ecr = PROTV_READ_MPU , \ -+ efa = MEM_ADDR13_2 , \ -+ eret = @test_13_illegal_read, \ -+ continue = @test_13_end -+ mpu_enable -+ ld r0, [TWO_PAGES_BEFORE+0x1000] ; must cache the page -+ ld r0, [TWO_PAGES_BEFORE+0x1100] ; reuse same information -+ ld r0, [ONE_PAGE_BEFORE +0x1FFC] ; oooh, just before the black hole -+ ld r0, [ONE_PAGE_BEFORE +0x0500] ; reuse from above -+ ld r0, [SAME_PAGE_BETWEEN ] ; too narrow to cache the page -+ ld r0, [SAME_PAGE_BETWEEN+0x10 ] ; permissions must be totally checked -+ ld r0, [SAME_PAGE_AFTER ] ; same page as the black holes -+ ld r0, [SAME_PAGE_AFTER+0x10 ] ; no caching must be used -+ ld r0, [ONE_PAGE_AFTER ] ; this area is safe and ... -+ ld r0, [ONE_PAGE_AFTER+0x04 ] ; ...can be cached -+test_13_illegal_read: -+ ld r0, [MEM_ADDR13_2 ] ; oops! -+ b @fail ; an exception must have been raised -+test_13_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; MMU and MPU may coexist but do not overlap. -+; This test assumes an "rwe" access for exception routine checks and an "re" -+; access for the page this test case is loaded in. If these two pages happen -+; to be the same, e.g. previous tests are commented out, then things will -+; get nasty, because the last attribute will be used for both. -+test_14: -+ .equ MMU_KRNL_RE , REG_PD1_KRNL_E | REG_PD1_KRNL_R -+ .equ MMU_KRNL_RWE, REG_PD1_KRNL_E | REG_PD1_KRNL_W | REG_PD1_KRNL_R -+ .equ MMU_VPN_GV , REG_PD0_GLOBAL | REG_PD0_VALID -+ .equ MEM_ADDR14 , 0x80000100 ; an address in MPU's interest -+ ; creates an entry in TLB with given permissions. -+ ; the translation is identical (virt = physical) -+ .macro add_mmu_entry addr, permission -+ mov r2, \addr -+ and r2, r2, PAGE_NUMBER_MSK -+ or r3, r2, \permission ; r3 holds physical address and permissoins -+ or r2, r2, MMU_VPN_GV ; r2 is a global valid virtual address -+ mmu_tlb_insert r2, r3 ; add entry for MMU -+ .endm -+ prep_test_case -+ mpu_reset -+ b @test_14_after_align -+ ; guarantee that current page won't be the same as @mp_ecr_ref's page -+ .align 0x2000 -+test_14_after_align: -+ ; add a read/write/execute permission for exception part page -+ ; @mpu_ecr_ref and ProtV handler must be in the same page. -+ add_mmu_entry @mpu_ecr_ref, MMU_KRNL_RWE -+ ; add a read/write/execute permission for vector table. -+ add_mmu_entry 0x0, MMU_KRNL_RWE -+ ; add a read/execute permission for current page -+ lr r1, [pc] -+ add_mmu_entry r1, MMU_KRNL_RE -+ ; exception for writing to the (2nd) MMU page -+ lr r0, [mpuic] ; don't care for mpu_ecr value -+ mpu_set_except_params mpu_ecr = r0 , \ -+ ecr = PROTV_WRITE_MMU , \ -+ efa = r1 , \ -+ eret = @test_14_illegal_write, \ -+ continue = @test_14_mpu -+ ; enable the guys -+ mmu_enable ; enable MMU -+ mpu_enable REG_MPU_EN_KW ; enable MPU with kernel write access -+ ; this is happening in MMU's territory -+test_14_illegal_write: -+ st r0, [r1] ; no write for this entry in TLB -+ b @fail ; an exception must have been raised -+ -+test_14_mpu: -+ add r0, r0, r0 ; a happy camper -+ st r0, [MEM_ADDR14] ; in MPU realm -+ ; MPU exception now -+ mpu_set_except_params mpu_ecr = MPU_ECR_R_DEF , \ -+ ecr = PROTV_READ_MPU , \ -+ efa = MEM_ADDR14 , \ -+ eret = @test_14_illegal_read, \ -+ continue = @test_14_end -+test_14_illegal_read: -+ ld r0, [MEM_ADDR14] ; uh-oh... -+ b @fail ; an exception must have been raised -+test_14_end: -+ mpu_disable -+ mmu_disable -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; Two overlapping regions test. One is 2 pages long and the other is inside -+; the second page of the first region: -+; ,----------. -+; | R2:rw- | region nr 2 with read/write permission. -+; page1 | | -+; | | -+; .......|..........|....... -+; | | -+; page2 |,________.| -+; ||R1:r-- || region nr 1 with read only permission. -+; |`--------'| this region is inside region nr 2. -+; `----------' -+; setup: R2 is 16kb with rw- -+; R1 is 4kb with r-- -+; write to the first page --> must go ok. -+; write to the first half of page 2 --> must go ok. -+; write to R1 --> expect an exception. -+; in the end read from R1 --> must go ok. -+test_15: -+ .equ MEM_ADDR15_R2 , 0x150000 -+ .equ MEM_ADDR15_R2_P2, MEM_ADDR15_R2 + PAGE_SIZE -+ .equ MEM_ADDR15_R1 , MEM_ADDR15_R2_P2 + PAGE_SIZE/2 -+ .equ DATA15_1 , 0x3ff0293f ; random magic -+ .equ DATA15_2 , DATA15_1+1 -+ .equ DATA15_3 , DATA15_1+2 -+ .equ MPU_ECR_W_R1, MPU_ECR_WRITE | 1 -+ prep_test_case -+ mpu_reset -+ mpu_add_base mpurdb1, MEM_ADDR15_R1 -+ mpu_add_region mpurdp1, REG_MPU_EN_KR, MPU_SIZE_4K -+ mpu_add_base mpurdb2, MEM_ADDR15_R2 -+ mpu_add_region mpurdp2, REG_MPU_EN_KR|REG_MPU_EN_KW, MPU_SIZE_16K -+ ; planting some data (for later read) -+ mpu_write_data DATA15_1, MEM_ADDR15_R1+24 -+ ; let the fun begin -+ mpu_enable -+ mpu_write_data DATA15_2, MEM_ADDR15_R2+20 -+ mpu_verify_data DATA15_2, MEM_ADDR15_R2+20 -+ mpu_write_data DATA15_3, MEM_ADDR15_R2+20+PAGE_SIZE -+ mpu_verify_data DATA15_3, MEM_ADDR15_R2+20+PAGE_SIZE -+ ; now time for some exception -+ mpu_set_except_params mpu_ecr = MPU_ECR_W_R1 , \ -+ ecr = PROTV_WRITE_MPU , \ -+ efa = MEM_ADDR15_R1+24 , \ -+ eret = @test_15_illegal_store, \ -+ continue = @test_15_cont -+ st r7, [MEM_ADDR15_R2_P2+32] ; write bogus data (region 2, page 2) -+test_15_illegal_store: -+ st r7, [MEM_ADDR15_R1+24] ; this shouldn't be allowed -+ b @fail ; an exception must have been raised -+test_15_cont: -+ mpu_verify_data DATA15_1, MEM_ADDR15_R1+24 ; this is allowed -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; Another overlapping regions test. In previous one, a page (nr=2) was split -+; among two regions. in this test, the page is contained inside another -+; region, which in return is inside yet another region: -+; ,----------. -+; page1 | R5:r--- | region nr 5 with read only permission. -+; .......|..........|....... -+; page2 | | -+; .......|..........|....... -+; page3 | | -+; .......|..........|....... -+; page4 | | -+; .......|,________.|....... -+; page5 ||R3:-w- || region nr 3 with write only permission. -+; .......||........||....... -+; page6 || || this region is inside region nr 5. -+; .......|`--------'|....... -+; page7 | | -+; .......|..........|....... -+; page8 | | -+; `----------' -+; setup: R3 is 16kb with -w- -+; R5 is 64kb with r-- -+; read from the fourth page --> must go ok. -+; read from page 7 --> must go ok. -+; write to page 4 --> expect an exception. -+; write to page 5 --> must go ok. -+; read from page 6 --> expect an exception. -+test_16: -+ .equ MEM_ADDR16_R5 , 0x160000 -+ .equ MEM_ADDR16_R5_P4, MEM_ADDR16_R5 + 3*PAGE_SIZE -+ .equ MEM_ADDR16_R5_P7, MEM_ADDR16_R5 + 6*PAGE_SIZE -+ .equ MEM_ADDR16_R3 , MEM_ADDR16_R5 + 4*PAGE_SIZE -+ .equ MEM_ADDR16_R3_P5, MEM_ADDR16_R3 -+ .equ MEM_ADDR16_R3_P6, MEM_ADDR16_R5 + 5*PAGE_SIZE -+ .equ DATA16_1 , 0x93822093 ; random magic -+ .equ DATA16_2 , DATA16_1+1 -+ .equ DATA16_3 , DATA16_1+2 -+ .equ MPU_ECR_R_R3, MPU_ECR_READ | 3 -+ .equ MPU_ECR_W_R5, MPU_ECR_WRITE | 5 -+ prep_test_case -+ mpu_reset -+ mpu_add_base mpurdb3, MEM_ADDR16_R3 -+ mpu_add_region mpurdp3, REG_MPU_EN_KW, MPU_SIZE_16K -+ mpu_add_base mpurdb5, MEM_ADDR16_R5 -+ mpu_add_region mpurdp5, REG_MPU_EN_KR, MPU_SIZE_64K -+ ; planting some data (for later read) -+ mpu_write_data DATA16_1, MEM_ADDR16_R5_P4+24 -+ mpu_write_data DATA16_3, MEM_ADDR16_R5_P7+24 -+ ; let the fun begin -+ mpu_enable -+ mpu_verify_data DATA16_1, MEM_ADDR16_R5_P4+24 -+ mpu_verify_data DATA16_3, MEM_ADDR16_R5_P7+24 -+ ; first exception because of writing in region 5 -+ mpu_set_except_params mpu_ecr = MPU_ECR_W_R5 , \ -+ ecr = PROTV_WRITE_MPU , \ -+ efa = MEM_ADDR16_R5_P4+24 , \ -+ eret = @test_16_illegal_store, \ -+ continue = @test_16_cont -+test_16_illegal_store: -+ st r7, [MEM_ADDR16_R5_P4+24] ; this shouldn't be allowed -+ b @fail ; an exception must have been raised -+test_16_cont: -+ mpu_write_data DATA16_2, MEM_ADDR16_R3_P5+24 ;will be checked later -+ ; second exception while reading in region 3 -+ mpu_set_except_params mpu_ecr = MPU_ECR_R_R3 , \ -+ ecr = PROTV_READ_MPU , \ -+ efa = MEM_ADDR16_R3_P6+24 , \ -+ eret = @test_16_illegal_read, \ -+ continue = @test_16_end -+test_16_illegal_read: -+ ld r7, [MEM_ADDR16_R3_P6+24] ; this shouldn't be allowed -+ b @fail ; an exception must have been raised -+test_16_end: -+ mpu_disable -+ mpu_verify_data DATA16_2, MEM_ADDR16_R3_P5+24 ; check if written -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [test_nr] -+ print "[FAIL" -+ print ":" -+ print_number r0 -+ print "]" -+1: -+ print " MPUv3: Memory protection unit v3.\n" -+ end -diff --git a/tests/tcg/arc/check_mpyd.S b/tests/tcg/arc/check_mpyd.S -new file mode 100644 -index 0000000000..1e94431d21 ---- /dev/null -+++ b/tests/tcg/arc/check_mpyd.S -@@ -0,0 +1,543 @@ -+; check_mpyd.S -+; -+; Tests for mpyd: mpyd mpydu -+; If the test fails, check the end of this file for how to troubleshoot. -+ -+ .include "macros.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case counter -+.data -+test_nr: -+ .word 0x0 -+ -+; Increment the test counter and set (Z,N,C,V) to (0,0,0,0). -+.macro prep_test_case -+ ld r13, [test_nr] -+ add_s r13, r13, 1 ; increase test case counter -+ st r13, [test_nr] -+ add.f 0, 0, 1 ; (Z, N, C, V) = (0, 0, 0, 0) -+.endm -+ -+; These flag checking macros do not directly load the -+; status32 register. Instead, they rely on the value -+; provided by the caller. The rationale is with all these -+; "cmp"s status32 will change. One must use a recorded -+; version of status32 at the right time and then try the -+; macros. -+.macro check_Z_is_clear status -+ mov r11, \status -+ mov r12, REG_STAT_Z -+ and r11, r11, r12 -+ cmp r11, 0 -+ bne @fail -+.endm -+.macro check_N_is_set status -+ mov r11, \status -+ mov r12, REG_STAT_N -+ and r11, r11, r12 -+ cmp r11, REG_STAT_N -+ bne @fail -+.endm -+.macro check_N_is_clear status -+ mov r11, \status -+ mov r12, REG_STAT_N -+ and r11, r11, r12 -+ cmp r11, 0 -+ bne @fail -+.endm -+.macro check_V_is_set status -+ mov r11, \status -+ mov r12, REG_STAT_V -+ and r11, r11, r12 -+ cmp r11, REG_STAT_V -+ bne @fail -+.endm -+.macro check_V_is_clear status -+ mov r11, \status -+ mov r12, REG_STAT_V -+ and r11, r11, r12 -+ cmp r11, 0 -+ bne @fail -+.endm -+ -+; pair(HI, LOW) == pair(REG_HI, REG_LO) == pair(R59, R58) -+.macro check_64bit_result hi, low, reg_hi, reg_lo -+ mov r11, \hi -+ mov r10, \low -+ cmp r11, \reg_hi -+ bne @fail -+ cmp r11, r59 -+ bne @fail -+ cmp r10, \reg_lo -+ bne @fail -+ cmp r10, r58 -+ bne @fail -+.endm -+ -+; (Z, N, C, V) = (0, 0, 0, 1) -+.macro clear_N_set_V -+ mov r11, 0x80000000 ; very small negative number -+ add.f 0, r11, r11 ; cause an overflow (with carry) -+ rol.f 0, 0x01 ; keep the V flag, set the rests to 0 -+.endm -+ -+; (Z, N, C, V) = (0, 1, 0, 1) -+.macro set_N_set_V -+ add.f 0, 0x7fffffff, 1 ; negative result with an overflow -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; parameters that an IllegalInstruction exception may set. -+ .align 4 -+ecr_ref : .word ILLEGAL_INSTRUCTION -+addr_ref : .word 0x0 ; for both eret and efa -+cont_addr: .word 0x0 -+ -+; exception: IllegalInstruction -+; regs used: r11, r12 -+; -+; A parameterized IllegalInstruction exception that checks the followings: -+; ecr == Illegal instruction -+; efa == efa_ref -+; eret == eret_ref -+; If everything passes, it will jump to 'cont_addr' parameter. The parameters -+; must be set beforehand using 'set_except_params' macro. This requires -+; ivt.S file to be compiled and linked. -+ .align 4 -+ .global instruction_error -+ .type instruction_error, @function -+instruction_error: -+ ld r11, [ecr_ref] -+ lr r12, [ecr] -+ cmp r12, r11 -+ bne @fail -+ ld r11, [addr_ref] -+ lr r12, [eret] -+ cmp r12, r11 -+ bne @fail -+ lr r12, [efa] -+ cmp r12, r11 -+ bne @fail -+ ; Success: continuing -+ ld r11, [cont_addr] -+ sr r11, [eret] -+ rtie -+ -+; macro: set_except_params -+; regs used: r11 -+; -+; This macro writes the provided parameters to a temporary place holder -+; that later will be used by exception above to verify as reference. -+.macro set_except_params addr, continue -+ mov r11, \addr -+ st r11, [addr_ref] -+ mov r11, \continue -+ st r11, [cont_addr] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; MPYD ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Let the tests begin -+ start -+ -+; Test case 1 -+; reg4 <- reg4, reg4 -+; 1 = (-1)*(-1) -+ prep_test_case -+ mov r4, -1 -+ mpyd r4, r4, r4 -+ check_64bit_result 0x0, 0x1, r5, r4 -+ -+; Test case 2 -+; reg0 <- reg1, reg0 -+; 0 = 0 * 0x22334455 -+ prep_test_case -+ mov r0, 0x22334455 ; bogus data -+ mov r1, 0 -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpyd.f r0, r1, r0 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_Z_is_clear r5 -+ check_N_is_clear r5 -+ check_V_is_clear r5 -+ check_64bit_result 0x0, 0x0, r1, r0 -+ -+; Test case 3 -+; reg2 <- reg3, limm -+; 0xc0000000_80000000 = 0x7ffffffff*0x80000000 -+; -4611686016279904256= 2147483647 * -2147483648 -+ prep_test_case -+ mov r3, 0x7fffffff ; biggest 32-bit positive number -+ clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) -+ mpyd.f r2, r3, 0x80000000 ; smallest 32-bit negative number -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_N_is_set r5 -+ check_V_is_clear r5 -+ check_64bit_result 0xc0000000, 0x80000000, r3, r2 -+ -+; Test case 4 -+; reg2 <- limm, reg3 -+; 0xffffffff_87654321 = 0x87654321 * 1 -+; This is like a sign extension -+ prep_test_case -+ mov r3, 1 -+ clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) -+ mpyd.f r2, 0x87654321, r3 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_N_is_set r5 -+ check_V_is_clear r5 -+ check_64bit_result 0xffffffff, 0x87654321, r3, r2 -+ -+; Test case 5 -+; reg0 <- limm, limm -+; 0x3fffffff_00000001 = 0x7fffffff*0x7fffffff -+; 4611686014132420609 = 2147483647*2147483647 -+ prep_test_case -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpyd r0, 0x7fffffff, 0x7fffffff -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_N_is_set r5 -+ check_V_is_set r5 -+ check_64bit_result 0x3fffffff, 0x00000001, r1, r0 -+ -+; Test case 6 -+; 0 <- limm, limm only (acch,accl) will be set. -+; It is expected that V=0 and N=0 -+; 4761 = 69 * 69 -+ prep_test_case -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpyd.f 0, 69, 69 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_N_is_clear r5 -+ check_V_is_clear r5 -+ check_64bit_result 0, 4761, r59, r58 -+ -+; Test case 7 -+; 0 <- limm, u6 only (acch,accl) will be set. -+; Checking that a result of 0 does not set the Z flag. -+; 0 = 0x12345678 * 0 -+ prep_test_case -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpyd.f 0, 0x12345678, 0 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_Z_is_clear r5 ; Z must have remained 0 -+ check_N_is_clear r5 -+ check_V_is_clear r5 -+ check_64bit_result 0, 0, r59, r58 -+ -+; Test case 8 -+; 0 <- reg2, limm (V is already 1) -+; Nothing should change, other than (acch,accl). -+; 0x2468a = 2 * 0x12345 -+ prep_test_case -+ mov r2, 2 -+ clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) -+ mpyd 0, r2, 0x12345 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_V_is_set r5 -+ check_64bit_result 0, 0x2468a, r59, r58 -+ -+; Test case 9 -+; reg0 <- reg2, u6 -+; -63 = -1 * 63 -+ prep_test_case -+ mov r2, -1 -+ mpyd r0, r2, 63 -+ check_64bit_result 0xffffffff, 0xffffffc1, r1, r0 -+ -+; Test case 10 -+; reg2 <- limm, u6 -+; 0x2_7d27d268 = 0x12345678 * 35 -+ prep_test_case -+ mpyd r2, 0x12345678, 35 -+ check_64bit_result 0x00000002, 0x7d27d268, r3, r2 -+ -+; Test case 11 -+; reg4 <- reg4, s12 -+; 0x0000002f_1c71c71c = 0x87654321 * 0xf9c -+; 202340681500 = -2023406815 * -100 -+ prep_test_case -+ mov r4, 0x87654321 -+ mpyd r4, r4, -100 -+ check_64bit_result 0x0000002f, 0x1c71c71c, r5, r4 -+ -+; Test case 12 -+; 0 <- limm, s12 -+; It is expected that V is cleared and N=1 -+; -1250000 = -10000 * 125 -+ prep_test_case -+ clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) -+ mpyd.f 0, -10000 , 125 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_N_is_set r5 -+ check_V_is_clear r5 -+ check_64bit_result -1, -1250000, r59, r58 -+ -+; Test case 13 -+; Testing when cc condition is met -+; 0 <- limm, u6 (V is already set) -+; It is expected that V is cleared and N=1 -+; -126 = -2 * 63 -+ prep_test_case -+ clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) -+ mpyd.v.f 0, -2, 63 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_N_is_set r5 -+ check_V_is_clear r5 -+ check_64bit_result -1, -126, r59, r58 -+ -+; Test case 14 -+; Testing when cc condition is not met -+; reg0 <- reg0, reg2 (V is already set) -+; It is expected that V is remanins set -+ prep_test_case -+ clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) -+ mov r0, 0xc0de ; must remain ... -+ mov r1, 0x1337 ; ... (0x1337,0xc0de) -+ mov r2, 0xf00d ; don't care ... -+ mov r3, 0xbad ; as long as not (0x0,0x1) -+ mov r4, r58 ; record accl -+ mov r5, r59 ; record acch -+ mpyd.nv.f r0, r0, r2 -+ lr r2, [status32] ; take a snapshot of statu32 as is -+ check_V_is_set r2 -+ cmp r1, 0x1337 -+ bne @fail -+ cmp r0, 0xc0de -+ bne @fail -+ check_64bit_result r5, r4, r59, r58 -+ -+; Test case 15 -+; Raise an Illegal Instruction exception if an odd register as dest. -+ prep_test_case -+ set_except_params @test_15_exception, @test_15_end -+test_15_exception: -+ mpyd r3, r2, r4 -+ b @fail -+test_15_end: -+ ; Fall through -+ -+; Test case 16 -+; Raise an Illegal Instruction exception if an odd register as dest. -+; The exception should be made even if the CC indicates no execution. -+ prep_test_case -+ set_except_params @test_16_exception, @test_16_end -+ add.f 0,0,1 ; (Z,N,C,V)=(0,0,0,0) -+test_16_exception: -+ mpyd.z r1, r1, r4 -+ b @fail -+test_16_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; MPYDU ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case 17 -+; reg2 <- reg2, reg2 -+; 1 = (-1)*(-1) -+; 0xfffffffe_00000001 = 0xffffffff * 0xffffffff -+ prep_test_case -+ mov r2, -1 -+ mpydu r2, r2, r2 -+ check_64bit_result 0xfffffffe, 0x00000001, r3, r2 -+ -+; Test case 18 -+; reg2 <- reg3, reg2 -+; 0 = 0 * 0x22334455 -+ prep_test_case -+ mov r2, 0x22334455 ; bogus data -+ mov r3, 0 -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpydu.f r2, r3, r2 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_Z_is_clear r5 -+ check_N_is_set r5 -+ check_V_is_clear r5 -+ check_64bit_result 0x0, 0x0, r3, r2 -+ -+; Test case 19 -+; reg2 <- reg3, limm -+; 0x3fffffff_80000000 = 0x7ffffffff*0x80000000 -+; 4611686016279904256 = 2147483647 * 2147483648 -+ prep_test_case -+ mov r3, 0x7fffffff ; what used to be the largest 32-bit number -+ clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) -+ mpydu.f r2, r3, 0x80000000 ; just another positive number -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_V_is_clear r5 -+ check_64bit_result 0x3fffffff, 0x80000000, r3, r2 -+ -+; Test case 20 -+; reg4 <- limm, reg5 -+; 0x00000000_87654321 = 0x87654321 * 1 -+; This is like an unsigned extension -+ prep_test_case -+ mov r5, 1 -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpydu.f r4, 0x87654321, r5 -+ lr r3, [status32] ; take a snapshot of statu32 as is -+ check_N_is_set r3 -+ check_V_is_clear r3 -+ check_64bit_result 0x00000000, 0x87654321, r5, r4 -+ -+; Test case 21 -+; reg0 <- limm, limm -+; 0x40000000_00000000 = 0x80000000*0x80000000 -+; 4611686018427387904 = 2147483648*2147483648 -+ prep_test_case -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpydu r0, 0x80000000, 0x80000000 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_N_is_set r5 -+ check_V_is_set r5 -+ check_64bit_result 0x40000000, 0x00000000, r1, r0 -+ -+; Test case 22 -+; 0 <- limm, limm only (acch,accl) will be set. -+; It is expected that V=0 and N=0 -+; 3876961 = 1969 * 1969 -+ prep_test_case -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpydu.f 0, 1969, 1969 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_N_is_set r5 -+ check_V_is_clear r5 -+ check_64bit_result 0, 3876961, r59, r58 -+ -+; Test case 23 -+; 0 <- limm, u6 only (acch,accl) will be set. -+; Checking that a result of 0 does not set the Z flag. -+; 0 = 0x12345678 * 0 -+ prep_test_case -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpydu.f 0, 0x12345678, 0 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_Z_is_clear r5 ; Z must have remained 0 -+ check_N_is_set r5 -+ check_V_is_clear r5 -+ check_64bit_result 0, 0, r59, r58 -+ -+; Test case 24 -+; 0 <- reg2, limm (V is already 1) -+; Nothing should change, other than (acch,accl). -+; 0x00001eac_0d5d17a4 = 0x1af54154 * 0x12345 -+; 33724307412900 = 452280660 * 74565 -+ prep_test_case -+ mov r2, 0x1af54154 ; I let an ant walk on the keyboard -+ clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) -+ mpydu 0, r2, 0x12345 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_V_is_set r5 -+ check_64bit_result 0x1eac, 0x0d5d17a4, r59, r58 -+ -+; Test case 25 -+; reg0 <- reg2, u6 -+; 0x3e_ffffffc1 = 0xffffffff * 0x3f -+; 270582939585 = 4294967295 * 63 -+ prep_test_case -+ mov r2, -1 -+ mpydu r0, r2, 63 -+ check_64bit_result 0x3e, 0xffffffc1, r1, r0 -+ -+; Test case 26 -+; reg4 <- limm, u6 -+; 0x2_7d27d268 = 0x12345678 * 35 -+ prep_test_case -+ mpydu r4, 0x12345678, 35 -+ check_64bit_result 0x00000002, 0x7d27d268, r5, r4 -+ -+; Test case 27 -+; reg2 <- reg2, s12 -+; 0x000003e3_8e36b328 = 0xfedcba09 * 0x3e8 -+; 4275878409000 = 4275878409 * 1000 -+ prep_test_case -+ mov r2, 0xfedcba09 -+ mpydu r2, r2, 1000 -+ check_64bit_result 0x000003e3, 0x8e36b328, r3, r2 -+ -+; Test case 28 -+; 0 <- limm, s12 -+; It is expected that V is cleared -+; 1250000 = 10000 * 125 -+ prep_test_case -+ clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) -+ mpydu.f 0, 10000 , 125 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_V_is_clear r5 -+ check_64bit_result 0, 1250000, r59, r58 -+ -+; Test case 29 -+; Testing when cc condition is met -+; 0 <- limm, u6 (V is already set) -+; It is expected that V is cleared and N=1 -+; 1781818164 = 28282828 * 63 -+ prep_test_case -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mpydu.n.f 0, 28282828, 63 -+ lr r5, [status32] ; take a snapshot of statu32 as is -+ check_N_is_set r5 -+ check_V_is_clear r5 -+ check_64bit_result 0, 1781818164, r59, r58 -+ -+; Test case 30 -+; Testing when cc condition is not met -+; reg0 <- reg0, reg2 (V is already set) -+; It is expected that V is remanins set -+ prep_test_case -+ set_N_set_V ; (Z,N,C,V)=(0,1,0,1) -+ mov r0, 0xc0de ; must remain ... -+ mov r1, 0x1337 ; ... (0x1337,0xc0de) -+ mov r2, 0xf00d ; don't care ... -+ mov r3, 0xbad ; as long as not (0x0,0x1) -+ mov r4, r58 ; record accl -+ mov r5, r59 ; record acch -+ mpyd.p.f r0, r0, r2 ; execute only if positive (N==0) -+ lr r2, [status32] ; take a snapshot of statu32 as is -+ check_V_is_set r2 -+ cmp r1, 0x1337 -+ bne @fail -+ cmp r0, 0xc0de -+ bne @fail -+ check_64bit_result r5, r4, r59, r58 -+ -+; Test case 31 -+; Raise an Illegal Instruction exception if an odd register as dest. -+ prep_test_case -+ set_except_params @test_31_exception, @test_31_end -+test_31_exception: -+ mpydu r1, r4, r0 -+ b @fail -+test_31_end: -+ ; Fall through -+ -+; Test case 32 -+; Raise an Illegal Instruction exception if an odd register as dest. -+; The exception should be made even if the CC indicates no execution. -+ prep_test_case -+ set_except_params @test_32_exception, @test_32_end -+ add.f 0,0,1 ; (Z,N,C,V)=(0,0,0,0) -+test_32_exception: -+ mpydu.v r5, r5, r4 -+ b @fail -+test_32_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [test_nr] -+ print_number r0 -+ print "[FAIL]" -+1: -+ print " mpyd: mpyd mpydu\n" -+ end -diff --git a/tests/tcg/arc/check_mpyw.S b/tests/tcg/arc/check_mpyw.S -new file mode 100644 -index 0000000000..091ee98975 ---- /dev/null -+++ b/tests/tcg/arc/check_mpyw.S -@@ -0,0 +1,41 @@ -+.include "macros.inc" -+ -+ -+.macro mul_test val1, val2, res, test_num -+ mov r0, \val1 -+ mov r1, \val2 -+ mpyw r2, r0, r1 -+ assert_eq \res, r2, \test_num -+.endm -+ -+ -+.macro mul_flags_test val1, val2, res, z=0, n=0, v=0, test_num -+ mov r0, \val1 -+ mov r1, \val2 -+ mpyw.f r2, r0, r1 -+ assert_eq \res, r2, \test_num -+ assert_flag REG_STAT_Z, \z, \test_num -+ assert_flag REG_STAT_N, \n, \test_num -+ assert_flag REG_STAT_C, 0, \test_num -+ assert_flag REG_STAT_V, \v, \test_num -+.endm -+ -+start -+ -+; 21 * 2 = 42 -+mul_test 21, 2, 42, test_num=1 -+ -+; make sure only the lower 16 bits are taken into account -+; 0x11220005 * 0x00120020 --> 0x0005 * 0x0020 = 160 -+mul_test 0x11220005, 0x00120020, 160, test_num=2 -+ -+; testing sign extension and the signed result -+; 0xFFFFFFFF * 0x00000007 --> 0xFFFF (-1) * 0x0007 = 0xFFFFFFF9 (-7) -+mul_test 0xFFFFFFFF, 0x00000007, 0xFFFFFFF9, test_num=3 -+ -+; testing flags -+mul_flags_test 1337 , 0 , res=0 , z=1, test_num=4 -+mul_flags_test 0x7FFF, 0x7FFF, res=0x3FFF0001, v=0, test_num=5 -+mul_flags_test 0xFFFF, 0x0C , res=0xFFFFFFF4, n=1, test_num=6 -+ -+end -diff --git a/tests/tcg/arc/check_norm.S b/tests/tcg/arc/check_norm.S -new file mode 100644 -index 0000000000..4e55b71589 ---- /dev/null -+++ b/tests/tcg/arc/check_norm.S -@@ -0,0 +1,40 @@ -+.include "macros.inc" -+ -+ start -+ -+ test_name NORM_1 -+ norm r2, 0x0 -+ check_r2 0x1f -+ -+ test_name NORM_2 -+ norm r2, 0x1 -+ check_r2 0x1e -+ -+ test_name NORM_3 -+ norm r2, 0x1fffffff -+ check_r2 0x02 -+ -+ test_name NORM_4 -+ norm r2, 0x3fffffff -+ check_r2 0x01 -+ -+ test_name NORM_5 -+ norm r2, 0x7fffffff -+ check_r2 0x00 -+ -+ test_name NORM_6 -+ norm r2, 0x80000000 -+ check_r2 0x00 -+ -+ test_name NORM_8 -+ norm r2, 0xc0000000 -+ check_r2 0x01 -+ -+ test_name NORM_9 -+ norm r2, 0xe0000000 -+ check_r2 0x02 -+ -+ test_name NORM_10 -+ norm r2, 0xffffffff -+ check_r2 0x1f -+ end -diff --git a/tests/tcg/arc/check_orx.S b/tests/tcg/arc/check_orx.S -new file mode 100644 -index 0000000000..c7a96b4edb ---- /dev/null -+++ b/tests/tcg/arc/check_orx.S -@@ -0,0 +1,34 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# or.S -+#----------------------------------------------------------------------------- -+# -+# Test or instruction. -+# -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ TEST_IMM_OP( 2, or, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f ); -+ TEST_IMM_OP( 3, or, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); -+ TEST_IMM_OP( 4, or, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); -+ TEST_IMM_OP( 5, or, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); -+ TEST_RR_3OP( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); -+ TEST_RR_3OP( 7, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); -+ TEST_RR_3OP( 8, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); -+ TEST_RR_3OP( 9, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 ); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ -+ TEST_IMM_SRC1_EQ_DEST( 10, or, 0xff00fff0, 0xff00ff00, 0x0f0 ); -+ TEST_RR_SRC1_EQ_DEST( 11, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); -+ TEST_RR_SRC2_EQ_DEST( 12, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); -+ TEST_RR_SRC12_EQ_DEST( 13, or, 0xff00ff00, 0xff00ff00 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_prefetch.S b/tests/tcg/arc/check_prefetch.S -new file mode 100644 -index 0000000000..3eb9900de0 ---- /dev/null -+++ b/tests/tcg/arc/check_prefetch.S -@@ -0,0 +1,37 @@ -+#***************************************************************************** -+# prefetch -+#----------------------------------------------------------------------------- -+# -+# This test verifies that prefetch works as expected -+# -+ -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ # testing the decoding -+ TEST_CASE( 2, r0, 0x00000000, "prefetch:2", prefetch [0x12]` mov r0, 0x0) -+ TEST_CASE( 3, r0, 0x00000000, "prefetch:3", prefetchw [0x12]` mov r0, 0x0) -+ TEST_CASE( 4, r0, 0x00000000, "prefetch:4", prefetchw [r1, r2]` mov r0, 0x0) -+ TEST_CASE( 5, r0, 0x00000000, "prefetch:5", prefetchw [0x12, 0x1]` mov r0, 0x0) -+ TEST_CASE( 6, r0, 0x00000000, "prefetch:6", prefetch [r1, r2]` mov r0, 0x0) -+ TEST_CASE( 7, r0, 0x00000000, "prefetch:7", prefetch [0x12, 0x1]` mov r0, 0x0) -+ -+ mov r13, @tdat -+ TEST_CASE( 8, r0, 0x00000004, "prefetch:8", prefetch [r13]` ld r0,[r13]) -+ TEST_CASE( 9, r0, 0x40000000, "prefetch:9", prefetch.aw [r13,4]` ld r0,[r13]) -+ TEST_CASE(10, r0, 0x40400000, "prefetch:10", prefetch.ab [r13,4]` ld r0,[r13]) -+ -+ARCTEST_END -+# TEST_DATA -+ -+tdat: -+.word 0x00000004 -+.word 0x40000000 -+.word 0x40400000 -+.word 0xc0800000 -+.word 0xdeadbeef -+.word 0xcafebabe -+.word 0xabad1dea -+.word 0x1337d00d -diff --git a/tests/tcg/arc/check_rolx.S b/tests/tcg/arc/check_rolx.S -new file mode 100644 -index 0000000000..4f2d939f69 ---- /dev/null -+++ b/tests/tcg/arc/check_rolx.S -@@ -0,0 +1,47 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# check_rolx.S -+#----------------------------------------------------------------------------- -+# -+# Test or instruction. -+# -+# .-------------.----------.--------------. -+# | instruction | check CC | update flags | -+# |-------------+----------+--------------| -+# | rol | no | Z, N, C | -+# | rol8 | no | Z, N | -+# `-------------^----------^--------------' -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ TEST_RR_2OP(2, rol , 0xbd5b7ddf, 0xdeadbeef); -+ TEST_RR_2OP(3, rol8, 0x00000001, 0x01000000); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ TEST_RR_2OP_SRC1_EQ_DEST(4, rol, 0x94001009, 0xca000804); -+ -+ #------------------------------------------------------------- -+ # Flag tests -+ #------------------------------------------------------------- -+ TEST_1OP_CARRY ( 5, rol , 0, 0x40000000); -+ TEST_1OP_CARRY ( 6, rol , 1, 0x80000000); -+ TEST_1OP_ZERO ( 8, rol , 0, 0x00001000); -+ TEST_1OP_ZERO ( 9, rol , 1, 0x00000000); -+ TEST_1OP_NEGATIVE(10, rol , 0, 0x80000000); -+ TEST_1OP_NEGATIVE(11, rol , 1, 0x40000000); -+ #rol8 does not update carry -+ TEST_1OP_CARRY (12, rol8, 0, 0x000000ff); -+ TEST_1OP_ZERO (13, rol8, 0, 0x00001000); -+ TEST_1OP_ZERO (14, rol8, 1, 0x00000000); -+ TEST_1OP_NEGATIVE(15, rol8, 0, 0x00000040); -+ TEST_1OP_NEGATIVE(16, rol8, 1, 0x00800000); -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_rorx.S b/tests/tcg/arc/check_rorx.S -new file mode 100644 -index 0000000000..2634e4e4a5 ---- /dev/null -+++ b/tests/tcg/arc/check_rorx.S -@@ -0,0 +1,64 @@ -+#define ARCTEST_ARC32 -+ -+#***************************************************************************** -+# check_rorx.S -+#----------------------------------------------------------------------------- -+# -+# Test or instruction. -+# -+# .--------------.----------.--------------. -+# | instruction | check CC | update flags | -+# |--------------+----------+--------------| -+# | ror | no | Z, N, C | -+# | ror multiple | yes | Z, N, C | -+# | ror8 | no | Z, N | -+# `--------------^----------^--------------' -+ -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ TEST_RR_3OP( 2, ror , 0xdeadbeef, 0xdeadbeef, 0x00000000); -+ TEST_RR_3OP( 3, ror , 0x00000001, 0x00000001, 0x00000000); -+ TEST_RR_3OP( 4, ror , 0x80000000, 0x80000000, 0x00000000); -+ TEST_RR_3OP( 5, ror , 0xbd5b7ddf, 0xdeadbeef, 0x0000001f); -+ TEST_RR_3OP( 6, ror , 0x00000002, 0x00000001, 0x0000001f); -+ TEST_RR_3OP( 7, ror , 0x00000001, 0x80000000, 0x0000001f); -+ TEST_RR_2OP( 8, ror , 0x80000000, 0x00000001); -+ TEST_RR_2OP( 9, ror , 0xdeadbeef, 0xbd5b7ddf); -+ TEST_RR_2OP(10, ror8, 0x01000000, 0x00000001); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ TEST_RR_SRC1_EQ_DEST (11, ror, 0xca000804, 0x000804ca, 0xfff80008); -+ TEST_RR_2OP_SRC1_EQ_DEST(12, ror, 0x80040265, 0x000804cb); -+ -+ #------------------------------------------------------------- -+ # Flag tests -+ #------------------------------------------------------------- -+ TEST_2OP_CARRY (13, ror , 0, 0x00000001, 0x02); -+ TEST_2OP_CARRY (14, ror , 1, 0x00000001, 0x01); -+ TEST_2OP_ZERO (15, ror , 0, 0x00000100, 0xbf); -+ TEST_2OP_ZERO (16, ror , 1, 0x00000000, 0xbf); -+ TEST_2OP_NEGATIVE(17, ror , 0, 0x00000001, 0x02); -+ TEST_2OP_NEGATIVE(18, ror , 1, 0x80000000, 0x00); -+ TEST_2OP_CARRY (19, ror , 1, 0x000000ff, 0x08); -+ TEST_1OP_CARRY (20, ror , 0, 0x00000002); -+ TEST_1OP_CARRY (21, ror , 1, 0x00000001); -+ TEST_1OP_ZERO (22, ror , 0, 0x00000100); -+ TEST_1OP_ZERO (23, ror , 1, 0x00000000); -+ TEST_1OP_NEGATIVE(24, ror , 0, 0x80000000); -+ TEST_1OP_NEGATIVE(25, ror , 1, 0x00000001); -+ TEST_1OP_CARRY (26, ror , 1, 0x80000001); -+ #ror8 does not update carry -+ TEST_1OP_CARRY (27, ror8, 0, 0x000000ff); -+ TEST_1OP_ZERO (28, ror8, 0, 0x00001000); -+ TEST_1OP_ZERO (29, ror8, 1, 0x00000000); -+ TEST_1OP_NEGATIVE(30, ror8, 0, 0x00000040); -+ TEST_1OP_NEGATIVE(31, ror8, 1, 0x00000080); -+ -+ARCTEST_END -diff --git a/tests/tcg/arc/check_rtc.S b/tests/tcg/arc/check_rtc.S -new file mode 100644 -index 0000000000..cb8a6ead9f ---- /dev/null -+++ b/tests/tcg/arc/check_rtc.S -@@ -0,0 +1,29 @@ -+ .include "macros.inc" -+ -+;;; Simple RTC test, read RTC value if it exists, spend some time, and -+;;; re-read it. Fail if the value is the same..data -+test_nr: -+ .word 0x0 -+ -+ start -+ test_name RTC -+ lr r0,[timer_build] -+ and.f 0,r0,0x400 -+ beq @.lfail -+ sr 1,[0x103] -+ lr r2,[0x104] -+.loop: -+ sub.f r0,r0,1 -+ bnz @.loop -+ lr r0,[0x104] -+ breq r0,r2,@.lfail -+ print "[PASS] " -+ b @1f -+ -+.lfail: -+ ld r0, [test_nr] -+ ;print_number r0 -+ print "[FAIL] " -+1: -+ printl r30 -+ end -diff --git a/tests/tcg/arc/check_rtie_user.S b/tests/tcg/arc/check_rtie_user.S -new file mode 100644 -index 0000000000..b29618a6ac ---- /dev/null -+++ b/tests/tcg/arc/check_rtie_user.S -@@ -0,0 +1,30 @@ -+ .include "macros.inc" -+ -+ start -+ enter_user_mode @user_mode -+ -+user_mode: -+ nop -+ ; must cause privilege violation exception -+faulty: -+ rtie -+ -+good: -+ print "You're on a righteous path.\n" -+ end -+ -+ .align 4 -+ .global EV_PrivilegeV -+ .type EV_PrivilegeV, @function -+EV_PrivilegeV: -+ lr r0, [eret] -+ brne r0, @faulty, @sucks -+ lr r0, [efa] -+ brne r0, @faulty, @sucks -+ mov r0, @good -+ sr r0, [eret] -+ rtie -+ -+sucks: -+ print "Life sucks. Get over it!\n" -+ end -diff --git a/tests/tcg/arc/check_stld.S b/tests/tcg/arc/check_stld.S -new file mode 100644 -index 0000000000..3817678b98 ---- /dev/null -+++ b/tests/tcg/arc/check_stld.S -@@ -0,0 +1,10 @@ -+.include "macros.inc" -+ -+ start -+ -+ test_name STLD_1 -+ st -32,[0x10000] -+ ld r2,[0x10000] -+ check_r2 -32 -+ -+ end -diff --git a/tests/tcg/arc/check_subf.S b/tests/tcg/arc/check_subf.S -new file mode 100644 -index 0000000000..10b98e803b ---- /dev/null -+++ b/tests/tcg/arc/check_subf.S -@@ -0,0 +1,67 @@ -+.include "macros.inc" -+ -+.macro validate res, actual, z, n, c, v, test_num -+ assert_eq \res, \actual, \test_num -+ assert_flag REG_STAT_Z, \z, \test_num -+ assert_flag REG_STAT_N, \n, \test_num -+ assert_flag REG_STAT_C, \c, \test_num -+ assert_flag REG_STAT_V, \v, \test_num -+.endm -+ -+.macro sub0_flags_test val1, val2, res, z=0, n=0, c=0, v=0, test_num=1 -+ mov r0, \val1 -+ mov r1, \val2 -+ sub.f r2, r0, r1 -+ validate \res, r2, \z, \n, \c, \v, \test_num -+.endm -+ -+.macro sub1_flags_test val1, val2, res, z=0, n=0, c=0, v=0, test_num=1 -+ mov r0, \val1 -+ mov r1, \val2 -+ sub1.f r2, r0, r1 -+ validate \res, r2, \z, \n, \c, \v, \test_num -+.endm -+ -+.macro sub2_flags_test val1, val2, res, z=0, n=0, c=0, v=0, test_num=1 -+ mov r0, \val1 -+ mov r1, \val2 -+ sub2.f r2, r0, r1 -+ validate \res, r2, \z, \n, \c, \v, \test_num -+.endm -+ -+.macro sub3_flags_test val1, val2, res, z=0, n=0, c=0, v=0, test_num=1 -+ mov r0, \val1 -+ mov r1, \val2 -+ sub3.f r2, r0, r1 -+ validate \res, r2, \z, \n, \c, \v, \test_num -+.endm -+ -+ -+start -+ -+sub0_flags_test 0xA0000000, 0xB0000000, 0xF0000000, z=0, n=1, c=1, v=0, test_num=0x01 -+sub1_flags_test 0xA0000000, 0x58000000, 0xF0000000, z=0, n=1, c=1, v=0, test_num=0x02 -+sub2_flags_test 0xA0000000, 0x2C000000, 0xF0000000, z=0, n=1, c=1, v=0, test_num=0x03 -+sub3_flags_test 0xA0000000, 0x16000000, 0xF0000000, z=0, n=1, c=1, v=0, test_num=0x04 -+ -+sub0_flags_test 0xFFFFFF80, 0xF0000000, 0x0FFFFF80, z=0, n=0, c=0, v=0, test_num=0x05 -+sub1_flags_test 0xFFFFFF80, 0x78000000, 0x0FFFFF80, z=0, n=0, c=0, v=0, test_num=0x06 -+sub2_flags_test 0xFFFFFF80, 0x3C000000, 0x0FFFFF80, z=0, n=0, c=0, v=0, test_num=0x07 -+sub3_flags_test 0xFFFFFF80, 0x1E000000, 0x0FFFFF80, z=0, n=0, c=0, v=0, test_num=0x08 -+ -+sub0_flags_test 0x80000000, 0x80000000, 0x00000000, z=1, n=0, c=0, v=0, test_num=0x09 -+sub1_flags_test 0x80000000, 0x40000000, 0x00000000, z=1, n=0, c=0, v=0, test_num=0x10 -+sub2_flags_test 0x80000000, 0x20000000, 0x00000000, z=1, n=0, c=0, v=0, test_num=0x11 -+sub3_flags_test 0x80000000, 0x10000000, 0x00000000, z=1, n=0, c=0, v=0, test_num=0x12 -+ -+sub0_flags_test 0x80000000, 0xC0000000, 0xC0000000, z=0, n=1, c=1, v=0, test_num=0x13 -+sub1_flags_test 0x80000000, 0x60000000, 0xC0000000, z=0, n=1, c=1, v=0, test_num=0x14 -+sub2_flags_test 0x80000000, 0x30000000, 0xC0000000, z=0, n=1, c=1, v=0, test_num=0x15 -+sub3_flags_test 0x80000000, 0x18000000, 0xC0000000, z=0, n=1, c=1, v=0, test_num=0x16 -+ -+sub0_flags_test 0x80000000, 0x00000008, 0x7FFFFFF8, z=0, n=0, c=0, v=1, test_num=0x17 -+sub1_flags_test 0x80000000, 0x00000004, 0x7FFFFFF8, z=0, n=0, c=0, v=1, test_num=0x18 -+sub2_flags_test 0x80000000, 0x00000002, 0x7FFFFFF8, z=0, n=0, c=0, v=1, test_num=0x19 -+sub3_flags_test 0x80000000, 0x00000001, 0x7FFFFFF8, z=0, n=0, c=0, v=1, test_num=0x20 -+ -+end -diff --git a/tests/tcg/arc/check_subx.S b/tests/tcg/arc/check_subx.S -new file mode 100644 -index 0000000000..7e4c4b1009 ---- /dev/null -+++ b/tests/tcg/arc/check_subx.S -@@ -0,0 +1,43 @@ -+#***************************************************************************** -+# sub.S -+#----------------------------------------------------------------------------- -+# -+# Test sub instruction. -+# -+ -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ -+ #------------------------------------------------------------- -+ # Arithmetic tests -+ #------------------------------------------------------------- -+ -+ TEST_RR_3OP( 2, sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); -+ TEST_RR_3OP( 3, sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 ); -+ TEST_RR_3OP( 4, sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 ); -+ -+ TEST_RR_3OP( 5, sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 ); -+ TEST_RR_3OP( 6, sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); -+ TEST_RR_3OP( 7, sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 ); -+ -+ TEST_RR_3OP( 8, sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff ); -+ TEST_RR_3OP( 9, sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); -+ TEST_RR_3OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff ); -+ -+ TEST_RR_3OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff ); -+ TEST_RR_3OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 ); -+ -+ TEST_RR_3OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff ); -+ TEST_RR_3OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 ); -+ TEST_RR_3OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff ); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ -+ TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 ); -+ TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 ); -+ TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/check_swi.S b/tests/tcg/arc/check_swi.S -new file mode 100644 -index 0000000000..6786807acd ---- /dev/null -+++ b/tests/tcg/arc/check_swi.S -@@ -0,0 +1,115 @@ -+ .include "macros.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; exception facilitators -+ .align 4 -+ecr_ref : .word 0x0 -+efa_ref : .word 0x0 -+eret_ref : .word 0x0 -+cont_addr : .word 0x0 -+test_number: .word 0x0 -+ -+; macro: set_excep_params -+; regs used: r11 -+; -+; this macro writes the provided parameters to a temporary place holder -+; later it will be used by SWI exception routine as a reference -+.macro set_excep_params ecr, efa, eret, continue, test_num -+ mov r11, \ecr -+ st r11, [ecr_ref] -+ mov r11, \efa -+ st r11, [efa_ref] -+ mov r11, \eret -+ st r11, [eret_ref] -+ mov r11, \continue -+ st r11, [cont_addr] -+ mov r11, \test_num -+ st r11, [test_number] -+.endm -+ -+; exception: software interrupt -+; regs used: r11, r12 -+; -+; this is a parameterized SWI exception that will check the followings: -+; ecr == ecr_ref -+; efa == efa_ref -+; eret == eret_ref -+; if everything passes, it will jump to 'cont_addr' parameter. -+; the parameters must be set beforehand using 'set_except_params' macro. -+; last but not least, this requires ivt.S file to be compiled and linked. -+ .align 4 -+ .global EV_SWI -+ .type EV_SWI, @function -+EV_SWI: -+ ld r11, [ecr_ref] -+ lr r12, [ecr] -+ brne r12, r11, @exc_fail -+ ld r11, [eret_ref] -+ lr r12, [eret] -+ brne r12, r11, @exc_fail -+ ld r11, [efa_ref] -+ lr r12, [efa] -+ brne r12, r11, @exc_fail -+ ; going back to the given address -+ ld r11, [cont_addr] -+ sr r11, [eret] -+ rtie -+exc_fail: -+ ld r11, [test_number] -+ print "[FAIL] " -+ print_number r11 -+ print ": exception is not sane!\n" -+ end -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; let the test code begin -+ start -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; check swi_s with no argument -+test01: -+ set_excep_params ecr = SOFTWARE_INTERRUPT, \ -+ efa = @test01_swis_addr , \ -+ eret = @test01_swis_addr , \ -+ continue = @test02 , \ -+ test_num = 0x01 -+ -+test01_swis_addr: -+ swi_s -+ -+ assert_eq 0, 1, 1 ; exception must have been raised -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; check swi_s with a u6 immediate -+test02: -+ .equ INTERRUPT_NUM , 42 -+ .equ TEST02_EXCP_REF, SOFTWARE_INTERRUPT | INTERRUPT_NUM -+ set_excep_params ecr = TEST02_EXCP_REF,\ -+ efa = @test02_swis_addr , \ -+ eret = @test02_swis_addr , \ -+ continue = @test03 , \ -+ test_num = 0x02 -+ -+test02_swis_addr: -+ swi_s INTERRUPT_NUM -+ -+ assert_eq 0, 1, 2 ; exception must have been raised -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; check swi -+test03: -+ set_excep_params ecr = SOFTWARE_INTERRUPT, \ -+ efa = @test03_swi_addr , \ -+ eret = @test03_swi_addr , \ -+ continue = @finish , \ -+ test_num = 0x01 -+ -+test03_swi_addr: -+ swi -+ -+ assert_eq 0, 1, 3 ; exception must have been raised -+ -+ -+finish: -+ print "[PASS] Software Interrupt\n" -+ end -diff --git a/tests/tcg/arc/check_swirq.S b/tests/tcg/arc/check_swirq.S -new file mode 100644 -index 0000000000..f3fb69d1ed ---- /dev/null -+++ b/tests/tcg/arc/check_swirq.S -@@ -0,0 +1,27 @@ -+ .include "macros.inc" -+ -+ start -+ ;; print "Start\n" -+ mov sp, 0x1000 -+ seti -+ sr 18, [aux_irq_hint] -+ print "[PASS] SW-IRQ:End\n" -+ end -+ -+ /* The delay between writing to the AUX_IRQ_HINT register and -+ the interrupt being taken is implementation specific. Hence, -+ we need to save/restore any clobber register by ISR. */ -+ .align 4 -+ .global IRQ_18 -+ .type IRQ_18, @function -+IRQ_18: -+ clri -+ push r11 -+ push r12 -+ sr 0, [aux_irq_hint] -+ print "[PASS] SW-IRQ:IRQ\n" -+ pop r12 -+ pop r11 -+ rtie -+ print "[FAIL] SW-IRQ\n" -+ end -diff --git a/tests/tcg/arc/check_swirq1.S b/tests/tcg/arc/check_swirq1.S -new file mode 100644 -index 0000000000..ca8e301dd3 ---- /dev/null -+++ b/tests/tcg/arc/check_swirq1.S -@@ -0,0 +1,31 @@ -+ .include "macros.inc" -+ -+ start -+ ;; print "Check normal IRQ functioning.\n" -+ ;; Set the stack somewhere -+ mov sp, 0x1000 -+ ;; Use IRQ18 for the test, change to a level 1, irq so we can -+ ;; avoid firq. -+ sr 18,[REG_IRQ_SELECT] -+ sr 1,[irq_priority] -+ set_interrupt_prio_level 1 -+ sr 16,[aux_irq_ctrl] -+ ;; Enable the interrupt system, and trigger the IRQ 18. -+ seti -+ sr 18, [aux_irq_hint] -+ print "[PASS] IRQ:End\n" -+ end -+ -+ /* The delay between writing to the AUX_IRQ_HINT register and -+ the interrupt being taken is implementation specific. Hence, -+ we need to save/restore any clobber register by ISR. */ -+ .align 4 -+ .global IRQ_18 -+ .type IRQ_18, @function -+IRQ_18: -+ clri -+ sr 0, [aux_irq_hint] -+ print "[PASS] IRQ:IRQ\n" -+ rtie -+ print "[FAIL] IRQ\n" -+ end -diff --git a/tests/tcg/arc/check_swirq3.S b/tests/tcg/arc/check_swirq3.S -new file mode 100644 -index 0000000000..2aa5bb8d82 ---- /dev/null -+++ b/tests/tcg/arc/check_swirq3.S -@@ -0,0 +1,49 @@ -+ .include "macros.inc" -+ -+ start -+;;; print "Check if an IRQ gets re-trigger while in ISR:" -+ ;; Set the stack somewhere -+ mov sp, 0x1000 -+ seti -+ mov r0,0 -+ ;; Use IRQ18 for the test. -+ sr 18, [AUX_IRQ_HINT] -+ ;; wait (sleep doesn't work as expected because all the irq -+ ;; are triggered BEFORE sleep is even fetch/executed. -+.llocal00: -+ breq r0, 0, @.llocal00 -+ brlt r0, 2, @.failMe -+ print "[PASS] SW-IRQ3\n" -+ end -+.failMe: -+ print "[PASS] SW-IRQ3\n" -+ end -+ -+ /* The delay between writing to the AUX_IRQ_HINT register and -+ the interrupt being taken is implementation specific. Hence, -+ we need to save/restore any clobber register by ISR. */ -+ .align 4 -+ .global IRQ_18 -+ .type IRQ_18, @function -+IRQ_18: -+#define AUX_IRQ_SELECT 0x40b -+#define AUX_IRQ_ENABLE 0x40c -+ clri -+ add r0,r0,1 -+ mov r1, AUX_IRQ_SELECT -+ mov r2, AUX_IRQ_ENABLE -+ ;; clean the IRQ -+ sr 18, [r1] -+ sr 0, [r2] -+ sr 0, [AUX_IRQ_HINT] -+ brgt r0,1,@.extisr -+ ;; retrigger the irq -+ sr 18, [AUX_IRQ_HINT] -+ sr 18, [r1] -+ sr 1, [r2] -+ ;; print " SW-IRQ 0," -+ rtie -+.extisr: -+ ;; print " SW-IRQ 1," -+ rtie -+ end -diff --git a/tests/tcg/arc/check_t01.S b/tests/tcg/arc/check_t01.S -new file mode 100644 -index 0000000000..c6cb9d0052 ---- /dev/null -+++ b/tests/tcg/arc/check_t01.S -@@ -0,0 +1,12 @@ -+ .include "macros.inc" -+ -+ start -+ test_name LOOP_1 -+ mov r2, 4 -+.L1: -+ sub_s r2,r2,1 -+ tst_s r2,r2 -+ bne @.L1 -+ check_r2 0x0 -+ -+ end -diff --git a/tests/tcg/arc/check_t02.S b/tests/tcg/arc/check_t02.S -new file mode 100644 -index 0000000000..1567bfe1d4 ---- /dev/null -+++ b/tests/tcg/arc/check_t02.S -@@ -0,0 +1,9 @@ -+ .include "macros.inc" -+ start -+ test_name PREDICATE_1 -+ mov r2,2 -+ lsr.f r2,r2 -+ mov.nc r2,1 -+ mov.cs r2,-1 # Should not execute -+ check_r2 0x01 -+ end -diff --git a/tests/tcg/arc/check_timer0.S b/tests/tcg/arc/check_timer0.S -new file mode 100644 -index 0000000000..f2afa83200 ---- /dev/null -+++ b/tests/tcg/arc/check_timer0.S -@@ -0,0 +1,36 @@ -+ .include "macros.inc" -+ -+ start -+ test_name TIMER0 -+ sr 0,[count0] -+ print "......" -+ lr r2,[count0] -+ breq r2, 0, @.lfail -+ print "X" -+ lr r0,[count0] -+ breq r0,r2,@.lfail -+ print "Pass\n" -+ sr 0x01,[control0] -+ mov r0, 0xffff -+ sr r0,[limit0] -+ sr 0,[count0] -+ mov r3, 0 -+ seti -+.loop0: -+ breq r3, 0, @.loop0 -+ print "The end\n" -+ end -+.lfail: -+ print "Fail\n" -+ end -+ -+ .align 4 -+ .global IRQ_Timer0 -+ .type IRQ_Timer0, @function -+IRQ_Timer0: -+ clri -+ sr 0x00,[control0] -+ print "Pass IRQ\n" -+ mov r3, 1 -+ rtie -+ end -diff --git a/tests/tcg/arc/check_timer0_loop.S b/tests/tcg/arc/check_timer0_loop.S -new file mode 100644 -index 0000000000..a1910a02ae ---- /dev/null -+++ b/tests/tcg/arc/check_timer0_loop.S -@@ -0,0 +1,34 @@ -+ .include "macros.inc" -+ -+ start -+ test_name TIMER0 -+ ;; enable TIMER0 interrupts -+ sr 0x01,[control0] -+ mov r0, 0x1fffff -+ sr r0,[limit0] -+ sr 0,[count0] -+ ;; Now wait for the counter to reach it's limit -+ mov r0,0 -+.loop1: -+ lr r0,[control0] -+ bbit0 r0,3,@.loop1 -+ ;; Now enable PIC interrupts, we expect the pending interrupt -+ ;; to kick in. -+ mov r3, 0 -+ seti -+.loop0: -+ breq r3, 0, @.loop0 -+ print "The end\n" -+ end -+ -+ .align 4 -+ .global IRQ_Timer0 -+ .type IRQ_Timer0, @function -+IRQ_Timer0: -+ clri -+ ;; reset interrupts -+ sr 0x00,[control0] -+ print "Pass IRQ\n" -+ mov r3, 1 -+ rtie -+ end -diff --git a/tests/tcg/arc/check_timer0_loop3.S b/tests/tcg/arc/check_timer0_loop3.S -new file mode 100644 -index 0000000000..c5a1013db4 ---- /dev/null -+++ b/tests/tcg/arc/check_timer0_loop3.S -@@ -0,0 +1,46 @@ -+ -+ .include "macros.inc" -+ -+.equ LIMIT, 0x1ff -+ -+ start -+ test_name TIMER0 -+ ;; enable TIMER0 interrupts -+ sr 0x01,[control0] -+ mov r0, LIMIT -+ sr r0,[limit0] -+ sr 0,[count0] -+ ;; Now wait for the counter to reach it's limit -+ mov r0,0 -+.loop1: -+ lr r0,[count0] -+ brgt r0,LIMIT,@.loop0 -+ ;; Now enable PIC interrupts, we expect the pending interrupt -+ ;; to kick in. -+ mov r3, 0 -+ seti -+.loop0: -+ lr r4,[count0] -+ breq r3, 1, @.pass -+ brgt r4,LIMIT,@.fail1 -+ j @.loop0 -+.pass: -+ print "[PASS]" -+ j @.end -+.fail1: -+ print "[FAIL]" -+ ;; print_number r4 -+.end: -+ print " TIMER0: Overflow\n" -+ end -+ -+ .align 4 -+ .global IRQ_Timer0 -+ .type IRQ_Timer0, @function -+IRQ_Timer0: -+ clri -+ ;; reset interrupts -+ sr 0x00,[control0] -+ mov r3, 1 -+ rtie -+ end -diff --git a/tests/tcg/arc/check_timer0_retrig.S b/tests/tcg/arc/check_timer0_retrig.S -new file mode 100644 -index 0000000000..f48e09504a ---- /dev/null -+++ b/tests/tcg/arc/check_timer0_retrig.S -@@ -0,0 +1,29 @@ -+ .include "macros.inc" -+ -+ start -+ test_name TIMER0_RETRIG -+ ;; enable TIMER0 interrupts -+ sr 0x01,[control0] -+ mov r0, 0x1fffff -+ sr r0,[limit0] -+ sr 0,[count0] -+ ;; Now wait for the counter to reach it's limit -+ mov r0,0 -+ seti -+.loop0: -+ brlt r3, 2, @.loop0 -+ print "[PASS] TIMER0: Re-trigger\n" -+ end -+ -+ .align 4 -+ .global IRQ_Timer0 -+ .type IRQ_Timer0, @function -+IRQ_Timer0: -+ clri -+ ;; reset interrupts & enable IRQ -+ sr 0x01,[control0] -+ ;; The timer needs to continue counting, and we expect a new -+ ;; interrupt soon. -+ add r3, r3, 1 -+ rtie -+ end -diff --git a/tests/tcg/arc/check_timer0_sleep.S b/tests/tcg/arc/check_timer0_sleep.S -new file mode 100644 -index 0000000000..87b58fcc78 ---- /dev/null -+++ b/tests/tcg/arc/check_timer0_sleep.S -@@ -0,0 +1,33 @@ -+ .include "macros.inc" -+ -+ start -+ -+ ; enable TIMER0 interrupts -+ sr 0x01,[control0] -+ mov r0, 0x5ffff -+ sr r0,[limit0] -+ sr 0,[count0] -+ mov r3, 0 -+ seti -+ -+ sleep -+ -+ breq r3, 1, @.passMe -+ print "[FAIL]" -+ b @.endtest -+.passMe: -+ print "[PASS]" -+.endtest: -+ print " TIMER0: sleep irq\n" -+ end -+ -+ .align 4 -+ .global IRQ_Timer0 -+ .type IRQ_Timer0, @function -+IRQ_Timer0: -+ clri -+ ; reset interrupts -+ sr 0x00,[control0] -+ mov r3, 1 -+ rtie -+ end -diff --git a/tests/tcg/arc/check_timerX_freq.S b/tests/tcg/arc/check_timerX_freq.S -new file mode 100644 -index 0000000000..606c3ca82d ---- /dev/null -+++ b/tests/tcg/arc/check_timerX_freq.S -@@ -0,0 +1,87 @@ -+ .include "macros.inc" -+ -+ start -+ test_name TIMER0vsTIMER1 -+ ;; enable TIMER0 interrupts -+ sr 0x01,[control0] -+ mov r0, 0x1ffff -+ sr r0,[limit0] -+ sr 0,[count0] -+ -+ ;; enable TIMER1 interrupts -+ sr 0x01,[control1] -+ mov r0, 0x3fffe ;Twice slower -+ sr r0,[limit1] -+ sr 0,[count1] -+ mov r4,0 -+ mov r5,0 -+ mov sp,0x1000 -+ seti -+ mov r3, 0 -+.loop: -+ sleep -+ add r3,r3,1 -+ brne r3,10,@.loop -+ clri -+ stb.ab 0,[sp,1] -+ mov r0,r4 -+.L02: -+ rem r2,r0,10 -+ add r2,r2,0x30 -+ stb.ab r2,[sp,1] -+ div.f r0,r0,10 -+ bne @.L02 -+.L03: -+ ld.aw r2,[sp,-1] -+ breq r2,0,@.L04 -+ ;; stb r2,[OUTPUT_DEVICE] -+ brne r2,0,@.L03 -+.L04: -+ -+ ;; print ">>>" -+ stb.ab 0,[sp,1] -+ mov r0,r5 -+.L12: -+ rem r2,r0,10 -+ add r2,r2,0x30 -+ stb.ab r2,[sp,1] -+ div.f r0,r0,10 -+ bne @.L12 -+.L13: -+ ld.aw r2,[sp,-1] -+ breq r2,0,@.L14 -+ ;; stb r2,[OUTPUT_DEVICE] -+ brne r2,0,@.L13 -+.L14: -+ breq r5, 0, @.failMe -+ brgt r4,r5, @.passMe -+.failMe: -+ print "[FAIL] " -+ b 1f -+.passMe: -+ print "[PASS] " -+1: -+ printl r30 -+ end -+ -+ .align 4 -+ .global IRQ_Timer0 -+ .type IRQ_Timer0, @function -+IRQ_Timer0: -+ clri -+ ;; reset interrupts -+ sr 0x01,[control0] -+ sr 0,[count0] -+ add r4,r4,1 -+ rtie -+ -+ .global IRQ_Timer1 -+ .type IRQ_Timer1, @function -+IRQ_Timer1: -+ clri -+ ;; reset interrupts -+ sr 0x01,[control1] -+ sr 0,[count1] -+ add r5,r5,1 -+ rtie -+ end -diff --git a/tests/tcg/arc/check_vadd.S b/tests/tcg/arc/check_vadd.S -new file mode 100644 -index 0000000000..5370452ed1 ---- /dev/null -+++ b/tests/tcg/arc/check_vadd.S -@@ -0,0 +1,510 @@ -+; check_vadd.S -+; -+; Tests for vadd: vadd2 vadd2h vadd4h -+; If the test fails, check the end of this file for how to troubleshoot. -+ -+ .include "macros.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case counter -+.data -+test_nr: -+ .word 0x0 -+ -+; Increment the test counter and set (Z,N,C,V) to (0,0,0,0). -+.macro prep_test_case -+ ld r13, [test_nr] -+ add_s r13, r13, 1 ; increase test case counter -+ st r13, [test_nr] -+ add.f 0, 0, 1 ; (Z, N, C, V) = (0, 0, 0, 0) -+.endm -+ -+; Checks if (Z,N,C,V) == (0,0,0,0). This relies on "ADD.F 0,0,1" -+; instruction in PREP_TEST_CASE macro. From a PREP_TEST_CASE macro -+; in a test case, and thence to a VECTOR instruction and finally to -+; this macro, none of the aforementioned flags must have been set, -+; because VECTOR instructions aren't supposed to do so. -+.macro check_flags_remained_zero -+ lr r11, [status32] -+ mov r12, REG_STAT_Z -+ or r12, r12, REG_STAT_N -+ or r12, r12, REG_STAT_C -+ or r12, r12, REG_STAT_V -+ and r11, r11, r12 -+ cmp r11, 0 -+ bne @fail -+.endm -+ -+; pair(HI, LOW) == pair(REG_HI, REG_LO) -+; HI, LO: 32-bit -+; REG_HI, REG_LO: 32-bit -+.macro check_64bit_double hi, low, reg_hi, reg_lo -+ check_flags_remained_zero -+ mov r11, \hi -+ mov r10, \low -+ cmp r11, \reg_hi -+ bne @fail -+ cmp r10, \reg_lo -+ bne @fail -+.endm -+ -+; REG == (HI, LO) -+; HI, LO: 16-bit -+; REG: 32-bit -+.macro check_32bit_double hi, low, reg -+ check_flags_remained_zero -+ mov r11, \hi -+ and r11, r11, 0xffff -+ lsl16 r11, r11 -+ mov r12, \low -+ and r12, r12, 0xffff -+ or r11, r11, r12 -+ cmp r11, \reg -+ bne @fail -+.endm -+ -+; quartet(q3, q2, q1, q0) == pair64(REG_HI, REG_LO) -+; Q3, Q2, Q1, Q0: 16-bit -+; REG_HI, REG_LO: 32-bit -+.macro check_64bit_quadruple q3, q2, q1, q0, reg_hi, reg_lo -+ check_flags_remained_zero -+ mov r11, \q3 -+ and r11, r11, 0xffff -+ lsl16 r11, r11 -+ mov r12, \q2 -+ and r12, r12, 0xffff -+ or r11, r11, r12 -+ mov r10, \q1 -+ and r10, r10, 0xffff -+ lsl16 r10, r10 -+ mov r12, \q0 -+ and r12, r12, 0xffff -+ or r10, r10, r12 -+ cmp r11, \reg_hi -+ bne @fail -+ cmp r10, \reg_lo -+ bne @fail -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; parameters that an IllegalInstruction exception may set. -+ .align 4 -+ecr_ref : .word ILLEGAL_INSTRUCTION -+addr_ref : .word 0x0 ; for both eret and efa -+cont_addr: .word 0x0 -+ -+; exception: IllegalInstruction -+; regs used: r11, r12 -+; -+; A parameterized IllegalInstruction exception that checks the followings: -+; ecr == Illegal instruction -+; efa == efa_ref -+; eret == eret_ref -+; If everything passes, it will jump to 'cont_addr' parameter. The parameters -+; must be set beforehand using 'set_except_params' macro. This requires -+; ivt.S file to be compiled and linked. -+ .align 4 -+ .global instruction_error -+ .type instruction_error, @function -+instruction_error: -+ ld r11, [ecr_ref] -+ lr r12, [ecr] -+ cmp r12, r11 -+ bne @fail -+ ld r11, [addr_ref] -+ lr r12, [eret] -+ cmp r12, r11 -+ bne @fail -+ lr r12, [efa] -+ cmp r12, r11 -+ bne @fail -+ ; Success: continuing -+ ld r11, [cont_addr] -+ sr r11, [eret] -+ rtie -+ -+; macro: set_except_params -+; regs used: r11 -+; -+; This macro writes the provided parameters to a temporary place holder -+; that later will be used by exception above to verify as reference. -+.macro set_except_params addr, continue -+ mov r11, \addr -+ st r11, [addr_ref] -+ mov r11, \continue -+ st r11, [cont_addr] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VADD2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Let the tests begin -+ start -+ -+; Test case 1 -+; reg2 <- reg2, reg2 -+; (0x00000006,0x00000004)=(0x80000003,0x80000002)+(0x80000003,0x80000002) -+; To boot, C and V flags must not be set. -+ prep_test_case -+ mov r2, 0x80000002 -+ mov r3, 0x80000003 -+ vadd2 r2, r2, r2 -+ check_64bit_double 0x00000006, 0x00000004, r3, r2 -+ -+; Test case 2 -+; reg0 <- reg2, reg0 -+; (4,6)=(1,2)+(3,4) -+ prep_test_case -+ mov r3, 0x00000001 -+ mov r2, 0x00000002 -+ mov r1, 0x00000003 -+ mov r0, 0x00000004 -+ vadd2 r0, r2, r0 -+ check_64bit_double 4, 6, r1, r0 -+ -+; Test case 3 -+; reg0 <- limm, reg4 -+; (0x00000000,0x00000000)=(0x12345678,0x12345678)+(0xedcba988,0xedcba988) -+; Moreover, Z flag mustn't be set. -+ prep_test_case -+ mov r0, 0x11111111 ; bogus data -+ mov r1, 0x22222222 ; bogus data -+ mov r4, 0xedcba988 ; neg(0x12345678) -+ mov r5, 0xedcba988 ; neg(0x12345678) -+ vadd2 r0, 0x12345678, r4 -+ check_64bit_double 0x00, 0x00, r1, r0 -+ -+; Test case 4 -+; reg4 <- reg2, limm -+; (-3,-2)=(-2,-1)+(-1,-1) -+; The N flag must not be set, irrespective of having negative results. -+ prep_test_case -+ mov r2, -1 -+ mov r3, -2 -+ vadd2 r4, r2, -1 -+ check_64bit_double -3, -2, r5, r4 -+ -+; Test case 5 -+; reg2 <- limm, limm (both limm should be the same) -+; (0x2468acf0,0x2468acf0)=(0x12345678,0x12345678)+(0x12345678,0x12345678) -+ prep_test_case -+ vadd2 r2, 0x12345678, 0x12345678 -+ check_64bit_double 0x2468acf0, 0x2468acf0, r3, r2 -+ -+; Test case 6 -+; reg4 <- limm, u6 -+; (0x01020343,0x01020343)=(0x01020304,0x01020304)+(0x3f,0x3f) -+ prep_test_case -+ vadd2 r4, 0x01020304, 63 -+ check_64bit_double 0x01020343, 0x01020343, r5, r4 -+ -+; Test case 7 -+; reg2 <- reg4, 0(u6) -+; (0x08070605,0x04030201)=(0x08070605,0x04030201)+(0,0) -+ prep_test_case -+ mov r5, 0x08070605 -+ mov r4, 0x04030201 -+ vadd2 r2, r4, 0 -+ check_64bit_double 0x08070605, 0x04030201, r3, r2 -+ -+; Test case 8 -+; reg2 <- reg2, s12 -+; (3000002048,2000002048)=(3000004096,2000004096)+(-2048,-2048) -+ prep_test_case -+ mov r3, 3000004096 -+ mov r2, 2000004096 -+ vadd2 r2, r2, -2048 -+ check_64bit_double 3000002048, 2000002048, r3, r2 -+ -+; Test case 9 -+; 0 <- limm, s12 -+; (X,X)=(0xffeeddbb,0xffeeddbb)+(-2048,-2048) -+ prep_test_case -+ vadd2 0, 0xffeeddbb, -2048 -+ -+; Test case 10 -+; Testing when cc condition is met -+; (6,4)=(3,2)+(3,2) -+ prep_test_case -+ mov r2, 2 -+ mov r3, 3 -+ mov r4, 0x80000000 ; setting... -+ add.f 0,r4,r4 ; ...C=1 -+ vadd2.c r2, r2, r2 -+ add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. -+ check_64bit_double 6, 4, r3, r2 -+ -+; Test case 11 -+; Testing when cc condition is not met -+; (2,0) -+ prep_test_case -+ mov r2, 0 -+ mov r3, 2 -+ vadd2.z r2, r2, r2 ; Z=0 because of PREP_TEST_CASE -+ check_64bit_double 2, 0, r3, r2 -+ -+; Test case 12 -+; Raise an Illegal Instruction exception if an odd register is used. -+; Even if there is no register to save the result to. -+ prep_test_case -+ set_except_params @test_12_exception, @test_12_end -+test_12_exception: -+ .word 0x003e2b3c ; vadd2 0, r3, r0 -+ b @fail -+test_12_end: -+ ; Fall through -+ -+; Test case 13 -+; Raise an Illegal Instruction exception if an odd register is used. -+; The exception should be made even if the CC indicates no execution. -+ prep_test_case ; (Z,N,C,V)=(0,0,0,0) -+ set_except_params @test_13_exception, @test_13_end -+test_13_exception: -+ .word 0x00012dfc ; vadd2.z r5, r5, r0 -+ b @fail -+test_13_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VADD2H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case 14 -+; reg1 <- reg1, reg1 -+; (0x0006,0x0004)=(0x8003,0x8002)+(0x8003,0x8002) -+; Moreover, the C and V flags are not going to be set. -+ prep_test_case -+ mov r1, 0x80038002 -+ vadd2h r1, r1, r1 -+ check_32bit_double 0x0006, 0x0004, r1 -+ -+; Test case 15 -+; reg1 <- reg1, reg3 -+; (4,6)=(1,2)+(3,4) -+ prep_test_case -+ mov r3, 0x00010002 -+ mov r1, 0x00030004 -+ vadd2h r1, r1, r3 -+ check_32bit_double 4, 6, r1 -+ -+; Test case 16 -+; reg0 <- limm, reg4 -+; (0x0000,0x0000)=(0x1234,0x5678)+(0xedcc,0xa988) -+; The Z flag must not be set. -+ prep_test_case -+ mov r0, 0x11112222 ; bogus data -+ mov r4, 0xedcca988 ; (neg(0x1234),neg(0x5678)) -+ vadd2h r0, 0x12345678, r4 -+ check_32bit_double 0x0000, 0x0000, r0 -+ -+; Test case 17 -+; reg5 <- reg3, limm -+; (-3,-2)=(-2,-1)+(-1,-1) -+; The N flag mustn't be set, irrespective of having negative results. -+ prep_test_case -+ mov r3, 0xfffeffff ; (-2,-1) -+ vadd2h r5, r3, -1 -+ check_32bit_double -3, -2, r5 -+ -+; Test case 18 -+; reg1 <- limm, limm (both limm should be the same) -+; (0x2468,0xacf0)=(0x1234,0x5678)+(0x1234,0x5678) -+ prep_test_case -+ vadd2h r1, 0x12345678, 0x12345678 -+ check_32bit_double 0x2468, 0xacf0, r1 -+ -+; Test case 19 -+; reg0 <- limm, u6 -+; (0x0141,0x0343)=(0x0102,0x0304)+(0x3f,0x3f) -+ prep_test_case -+ vadd2h r0, 0x01020304, 63 -+ check_32bit_double 0x0141, 0x0343, r0 -+ -+; Test case 20 -+; reg1 <- reg0, 0(u6) -+; (0x0403,0x0201)=(0x0403,0x0201)+(0,0) -+ prep_test_case -+ mov r0, 0x04030201 -+ vadd2h r1, r0, 0 -+ check_32bit_double 0x0403, 0x0201, r1 -+ -+; Test case 21 -+; reg3 <- reg3, s12 -+ ; (30064,-1)=(30000,-65)+(-125,-125) -+ prep_test_case -+ mov r3, 0x7530ffbf ; (30000,-65) -+ vadd2h r3, r3, -125 -+ check_32bit_double 29875, -190, r3 -+ -+; Test case 22 -+; 0 <- limm, s12 -+; (X,X)=(0xffee,0xddbb)+(-2048,-2048) -+ prep_test_case -+ vadd2h 0, 0xffeeddbb, -2048 -+ -+; Test case 23 -+; Testing when cc condition is met -+; (6,4)=(3,2)+(3,2) -+ prep_test_case -+ mov r1, 0x00030002 -+ mov r0, 0x80000000 ; setting... -+ add.f 0,r0,r0 ; ...V=1 -+ vadd2h.v r1, r1, r1 -+ add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. -+ check_32bit_double 6, 4, r1 -+ -+; Test case 24 -+; Testing when cc condition is not met -+; (2,0) -+ prep_test_case -+ mov r4, 0x00020000 -+ vadd2h.n r4, r4, r4 ; N is already 0 because of PRE_TEST_CASE. -+ check_32bit_double 2, 0, r4 -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VADD4H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case 25 -+; reg2 <- reg2, reg2 -+; (0x0000,0x0006,0x0000,0x0004)=(0x8000,0x8003,0x8000,0x8002)+ -+; (0x8000,0x8003,0x8000,0x8002) -+; Moreover, the C and V flags must not be set. -+ prep_test_case -+ mov r2, 0x80008002 -+ mov r3, 0x80008003 -+ vadd4h r2, r2, r2 -+ check_64bit_quadruple 0x0000, 0x0006, 0x0000, 0x0004, r3, r2 -+ -+; Test case 26 -+; reg0 <- reg2, reg0 -+; (6,8,10,12)=(1,2,3,4)+(5,6,7,8) -+ prep_test_case -+ mov r3, 0x00010002 -+ mov r2, 0x00030004 -+ mov r1, 0x00050006 -+ mov r0, 0x00070008 -+ vadd4h r0, r2, r0 -+ check_64bit_quadruple 6, 8, 10, 12, r1, r0 -+ -+; Test case 27 -+; reg0 <- limm, reg4 -+; (0x0000,0x0000,0x0000,0x0000)=(0x1234,0x5678,0x1234,0x5678)+ -+; (0xedcc,0xa988,0xedcc,0xa988) -+; also the Z flag mustn't be set. -+ prep_test_case -+ mov r0, 0x11111111 ; bogus data -+ mov r1, 0x22222222 ; bogus data -+ mov r4, 0xedcca988 ; (neg(0x1234),neg(0x5678)) -+ mov r5, 0xedcca988 ; (neg(0x1234),neg(0x5678)) -+ vadd4h r0, 0x12345678, r4 -+ check_64bit_quadruple 0x00, 0x00, 0x00, 0x00, r1, r0 -+ -+; Test case 28 -+; reg4 <- reg2, limm -+; (-5,-4,-3,-2)=(-4,-3,-2,-1)+(-1,-1,-1,-1) -+; The N flag must not be set, irrespective of having negative results. -+ prep_test_case -+ mov r2, 0xfffeffff ; (-2,-1) -+ mov r3, 0xfffcfffd ; (-4,-3) -+ vadd4h r4, r2, -1 -+ check_64bit_quadruple -5, -4, -3, -2, r5, r4 -+ -+; Test case 29 -+; reg2 <- limm, limm (both limm should be the same) -+; (0x2468,0xacf0,0x2468,0xacf0)=(0x1234,0x5678,0x1234,0x5678)+ -+; (0x1234,0x5678,0x1234,0x5678) -+ prep_test_case -+ vadd4h r2, 0x12345678, 0x12345678 -+ check_64bit_quadruple 0x2468, 0xacf0, 0x2468, 0xacf0, r3, r2 -+ -+; Test case 30 -+; reg4 <- limm, u6 -+; (0x0141,0x0343,0x0141,0x0343)=(0x0102,0x0304,0x0102,0x0304)+ -+; ( 0x3f, 0x3f, 0x3f, 0x3f) -+ prep_test_case -+ vadd4h r4, 0x01020304, 63 -+ check_64bit_quadruple 0x0141, 0x0343, 0x0141, 0x0343, r5, r4 -+ -+; Test case 31 -+; reg0 <- reg4, 0(u6) -+; (0x1122,0x3344,0x5566,0x7788)=(0x1122,0x3344,0x5566,0x7788)+ -+; (0x0000,0x0000,0x0000,0x0000) -+ prep_test_case -+ mov r5, 0x11223344 -+ mov r4, 0x55667788 -+ vadd4h r0, r4, 0 -+ check_64bit_quadruple 0x1122, 0x3344, 0x5566, 0x7788, r1, r0 -+ -+; Test case 32 -+; reg0 <- reg0, s12 -+; (2048,2046,2049,2035)=(1,-1,2,-12)+(2047,2047,2047,2047) -+ prep_test_case -+ mov r1, 0x0001ffff ; (1,-1) -+ mov r0, 0x0002fff4 ; (2,-12) -+ vadd4h r0, r0, 2047 -+ check_64bit_quadruple 2048, 2046, 2049, 2035, r1, r0 -+ -+; Test case 33 -+; 0 <- limm, s12 -+; (X,X,X,X)=(0xffee,0xddbb,0xffee,0xddbb)+(-2048,-2048,-2048,-2048) -+ prep_test_case -+ vadd4h 0, 0xffeeddbb, -2048 -+ -+; Test case 34 -+; Testing when cc condition is met -+; (40,80,120,160)=(20,40,60,80)+(20,40,60,80) -+ prep_test_case -+ mov r2, 0x003c0050 ; (60,80) -+ mov r3, 0x00140028 ; (20,40) -+ mov r4, 0x80000000 ; setting... -+ add.f 0,r4,r4 ; ...C=1 -+ vadd4h.c r2, r2, r2 -+ add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. -+ check_64bit_quadruple 40, 80, 120, 160, r3, r2 -+ -+; Test case 35 -+; Testing when cc condition is not met -+; (2,0) -+ prep_test_case -+ mov r2, 0x00020000 -+ mov r3, 0x00020000 -+ vadd4h.z r2, r2, r2 ; Z is already 0 because of PREP_TEST_CASE. -+ check_64bit_quadruple 2, 0, 2, 0, r3, r2 -+ -+; Test case 36 -+; Raise an Illegal Instruction exception if an odd register is used. -+; Even if there is no register to save the result to. -+ prep_test_case -+ set_except_params @test_36_exception, @test_36_end -+test_36_exception: -+ .word 0x00fe2a38 ; vadd4h 0, r2, r3 -+ b @fail -+test_36_end: -+ ; Fall through -+ -+; Test case 37 -+; Raise an Illegal Instruction exception if an odd register is used. -+; The exception should be made even if the CC indicates no execution. -+ prep_test_case ; (Z,N,C,V)=(0,0,0,0) -+ set_except_params @test_37_exception, @test_37_end -+test_37_exception: -+ .word 0x000429f8 ; vadd4h.n r1, r1, r0 -+ b @fail -+test_37_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [test_nr] -+ ;print_number r0 -+ print "[FAIL]" -+1: -+ print " vadd: vadd2 vadd2h vadd4h\n" -+ end -diff --git a/tests/tcg/arc/check_vsub.S b/tests/tcg/arc/check_vsub.S -new file mode 100644 -index 0000000000..327cd0cbda ---- /dev/null -+++ b/tests/tcg/arc/check_vsub.S -@@ -0,0 +1,510 @@ -+; check_vsub.S -+; -+; Tests for vsub: vsub2 vsub2h vsub4h -+; If the test fails, check the end of this file for how to troubleshoot. -+ -+ .include "macros.inc" -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case counter -+.data -+test_nr: -+ .word 0x0 -+ -+; Increment the test counter and set (Z,N,C,V) to (0,0,0,0). -+.macro prep_test_case -+ ld r13, [test_nr] -+ add_s r13, r13, 1 ; increase test case counter -+ st r13, [test_nr] -+ add.f 0, 0, 1 ; (Z, N, C, V) = (0, 0, 0, 0) -+.endm -+ -+; Checks if (Z,N,C,V) == (0,0,0,0). This relies on "ADD.F 0,0,1" -+; instruction in PREP_TEST_CASE macro. From a PREP_TEST_CASE macro -+; in a test case, and thence to a VECTOR instruction and finally to -+; this macro, none of the aforementioned flags must have been set, -+; because VECTOR instructions aren't supposed to do so. -+.macro check_flags_remained_zero -+ lr r11, [status32] -+ mov r12, REG_STAT_Z -+ or r12, r12, REG_STAT_N -+ or r12, r12, REG_STAT_C -+ or r12, r12, REG_STAT_V -+ and r11, r11, r12 -+ cmp r11, 0 -+ bne @fail -+.endm -+ -+; pair(HI, LOW) == pair(REG_HI, REG_LO) -+; HI, LO: 32-bit -+; REG_HI, REG_LO: 32-bit -+.macro check_64bit_double hi, low, reg_hi, reg_lo -+ check_flags_remained_zero -+ mov r11, \hi -+ mov r10, \low -+ cmp r11, \reg_hi -+ bne @fail -+ cmp r10, \reg_lo -+ bne @fail -+.endm -+ -+; REG == (HI, LO) -+; HI, LO: 16-bit -+; REG: 32-bit -+.macro check_32bit_double hi, low, reg -+ check_flags_remained_zero -+ mov r11, \hi -+ and r11, r11, 0xffff -+ lsl16 r11, r11 -+ mov r12, \low -+ and r12, r12, 0xffff -+ or r11, r11, r12 -+ cmp r11, \reg -+ bne @fail -+.endm -+ -+; quartet(q3, q2, q1, q0) == pair64(REG_HI, REG_LO) -+; Q3, Q2, Q1, Q0: 16-bit -+; REG_HI, REG_LO: 32-bit -+.macro check_64bit_quadruple q3, q2, q1, q0, reg_hi, reg_lo -+ check_flags_remained_zero -+ mov r11, \q3 -+ and r11, r11, 0xffff -+ lsl16 r11, r11 -+ mov r12, \q2 -+ and r12, r12, 0xffff -+ or r11, r11, r12 -+ mov r10, \q1 -+ and r10, r10, 0xffff -+ lsl16 r10, r10 -+ mov r12, \q0 -+ and r12, r12, 0xffff -+ or r10, r10, r12 -+ cmp r11, \reg_hi -+ bne @fail -+ cmp r10, \reg_lo -+ bne @fail -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; parameters that an IllegalInstruction exception may set. -+ .align 4 -+ecr_ref : .word ILLEGAL_INSTRUCTION -+addr_ref : .word 0x0 ; for both eret and efa -+cont_addr: .word 0x0 -+ -+; exception: IllegalInstruction -+; regs used: r11, r12 -+; -+; A parameterized IllegalInstruction exception that checks the followings: -+; ecr == Illegal instruction -+; efa == efa_ref -+; eret == eret_ref -+; If everything passes, it will jump to 'cont_addr' parameter. The parameters -+; must be set beforehand using 'set_except_params' macro. This requires -+; ivt.S file to be compiled and linked. -+ .align 4 -+ .global instruction_error -+ .type instruction_error, @function -+instruction_error: -+ ld r11, [ecr_ref] -+ lr r12, [ecr] -+ cmp r12, r11 -+ bne @fail -+ ld r11, [addr_ref] -+ lr r12, [eret] -+ cmp r12, r11 -+ bne @fail -+ lr r12, [efa] -+ cmp r12, r11 -+ bne @fail -+ ; Success: continuing -+ ld r11, [cont_addr] -+ sr r11, [eret] -+ rtie -+ -+; macro: set_except_params -+; regs used: r11 -+; -+; This macro writes the provided parameters to a temporary place holder -+; that later will be used by exception above to verify as reference. -+.macro set_except_params addr, continue -+ mov r11, \addr -+ st r11, [addr_ref] -+ mov r11, \continue -+ st r11, [cont_addr] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VSUB2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Let the tests begin -+ start -+ -+; Test case 1 -+; reg2 <- reg2, reg2 -+; (0x00000000,0x00000000)=(0x80000000,0xffffffff)-(0x80000000,0xffffffff) -+; The Z flag must remain 0. -+ prep_test_case -+ mov r2, 0xffffffff -+ mov r3, 0x80000000 -+ vsub2 r2, r2, r2 -+ check_64bit_double 0, 0, r3, r2 -+ -+; Test case 2 -+; reg0 <- reg2, reg0 -+; (0x7fffffff,0x80000000)=(-1,0x7fffffff)-(0x80000000,-1) -+; The V and N flags must remain zero. -+ prep_test_case -+ mov r3, 0xffffffff -+ mov r2, 0x7fffffff -+ mov r1, 0x80000000 -+ mov r0, 0xffffffff -+ vsub2 r0, r2, r0 -+ check_64bit_double 0x7fffffff, 0x80000000, r1, r0 -+ -+; Test case 3 -+; reg0 <- limm, reg4 -+; (0x90abcdef,0x00000001)=(0x12345678,0x12345678)-(0x81888889,0x12345677) -+ prep_test_case -+ mov r0, 0x11111111 ; bogus data -+ mov r1, 0x22222222 ; bogus data -+ mov r4, 0x12345677 -+ mov r5, 0x81888889 -+ vsub2 r0, 0x12345678, r4 -+ check_64bit_double 0x90abcdef, 0x01, r1, r0 -+ -+; Test case 4 -+; reg4 <- reg2, limm -+; (-999999999,-999999998)=(1,2)-(1000000000,1000000000) -+; The N flag must not be set, irrespective of having negative results. -+ prep_test_case -+ mov r2, 2 -+ mov r3, 1 -+ vsub2 r4, r2, 0x3b9aca00 ; 0x3b9aca00=1000000000 -+ check_64bit_double -999999999, -999999998, r5, r4 -+ -+; Test case 5 -+; reg2 <- limm, limm (both limm should be the same) -+; (0x00,0x00)=(0x12345678,0x12345678)-(0x12345678,0x12345678) -+ prep_test_case -+ vsub2 r2, 0x12345678, 0x12345678 -+ check_64bit_double 0, 0, r3, r2 -+ -+; Test case 6 -+; reg4 <- limm, u6 -+; (0x010202c5,0x010202c5)=(0x01020304,0x01020304)-(0x3f,0x3f) -+ prep_test_case -+ vsub2 r4, 0x01020304, 63 -+ check_64bit_double 0x010202c5, 0x010202c5, r5, r4 -+ -+; Test case 7 -+; reg2 <- reg4, 0(u6) -+; (0x08070605,0x04030201)=(0x08070605,0x04030201)-(0,0) -+ prep_test_case -+ mov r5, 0x08070605 -+ mov r4, 0x04030201 -+ vsub2 r2, r4, 0 -+ check_64bit_double 0x08070605, 0x04030201, r3, r2 -+ -+; Test case 8 -+; reg0 <- reg0, s12 -+; (2048,-200000000)=(0,-2000002048)-(-2048,-2048) -+ prep_test_case -+ mov r1, 0 -+ mov r0, -2000002048 -+ vsub2 r0, r0, -2048 -+ check_64bit_double 2048, -2000000000, r1, r0 -+ -+; Test case 9 -+; 0 <- limm, s12 -+; (X,X)=(0xffeeddbb,0xffeeddbb)-(-2048,-2048) -+ prep_test_case -+ vsub2 0, 0xffeeddbb, -2048 -+ -+; Test case 10 -+; Testing when cc condition is met -+; (0,0)=(3,2)+(3,2) -+ prep_test_case -+ mov r2, 2 -+ mov r3, 3 -+ mov r4, 0x80000000 ; setting... -+ add.f 0,r4,r4 ; ...C=1 -+ vsub2.c r2, r2, r2 -+ add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. -+ check_64bit_double 0, 0, r3, r2 -+ -+; Test case 11 -+; Testing when cc condition is not met -+; (2,0) -+ prep_test_case -+ mov r2, 0 -+ mov r3, 2 -+ vsub2.z r2, r2, r2 ; Z=0 because of PREP_TEST_CASE -+ check_64bit_double 2, 0, r3, r2 -+ -+; Test case 12 -+; Raise an Illegal Instruction exception if an odd register is used. -+; Even if there is no register to save the result to. -+ prep_test_case -+ set_except_params @test_12_exception, @test_12_end -+test_12_exception: -+ vsub2 0, r5, r0 -+ b @fail -+test_12_end: -+ ; Fall through -+ -+; Test case 13 -+; Raise an Illegal Instruction exception if an odd register is used. -+; The exception should be made even if the CC indicates no execution. -+ prep_test_case ; (Z,N,C,V)=(0,0,0,0) -+ set_except_params @test_13_exception, @test_13_end -+test_13_exception: -+ vsub2.c r1, r1, r0 -+ b @fail -+test_13_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VSUB2H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case 14 -+; reg1 <- reg1, reg1 -+; (0x0000,0x0000)=(0x8000,0xffff)-(0x8000,0xffff) -+; To boot, the Z flag must remain unsett. -+ prep_test_case -+ mov r1, 0x8000ffff -+ vsub2h r1, r1, r1 -+ check_32bit_double 0, 0, r1 -+ -+; Test case 15 -+; reg1 <- reg1, reg3 -+; (0x7fff,0x8000)=(-1,0x7fff)-(0x8000,-1) -+; The V and N flags must remain zero. -+ prep_test_case -+ mov r1, 0xffff7fff -+ mov r3, 0x8000ffff -+ vsub2h r1, r1, r3 -+ check_32bit_double 0x7fff, 0x8000, r1 -+ -+; Test case 16 -+; reg0 <- limm, reg4 -+; (0x4321,0x0001)=(0x1234,0x5678)-(0xcf13,0x5677) -+ prep_test_case -+ mov r0, 0x11111111 ; bogus data -+ mov r4, 0xcf135677 -+ vsub2h r0, 0x12345678, r4 -+ check_32bit_double 0x4321, 0x0001, r0 -+ -+; Test case 17 -+; reg5 <- reg3, limm -+; (-9999,-9998)=(1,2)-(10000,10000) -+; The N flag must not be set, irrespective of having negative results. -+ prep_test_case -+ mov r3, 0x00010002 ; (1,2) -+ vsub2h r5, r3, 0x27102710 ; (1,2)-(10000,10000) -+ check_32bit_double -9999, -9998, r5 -+ -+; Test case 18 -+; reg1 <- limm, limm (both limm should be the same) -+; (0x00,0x00)=(0x1234,0x5678)-(0x1234,0x5678) -+ prep_test_case -+ vsub2h r1, 0x12345678, 0x12345678 -+ check_32bit_double 0, 0, r1 -+ -+; Test case 19 -+; reg0 <- limm, u6 -+; (0x00c3,0x02c5)=(0x0102,0x0304)-(0x3f,0x3f) -+ prep_test_case -+ vsub2h r0, 0x01020304, 63 -+ check_32bit_double 0x00c3, 0x02c5, r0 -+ -+; Test case 20 -+; reg1 <- reg0, 0(u6) -+; (0x0403,0x0201)=(0x0403,0x0201)-(0,0) -+ prep_test_case -+ mov r0, 0x04030201 -+ vsub2h r1, r0, 0 -+ check_32bit_double 0x0403, 0x0201, r1 -+ -+; Test case 21 -+; reg5 <- reg5, s12 -+; (66,-20415)=(1,-20480)-(-65,-65) -+ prep_test_case -+ mov r5, 0x0001b000 ; (1,-20480) -+ vsub2h r5, r5, -65 -+ check_32bit_double 66, -20415, r5 -+ -+; Test case 22 -+; 0 <- limm, s12 -+; (X,X)=(0xffee,0xddbb)-(-2048,-2048) -+ prep_test_case -+ vsub2h 0, 0xffeeddbb, -2048 -+ -+; Test case 23 -+; Testing when cc condition is met -+; (0,0)=(3,2)+(3,2) -+ prep_test_case -+ mov r1, 0x00030002 -+ mov r0, 0x80000000 ; setting... -+ add.f 0,r0,r0 ; ...V=1 -+ vsub2h.v r1, r1, r1 -+ add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. -+ check_32bit_double 0, 0, r1 -+ -+; Test case 24 -+; Testing when cc condition is not met -+; (2,0) -+ prep_test_case -+ mov r4, 0x00020000 -+ vsub2h.n r4, r4, r4 ; N=0 because of PREP_TEST_CASE -+ check_32bit_double 2, 0, r4 -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VSUB4H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case 25 -+; reg2 <- reg2, reg2 -+; (0x0000,0x0000,0x0000,0x0000)=(0x8000,0x7000,0xfffe,0xffff)- -+; (0x8000,0x7000,0xfffe,0xffff) -+; The Z flag must remain 0. -+ prep_test_case -+ mov r2, 0xfffeffff -+ mov r3, 0x80007000 -+ vsub4h r2, r2, r2 -+ check_64bit_quadruple 0, 0, 0, 0, r3, r2 -+ -+; Test case 26 -+; reg0 <- reg2, reg0 -+; (0x7fff,-2,977,0x8000)=(-1,10,1000,0x7fff)-(0x8000,12,23,-1) -+; The V and N flags must remain zero. -+ prep_test_case -+ mov r3, 0xffff000a ; (-1 , 10) -+ mov r2, 0x03e87fff ; (1000 , 0x7fff) -+ mov r1, 0x8000000c ; (0x8000, 12) -+ mov r0, 0x0017ffff ; (23 , -1) -+ vsub4h r0, r2, r0 -+ check_64bit_quadruple 0x7fff, -2, 977, 0x8000, r1, r0 -+ -+; Test case 27 -+; reg0 <- limm, reg4 -+; (0x4321,0x8765,0x90ab,0xcdef)=(0x1234,0x5678,0x1234,0x5678)- -+; (0xcf13,0xcf13,0x8189,0x8889) -+ prep_test_case -+ mov r0, 0x11111111 ; bogus data -+ mov r1, 0x22222222 ; bogus data -+ mov r5, 0xcf13cf13 -+ mov r4, 0x81898889 -+ vsub4h r0, 0x12345678, r4 -+ check_64bit_quadruple 0x4321, 0x8765, 0x90ab, 0xcdef, r1, r0 -+ -+; Test case 28 -+; reg4 <- reg2, limm -+; (-9999,-10,-9653,417)=(1,2,347,429)-(10000,12,10000,12) -+; The N flag must not be set, irrespective of having negative results. -+ prep_test_case -+ mov r3, 0x00010002 ; (1 , 2) -+ mov r2, 0x015b01ad ; (347, 429) -+ vsub4h r4, r2, 0x2710000c ; (0x2710,000c)=(10000,12) -+ check_64bit_quadruple -9999, -10, -9653, 417, r5, r4 -+ -+; Test case 29 -+; reg2 <- limm, limm (both limm should be the same) -+; (0x0000,0x0000,0x0000,0x0000)=(0x1234,0x5678,0x1234,0x5678)- -+; (0x1234,0x5678,0x1234,0x5678) -+ prep_test_case -+ vsub4h r2, 0x12345678, 0x12345678 -+ check_64bit_quadruple 0, 0, 0, 0, r3, r2 -+ -+; Test case 30 -+; reg4 <- limm, u6 -+; (0x00c3,0x02c5,0x00c3,0x02c5)=(0x0102,0x0304,0x0102,0x0304)- -+; ( 0x3f, 0x3f, 0x3f, 0x3f) -+ prep_test_case -+ vsub4h r4, 0x01020304, 63 -+ check_64bit_quadruple 0x00c3,0x02c5, 0x00c3, 0x02c5, r5, r4 -+ -+; Test case 31 -+; reg0 <- reg4, 0(u6) -+; (0x1122,0x3344,0x5566,0x7788)=(0x1122,0x3344,0x5566,0x7788)- -+; (0x0000,0x0000,0x0000,0x0000) -+ prep_test_case -+ mov r5, 0x11223344 -+ mov r4, 0x55667788 -+ vsub4h r0, r4, 0 -+ check_64bit_quadruple 0x1122, 0x3344, 0x5566, 0x7788, r1, r0 -+ -+; Test case 32 -+; reg2 <- reg2, s12 -+; (-4094,1,-2035,-2049)=(-2047,2048,12,-2)-(2047,2047,2047,2047) -+ prep_test_case -+ mov r3, 0xf8010800 -+ mov r2, 0x000cfffe ; (12, -2) -+ vsub4h r2, r2, 2047 -+ check_64bit_quadruple -4094, 1, -2035, -2049, r3, r2 -+ -+; Test case 33 -+; 0 <- limm, s12 -+; (X,X,X,X)=(0xffee,0xddbb,0xffee,0xddbb)-(-2048,-2048,-2048,-2048) -+ prep_test_case -+ vsub4h 0, 0xffeeddbb, -2048 -+ -+; Test case 34 -+; Testing when cc condition is met -+; (0,0,0,0)=(3,2,1,0)-(3,2,1,0) -+ prep_test_case -+ mov r3, 0x00030002 -+ mov r2, 0x00010000 -+ mov r4, 0x80000000 ; setting... -+ add.f 0,r4,r4 ; ...C=1 -+ vsub4h.c r2, r2, r2 -+ add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. -+ check_64bit_quadruple 0, 0, 0, 0, r3, r2 -+ -+; Test case 35 -+; Testing when cc condition is not met -+; (2,0,2,0) -+ prep_test_case -+ mov r3, 0x00020000 -+ mov r2, 0x00020000 -+ vsub4h.z r2, r2, r2 ; Z=0 because of PREP_TEST_CASE -+ check_64bit_quadruple 2, 0, 2, 0, r3, r2 -+ -+; Test case 36 -+; Raise an Illegal Instruction exception if an odd register is used. -+; Even if there is no register to save the result to. -+ prep_test_case -+ set_except_params @test_36_exception, @test_36_end -+test_36_exception: -+ .word 0x003e2b39 ; vsub4h 0, r3, r0 -+ b @fail -+test_36_end: -+ ; Fall through -+ -+; Test case 37 -+; Raise an Illegal Instruction exception if an odd register is used. -+; The exception should be made even if the CC indicates no execution. -+ prep_test_case ; (Z,N,C,V)=(0,0,0,0) -+ set_except_params @test_37_exception, @test_37_end -+test_37_exception: -+ .word 0x00072df9 ; vsub4h.v r5, r5, r0 -+ b @fail -+test_37_end: -+ ; Fall through -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+valhalla: -+ print "[PASS]" -+ b @1f -+ -+; If a test fails, it jumps here. Although, for the sake of uniformity, -+; the printed output does not say much about which test case failed, -+; one can uncomment the print_number line below or set a breakpoint -+; here to check the R0 register for the test case number. -+fail: -+ ld r0, [test_nr] -+ ;print_number r0 -+ print "[FAIL]" -+1: -+ print " vsub: vsub2 vsub2h vsub4h\n" -+ end -diff --git a/tests/tcg/arc/check_xorx.S b/tests/tcg/arc/check_xorx.S -new file mode 100644 -index 0000000000..b0f5963eac ---- /dev/null -+++ b/tests/tcg/arc/check_xorx.S -@@ -0,0 +1,32 @@ -+#***************************************************************************** -+# xor.S -+#----------------------------------------------------------------------------- -+# -+# Test xor instruction. -+# -+#define ARCTEST_ARC32 -+#include "test_macros.h" -+ -+ARCTEST_BEGIN -+ #------------------------------------------------------------- -+ # Logical tests -+ #------------------------------------------------------------- -+ -+ TEST_IMM_OP( 2, xor, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f ); -+ TEST_IMM_OP( 3, xor, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); -+ TEST_IMM_OP( 4, xor, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); -+ TEST_IMM_OP( 5, xor, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); -+ TEST_RR_3OP( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); -+ TEST_RR_3OP( 7, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); -+ TEST_RR_3OP( 8, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); -+ TEST_RR_3OP( 9, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 ); -+ -+ #------------------------------------------------------------- -+ # Source/Destination tests -+ #------------------------------------------------------------- -+ -+ TEST_IMM_SRC1_EQ_DEST( 10, xor, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f ); -+ TEST_RR_SRC1_EQ_DEST( 11, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); -+ TEST_RR_SRC2_EQ_DEST( 12, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); -+ TEST_RR_SRC12_EQ_DEST( 13, xor, 0x00000000, 0xff00ff00 ); -+ARCTEST_END -diff --git a/tests/tcg/arc/ivt.S b/tests/tcg/arc/ivt.S -new file mode 100644 -index 0000000000..39af256ed8 ---- /dev/null -+++ b/tests/tcg/arc/ivt.S -@@ -0,0 +1,38 @@ -+ .include "macros.inc" -+ -+ .section .ivt, "a", @progbits -+#define IVT_ENTRY(name) \ -+ .word name `\ -+ .weak name `\ -+ .set name, _exit_halt -+ -+; handler's name, number, name, offset in IVT (hex/dec) -+ IVT_ENTRY(main) ; 0 program entry point 0x00 0 -+ IVT_ENTRY(memory_error) ; 1 memory_error 0x04 4 -+ IVT_ENTRY(instruction_error) ; 2 instruction_error 0x08 8 -+ IVT_ENTRY(EV_MachineCheck) ; 3 EV_MachineCheck 0x0C 12 -+ IVT_ENTRY(EV_TLBMissI) ; 4 EV_TLBMissI 0x10 16 -+ IVT_ENTRY(EV_TLBMissD) ; 5 EV_TLBMissD 0x14 20 -+ IVT_ENTRY(EV_ProtV) ; 6 EV_ProtV 0x18 24 -+ IVT_ENTRY(EV_PrivilegeV) ; 7 EV_PrivilegeV 0x1C 28 -+ IVT_ENTRY(EV_SWI) ; 8 EV_SWI 0x20 32 -+ IVT_ENTRY(EV_Trap) ; 9 EV_Trap 0x24 36 -+ IVT_ENTRY(EV_Extension) ; 10 EV_Extension 0x28 40 -+ IVT_ENTRY(EV_DivZero) ; 11 EV_DivZero 0x2C 44 -+ IVT_ENTRY(EV_DCError) ; 12 EV_DCError 0x30 48 -+ IVT_ENTRY(EV_Misaligned) ; 13 EV_Misaligned 0x34 52 -+ IVT_ENTRY(EV_Ex14) ; 14 unused 0x38 56 -+ IVT_ENTRY(EV_Ex15) ; 15 unused 0x3C 60 -+ IVT_ENTRY(IRQ_Timer0) ; 16 Timer 0 0x40 64 -+ IVT_ENTRY(IRQ_Timer1) ; 17 Timer 1 0x44 68 -+ IVT_ENTRY(IRQ_18) ; 18 0x48 72 -+ IVT_ENTRY(IRQ_19) ; 19 0x4C 76 -+ IVT_ENTRY(IRQ_20) ; 20 0x50 80 -+ -+ .text -+ .global _exit_halt -+ .type _exit_halt, @function -+ .align 4 -+_exit_halt: -+ print "Fail\n" -+ end -diff --git a/tests/tcg/arc/macros.inc b/tests/tcg/arc/macros.inc -new file mode 100644 -index 0000000000..37530ecf3e ---- /dev/null -+++ b/tests/tcg/arc/macros.inc -@@ -0,0 +1,261 @@ -+.equ MAX_TESTNAME_LEN, 32 -+.macro test_name name -+ .data -+tn_\name: -+ .asciz "\name\n" -+ .space MAX_TESTNAME_LEN - (. - tn_\name), ' ' -+ .align 4 -+ .text -+ mov r30, @tn_\name -+.endm -+ -+.macro check_r2 val -+ sub.f r0, r2, \val -+ bne @1000f -+ print "[PASS] " -+ b @1001f -+1000: -+ print "[FAIL] " -+1001: -+ printl r30 -+.endm -+ -+ -+.macro start -+ .text -+ .global main -+ .align 4 -+ main: -+.endm -+ -+.macro end -+1001: -+ st 1, [POWER_DEVICE] -+ b @1001b -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+.equ OUTPUT_DEVICE, 0x90000000 ; output device address in QEMU -+.equ POWER_DEVICE, 0xF0000008 ; power management device -+ -+; macro: print -+; input: message - the string to be printed -+; regs used: r11, r12 -+; example: print "hello world\n" -+.macro print message -+ -+ .data -+ 2010: -+ .asciz "\message" -+ .align 4 -+ -+ .text -+ mov_s r11, @2010b ; the message to be printed -+ 1010: -+ ldb.ab r12, [r11, 1] -+ breq r12, 0, @1011f -+ stb r12, [OUTPUT_DEVICE] -+ j @1010b -+ 1011: -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; macro: printl -+; input: label - pointer to the string to be printed -+; regs used: r11, r12 -+; example: print @l1 -+.macro printl reg -+ -+ .text -+ mov r11, \reg ; the message to be printed -+ 3010: -+ ldb.ab r12, [r11, 1] -+ breq r12, 0, @3011f -+ stb r12, [OUTPUT_DEVICE] -+ j @3010b -+ 3011: -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; macro: print_number -+; input: number -+; regs used: r11, r12, r13, r14 -+; example: print_number 0x123 -+; print_number 11 -+; -+; description: -+; given a number, prints it to the output as a decimal string. -+.macro print_number number -+ .data -+ .align 4 -+2020: ; place holder for printed number in reverse -+ .skip 12 -+ -+ .text -+ mov r11, \number -+ mov r13, @2020b -+ mov r14, @2020b -+1020: -+ remu r12, r11, 10 -+ add_s r12, r12, 0x30 -+ stb.ab r12, [r13, 1] -+ divu r11, r11, 10 -+ brne r11, 0, @1020b -+ -+1021: -+ ldb.aw r12, [r13, -1] -+ stb r12, [0x90000000] -+ brne r13, r14, @1021b -+.endm -+ -+ -+; macro: print_number_hex -+; input: number -+; regs used: r11, r12, r13, r14 -+; example: print_number_hex 0x123 -+; print_number_hex 11 -+; -+; description: -+; given a number, prints it to the output with "0x" prefix and in -+; hexadecimal format. -+.macro print_number_hex num -+ .data -+ .align 4 -+2030: ; number printed in reverse order -+ .skip 12 -+ -+ .text -+ mov r11, \num -+ mov r13, @2030b -+ mov r14, @2030b -+1030: -+ and r12, r11, 0x0F -+ brgt r12, 9, @1031f -+ add_s r12, r12, '0' -+ j @1032f -+1031: -+ add_s r12, r12, 'W' -+1032: -+ stb.ab r12, [r13, 1] -+ lsr.f r11, r11, 4 -+ bnz @1030b -+ -+ print "0x" -+10333: -+ ldb.aw r12, [r13, -1] -+ stb r12, [OUTPUT_DEVICE] -+ brgt r13, r14, @10333b -+.endm -+ -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; macro: assert_eq -+; input: a, b - two values/registers to be compared -+; test_num - optional: printed error number, default is 1. -+; regs used: r11, r12 -+; example: assert_eq 12, r2 -+; assert_eq r1, 8 -+; assert_eq r3, r4 -+; assert_eq 8 , 9 (although useless for tests) -+; -+; description: -+; compares the two inputs. if they are equal, nothing happens. -+; but if not, then it is going to print "Ret:1" and exit. -+.macro assert_eq a, b, test_num=1 -+ mov r11, \a -+ mov r12, \b -+ breq r11, r12, @1040f -+ print "FAIL:" -+ print_number \test_num -+ end -+1040: -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Auxilary registers -+.equ REG_IRQ_SELECT, 0x40B -+ -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Exceptions -+.equ ILLEGAL_INSTRUCTION , 0x00020000 -+.equ ILLEGAL_INSTRUCTION_SEQUENCE, 0x00020100 -+.equ MACHINE_CHECK , 0x00030000 -+.equ TLB_MISS_I , 0x00040000 -+.equ TLB_MISS_D_READ , 0x00050100 -+.equ PRIVILEGE_VIOLATION , 0x00070000 -+.equ SOFTWARE_INTERRUPT , 0x00080000 -+.equ MISALIGNED_DATA_ACCESS , 0x000D0000 -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; macro: set_interrupt_prio_level -+; input: prio - number in range 0..7 -+; regs used: r11 -+; example: set_interrupt_prio_level 1 -+; -+; description: -+; sets the bits 1 to 3 of "status" register to the given priority. -+.macro set_interrupt_prio_level prio -+ lr r11, [status32] -+ asl r12, \prio -+ and r12, r12, 0xE -+ or r11, r11, r12 -+ sr r11, [status32] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; STATUS register and its masks -+.equ REG_STAT, 0x0A ; STATUS32 register -+.equ REG_IVT_BASE, 0x25 ; Interrupt vector base -+.equ REG_STAT_V, 0x0100 ; mask for Over flow bit -+.equ REG_STAT_C, 0x0200 ; mask for Carry bit -+.equ REG_STAT_N, 0x0400 ; mask for Negative bit -+.equ REG_STAT_Z, 0x0800 ; mask for Zero bit -+ -+; macro: assert_flag -+; input: reg_stat_flag - index to get the corresponding flag -+; bit - verification value: 0 or 1 -+; test_num - optional: printed error number, default -+; is 1. valid range is: [0 ... 9] -+; regs used: r11, r12 -+; example: assert_flag REG_STAT_Z, 1, num=8 -+; assert_flag 0x0200 , 0, num=3 -+; -+; description: -+; extracts the corresponding bit at given index by reg_stat_flag. -+; if it holds the same value as given 'bit', nothing happens, -+; else it will print an error and exit. -+.macro assert_flag reg_stat_flag, bit, test_num -+ lr r11, [REG_STAT] -+ and r11, r11, \reg_stat_flag -+ ; if bit=0 then checking if r11 == 0 -+ ; if bit=1 then checking if r11 == bit_mask -+ assert_eq r11, \bit*\reg_stat_flag, \test_num -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; macro: enter_user_mode -+; input: user_space - where the user code begins -+; -+; regs used: r11 -+; example: enter_user_mode @my_user_space_entry -+; -+; description: -+; this piece of code sets the user flag and jumps to given address -+.macro enter_user_mode user_space -+ lr r11, [status32] -+ or r11, r11, 0x80 ; set the STATUS32.U -+ sr r11, [erstatus] -+ mov r11, \user_space -+ sr r11, [eret] -+ rtie -+.endm -diff --git a/tests/tcg/arc/memory.x b/tests/tcg/arc/memory.x -new file mode 100644 -index 0000000000..53772484fc ---- /dev/null -+++ b/tests/tcg/arc/memory.x -@@ -0,0 +1,12 @@ -+MEMORY -+{ -+ RAM : ORIGIN = 0x00000000, LENGTH = 128M -+} -+ -+REGION_ALIAS("startup", RAM) -+REGION_ALIAS("text", RAM) -+REGION_ALIAS("data", RAM) -+REGION_ALIAS("sdata", RAM) -+ -+PROVIDE (__stack_top = (0xFFFF & -4) ); -+PROVIDE (__end_heap = (0xFFFF) ); -diff --git a/tests/tcg/arc/mmu.inc b/tests/tcg/arc/mmu.inc -new file mode 100644 -index 0000000000..c20c6e6bdd ---- /dev/null -+++ b/tests/tcg/arc/mmu.inc -@@ -0,0 +1,132 @@ -+ -+; auxilary registers -+.equ REG_PD0 , 0x460 ; TLBPD0 -+.equ REG_PD1 , 0x461 ; TLBPD1 -+.equ REG_TLB_INDX, 0x464 ; TLB index -+.equ REG_TLB_CMD , 0x465 ; TLB command -+.equ REG_PID , 0x468 ; Process Identity -+ -+; exceptions (ecr values) -+.equ PROTV_FETCH_MMU, 0x060008 -+.equ PROTV_READ_MMU , 0x060108 -+.equ PROTV_WRITE_MMU, 0x060208 -+.equ PROTV_RW_MMU , 0x060308 -+ -+; PID register bit masks -+.equ REG_PID_TLB_SET, 0x80000000 ; TLB enable bit in PID -+.equ REG_PID_TLB_CLR, ~REG_PID_TLB_SET ; TLB disable bit in PID -+ -+; bit masks related to page size -+.equ PAGE_INDEX_BITS, 13 ; page size is _assumed_ to be 8 KB -+.equ PAGE_SIZE , 1 << PAGE_INDEX_BITS -+.equ PAGE_OFFSET_MSK, PAGE_SIZE - 1 -+.equ PAGE_NUMBER_MSK, ~PAGE_OFFSET_MSK -+ -+; TLBPD0 bit masks -+.equ REG_PD0_GLOBAL, 0x100 ; Global bit -+.equ REG_PD0_VALID , 0x200 ; Valid bit -+ -+; TLBPD1 bit masks -+.equ REG_PD1_KRNL_E, 0x10 ; kernel execute -+.equ REG_PD1_KRNL_W, 0x20 ; kernel write -+.equ REG_PD1_KRNL_R, 0x40 ; kernel read -+ -+; TLB commands -+.equ TLB_CMD_WRITE , 0x01 ; write -+.equ TLB_CMD_READ , 0x02 ; read -+.equ TLB_CMD_GET_INDX, 0x03 ; get index -+.equ TLB_CMD_PROBE , 0x04 ; probe -+.equ TLB_CMD_INSERT , 0x07 ; insert -+.equ TLB_CMD_DELETE , 0x08 ; delete -+ -+ -+.macro extract_page_number address -+ (address & PAGE_NUMBER_MSK) -+.endm -+ -+ -+; macro: mmu_enable -+; regs used: r11 -+; -+; enable MMU on ARC HS systems -+.macro mmu_enable -+ lr r11, [REG_PID] -+ or r11, r11, REG_PID_TLB_SET -+ sr r11, [REG_PID] -+.endm -+ -+ -+; macro: mmu_disable -+; regs used: r11 -+; -+; disable MMU on ARC HS systems -+.macro mmu_disable -+ lr r11, [REG_PID] -+ and r11, r11, REG_PID_TLB_CLR -+ sr r11, [REG_PID] -+.endm -+ -+ -+; macro: mmu_tlb_insert -+; regs used: r11 -+; -+; inserts (TLBPD0, TLBPD1) registers as a TLB entry -+.macro mmu_tlb_insert PD0, PD1 -+ mov r11, \PD0 -+ sr r11, [REG_PD0] -+ mov r11, \PD1 -+ sr r11, [REG_PD1] -+ mov r11, TLB_CMD_INSERT -+ sr r11, [REG_TLB_CMD] -+.endm -+ -+ -+; macro: mmu_tlb_delete -+; regs used: r11 -+; -+; removes any entry with PD0 as page description -+.macro mmu_tlb_delete PD0, PD1 -+ mov r11, \PD0 -+ sr r11, [REG_PD0] -+ mov r11, \PD1 -+ sr r11, [REG_PD1] -+ mov r11, TLB_CMD_INSERT -+ sr r11, [REG_TLB_CMD] -+.endm -+; vim: set syntax=asm ts=2 sw=2 et: -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Test case counter -+.data -+mmu_test_nr: -+ .word 0x0 -+ -+; Increment the test counter -+.macro mmu_prep_test_case -+ ld r13, [mmu_test_nr] -+ add_s r13, r13, 1 ; increase test case counter -+ st r13, [mmu_test_nr] -+ mmu_disable -+ set_except_handler 0x0 -+ enable_alignment -+.endm -+ -+; Increment the test counter -+.macro mmu_prep_test_case_address -+ st pcl, [mmu_test_nr] -+.endm -+ -+; Disable alignment so there will be no Misaligned exception -+.macro disable_alignment -+ lr r11, [status32] -+ bset r11, r11, STATUS32_AD_BIT -+ flag r11 -+.endm -+ -+; Enable alignment again. -+.macro enable_alignment -+ lr r11, [status32] -+ bclr r11, r11, STATUS32_AD_BIT -+ flag r11 -+.endm -diff --git a/tests/tcg/arc/mpu.inc b/tests/tcg/arc/mpu.inc -new file mode 100644 -index 0000000000..421cd96846 ---- /dev/null -+++ b/tests/tcg/arc/mpu.inc -@@ -0,0 +1,269 @@ -+; MPU related defines and macros -+ -+ .equ REG_MPU_EN_EN , 0x40000000 ; enable bit -+ .equ REG_MPU_EN_KR , 0b100000000 ; kernel read -+ .equ REG_MPU_EN_KW , 0b010000000 ; kernel write -+ .equ REG_MPU_EN_KE , 0b001000000 ; kernel execute -+ .equ REG_MPU_EN_UR , 0b000100000 ; user read -+ .equ REG_MPU_EN_UW , 0b000010000 ; user write -+ .equ REG_MPU_EN_UE , 0b000001000 ; user execute -+ .equ REG_MPU_EN_MSK, REG_MPU_EN_EN | REG_MPU_EN_KR | REG_MPU_EN_KW | REG_MPU_EN_KE | REG_MPU_EN_UR | REG_MPU_EN_UW | REG_MPU_EN_UE -+ -+ ; full access for user ===> if a user can access, kernel can too -+ .equ REG_MPU_EN_FULL_ACCESS, REG_MPU_EN_UR | REG_MPU_EN_UW | REG_MPU_EN_UE -+ -+ .equ MPU_SIZE_32B , 0b00100 -+ .equ MPU_SIZE_64B , 0b00101 -+ .equ MPU_SIZE_128B, 0b00110 -+ .equ MPU_SIZE_256B, 0b00111 -+ .equ MPU_SIZE_512B, 0b01000 -+ .equ MPU_SIZE_1K , 0b01001 -+ .equ MPU_SIZE_2K , 0b01010 -+ .equ MPU_SIZE_4K , 0b01011 -+ .equ MPU_SIZE_8K , 0b01100 -+ .equ MPU_SIZE_16K , 0b01101 -+ .equ MPU_SIZE_32K , 0b01110 -+ .equ MPU_SIZE_64K , 0b01111 -+ .equ MPU_SIZE_128K, 0b10000 -+ .equ MPU_SIZE_256K, 0b10001 -+ .equ MPU_SIZE_512K, 0b10010 -+ .equ MPU_SIZE_1M , 0b10011 -+ .equ MPU_SIZE_2M , 0b10100 -+ .equ MPU_SIZE_4M , 0b10101 -+ .equ MPU_SIZE_8M , 0b10110 -+ .equ MPU_SIZE_16M , 0b10111 -+ .equ MPU_SIZE_32M , 0b11000 -+ .equ MPU_SIZE_64M , 0b11001 -+ .equ MPU_SIZE_128M, 0b11010 -+ .equ MPU_SIZE_256M, 0b11011 -+ .equ MPU_SIZE_512M, 0b11100 -+ .equ MPU_SIZE_1G , 0b11101 -+ .equ MPU_SIZE_2G , 0b11110 -+ .equ MPU_SIZE_4G , 0b11111 -+ -+ ; least byte is used for region -+ .equ MPU_ECR_FETCH, 0x060000 -+ .equ MPU_ECR_READ, 0x060100 -+ .equ MPU_ECR_WRITE, 0x060200 -+ .equ MPU_ECR_RW, 0x060300 -+ -+ .equ PROTV_FETCH_MPU, 0x060004 -+ .equ PROTV_READ_MPU, 0x060104 -+ .equ PROTV_WRITE_MPU, 0x060204 -+ .equ PROTV_RW_MPU, 0x060304 -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Macro: mpu_enable -+; Regs used: r11 -+; -+; Enable MPU on ARC HS systems -+; "def_access" determines the _default region_ access -+.macro mpu_enable def_access=REG_MPU_EN_FULL_ACCESS -+ mov r11, \def_access -+ or r11, r11, REG_MPU_EN_EN -+ and r11, r11, REG_MPU_EN_MSK -+ sr r11, [mpuen] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+.macro mpu_disable -+ mov r11, 0 -+ sr r11, [mpuen] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Macro: mpu_add_base -+; Regs used: r11 -+; -+; Adds the base address to the given MPU base register. -+; "reg" is the mpu base register: mpurdb0 ... mpurdb15 -+; "addr" is the base address you are interested in, e.g.: 0x4000 -+.macro mpu_add_base reg, addr -+ mov r11, \addr -+ and r11, r11, 0xffffffe0 ; the last 5 bits must be 0 -+ or r11, r11, 1 ; set valid flag -+ sr r11, [\reg] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Macro: mpu_add_region -+; Regs used: r11, r12 -+; -+; Adds the region permission and size to the given MPU permission register. -+; "reg" is the mpu permission register: mpurdp0 ... mpurdp15 -+; "access" detemines the access type -+; "size" is the region size: 00100b (32 bytes) ... 11111b (4 gigabytes) -+.macro mpu_add_region reg, access, size=0b100 -+ mov r12, \size -+ and r11, r12, 3 ; get the lower 2 bits -+ asl r12, r12, 7 ; getting the upper 3 bits in position -+ and r12, r12, 0xe00 ; keeping only bits[11:9] in place -+ or r11, r11, r12 ; r11 has the size bits now -+ or r11, r11, \access -+ sr r11, [\reg] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Macro: mpu_reset -+; Regs used: r11 -+; -+; Resets all the regions and disables MPU -+.macro mpu_reset -+ lr r12, [mpu_build] -+ and r11, r12, 0xff -+ breq r11, 0, @6666f ; no mpu? then skip! -+ mpu_disable -+ lsr r12, r12, 8 -+ brlt r12, 1, @6666f ; no region at all? then skip! -+ mov r11, 0 -+ sr r11, [mpurdb0] -+ sr r11, [mpurdp0] -+ brlt r12, 2, @6666f ; only 1 region? then skip! -+ sr r11, [mpurdb1] -+ sr r11, [mpurdp1] -+ brlt r12, 4, @6666f ; only 2 regions? then skip! -+ sr r11, [mpurdb2] -+ sr r11, [mpurdp2] -+ sr r11, [mpurdb3] -+ sr r11, [mpurdp3] -+ brlt r12, 8, @6666f ; only 4 regions? then skip! -+ sr r11, [mpurdb4] -+ sr r11, [mpurdp4] -+ sr r11, [mpurdb5] -+ sr r11, [mpurdp5] -+ sr r11, [mpurdb6] -+ sr r11, [mpurdp6] -+ sr r11, [mpurdb7] -+ sr r11, [mpurdp7] -+ brlt r12, 16, @6666f ; only 8 regions? then skip! -+ sr r11, [mpurdb8] -+ sr r11, [mpurdp8] -+ sr r11, [mpurdb9] -+ sr r11, [mpurdp9] -+ sr r11, [mpurdb10] -+ sr r11, [mpurdp10] -+ sr r11, [mpurdb11] -+ sr r11, [mpurdp11] -+ sr r11, [mpurdb12] -+ sr r11, [mpurdp12] -+ sr r11, [mpurdb13] -+ sr r11, [mpurdp13] -+ sr r11, [mpurdb14] -+ sr r11, [mpurdp14] -+ sr r11, [mpurdb15] -+ sr r11, [mpurdp15] -+6666: -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; These are the parameters that the ProtV exception routine uses as reference -+; There are tests that want to disable the R(ead) permission for the whole -+; memory layout, but they do make an exception for the parameters below. To -+; achieve that, they allow reading for a region of 32 bytes (minimum possible -+; size for a region) that these parameters reside in. Therefore, we have to -+; make sure these are the one and only things in this region by guarding them -+; with ".align 32" and nothing else. -+ .align 32 -+mpu_ecr_ref: .word 0x0 -+ecr_ref : .word 0x0 -+efa_ref : .word 0x0 -+eret_ref : .word 0x0 -+cont_addr : .word 0x0 -+ .align 32 -+ -+; Exception: Protection Violation -+; Regs used: r11, r12 -+; -+; This is a parameterized ProtV exception that will check the followings: -+; mpuic == mpu_ecr_ref -+; ecr == ecr_ref -+; efa == efa_ref -+; eret == eret_ref -+; If everything passes, it will jump to 'cont_addr' parameter. It will clear -+; the user bit before the jump, i.e. if an exception is raised in user mode, -+; the continuation after exception will be in kernel mode. If the check -+; should fail, it jumps to "fail" label which must exist in the test file. -+; The parameters must be set beforehand using 'mpu_set_except_params' macro. -+; Last but not least, this requires ivt.S file to be compiled and linked. -+ .align 4 -+ .global instruction_error -+ .global EV_PrivilegeV -+ .global EV_ProtV -+ .type instruction_error, @function -+ .type EV_PrivilegeV, @function -+ .type EV_ProtV, @function -+instruction_error: -+EV_PrivilegeV: -+EV_ProtV: -+ ld r11, [mpu_ecr_ref] -+ lr r12, [mpuic] -+ cmp r12, r11 -+ bne @fail -+ ld r11, [ecr_ref] -+ lr r12, [ecr] -+ cmp r12, r11 -+ bne @fail -+ ld r11, [eret_ref] -+ lr r12, [eret] -+ cmp r12, r11 -+ bne @fail -+ ld r11, [efa_ref] -+ lr r12, [efa] -+ cmp r12, r11 -+ bne @fail -+ ; going back to the given address in kernel mode -+ ld r11, [cont_addr] -+ sr r11, [eret] -+ lr r11, [erstatus] -+ and r11, r11, ~0x80 ; clear user mode bit -+ sr r11, [erstatus] -+ rtie -+ -+; Macro: mpu_set_except_params -+; Regs used: r11 -+; -+; This macro writes the provided parameters to a temporary place holder -+; that later will be used by ProtV exception above to verify as reference. -+.macro mpu_set_except_params mpu_ecr, ecr, efa, eret, continue -+ mov r11, \mpu_ecr -+ st r11, [mpu_ecr_ref] -+ mov r11, \ecr -+ st r11, [ecr_ref] -+ mov r11, \efa -+ st r11, [efa_ref] -+ mov r11, \eret -+ st r11, [eret_ref] -+ mov r11, \continue -+ st r11, [cont_addr] -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Macro: mpu_verify_data -+; Regs used: r11, r12 -+; -+; Reads the data at the given address and check if it holds a certain value. -+; It requires the test source file to have "fail" label. -+.macro mpu_verify_data ref, addr -+ ld r11, [\addr] -+ mov r12, \ref -+ cmp r11, r12 -+ bne @fail -+.endm -+ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ -+; Macro: mpu_write_data -+; Regs used: r11, r12 -+.macro mpu_write_data data, addr -+ mov r11, \data -+ st r11, [\addr] -+.endm -+ -+; vim: set syntax=asm ts=2 sw=2 et: -diff --git a/tests/tcg/arc/tarc.ld b/tests/tcg/arc/tarc.ld -new file mode 100644 -index 0000000000..8146162d12 ---- /dev/null -+++ b/tests/tcg/arc/tarc.ld -@@ -0,0 +1,15 @@ -+ENTRY(main) -+SECTIONS -+{ -+ .ivt 0x00 : -+ { -+ KEEP (*(.ivt)); -+ } -+ . = 0x100; -+ .text : { *(.text) } -+ .data : { *(.data) } -+ .bss : { *(.bss COMMON) } -+ . = ALIGN(8); -+ . = . + 0x1000; /* 4kB of stack memory */ -+ stack_top = .; -+} -diff --git a/tests/tcg/arc/tarc_mmu.ld b/tests/tcg/arc/tarc_mmu.ld -new file mode 100644 -index 0000000000..4112c0a927 ---- /dev/null -+++ b/tests/tcg/arc/tarc_mmu.ld -@@ -0,0 +1,15 @@ -+ENTRY(main) -+SECTIONS -+{ -+ .ivt 0x80000000 : -+ { -+ KEEP (*(.ivt)); -+ } -+ . = 0x80000100; -+ .text : { *(.text) } -+ .data : { *(.data) } -+ .bss : { *(.bss COMMON) } -+ . = ALIGN(8); -+ . = . + 0x1000; /* 4kB of stack memory */ -+ stack_top = .; -+} -diff --git a/tests/tcg/arc/test_macros.h b/tests/tcg/arc/test_macros.h -new file mode 100644 -index 0000000000..15325e1ffa ---- /dev/null -+++ b/tests/tcg/arc/test_macros.h -@@ -0,0 +1,257 @@ -+#ifndef __TEST_MACROS_SCALAR_H -+#define __TEST_MACROS_SCALAR_H -+ -+#ifdef ARCTEST_ARC32 -+#define __arc_xlen 32 -+#else -+#define __arc_xlen 64 -+#endif -+ -+#define xstr(a) str(a) -+#define str(a) #a -+ -+#define MASK_XLEN(x) ((x) & ((1 << (__arc_xlen - 1) << 1) - 1)) -+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) -+ -+#define TEST_CASE( testnum, testreg, correctval, name, code... ) \ -+ test_ ## testnum: \ -+ code` \ -+ mov r12, testnum` \ -+ sub.f 0,testreg, correctval` \ -+ bne @fail` \ -+ PASS_TEST(name) -+ -+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ -+ TEST_CASE( testnum, r0, result, xstr(inst) ":" xstr(testnum), \ -+ mov r1, MASK_XLEN(val1)` \ -+ inst r0, r1, SEXT_IMM(imm) \ -+ ) -+ -+#define TEST_RR_3OP( testnum, inst, result, val1, val2 ) \ -+ TEST_CASE( testnum, r0, result, xstr(inst) ":" xstr(testnum), \ -+ mov r1, MASK_XLEN(val1)` \ -+ mov r2, MASK_XLEN(val2)` \ -+ inst r0, r1, r2 \ -+ ) -+ -+#define TEST_RR_2OP( testnum, inst, result, val) \ -+ TEST_CASE( testnum, r0, result, xstr(inst) ":" xstr(testnum), \ -+ mov r1, MASK_XLEN(val)` \ -+ inst r0, r1 \ -+ ) -+ -+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ -+ TEST_CASE( testnum, r1, result, xstr(inst) ":" xstr(testnum), \ -+ mov r1, MASK_XLEN(val1)` \ -+ inst r1, r1, SEXT_IMM(imm) \ -+ ) -+ -+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ -+ TEST_CASE( testnum, r1, result, xstr(inst) ":" xstr(testnum), \ -+ mov r1, MASK_XLEN(val1)` \ -+ mov r2, MASK_XLEN(val2)` \ -+ inst r1, r1, r2 \ -+ ) -+ -+#define TEST_RR_2OP_SRC1_EQ_DEST( testnum, inst, result, val ) \ -+ TEST_CASE( testnum, r1, result, xstr(inst) ":" xstr(testnum), \ -+ mov r1, MASK_XLEN(val)` \ -+ inst r1, r1 \ -+ ) -+ -+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ -+ TEST_CASE( testnum, r2, result, xstr(inst) ":" xstr(testnum), \ -+ mov r1, MASK_XLEN(val1)` \ -+ mov r2, MASK_XLEN(val2)` \ -+ inst r2, r1, r2 \ -+ ) -+ -+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ -+ TEST_CASE( testnum, r1, result, xstr(inst) ":" xstr(testnum), \ -+ mov r1, MASK_XLEN(val1)` \ -+ inst r1, r1, r1 \ -+ ) -+ -+#define TEST_2OP_CARRY( testnum, inst, expected, val1, val2) \ -+ test_ ## testnum: \ -+ mov r12, testnum` \ -+ mov r1, MASK_XLEN(val1)` \ -+ mov r2, MASK_XLEN(val2)` \ -+ inst.f 0, r1, r2` \ -+ mov.cs r3,(~expected) & 0x01` \ -+ mov.cc r3, (expected) & 0x01` \ -+ cmp r3, 0` \ -+ bne @fail -+ -+#define TEST_1OP_CARRY( testnum, inst, expected, val) \ -+ test_ ## testnum: \ -+ mov r12, testnum` \ -+ add.f 0, r0, r0` \ -+ mov r1, MASK_XLEN(val)` \ -+ inst.f 0, r1` \ -+ mov.cs r3,(~expected) & 0x01` \ -+ mov.cc r3, (expected) & 0x01` \ -+ cmp r3, 0` \ -+ bne @fail -+ -+#define TEST_2OP_ZERO( testnum, inst, expected, val1, val2) \ -+ test_ ## testnum: \ -+ mov r12, testnum` \ -+ mov r1, MASK_XLEN(val1)` \ -+ mov r2, MASK_XLEN(val2)` \ -+ inst.f 0, r1, r2` \ -+ mov.eq r3, (~expected) & 0x01` \ -+ mov.ne r3, (expected) & 0x01` \ -+ cmp r3, 0` \ -+ bne @fail -+ -+#define TEST_1OP_ZERO( testnum, inst, expected, val) \ -+ test_ ## testnum: \ -+ mov r12, testnum` \ -+ add.f 0, r0, r0` \ -+ mov r1, MASK_XLEN(val)` \ -+ inst.f 0, r1` \ -+ mov.eq r3, (~expected) & 0x01` \ -+ mov.ne r3, (expected) & 0x01` \ -+ cmp r3, 0` \ -+ bne @fail -+ -+#define TEST_2OP_OVERFLOW( testnum, inst, expected, val1, val2) \ -+ test_ ## testnum: \ -+ mov r12, testnum` \ -+ mov r1, MASK_XLEN(val1)` \ -+ mov r2, MASK_XLEN(val2)` \ -+ inst.f 0, r1, r2` \ -+ mov.vs r3,(~expected) & 0x01` \ -+ mov.vc r3, (expected) & 0x01` \ -+ cmp r3, 0` \ -+ bne @fail -+ -+#define TEST_1OP_OVERFLOW( testnum, inst, expected, val) \ -+ test_ ## testnum: \ -+ mov r12, testnum` \ -+ add.f 0, r0, r0` \ -+ mov r1, MASK_XLEN(val)` \ -+ inst.f 0, r1` \ -+ mov.vs r3,(~expected) & 0x01` \ -+ mov.vc r3, (expected) & 0x01` \ -+ cmp r3, 0` \ -+ bne @fail -+ -+#define TEST_2OP_NEGATIVE( testnum, inst, expected, val1, val2) \ -+ test_ ## testnum: \ -+ mov r12, testnum` \ -+ mov r1, MASK_XLEN(val1)` \ -+ mov r2, MASK_XLEN(val2)` \ -+ inst.f 0, r1, r2` \ -+ mov.mi r3,(~expected) & 0x01` \ -+ mov.pl r3, (expected) & 0x01` \ -+ cmp r3, 0` \ -+ bne @fail -+ -+#define TEST_1OP_NEGATIVE( testnum, inst, expected, val) \ -+ test_ ## testnum: \ -+ mov r12, testnum` \ -+ add.f 0, r0, r0` \ -+ mov r1, MASK_XLEN(val)` \ -+ inst.f 0, r1` \ -+ mov.mi r3,(~expected) & 0x01` \ -+ mov.pl r3, (expected) & 0x01` \ -+ cmp r3, 0` \ -+ bne @fail -+ -+ -+#endif -+ -+#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ -+ test_ ## testnum:` \ -+ mov r12, testnum` \ -+ mov r1, val1` \ -+ mov r2, val2` \ -+ sub.f 0,r1,r2` \ -+ inst 1f` \ -+ b @fail` \ -+ 1: -+ -+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ -+ test_ ## testnum:` \ -+ mov r12,testnum` \ -+ mov r1, val1` \ -+ mov r2, val2` \ -+ sub.f 0,r1,r2` \ -+ inst @fail -+ -+#define TEST_BR_OP_TAKEN( testnum, inst, val1, val2 ) \ -+ test_ ## testnum:` \ -+ mov r12, testnum` \ -+ mov r1, val1` \ -+ mov r2, val2` \ -+ inst r1,r2,1f` \ -+ b @fail` \ -+ 1: -+ -+#define TEST_BR_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ -+ test_ ## testnum:` \ -+ mov r12,testnum` \ -+ mov r1, val1` \ -+ mov r2, val2` \ -+ inst r1,r2,@fail -+ -+#define ARCTEST_BEGIN \ -+ .text` \ -+ .align 4 ` \ -+ .global main` \ -+ main: \ -+ test_1:` \ -+ mov r12,1` \ -+ mov.f 0,0` \ -+ bne @fail -+ -+#define ARCTEST_END \ -+ .align 4 ` \ -+1:`\ -+ st 1,[0xf0000008]`\ -+ b @1b`\ -+fail:`\ -+ mov r2, '['`\ -+ st r2, [0x90000000]`\ -+ mov r2, 'F'`\ -+ st r2, [0x90000000]`\ -+ mov r2, 'a'`\ -+ st r2, [0x90000000]`\ -+ mov r2, 'i'`\ -+ st r2, [0x90000000]`\ -+ mov r2, 'l'`\ -+ st r2, [0x90000000]`\ -+ mov r2, ']'`\ -+ st r2, [0x90000000]`\ -+ mov r2, ' '`\ -+ st r2, [0x90000000]`\ -+ mov r13, r12`\ -+ mov r15, 0x30`\ -+ mov r14, r12`\ -+loop_z: `\ -+ sub.f r13, r13, 0x0A`\ -+ add.pl r15, r15, 1`\ -+ mov.pl r14, r13 `\ -+ bpl @loop_z`\ -+ st r15, [0x90000000]`\ -+ add r14, r14, 0x30`\ -+ st r14, [0x90000000]`\ -+ mov r2, '\n'`\ -+ st r2, [0x90000000]`\ -+ b 1b` -+ -+#define PASS_TEST(name)\ -+ .data ` \ -+2010:`\ -+ .ascii "[PASS] ",name ,"\n\0"` \ -+ .align 4`\ -+ .text`\ -+ mov_s r11, @2010b`\ -+ 1010:`\ -+ ldb.ab r12, [r11, 1]`\ -+ breq r12, 0, @1011f`\ -+ stb r12, [0x90000000]`\ -+ j @1010b`\ -+ 1011:` -diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh -index fa1a4261a4..7ab39da79e 100755 ---- a/tests/tcg/configure.sh -+++ b/tests/tcg/configure.sh -@@ -47,6 +47,7 @@ fi - : ${cross_cc_aarch64_be="$cross_cc_aarch64"} - : ${cross_cc_cflags_aarch64_be="-mbig-endian"} - : $(cross_cc_alpha="alpha-linux-gnu-gcc") -+: ${cross_cc_arc="arc-elf32-gcc"} - : ${cross_cc_arm="arm-linux-gnueabihf-gcc"} - : ${cross_cc_cflags_armeb="-mbig-endian"} - : ${cross_cc_hexagon="hexagon-unknown-linux-musl-clang"} -@@ -96,7 +97,7 @@ for target in $target_list; do - xtensa|xtensaeb) - arches=xtensa - ;; -- alpha|cris|hexagon|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64) -+ arc|alpha|cris|hexagon|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64) - arches=$target - ;; - *) --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0011-hw-arm-mps2-tz-Don-t-duplicate-modelling-of-SRAM-in-.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0011-hw-arm-mps2-tz-Don-t-duplicate-modelling-of-SRAM-in-.patch deleted file mode 100644 index 8c9ac2ac..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0011-hw-arm-mps2-tz-Don-t-duplicate-modelling-of-SRAM-in-.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 78ec7edffef0c0265c80d47b7716a11cf4376b32 Mon Sep 17 00:00:00 2001 -From: Peter Maydell -Date: Mon, 10 May 2021 20:08:39 +0100 -Subject: [PATCH 11/16] hw/arm/mps2-tz: Don't duplicate modelling of SRAM in - AN524 - -The SRAM at 0x2000_0000 is part of the SSE-200 itself, and we model -it that way in hw/arm/armsse.c (along with the associated MPCs). We -incorrectly also added an entry to the RAMInfo array for the AN524 in -hw/arm/mps2-tz.c, which was pointless because the CPU would never see -it. Delete it. - -The bug had no guest-visible effect because devices in the SSE-200 -take priority over those in the board model (armsse.c maps -s->board_memory at priority -2). - -Signed-off-by: Peter Maydell ---- - hw/arm/mps2-tz.c | 8 +------- - 1 file changed, 1 insertion(+), 7 deletions(-) - -diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c -index 70aa31a7f6..77ff83acb0 100644 ---- a/hw/arm/mps2-tz.c -+++ b/hw/arm/mps2-tz.c -@@ -243,19 +243,13 @@ static const RAMInfo an524_raminfo[] = { { - .size = 512 * KiB, - .mpc = 0, - .mrindex = 0, -- }, { -- .name = "sram", -- .base = 0x20000000, -- .size = 32 * 4 * KiB, -- .mpc = -1, -- .mrindex = 1, - }, { - /* We don't model QSPI flash yet; for now expose it as simple ROM */ - .name = "QSPI", - .base = 0x28000000, - .size = 8 * MiB, - .mpc = 1, -- .mrindex = 2, -+ .mrindex = 1, - .flags = IS_ROM, - }, { - .name = "DDR", --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0012-hw-arm-mps2-tz-Make-SRAM_ADDR_WIDTH-board-specific.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0012-hw-arm-mps2-tz-Make-SRAM_ADDR_WIDTH-board-specific.patch deleted file mode 100644 index 48c1ce75..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0012-hw-arm-mps2-tz-Make-SRAM_ADDR_WIDTH-board-specific.patch +++ /dev/null @@ -1,70 +0,0 @@ -From d18f61482ab637263731f3296e47ad5ea8256447 Mon Sep 17 00:00:00 2001 -From: Peter Maydell -Date: Mon, 10 May 2021 20:08:40 +0100 -Subject: [PATCH 12/16] hw/arm/mps2-tz: Make SRAM_ADDR_WIDTH board-specific - -The AN547 sets the SRAM_ADDR_WIDTH for the SSE-300 to 21; -since this is not the default value for the SSE-300, model this -in mps2-tz.c as a per-board value. - -Reported-by: Devaraj Ranganna -Signed-off-by: Peter Maydell ---- - hw/arm/mps2-tz.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c -index 77ff83acb0..f2595b1c7f 100644 ---- a/hw/arm/mps2-tz.c -+++ b/hw/arm/mps2-tz.c -@@ -123,6 +123,7 @@ struct MPS2TZMachineClass { - int numirq; /* Number of external interrupts */ - int uart_overflow_irq; /* number of the combined UART overflow IRQ */ - uint32_t init_svtor; /* init-svtor setting for SSE */ -+ uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ - const RAMInfo *raminfo; - const char *armsse_type; - }; -@@ -806,6 +807,7 @@ static void mps2tz_common_init(MachineState *machine) - OBJECT(system_memory), &error_abort); - qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); - qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); -+ qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); - qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); - qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); - sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); -@@ -1263,6 +1265,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) - mmc->numirq = 92; - mmc->uart_overflow_irq = 47; - mmc->init_svtor = 0x10000000; -+ mmc->sram_addr_width = 15; - mmc->raminfo = an505_raminfo; - mmc->armsse_type = TYPE_IOTKIT; - mps2tz_set_default_ram_info(mmc); -@@ -1290,6 +1293,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) - mmc->numirq = 92; - mmc->uart_overflow_irq = 47; - mmc->init_svtor = 0x10000000; -+ mmc->sram_addr_width = 15; - mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ - mmc->armsse_type = TYPE_SSE200; - mps2tz_set_default_ram_info(mmc); -@@ -1317,6 +1321,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) - mmc->numirq = 95; - mmc->uart_overflow_irq = 47; - mmc->init_svtor = 0x10000000; -+ mmc->sram_addr_width = 15; - mmc->raminfo = an524_raminfo; - mmc->armsse_type = TYPE_SSE200; - mps2tz_set_default_ram_info(mmc); -@@ -1349,6 +1354,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data) - mmc->numirq = 96; - mmc->uart_overflow_irq = 48; - mmc->init_svtor = 0x00000000; -+ mmc->sram_addr_width = 21; - mmc->raminfo = an547_raminfo; - mmc->armsse_type = TYPE_SSE300; - mps2tz_set_default_ram_info(mmc); --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0013-hw-arm-armsse.c-Correct-modelling-of-SSE-300-interna.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0013-hw-arm-armsse.c-Correct-modelling-of-SSE-300-interna.patch deleted file mode 100644 index 34838d89..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0013-hw-arm-armsse.c-Correct-modelling-of-SSE-300-interna.patch +++ /dev/null @@ -1,79 +0,0 @@ -From d49498231b76639cf97d6a3db7386fa94f2897c2 Mon Sep 17 00:00:00 2001 -From: Peter Maydell -Date: Mon, 10 May 2021 20:08:41 +0100 -Subject: [PATCH 13/16] hw/arm/armsse.c: Correct modelling of SSE-300 internal - SRAMs - -The SSE-300 was not correctly modelling its internal SRAMs: - * the SRAM address width default is 18 - * the SRAM is mapped at 0x2100_0000, not 0x2000_0000 like - the SSE-200 and IoTKit - -The default address width is no longer guest-visible since -our only SSE-300 board sets it explicitly to a non-default -value, but following the hardware's default will help for -any future boards we need to model. - -Reported-by: Devaraj Ranganna -Signed-off-by: Peter Maydell ---- - hw/arm/armsse.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - -diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c -index 2e5d0679e7..1729f09c7c 100644 ---- a/hw/arm/armsse.c -+++ b/hw/arm/armsse.c -@@ -59,6 +59,7 @@ struct ARMSSEInfo { - const char *cpu_type; - uint32_t sse_version; - int sram_banks; -+ uint32_t sram_bank_base; - int num_cpus; - uint32_t sys_version; - uint32_t iidr; -@@ -102,7 +103,7 @@ static Property sse300_properties[] = { - DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, - MemoryRegion *), - DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), -- DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), -+ DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 18), - DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), - DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), - DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), -@@ -504,6 +505,7 @@ static const ARMSSEInfo armsse_variants[] = { - .sse_version = ARMSSE_IOTKIT, - .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"), - .sram_banks = 1, -+ .sram_bank_base = 0x20000000, - .num_cpus = 1, - .sys_version = 0x41743, - .iidr = 0, -@@ -523,6 +525,7 @@ static const ARMSSEInfo armsse_variants[] = { - .sse_version = ARMSSE_SSE200, - .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"), - .sram_banks = 4, -+ .sram_bank_base = 0x20000000, - .num_cpus = 2, - .sys_version = 0x22041743, - .iidr = 0, -@@ -542,6 +545,7 @@ static const ARMSSEInfo armsse_variants[] = { - .sse_version = ARMSSE_SSE300, - .cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"), - .sram_banks = 2, -+ .sram_bank_base = 0x21000000, - .num_cpus = 1, - .sys_version = 0x7e00043b, - .iidr = 0x74a0043b, -@@ -1161,7 +1165,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) - /* Map the upstream end of the MPC into the right place... */ - sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); - memory_region_add_subregion(&s->container, -- 0x20000000 + i * sram_bank_size, -+ info->sram_bank_base + i * sram_bank_size, - sysbus_mmio_get_region(sbd_mpc, 1)); - /* ...and its register interface */ - memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0014-hw-arm-armsse-Convert-armsse_realize-to-use-ERRP_GUA.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0014-hw-arm-armsse-Convert-armsse_realize-to-use-ERRP_GUA.patch deleted file mode 100644 index 5b374a14..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0014-hw-arm-armsse-Convert-armsse_realize-to-use-ERRP_GUA.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 8e14fb74cfd99b30f8cb6d7ac79a0c0e9bb1895a Mon Sep 17 00:00:00 2001 -From: Peter Maydell -Date: Mon, 10 May 2021 20:08:42 +0100 -Subject: [PATCH 14/16] hw/arm/armsse: Convert armsse_realize() to use - ERRP_GUARD - -Convert armsse_realize() to use ERRP_GUARD(), following -the rules in include/qapi/error.h. - -Signed-off-by: Peter Maydell ---- - hw/arm/armsse.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c -index 1729f09c7c..be5aa1f113 100644 ---- a/hw/arm/armsse.c -+++ b/hw/arm/armsse.c -@@ -913,7 +913,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) - const ARMSSEDeviceInfo *devinfo; - int i; - MemoryRegion *mr; -- Error *err = NULL; - SysBusDevice *sbd_apb_ppc0; - SysBusDevice *sbd_secctl; - DeviceState *dev_apb_ppc0; -@@ -922,6 +921,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) - DeviceState *dev_splitter; - uint32_t addr_width_max; - -+ ERRP_GUARD(); -+ - if (!s->board_memory) { - error_setg(errp, "memory property was not set"); - return; -@@ -1151,10 +1152,9 @@ static void armsse_realize(DeviceState *dev, Error **errp) - uint32_t sram_bank_size = 1 << s->sram_addr_width; - - memory_region_init_ram(&s->sram[i], NULL, ramname, -- sram_bank_size, &err); -+ sram_bank_size, errp); - g_free(ramname); -- if (err) { -- error_propagate(errp, err); -+ if (*errp) { - return; - } - object_property_set_link(OBJECT(&s->mpc[i]), "downstream", --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0015-hw-arm-mps2-tz-Allow-board-to-specify-a-boot-RAM-siz.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0015-hw-arm-mps2-tz-Allow-board-to-specify-a-boot-RAM-siz.patch deleted file mode 100644 index 0ca3782a..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0015-hw-arm-mps2-tz-Allow-board-to-specify-a-boot-RAM-siz.patch +++ /dev/null @@ -1,83 +0,0 @@ -From cc6e0c017afd9b894f9072d49e510284731f7ca0 Mon Sep 17 00:00:00 2001 -From: Peter Maydell -Date: Mon, 10 May 2021 20:08:43 +0100 -Subject: [PATCH 15/16] hw/arm/mps2-tz: Allow board to specify a boot RAM size - -Currently we model the ITCM in the AN547's RAMInfo list. This is incorrect -because this RAM is really a part of the SSE-300. We can't just delete -it from the RAMInfo list, though, because this would make boot_ram_size() -assert because it wouldn't be able to find an entry in the list covering -guest address 0. - -Allow a board to specify a boot RAM size manually if it doesn't have -any RAM itself at address 0 and is relying on the SSE for that, and -set the correct value for the AN547. The other boards can continue -to use the "look it up from the RAMInfo list" logic. - -Signed-off-by: Peter Maydell ---- - hw/arm/mps2-tz.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c -index f2595b1c7f..8d921afec1 100644 ---- a/hw/arm/mps2-tz.c -+++ b/hw/arm/mps2-tz.c -@@ -126,6 +126,7 @@ struct MPS2TZMachineClass { - uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ - const RAMInfo *raminfo; - const char *armsse_type; -+ uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */ - }; - - struct MPS2TZMachineState { -@@ -761,6 +762,14 @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms) - const RAMInfo *p; - MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); - -+ /* -+ * Use a per-board specification (for when the boot RAM is in -+ * the SSE and so doesn't have a RAMInfo list entry) -+ */ -+ if (mmc->boot_ram_size) { -+ return mmc->boot_ram_size; -+ } -+ - for (p = mmc->raminfo; p->name; p++) { - if (p->base == boot_mem_base(mms)) { - return p->size; -@@ -1268,6 +1277,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) - mmc->sram_addr_width = 15; - mmc->raminfo = an505_raminfo; - mmc->armsse_type = TYPE_IOTKIT; -+ mmc->boot_ram_size = 0; - mps2tz_set_default_ram_info(mmc); - } - -@@ -1296,6 +1306,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) - mmc->sram_addr_width = 15; - mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ - mmc->armsse_type = TYPE_SSE200; -+ mmc->boot_ram_size = 0; - mps2tz_set_default_ram_info(mmc); - } - -@@ -1324,6 +1335,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) - mmc->sram_addr_width = 15; - mmc->raminfo = an524_raminfo; - mmc->armsse_type = TYPE_SSE200; -+ mmc->boot_ram_size = 0; - mps2tz_set_default_ram_info(mmc); - - object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); -@@ -1357,6 +1369,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data) - mmc->sram_addr_width = 21; - mmc->raminfo = an547_raminfo; - mmc->armsse_type = TYPE_SSE300; -+ mmc->boot_ram_size = 512 * KiB; - mps2tz_set_default_ram_info(mmc); - } - --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0016-hw-arm-Model-TCMs-in-the-SSE-300-not-the-AN547.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0016-hw-arm-Model-TCMs-in-the-SSE-300-not-the-AN547.patch deleted file mode 100644 index 27b08051..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0016-hw-arm-Model-TCMs-in-the-SSE-300-not-the-AN547.patch +++ /dev/null @@ -1,128 +0,0 @@ -From a0591b384231665cd4a671981f740e6f26f93a94 Mon Sep 17 00:00:00 2001 -From: Peter Maydell -Date: Mon, 10 May 2021 20:08:44 +0100 -Subject: [PATCH 16/16] hw/arm: Model TCMs in the SSE-300, not the AN547 - -The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000. -Currently we model these in the AN547 board, but this is conceptually -wrong, because they are a part of the SSE-300 itself. Move the -modelling of the TCMs out of mps2-tz.c into sse300.c. - -This has no guest-visible effects. - -Signed-off-by: Peter Maydell ---- - hw/arm/armsse.c | 19 +++++++++++++++++++ - hw/arm/mps2-tz.c | 12 ------------ - include/hw/arm/armsse.h | 2 ++ - 3 files changed, 21 insertions(+), 12 deletions(-) - -diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c -index be5aa1f113..a1456cb0f4 100644 ---- a/hw/arm/armsse.c -+++ b/hw/arm/armsse.c -@@ -13,6 +13,7 @@ - #include "qemu/log.h" - #include "qemu/module.h" - #include "qemu/bitops.h" -+#include "qemu/units.h" - #include "qapi/error.h" - #include "trace.h" - #include "hw/sysbus.h" -@@ -70,6 +71,7 @@ struct ARMSSEInfo { - bool has_cpuid; - bool has_cpu_pwrctrl; - bool has_sse_counter; -+ bool has_tcms; - Property *props; - const ARMSSEDeviceInfo *devinfo; - const bool *irq_is_common; -@@ -516,6 +518,7 @@ static const ARMSSEInfo armsse_variants[] = { - .has_cpuid = false, - .has_cpu_pwrctrl = false, - .has_sse_counter = false, -+ .has_tcms = false, - .props = iotkit_properties, - .devinfo = iotkit_devices, - .irq_is_common = sse200_irq_is_common, -@@ -536,6 +539,7 @@ static const ARMSSEInfo armsse_variants[] = { - .has_cpuid = true, - .has_cpu_pwrctrl = false, - .has_sse_counter = false, -+ .has_tcms = false, - .props = sse200_properties, - .devinfo = sse200_devices, - .irq_is_common = sse200_irq_is_common, -@@ -556,6 +560,7 @@ static const ARMSSEInfo armsse_variants[] = { - .has_cpuid = true, - .has_cpu_pwrctrl = true, - .has_sse_counter = true, -+ .has_tcms = true, - .props = sse300_properties, - .devinfo = sse300_devices, - .irq_is_common = sse300_irq_is_common, -@@ -1214,6 +1219,20 @@ static void armsse_realize(DeviceState *dev, Error **errp) - sysbus_mmio_get_region(sbd, 1)); - } - -+ if (info->has_tcms) { -+ /* The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000 */ -+ memory_region_init_ram(&s->itcm, NULL, "sse300-itcm", 512 * KiB, errp); -+ if (*errp) { -+ return; -+ } -+ memory_region_init_ram(&s->dtcm, NULL, "sse300-dtcm", 512 * KiB, errp); -+ if (*errp) { -+ return; -+ } -+ memory_region_add_subregion(&s->container, 0x00000000, &s->itcm); -+ memory_region_add_subregion(&s->container, 0x20000000, &s->dtcm); -+ } -+ - /* Devices behind APB PPC0: - * 0x40000000: timer0 - * 0x40001000: timer1 -diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c -index 8d921afec1..e23830f4b7 100644 ---- a/hw/arm/mps2-tz.c -+++ b/hw/arm/mps2-tz.c -@@ -265,23 +265,11 @@ static const RAMInfo an524_raminfo[] = { { - }; - - static const RAMInfo an547_raminfo[] = { { -- .name = "itcm", -- .base = 0x00000000, -- .size = 512 * KiB, -- .mpc = -1, -- .mrindex = 0, -- }, { - .name = "sram", - .base = 0x01000000, - .size = 2 * MiB, - .mpc = 0, - .mrindex = 1, -- }, { -- .name = "dtcm", -- .base = 0x20000000, -- .size = 4 * 128 * KiB, -- .mpc = -1, -- .mrindex = 2, - }, { - .name = "sram 2", - .base = 0x21000000, -diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h -index 36592be62c..9648e7a419 100644 ---- a/include/hw/arm/armsse.h -+++ b/include/hw/arm/armsse.h -@@ -198,6 +198,8 @@ struct ARMSSE { - MemoryRegion alias2; - MemoryRegion alias3[SSE_MAX_CPUS]; - MemoryRegion sram[MAX_SRAM_BANKS]; -+ MemoryRegion itcm; -+ MemoryRegion dtcm; - - qemu_irq *exp_irqs[SSE_MAX_CPUS]; - qemu_irq ppc0_irq; --- -2.30.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0017-target-arm-Use-correct-SP-in-M-profile-exception-ret.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0017-target-arm-Use-correct-SP-in-M-profile-exception-ret.patch deleted file mode 100644 index 6a5ebf3a..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0017-target-arm-Use-correct-SP-in-M-profile-exception-ret.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 74dc54a4de3347f8048866c635fd0c1cc0740ed4 Mon Sep 17 00:00:00 2001 -From: Peter Maydell -Date: Thu, 20 May 2021 14:09:05 +0100 -Subject: [PATCH 17/17] target/arm: Use correct SP in M-profile exception - return - -When an M-profile CPU is restoring registers from the stack on -exception return, the stack pointer to use is determined based on -bits in the magic exception return type value. We were not getting -this logic entirely correct. - -Whether we use one of the Secure stack pointers or one of the -Non-Secure stack pointers depends on the EXCRET.S bit. However, -whether we use the MSP or the PSP then depends on the SPSEL bit in -either the CONTROL_S or CONTROL_NS register. We were incorrectly -selecting MSP vs PSP based on the EXCRET.SPSEL bit. - -(In the pseudocode this is in the PopStack() function, which calls -LookUpSp_with_security_mode() which in turn looks at the relevant -CONTROL.SPSEL bit.) - -The buggy behaviour wasn't noticeable in most cases, because we write -EXCRET.SPSEL to the CONTROL.SPSEL bit for the S/NS register selected -by EXCRET.ES, so we only do the wrong thing when EXCRET.S and -EXCRET.ES are different. This will happen when secure code takes a -secure exception, which then tail-chains to a non-secure exception -which finally returns to the original secure code. - -Signed-off-by: Peter Maydell -Reviewed-by: Richard Henderson -Message-id: 20210520130905.2049-1-peter.maydell@linaro.org ---- - target/arm/m_helper.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c -index d63ae465e1..eda74e5545 100644 ---- a/target/arm/m_helper.c -+++ b/target/arm/m_helper.c -@@ -1597,10 +1597,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu) - * We use this limited C variable scope so we don't accidentally - * use 'frame_sp_p' after we do something that makes it invalid. - */ -+ bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK; - uint32_t *frame_sp_p = get_v7m_sp_ptr(env, - return_to_secure, - !return_to_handler, -- return_to_sp_process); -+ spsel); - uint32_t frameptr = *frame_sp_p; - bool pop_ok = true; - ARMMMUIdx mmu_idx; --- -2.31.1 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0018-arc-virt-Make-target-memory-size-configurable.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0018-arc-virt-Make-target-memory-size-configurable.patch deleted file mode 100644 index 654053c8..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/0018-arc-virt-Make-target-memory-size-configurable.patch +++ /dev/null @@ -1,73 +0,0 @@ -From a76ddb02f29a696dd70a251055aacf9956cd8149 Mon Sep 17 00:00:00 2001 -From: Alexey Brodkin -Date: Mon, 9 Aug 2021 06:55:54 -0700 -Subject: [PATCH] arc: virt: Make target memory size configurable - -We used to allocate entire usable 2GiB of memory for ARC's "virt" board -assuming the Linux kernel with its user-space will anyway utilize all that. - -But since then "virt" board was accommodated by Zephyr project where much -smaller apps are being executed and that huge overhead in memory -footprint started to get in the way. - -See https://github.com/zephyrproject-rtos/sdk-ng/issues/291 for example. - -With this change one may say "-m 8M" and get only 8 MiB DDR instantiated -for the simulated board. - -Still we keep the same default of 2 GiB in case no "-m" option is given. - -Signed-off-by: Alexey Brodkin ---- - hw/arc/virt.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/hw/arc/virt.c b/hw/arc/virt.c -index 5ba05b6452..e2132671f7 100644 ---- a/hw/arc/virt.c -+++ b/hw/arc/virt.c -@@ -14,6 +14,7 @@ - */ - - #include "qemu/osdep.h" -+#include "qemu/units.h" - #include "qapi/error.h" - #include "boot.h" - #include "hw/boards.h" -@@ -26,7 +27,6 @@ - #include "hw/sysbus.h" - - #define VIRT_RAM_BASE 0x80000000 --#define VIRT_RAM_SIZE 0x80000000 - #define VIRT_IO_BASE 0xf0000000 - #define VIRT_IO_SIZE 0x10000000 - #define VIRT_UART0_OFFSET 0x0 -@@ -115,7 +115,7 @@ static void virt_init(MachineState *machine) - int n; - - boot_info.ram_start = VIRT_RAM_BASE; -- boot_info.ram_size = VIRT_RAM_SIZE; -+ boot_info.ram_size = machine->ram_size; - boot_info.kernel_filename = machine->kernel_filename; - boot_info.kernel_cmdline = machine->kernel_cmdline; - -@@ -139,7 +139,7 @@ static void virt_init(MachineState *machine) - - /* Init system DDR */ - system_ram = g_new(MemoryRegion, 1); -- memory_region_init_ram(system_ram, NULL, "arc.ram", VIRT_RAM_SIZE, -+ memory_region_init_ram(system_ram, NULL, "arc.ram", machine->ram_size, - &error_fatal); - memory_region_add_subregion(system_memory, VIRT_RAM_BASE, system_ram); - -@@ -175,6 +175,7 @@ static void virt_machine_init(MachineClass *mc) - mc->init = virt_init; - mc->max_cpus = 1; - mc->is_default = true; -+ mc->default_ram_size = 2 * GiB; - } - - DEFINE_MACHINE("virt", virt_machine_init) --- -2.16.2 - diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/cross.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/cross.patch index e118b6e8..fd6d4268 100644 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/cross.patch +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/cross.patch @@ -10,21 +10,21 @@ Index: qemu/configure =================================================================== --- a/configure +++ b/configure -@@ -6345,7 +6345,6 @@ if has $sdl2_config; then - fi - echo "strip = [$(meson_quote $strip)]" >> $cross - echo "windres = [$(meson_quote $windres)]" >> $cross --if test "$cross_compile" = "yes"; then +@@ -3932,7 +3932,6 @@ if test "$skip_meson" = no; then + fi + echo "strip = [$(meson_quote $strip)]" >> $cross + echo "windres = [$(meson_quote $windres)]" >> $cross +- if test "$cross_compile" = "yes"; then cross_arg="--cross-file config-meson.cross" echo "[host_machine]" >> $cross if test "$mingw32" = "yes" ; then -@@ -6377,9 +6376,6 @@ if test "$cross_compile" = "yes"; then +@@ -3964,9 +3963,6 @@ if test "$skip_meson" = no; then else echo "endian = 'little'" >> $cross fi --else +- else - cross_arg="--native-file config-meson.cross" --fi - mv $cross config-meson.cross - - rm -rf meson-private meson-info meson-logs +- fi + mv $cross config-meson.cross + + rm -rf meson-private meson-info meson-logs diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/zephyr-qemu_git.bb b/meta-zephyr-sdk/recipes-devtools/qemu/zephyr-qemu_git.bb index 2138f2b3..b3c0a029 100644 --- a/meta-zephyr-sdk/recipes-devtools/qemu/zephyr-qemu_git.bb +++ b/meta-zephyr-sdk/recipes-devtools/qemu/zephyr-qemu_git.bb @@ -1,33 +1,15 @@ -DEPENDS = "glib-2.0 zlib pixman gnutls dtc ninja-native meson-native" +DEPENDS = "glib-2.0 zlib pixman gnutls libtasn1 dtc ninja-native meson-native" LICENSE = "GPLv2" FILESEXTRAPATHS_prepend := "${THISDIR}/files:" LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" -SRCREV = "609d7596524ab204ccd71ef42c9eee4c7c338ea4" -SRC_URI = "git://github.com/qemu/qemu.git;protocol=https \ +SRCREV = "59f1efa351fefd631650a9a49da64fa082103ac2" +SRC_URI = "git://github.com/zephyrproject-rtos/qemu.git;protocol=https;nobranch=1 \ https://github.com/zephyrproject-rtos/seabios/releases/download/zephyr-v1.0.0/bios-128k.bin;name=bios-128k \ https://github.com/zephyrproject-rtos/seabios/releases/download/zephyr-v1.0.0/bios-256k.bin;name=bios-256k \ file://cross.patch \ - file://0001-hw-misc-mps2-scc-Add-QEMU-interface-comment.patch \ - file://0002-hw-misc-mps2-scc-Support-using-CFG0-bit-0-for-remapp.patch \ - file://0003-hw-arm-mps2-tz-Implement-AN524-memory-remapping-via-.patch \ - file://0004-qemu-nios2-Add-Altera-MAX-10-board-support-for-Zephy.patch \ - file://0005-hw-sparc-Add-leon-at697-machine.patch \ - file://0006-hw-sparc-leon-Fix-compilation-errors.patch \ - file://0007-hw-sparc-leon-timer-Call-leon_timer_io_read-for-TIME.patch \ - file://0008-hw-sparc-leon-Switch-to-transaction-based-ptimer-API.patch \ - file://0009-hw-sparc-leon-Fix-compilation-errors-with-qemu-6-cha.patch \ - file://0010-Add-ARC-support.patch \ - file://0011-hw-arm-mps2-tz-Don-t-duplicate-modelling-of-SRAM-in-.patch \ - file://0012-hw-arm-mps2-tz-Make-SRAM_ADDR_WIDTH-board-specific.patch \ - file://0013-hw-arm-armsse.c-Correct-modelling-of-SSE-300-interna.patch \ - file://0014-hw-arm-armsse-Convert-armsse_realize-to-use-ERRP_GUA.patch \ - file://0015-hw-arm-mps2-tz-Allow-board-to-specify-a-boot-RAM-siz.patch \ - file://0016-hw-arm-Model-TCMs-in-the-SSE-300-not-the-AN547.patch \ - file://0017-target-arm-Use-correct-SP-in-M-profile-exception-ret.patch \ - file://0018-arc-virt-Make-target-memory-size-configurable.patch \ " SRC_URI[bios-128k.sha256sum] = "943c077c3925ee7ec85601fb12937a0988c478a95523a628cd7e61c639dd6e81" @@ -216,13 +198,13 @@ inherit autotools pkgconfig #--disable-blobs : BIOS needed for x86 #--disable-fdt: Cannot use if supporting ARM -QEMUS_BUILT = "aarch64-softmmu arm-softmmu i386-softmmu mips-softmmu mipsel-softmmu nios2-softmmu xtensa-softmmu riscv32-softmmu riscv64-softmmu sparc-softmmu x86_64-softmmu arc-softmmu arc64-softmmu" +QEMUS_BUILT = "aarch64-softmmu arm-softmmu i386-softmmu mips-softmmu mipsel-softmmu nios2-softmmu xtensa-softmmu riscv32-softmmu riscv64-softmmu sparc-softmmu x86_64-softmmu" QEMU_FLAGS = "--disable-docs --disable-sdl --disable-debug-info --disable-cap-ng \ --disable-libnfs --disable-libusb --disable-libiscsi --disable-usb-redir --disable-linux-aio\ --disable-guest-agent --disable-libssh --disable-vnc-png --disable-seccomp \ --disable-tpm --disable-numa --disable-glusterfs \ --disable-virtfs --disable-xen --disable-curl --disable-attr --disable-curses --disable-iconv \ - --disable-kvm --disable-sheepdog --disable-parallels --disable-replication \ + --disable-kvm --disable-parallels --disable-replication \ --disable-live-block-migration --disable-dmg \ " @@ -242,8 +224,13 @@ do_configure() { } do_install_append() { + # Link Xilinx QEMU executables ln -sf ../xilinx/bin/qemu-system-aarch64 ${D}${bindir}/qemu-system-xilinx-aarch64 ln -sf ../xilinx/bin/qemu-system-microblazeel ${D}${bindir}/qemu-system-xilinx-microblazeel + + # Link ARC (Synopsys) QEMU executables + ln -sf ../synopsys/bin/qemu-system-arc ${D}${bindir}/qemu-system-arc + ln -sf ../synopsys/bin/qemu-system-arc64 ${D}${bindir}/qemu-system-arc64 } FILES_${PN} = " \ diff --git a/meta-zephyr-sdk/recipes-hosttools/hosttools/hosttools-tarball.bb b/meta-zephyr-sdk/recipes-hosttools/hosttools/hosttools-tarball.bb index 395cf613..396251dc 100644 --- a/meta-zephyr-sdk/recipes-hosttools/hosttools/hosttools-tarball.bb +++ b/meta-zephyr-sdk/recipes-hosttools/hosttools/hosttools-tarball.bb @@ -6,6 +6,7 @@ LIC_FILES_CHKSUM = "file://${COREBASE}/meta/COPYING.MIT;md5=3da9cfbcb788c80a0384 TOOLCHAIN_TARGET_TASK ?= "" TOOLCHAIN_HOST_TASK ?= "\ + nativesdk-arc-qemu \ nativesdk-zephyr-qemu \ nativesdk-xilinx-qemu \ nativesdk-openocd \ diff --git a/release-notes.md b/release-notes.md index 3c6b2cd9..3ffef173 100644 --- a/release-notes.md +++ b/release-notes.md @@ -1,5 +1,10 @@ # Notes / Changes in various releases +## Zephyr SDK 0.14.1 + +- qemu: + * Updated to QEMU 6.2 release. + ## Zephyr SDK 0.14.0 - general: