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riscv: make core code 64-bit compatible

There are two aspects to this: CPU registers are twice as big, and the
load and store instructions must use the 'd' suffix instead of the 'w'
one. To abstract register differences, we simply use a ulong_t instead
of u32_t given that RISC-V is either ILP32 or LP64. And the relevant
lw/sw instructions are replaced by LR/SR (load/store register) that get
defined as either lw/sw or ld/sd. Finally a few constants to deal with
register offsets are also provided.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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Nicolas Pitre authored and andrewboie committed Jul 24, 2019
1 parent 1f4b5dd commit 0440a815a91b83bdb27e272b9770f558c1b8975c
@@ -13,25 +13,25 @@ FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
const z_arch_esf_t *esf)
{
if (esf != NULL) {
z_fatal_print("Faulting instruction address = 0x%08x",
z_fatal_print("Faulting instruction address = 0x%08lx",
esf->mepc);
z_fatal_print(" ra: 0x%08x gp: 0x%08x tp: 0x%08x t0: 0x%08x",
z_fatal_print(" ra: 0x%08lx gp: 0x%08lx tp: 0x%08lx t0: 0x%08lx",
esf->ra, esf->gp, esf->tp, esf->t0);
z_fatal_print(" t1: 0x%08x t2: 0x%08x t3: 0x%08x t4: 0x%08x",
z_fatal_print(" t1: 0x%08lx t2: 0x%08lx t3: 0x%08lx t4: 0x%08lx",
esf->t1, esf->t2, esf->t3, esf->t4);
z_fatal_print(" t5: 0x%08x t6: 0x%08x a0: 0x%08x a1: 0x%08x",
z_fatal_print(" t5: 0x%08lx t6: 0x%08lx a0: 0x%08lx a1: 0x%08lx",
esf->t5, esf->t6, esf->a0, esf->a1);
z_fatal_print(" a2: 0x%08x a3: 0x%08x a4: 0x%08x a5: 0x%08x",
z_fatal_print(" a2: 0x%08lx a3: 0x%08lx a4: 0x%08lx a5: 0x%08lx",
esf->a2, esf->a3, esf->a4, esf->a5);
z_fatal_print(" a6: 0x%08x a7: 0x%08x\n",
z_fatal_print(" a6: 0x%08lx a7: 0x%08lx\n",
esf->a6, esf->a7);
}

z_fatal_error(reason, esf);
CODE_UNREACHABLE;
}

static char *cause_str(u32_t cause)
static char *cause_str(ulong_t cause)
{
switch (cause) {
case 0:
@@ -53,13 +53,12 @@ static char *cause_str(u32_t cause)

FUNC_NORETURN void _Fault(const z_arch_esf_t *esf)
{
u32_t mcause;
ulong_t mcause;

__asm__ volatile("csrr %0, mcause" : "=r" (mcause));

mcause &= SOC_MCAUSE_EXP_MASK;
z_fatal_print("Exception cause %s (%d)", cause_str(mcause),
(int)mcause);
z_fatal_print("Exception cause %s (%ld)", cause_str(mcause), mcause);

z_riscv_fatal_error(K_ERR_CPU_EXCEPTION, esf);
}
@@ -9,15 +9,15 @@

FUNC_NORETURN void z_irq_spurious(void *unused)
{
u32_t mcause;
ulong_t mcause;

ARG_UNUSED(unused);

__asm__ volatile("csrr %0, mcause" : "=r" (mcause));

mcause &= SOC_MCAUSE_EXP_MASK;

z_fatal_print("Spurious interrupt detected! IRQ: %d", (int)mcause);
z_fatal_print("Spurious interrupt detected! IRQ: %ld", mcause);
#if defined(CONFIG_RISCV_HAS_PLIC)
if (mcause == RISCV_MACHINE_EXT_IRQ) {
z_fatal_print("PLIC interrupt line causing the IRQ: %d",

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