Please sign in to comment.
riscv: make core code 64-bit compatible
There are two aspects to this: CPU registers are twice as big, and the load and store instructions must use the 'd' suffix instead of the 'w' one. To abstract register differences, we simply use a ulong_t instead of u32_t given that RISC-V is either ILP32 or LP64. And the relevant lw/sw instructions are replaced by LR/SR (load/store register) that get defined as either lw/sw or ld/sd. Finally a few constants to deal with register offsets are also provided. Signed-off-by: Nicolas Pitre <email@example.com>
- Loading branch information...
Showing with 235 additions and 213 deletions.
- +9 −10 arch/riscv/core/fatal.c
- +2 −2 arch/riscv/core/irq_manage.c
- +121 −121 arch/riscv/core/isr.S
- +37 −37 arch/riscv/core/swap.S
- +7 −7 arch/riscv/core/thread.c
- +14 −14 arch/riscv/include/kernel_arch_thread.h
- +15 −2 include/arch/riscv/arch.h
- +20 −20 include/arch/riscv/exp.h
- +3 −0 include/zephyr/types.h
- +7 −0 soc/riscv/riscv-privilege/common/soc_common.h
Oops, something went wrong.