Skip to content
Permalink
Browse files

logging: log_backend_swo: Get clock frequency from DTS

The log_backend_swo used system clock frequency
as a base for SWO clock calculation. This commit
corrects that by obtaining the needed value from DTS.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
  • Loading branch information...
pizi-nordic authored and carlescufi committed Apr 11, 2019
1 parent 0509d06 commit 09b64467a9a1c7a839249bbf89474cfc8f64873f
@@ -9,6 +9,7 @@
/* SoC level DTS fixup file */

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY

#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL
@@ -7,6 +7,7 @@
/* SoC level DTS fixup file */

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY

#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
@@ -9,6 +9,7 @@
/* SoC level DTS fixup file */

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY

#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL
@@ -9,6 +9,7 @@
/* SoC level DTS fixup file */

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY

#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
@@ -9,6 +9,7 @@
/* SoC level DTS fixup file */

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY

#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
@@ -18,8 +18,8 @@
* this frequency should much the one set by the SWO viewer program.
*
* The initialization code assumes that SWO core frequency is equal to HCLK
* as defined by SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option. This may require
* additional, vendor specific configuration.
* as defined by DT_CPU_CLOCK_FREQUENCY. This may require additional,
* vendor specific configuration.
*/

#include <logging/log_backend.h>
@@ -36,13 +36,12 @@
#if CONFIG_LOG_BACKEND_SWO_FREQ_HZ == 0
#define SWO_FREQ_DIV 1
#else
#define SWO_FREQ (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
+ (CONFIG_LOG_BACKEND_SWO_FREQ_HZ / 2))
#define SWO_FREQ (DT_CPU_CLOCK_FREQUENCY + (CONFIG_LOG_BACKEND_SWO_FREQ_HZ / 2))
#define SWO_FREQ_DIV (SWO_FREQ / CONFIG_LOG_BACKEND_SWO_FREQ_HZ)
#if SWO_FREQ_DIV > 0xFFFF
#error CONFIG_LOG_BACKEND_SWO_FREQ_HZ is too low. SWO clock divider is 16-bit. \
Minimum supported SWO clock frequency is \
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC/2^16.
[CPU Clock Frequency]/2^16.
#endif
#endif

0 comments on commit 09b6446

Please sign in to comment.
You can’t perform that action at this time.