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soc: stm32h7: Add support for Cortex-M4 core

Add support for C-M4 core on STM32H7 series.
It is enabled in Dual core context with 2 alternatives boot methods:
* Boot CM4 CM7: Both core boot at reset, then CM4 enters Stop mode.
CM7 performs system configuration then finally wakes up CM4
* Boot CM7, CM4 Gated: Only CM7 boots at reset. Once done with
system configuration it triggers (requires option byte update)

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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erwango authored and nashif committed Jul 1, 2019
1 parent afcb1ae commit 141b6500c9c1c89a652917a47b69390e2c6f9a71
@@ -3,3 +3,4 @@
zephyr_include_directories(${ZEPHYR_BASE}/drivers)

zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c)
zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M4 soc_m4.c)
@@ -13,5 +13,33 @@ config SOC_SERIES_STM32H7X
select CPU_HAS_ARM_MPU
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
select NEWLIB_LIBC
select USE_STM32_HAL_RCC_EX if CPU_CORTEX_M4
help
Enable support for STM32H7 MCU series

config STM32H7_DUAL_CORE
bool "Enable Dual Core"
depends on SOC_SERIES_STM32H7X

choice STM32H7_DUAL_CORE_BOOT
prompt "STM32H7x Boot type selection"
depends on STM32H7_DUAL_CORE

config STM32H7_BOOT_CM4_CM7
bool "Boot both CM4 and CM7"
help
Cortex-M7 and Cortex-M4 running from the flash (each from a bank)
System configuration performed by the Cortex-M7
Cortex-M4 goes to STOP after boot, then woken-up by Cortex-M7 using
a HW semaphore

config STM32H7_BOOT_CM7_CM4GATED
bool "Boot CM7. CM4 boot gated"
help
Cortex-M4 boot is gated using Flash option bytes
Cortex-M7 and Cortex-M4 running from the flash (each from a bank)
Cortex-M7 boots , performs the System configuration then enable the
Cortex-M4 boot using RCC.
This mode requires option byte setting update (BCM4 uncheked)

endchoice
@@ -17,6 +17,23 @@
*/
#include <kernel_includes.h>

#ifdef CONFIG_STM32H7_DUAL_CORE

#define LL_HSEM_ID_0 (0U) /* HW semaphore 0 */
#define LL_HSEM_MASK_0 (1 << LL_HSEM_ID_0)

#include <stm32h7xx_ll_hsem.h>

#ifdef CONFIG_CPU_CORTEX_M4

#include <stm32h7xx_ll_bus.h>
#include <stm32h7xx_ll_pwr.h>
#include <stm32h7xx_ll_cortex.h>

#endif /* CONFIG_CPU_CORTEX_M4 */

#endif /* CONFIG_STM32H7_DUAL_CORE */

#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#include <stm32h7xx_ll_bus.h>
#include <stm32h7xx_ll_rcc.h>
@@ -0,0 +1,92 @@
/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/

/**
* @file
* @brief System/hardware module for STM32H7 CM4 processor
*/

#include <kernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <arch/cpu.h>
#include <cortex_m/exc.h>

#if defined(CONFIG_STM32H7_BOOT_CM4_CM7)
void stm32h7_m4_boot_stop(void)
{
/*
* Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for
* Cortex-M7 to perform system initialization (system clock config,
* external memory configuration.. )
*/

/* Clear pending events if any */
__SEV();
__WFE();

/* Select the domain Power Down DeepSleep */
LL_PWR_SetRegulModeDS(LL_PWR_REGU_DSMODE_MAIN);
/* Keep DSTOP mode when D2 domain enters Deepsleep */
LL_PWR_CPU_SetD2PowerMode(LL_PWR_CPU_MODE_D2STOP);
LL_PWR_CPU2_SetD2PowerMode(LL_PWR_CPU2_MODE_D2STOP);
/* Set SLEEPDEEP bit of Cortex System Control Register */
LL_LPM_EnableDeepSleep();

/* Ensure that all instructions done before entering STOP mode */
__DSB();
__ISB();
/* Request Wait For Event */
__WFE();

/* Reset SLEEPDEEP bit of Cortex System Control Register,
* the following LL API Clear SLEEPDEEP bit of Cortex
* System Control Register
*/
LL_LPM_EnableSleep();
}
#endif /* CONFIG_STM32H7_BOOT_CM4_CM7 */

/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int stm32h7_m4_init(struct device *arg)
{
u32_t key;

key = irq_lock();

/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();

irq_unlock(key);

/*HW semaphore Clock enable*/
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);

#if defined(CONFIG_STM32H7_BOOT_CM4_CM7)
/* Activate HSEM notification for Cortex-M4*/
LL_HSEM_EnableIT_C2IER(HSEM, LL_HSEM_MASK_0);

/* Boot and enter stop mode */
stm32h7_m4_boot_stop();

/* Clear HSEM flag */
LL_HSEM_ClearFlag_C2ICR(HSEM, LL_HSEM_MASK_0);
#endif /* CONFIG_STM32H7_BOOT_CM4_CM7 */

return 0;
}

SYS_INIT(stm32h7_m4_init, PRE_KERNEL_1, 0);
@@ -16,6 +16,41 @@
#include <arch/cpu.h>
#include <cortex_m/exc.h>

#if defined(CONFIG_STM32H7_DUAL_CORE)
static int stm32h7_m4_wakeup(struct device *arg)
{

/*HW semaphore Clock enable*/
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);

if (IS_ENABLED(CONFIG_STM32H7_BOOT_CM4_CM7)) {
u32_t timeout;

/*
* When system initialization is finished, Cortex-M7 will
* release Cortex-M4 by means of HSEM notification
*/

/*Take HSEM */
LL_HSEM_1StepLock(HSEM, LL_HSEM_ID_0);
/*Release HSEM in order to notify the CPU2(CM4)*/
LL_HSEM_ReleaseLock(HSEM, LL_HSEM_ID_0, 0);

/* wait until CPU2 wakes up from stop mode */
timeout = 0xFFFF;
while ((LL_RCC_D2CK_IsReady() == 0) && ((timeout--) > 0)) {
}
if (timeout < 0) {
return -EIO;
}
} else if (IS_ENABLED(CONFIG_STM32H7_BOOT_CM7_CM4GATED)) {
/* Start CM4 */
LL_RCC_ForceCM4Boot();
}

return 0;
}
#endif /* CONFIG_STM32H7_DUAL_CORE */

/**
* @brief Perform basic hardware initialization at boot.
@@ -55,3 +90,8 @@ static int stm32h7_init(struct device *arg)

SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);


#if defined(CONFIG_STM32H7_DUAL_CORE)
/* Unlock M4 once system configuration has been done */
SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
#endif /* CONFIG_STM32H7_DUAL_CORE */

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