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riscv32: rename to riscv

With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
  • Loading branch information...
Nicolas Pitre authored and andrewboie committed Jul 17, 2019
1 parent 48b4ad4 commit 1f4b5ddd0fa84f828213fe1200917bad480bce7b
Showing with 125 additions and 118 deletions.
  1. +10 −8 CODEOWNERS
  2. +2 −2 arch/Kconfig
  3. 0 arch/{riscv32 → riscv}/CMakeLists.txt
  4. +4 −3 arch/{riscv32 → riscv}/Kconfig
  5. 0 arch/{riscv32 → riscv}/core/CMakeLists.txt
  6. 0 arch/{riscv32 → riscv}/core/cpu_idle.c
  7. +3 −3 arch/{riscv32 → riscv}/core/fatal.c
  8. +1 −1 arch/{riscv32 → riscv}/core/irq_manage.c
  9. 0 arch/{riscv32 → riscv}/core/irq_offload.c
  10. 0 arch/{riscv32 → riscv}/core/isr.S
  11. 0 arch/{riscv32 → riscv}/core/offsets/offsets.c
  12. 0 arch/{riscv32 → riscv}/core/prep_c.c
  13. 0 arch/{riscv32 → riscv}/core/reset.S
  14. 0 arch/{riscv32 → riscv}/core/swap.S
  15. 0 arch/{riscv32 → riscv}/core/thread.c
  16. +4 −4 arch/{riscv32 → riscv}/include/kernel_arch_data.h
  17. +6 −6 arch/{riscv32 → riscv}/include/kernel_arch_func.h
  18. +3 −4 arch/{riscv32 → riscv}/include/kernel_arch_thread.h
  19. +3 −3 arch/{riscv32 → riscv}/include/offsets_short_arch.h
  20. +1 −1 boards/index.rst
  21. 0 boards/{riscv32 → riscv}/hifive1/CMakeLists.txt
  22. 0 boards/{riscv32 → riscv}/hifive1/Kconfig.board
  23. 0 boards/{riscv32 → riscv}/hifive1/Kconfig.defconfig
  24. 0 boards/{riscv32 → riscv}/hifive1/board.cmake
  25. +0 −1 boards/{riscv32 → riscv}/hifive1/doc/index.rst
  26. +0 −1 boards/{riscv32 → riscv}/hifive1/hifive1.dts
  27. 0 boards/{riscv32 → riscv}/hifive1/hifive1.yaml
  28. +1 −1 boards/{riscv32 → riscv}/hifive1/hifive1_defconfig
  29. 0 boards/{riscv32 → riscv}/hifive1/pinmux.c
  30. 0 boards/{riscv32 → riscv}/hifive1/support/openocd.cfg
  31. 0 boards/{riscv32 → riscv}/hifive1_revb/CMakeLists.txt
  32. 0 boards/{riscv32 → riscv}/hifive1_revb/Kconfig.board
  33. 0 boards/{riscv32 → riscv}/hifive1_revb/Kconfig.defconfig
  34. 0 boards/{riscv32 → riscv}/hifive1_revb/board.cmake
  35. +0 −1 boards/{riscv32 → riscv}/hifive1_revb/doc/index.rst
  36. +0 −1 boards/{riscv32 → riscv}/hifive1_revb/hifive1_revb.dts
  37. 0 boards/{riscv32 → riscv}/hifive1_revb/hifive1_revb.yaml
  38. +1 −1 boards/{riscv32 → riscv}/hifive1_revb/hifive1_revb_defconfig
  39. 0 boards/{riscv32 → riscv}/hifive1_revb/pinmux.c
  40. +2 −2 boards/{riscv32 → riscv}/index.rst
  41. 0 boards/{riscv32 → riscv}/litex_vexriscv/CMakeLists.txt
  42. 0 boards/{riscv32 → riscv}/litex_vexriscv/Kconfig.board
  43. 0 boards/{riscv32 → riscv}/litex_vexriscv/Kconfig.defconfig
  44. 0 boards/{riscv32 → riscv}/litex_vexriscv/doc/litex_vexriscv.rst
  45. 0 boards/{riscv32 → riscv}/litex_vexriscv/litex_vexriscv.dts
  46. 0 boards/{riscv32 → riscv}/litex_vexriscv/litex_vexriscv.yaml
  47. +1 −1 boards/{riscv32 → riscv}/litex_vexriscv/litex_vexriscv_defconfig
  48. 0 boards/{riscv32 → riscv}/m2gl025_miv/CMakeLists.txt
  49. 0 boards/{riscv32 → riscv}/m2gl025_miv/Kconfig.board
  50. 0 boards/{riscv32 → riscv}/m2gl025_miv/Kconfig.defconfig
  51. 0 boards/{riscv32 → riscv}/m2gl025_miv/board.cmake
  52. +0 −1 boards/{riscv32 → riscv}/m2gl025_miv/doc/index.rst
  53. 0 boards/{riscv32 → riscv}/m2gl025_miv/m2gl025_miv.dts
  54. 0 boards/{riscv32 → riscv}/m2gl025_miv/m2gl025_miv.yaml
  55. +1 −1 boards/{riscv32 → riscv}/m2gl025_miv/m2gl025_miv_defconfig
  56. 0 boards/{riscv32 → riscv}/m2gl025_miv/support/m2gl025_miv.resc
  57. 0 boards/{riscv32 → riscv}/qemu_riscv32/Kconfig.board
  58. 0 boards/{riscv32 → riscv}/qemu_riscv32/Kconfig.defconfig
  59. +1 −0 boards/{riscv32 → riscv}/qemu_riscv32/board.cmake
  60. 0 boards/{riscv32 → riscv}/qemu_riscv32/doc/index.rst
  61. BIN boards/{riscv32 → riscv}/qemu_riscv32/doc/qemu_riscv32.png
  62. +0 −1 boards/{riscv32 → riscv}/qemu_riscv32/qemu_riscv32.dts
  63. 0 boards/{riscv32 → riscv}/qemu_riscv32/qemu_riscv32.yaml
  64. +1 −1 boards/{riscv32 → riscv}/qemu_riscv32/qemu_riscv32_defconfig
  65. 0 boards/{riscv32 → riscv}/rv32m1_vega/CMakeLists.txt
  66. 0 boards/{riscv32 → riscv}/rv32m1_vega/Kconfig.board
  67. 0 boards/{riscv32 → riscv}/rv32m1_vega/Kconfig.defconfig
  68. 0 boards/{riscv32 → riscv}/rv32m1_vega/board.cmake
  69. 0 boards/{riscv32 → riscv}/rv32m1_vega/doc/index.rst
  70. BIN boards/{riscv32 → riscv}/rv32m1_vega/doc/ri5cy_boot.jpg
  71. BIN boards/{riscv32 → riscv}/rv32m1_vega/doc/rv32m1_vega.png
  72. BIN boards/{riscv32 → riscv}/rv32m1_vega/doc/rv32m1_vega_jtag.jpg
  73. 0 boards/{riscv32 → riscv}/rv32m1_vega/pinmux.c
  74. 0 boards/{riscv32 → riscv}/rv32m1_vega/rv32m1_vega.dtsi
  75. 0 boards/{riscv32 → riscv}/rv32m1_vega/rv32m1_vega_ri5cy.dts
  76. 0 boards/{riscv32 → riscv}/rv32m1_vega/rv32m1_vega_ri5cy.yaml
  77. +1 −1 boards/{riscv32 → riscv}/rv32m1_vega/rv32m1_vega_ri5cy_defconfig
  78. 0 boards/{riscv32 → riscv}/rv32m1_vega/rv32m1_vega_zero_riscy.dts
  79. 0 boards/{riscv32 → riscv}/rv32m1_vega/rv32m1_vega_zero_riscy.yaml
  80. +1 −1 boards/{riscv32 → riscv}/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig
  81. 0 boards/{riscv32 → riscv}/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
  82. 0 boards/{riscv32 → riscv}/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg
  83. +1 −1 cmake/toolchain/xtools/target.cmake
  84. +1 −1 cmake/toolchain/zephyr/0.10.0/target.cmake
  85. +1 −1 cmake/toolchain/zephyr/0.10.1/target.cmake
  86. +12 −4 doc/conf.py
  87. +1 −1 drivers/interrupt_controller/plic.c
  88. 0 dts/{riscv32 → riscv}/microsemi-miv.dtsi
  89. 0 dts/{riscv32 → riscv}/riscv32-fe310.dtsi
  90. 0 dts/{riscv32 → riscv}/riscv32-litex-vexriscv.dtsi
  91. 0 dts/{riscv32 → riscv}/rv32m1.dtsi
  92. +1 −1 dts/{riscv32 → riscv}/rv32m1_ri5cy.dtsi
  93. +1 −1 dts/{riscv32 → riscv}/rv32m1_zero_riscy.dtsi
  94. +2 −2 include/arch/cpu.h
  95. +6 −6 include/arch/{riscv32 → riscv}/arch.h
  96. +1 −1 include/arch/{riscv32 → riscv}/common/linker.ld
  97. +5 −5 include/arch/{riscv32 → riscv}/exp.h
  98. +4 −4 include/arch/{riscv32 → riscv}/riscv-privilege/asm_inline.h
  99. +3 −3 include/arch/{riscv32 → riscv}/riscv-privilege/asm_inline_gcc.h
  100. +5 −1 include/linker/linker-tool-gcc.h
  101. +1 −1 include/toolchain/common.h
  102. +2 −2 include/toolchain/gcc.h
  103. +2 −2 kernel/Kconfig
  104. +1 −1 lib/libc/newlib/libc-hooks.c
  105. +2 −2 soc/Kconfig
  106. +0 −1 soc/{riscv32 → riscv}/CMakeLists.txt
  107. 0 soc/{riscv32 → riscv}/litex-vexriscv/CMakeLists.txt
  108. 0 soc/{riscv32 → riscv}/litex-vexriscv/Kconfig.defconfig
  109. 0 soc/{riscv32 → riscv}/litex-vexriscv/Kconfig.soc
  110. +1 −1 soc/{riscv32 → riscv}/litex-vexriscv/linker.ld
  111. 0 soc/{riscv32 → riscv}/litex-vexriscv/soc.h
  112. 0 soc/{riscv32 → riscv}/openisa_rv32m1/CMakeLists.txt
  113. +2 −2 soc/{riscv32 → riscv}/openisa_rv32m1/Kconfig
  114. +2 −2 soc/{riscv32 → riscv}/openisa_rv32m1/Kconfig.defconfig
  115. +1 −1 soc/{riscv32 → riscv}/openisa_rv32m1/Kconfig.soc
  116. 0 soc/{riscv32 → riscv}/openisa_rv32m1/dts_fixup.h
  117. +3 −3 soc/{riscv32 → riscv}/openisa_rv32m1/linker.ld
  118. 0 soc/{riscv32 → riscv}/openisa_rv32m1/soc.c
  119. 0 soc/{riscv32 → riscv}/openisa_rv32m1/soc.h
  120. 0 soc/{riscv32 → riscv}/openisa_rv32m1/soc_context.h
  121. 0 soc/{riscv32 → riscv}/openisa_rv32m1/soc_irq.S
  122. 0 soc/{riscv32 → riscv}/openisa_rv32m1/soc_offsets.h
  123. 0 soc/{riscv32 → riscv}/openisa_rv32m1/soc_ri5cy.h
  124. 0 soc/{riscv32 → riscv}/openisa_rv32m1/soc_zero_riscy.h
  125. 0 soc/{riscv32 → riscv}/openisa_rv32m1/vector.S
  126. 0 soc/{riscv32 → riscv}/openisa_rv32m1/wdog.S
  127. 0 soc/{riscv32 → riscv}/riscv-privilege/CMakeLists.txt
  128. +1 −1 soc/{riscv32 → riscv}/riscv-privilege/Kconfig
  129. +1 −1 soc/{riscv32 → riscv}/riscv-privilege/Kconfig.defconfig
  130. +1 −1 soc/{riscv32 → riscv}/riscv-privilege/Kconfig.soc
  131. 0 soc/{riscv32 → riscv}/riscv-privilege/common/CMakeLists.txt
  132. 0 soc/{riscv32 → riscv}/riscv-privilege/common/idle.c
  133. 0 soc/{riscv32 → riscv}/riscv-privilege/common/soc_common.h
  134. 0 soc/{riscv32 → riscv}/riscv-privilege/common/soc_common_irq.c
  135. 0 soc/{riscv32 → riscv}/riscv-privilege/common/soc_irq.S
  136. 0 soc/{riscv32 → riscv}/riscv-privilege/common/vector.S
  137. 0 soc/{riscv32 → riscv}/riscv-privilege/miv/CMakeLists.txt
  138. 0 soc/{riscv32 → riscv}/riscv-privilege/miv/Kconfig.defconfig.series
  139. +1 −1 soc/{riscv32 → riscv}/riscv-privilege/miv/Kconfig.series
  140. 0 soc/{riscv32 → riscv}/riscv-privilege/miv/Kconfig.soc
  141. +0 −1 soc/{riscv32 → riscv}/riscv-privilege/miv/dts_fixup.h
  142. +1 −1 soc/{riscv32 → riscv}/riscv-privilege/miv/linker.ld
  143. 0 soc/{riscv32 → riscv}/riscv-privilege/miv/soc.h
  144. 0 soc/{riscv32 → riscv}/riscv-privilege/sifive-freedom/CMakeLists.txt
  145. 0 soc/{riscv32 → riscv}/riscv-privilege/sifive-freedom/Kconfig.defconfig.series
  146. +1 −1 soc/{riscv32 → riscv}/riscv-privilege/sifive-freedom/Kconfig.series
  147. 0 soc/{riscv32 → riscv}/riscv-privilege/sifive-freedom/Kconfig.soc
  148. 0 soc/{riscv32 → riscv}/riscv-privilege/sifive-freedom/fe310_clock.c
  149. 0 soc/{riscv32 → riscv}/riscv-privilege/sifive-freedom/fe310_prci.h
  150. +1 −1 soc/{riscv32 → riscv}/riscv-privilege/sifive-freedom/linker.ld
  151. 0 soc/{riscv32 → riscv}/riscv-privilege/sifive-freedom/soc.h
  152. +1 −1 subsys/debug/openocd.c
  153. +1 −1 subsys/logging/log_core.c
  154. +1 −1 subsys/testsuite/include/test_asm_inline_gcc.h
  155. +2 −2 tests/kernel/context/src/main.c
  156. +1 −1 tests/kernel/fatal/src/main.c
  157. +2 −2 tests/kernel/gen_isr_table/src/main.c
  158. +1 −1 tests/kernel/interrupt/src/interrupt.h
  159. +1 −1 tests/kernel/mem_pool/mem_pool_concept/src/test_mpool.h
@@ -39,10 +39,10 @@
/arch/x86/ @andrewboie @gnuless
/arch/nios2/ @andrewboie @wentongwu
/arch/posix/ @aescolar
/arch/riscv32/ @kgugala @pgielda @nategraff-sifive
/arch/riscv/ @kgugala @pgielda @nategraff-sifive
/soc/posix/ @aescolar
/soc/riscv32/ @kgugala @pgielda @nategraff-sifive
/soc/riscv32/openisa*/ @MaureenHelm
/soc/riscv/ @kgugala @pgielda @nategraff-sifive
/soc/riscv/openisa*/ @MaureenHelm
/arch/x86/core/ @andrewboie @gnuless
/arch/x86/core/ia32/crt0.S @andrewboie @gnuless
/arch/x86/core/pcie.c @gnuless
@@ -88,8 +88,8 @@
/boards/nios2/altera_max10/ @wentongwu
/boards/arm/stm32_min_dev/ @cbsiddharth
/boards/posix/ @aescolar
/boards/riscv32/ @kgugala @pgielda @nategraff-sifive
/boards/riscv32/rv32m1_vega/ @MaureenHelm
/boards/riscv/ @kgugala @pgielda @nategraff-sifive
/boards/riscv/rv32m1_vega/ @MaureenHelm
/boards/shields/ @erwango
/boards/x86/ @andrewboie @nashif
/boards/x86/up_squared/ @gnuless
@@ -178,8 +178,10 @@
/dts/arm/nordic/ @ioannisg @carlescufi
/dts/arm/nxp/ @MaureenHelm
/dts/arm/microchip/ @franciscomunoz @albertofloyd @scottwcpg
/dts/riscv32/rv32m1* @MaureenHelm
/dts/riscv32/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda
/dts/riscv/microsemi-miv.dtsi @galak
/dts/riscv/rv32m1* @MaureenHelm
/dts/riscv/riscv32-fe310.dtsi @nategraff-sifive
/dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda
/dts/xtensa/xtensa.dtsi @ydamigos
/dts/bindings/ @galak
/dts/bindings/can/ @alexanderwachter
@@ -227,7 +229,7 @@
/include/arch/nios2/ @andrewboie
/include/arch/nios2/arch.h @andrewboie
/include/arch/posix/ @aescolar
/include/arch/riscv32/ @nategraff-sifive @kgugala @pgielda
/include/arch/riscv/ @nategraff-sifive @kgugala @pgielda
/include/arch/x86/ @andrewboie @wentongwu
/include/arch/common/ @andrewboie @andyross @nashif
/include/arch/x86/ia32/arch.h @andrewboie
@@ -41,8 +41,8 @@ config NIOS2
select ATOMIC_OPERATIONS_C
select HAS_DTS

config RISCV32
bool "RISCV32 architecture"
config RISCV
bool "RISCV architecture"
select HAS_DTS

config XTENSA
File renamed without changes.
@@ -4,14 +4,15 @@
# SPDX-License-Identifier: Apache-2.0
#

menu "RISCV32 Options"
depends on RISCV32
menu "RISCV Options"
depends on RISCV

config ARCH
string
default "riscv64" if 64BIT
default "riscv32"

menu "RISCV32 Processor Options"
menu "RISCV Processor Options"

config INCLUDE_RESET_VECTOR
bool "Include Reset vector"
File renamed without changes.
File renamed without changes.
@@ -9,8 +9,8 @@
#include <inttypes.h>
#include <logging/log_ctrl.h>

FUNC_NORETURN void z_riscv32_fatal_error(unsigned int reason,
const z_arch_esf_t *esf)
FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
const z_arch_esf_t *esf)
{
if (esf != NULL) {
z_fatal_print("Faulting instruction address = 0x%08x",
@@ -61,5 +61,5 @@ FUNC_NORETURN void _Fault(const z_arch_esf_t *esf)
z_fatal_print("Exception cause %s (%d)", cause_str(mcause),
(int)mcause);

z_riscv32_fatal_error(K_ERR_CPU_EXCEPTION, esf);
z_riscv_fatal_error(K_ERR_CPU_EXCEPTION, esf);
}
@@ -24,7 +24,7 @@ FUNC_NORETURN void z_irq_spurious(void *unused)
riscv_plic_get_irq());
}
#endif
z_riscv32_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
z_riscv_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
}

#ifdef CONFIG_DYNAMIC_INTERRUPTS
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@@ -9,11 +9,11 @@
* @brief Private kernel definitions
*
* This file contains private kernel structures definitions and various
* other definitions for the RISCV32 processor architecture.
* other definitions for the RISCV processor architecture.
*/

#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_DATA_H_
#define ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_DATA_H_
#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_DATA_H_
#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_DATA_H_

#ifdef __cplusplus
extern "C" {
@@ -35,4 +35,4 @@ extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE);

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_DATA_H_ */
#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_DATA_H_ */
@@ -9,11 +9,11 @@
* @brief Private kernel definitions
*
* This file contains private kernel function/macro definitions and various
* other definitions for the RISCV32 processor architecture.
* other definitions for the RISCV processor architecture.
*/

#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_FUNC_H_
#define ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_FUNC_H_
#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_
#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_

#include <soc.h>

@@ -37,8 +37,8 @@ z_set_thread_return_value(struct k_thread *thread, unsigned int value)
thread->arch.swap_return_value = value;
}

FUNC_NORETURN void z_riscv32_fatal_error(unsigned int reason,
const z_arch_esf_t *esf);
FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
const z_arch_esf_t *esf);

#define z_is_in_isr() (_kernel.nested != 0U)

@@ -52,4 +52,4 @@ int z_irq_do_offload(void);
}
#endif

#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_FUNC_H_ */
#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_ */
@@ -16,8 +16,8 @@
* necessary to instantiate instances of struct k_thread.
*/

#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_THREAD_H_
#define ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_THREAD_H_
#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_
#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_

#ifndef _ASMLANGUAGE
#include <zephyr/types.h>
@@ -52,5 +52,4 @@ typedef struct _thread_arch _thread_arch_t;

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_THREAD_H_ */

#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_ */
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/

#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_OFFSETS_SHORT_ARCH_H_
#define ZEPHYR_ARCH_RISCV32_INCLUDE_OFFSETS_SHORT_ARCH_H_
#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_
#define ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_

#include <offsets.h>

@@ -61,4 +61,4 @@

/* end - threads */

#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_OFFSETS_SHORT_ARCH_H_ */
#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_ */
@@ -19,5 +19,5 @@ under :zephyr_file:`doc/templates/board.tmpl`
nios2/index.rst
xtensa/index.rst
posix/index.rst
riscv32/index.rst
riscv/index.rst
shields/index.rst
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@@ -56,4 +56,3 @@ Debugging
=========

Refer to the detailed overview about :ref:`application_debugging`.

@@ -94,4 +94,3 @@
status = "okay";
clock-frequency = <16000000>;
};

File renamed without changes.
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_RISCV32=y
CONFIG_RISCV=y
CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
CONFIG_BOARD_HIFIVE1=y
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@@ -43,4 +43,3 @@ Debugging
=========

Refer to the detailed overview about :ref:`application_debugging`.

@@ -98,4 +98,3 @@
input-frequency = <16000000>;
clock-frequency = <100000>;
};

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@@ -1,4 +1,4 @@
CONFIG_RISCV32=y
CONFIG_RISCV=y
CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
CONFIG_BOARD_HIFIVE1_REVB=y
File renamed without changes.
@@ -1,6 +1,6 @@
.. _boards-riscv32:
.. _boards-riscv:

RISCV32 Boards
RISCV Boards
##############

.. toctree::
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@@ -4,7 +4,7 @@
# SPDX-License-Identifier: Apache-2.0
#

CONFIG_RISCV32=y
CONFIG_RISCV=y
CONFIG_SOC_RISCV32_LITEX_VEXRISCV=y
CONFIG_BOARD_LITEX_VEXRISCV=y
CONFIG_VEXRISCV_LITEX_IRQ=y
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@@ -64,4 +64,3 @@ Debugging
=========

Refer to the detailed overview of :ref:`application_debugging`.

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@@ -1,6 +1,6 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_RISCV32=y
CONFIG_RISCV=y
CONFIG_SOC_SERIES_RISCV32_MIV=y
CONFIG_SOC_RISCV32_MIV=y
CONFIG_BOARD_M2GL025_MIV=y
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@@ -2,6 +2,7 @@

set(EMU_PLATFORM qemu)

set(QEMU_binary_suffix riscv32)
set(QEMU_CPU_TYPE_${ARCH} riscv32)

set(QEMU_FLAGS_${ARCH}
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@@ -46,4 +46,3 @@
spi-max-frequency = <0>;
};
};

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@@ -1,6 +1,6 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_RISCV32=y
CONFIG_RISCV=y
CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
CONFIG_BOARD_QEMU_RISCV32=y
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@@ -1,6 +1,6 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_RISCV32=y
CONFIG_RISCV=y
CONFIG_SOC_OPENISA_RV32M1_RISCV32=y
CONFIG_SOC_OPENISA_RV32M1_RI5CY=y
CONFIG_BOARD_RV32M1_VEGA=y
@@ -1,4 +1,4 @@
CONFIG_RISCV32=y
CONFIG_RISCV=y
CONFIG_SOC_OPENISA_RV32M1_RISCV32=y
CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY=y
CONFIG_BOARD_RV32M1_VEGA=y
@@ -9,7 +9,7 @@ endif()

set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi)
set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf)
set(CROSS_COMPILE_TARGET_riscv32 riscv32-zephyr-elf)
set(CROSS_COMPILE_TARGET_riscv riscv32-zephyr-elf)
set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf)
set(CROSS_COMPILE_TARGET_xtensa xtensa-zephyr-elf)
set(CROSS_COMPILE_TARGET_arc arc-zephyr-elf)
@@ -9,7 +9,7 @@ endif()

set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi)
set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf)
set(CROSS_COMPILE_TARGET_riscv32 riscv32-zephyr-elf)
set(CROSS_COMPILE_TARGET_riscv riscv32-zephyr-elf)
set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf)
set(CROSS_COMPILE_TARGET_xtensa xtensa-zephyr-elf)
set(CROSS_COMPILE_TARGET_arc arc-zephyr-elf)
@@ -9,7 +9,7 @@ endif()

set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi)
set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf)
set(CROSS_COMPILE_TARGET_riscv32 riscv32-zephyr-elf)
set(CROSS_COMPILE_TARGET_riscv riscv32-zephyr-elf)
set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf)
set(CROSS_COMPILE_TARGET_xtensa xtensa-zephyr-elf)
set(CROSS_COMPILE_TARGET_arc arc-zephyr-elf)
@@ -402,10 +402,18 @@
('boards/nios2/altera_max10/doc/board', 'boards/nios2/altera_max10/doc/index'),
('boards/nios2/qemu_nios2/doc/board', 'boards/nios2/qemu_nios2/doc/index'),
('boards/posix/native_posix/doc/board', 'boards/posix/native_posix/doc/index'),
('boards/riscv32/hifive1/doc/hifive1', 'boards/riscv32/hifive1/doc/index'),
('boards/riscv32/m2gl025_miv/doc/m2g1025_miv', 'boards/riscv32/m2gl025_miv/doc/index'),
('boards/riscv32/qemu_riscv32/doc/board', 'boards/riscv32/qemu_riscv32/doc/index'),
('boards/riscv32/zedboard_pulpino/doc/zedboard_pulpino', 'boards/riscv32/zedboard_pulpino/doc/index'),
('boards/riscv32/hifive1/doc/hifive1', 'boards/riscv/hifive1/doc/index'),
('boards/riscv32/m2gl025_miv/doc/m2g1025_miv', 'boards/riscv/m2gl025_miv/doc/index'),
('boards/riscv32/qemu_riscv32/doc/board', 'boards/riscv/qemu_riscv32/doc/index'),
('boards/riscv32/zedboard_pulpino/doc/zedboard_pulpino', 'boards/riscv/zedboard_pulpino/doc/index'),
('boards/riscv32/hifive1/doc/index', 'boards/riscv/hifive1/doc/index'),
('boards/riscv32/hifive1_revb/doc/index', 'boards/riscv/hifive1_revb/doc/index'),
('boards/riscv32/litex_vexriscv/doc/litex_vexriscv', 'boards/riscv/litex_vexriscv/doc/litex_vexriscv'),
('boards/riscv32/m2gl025_miv/doc/index', 'boards/riscv/m2gl025_miv/doc/index'),
('boards/riscv32/qemu_riscv32/doc/index', 'boards/riscv/qemu_riscv32/doc/index'),
('boards/riscv32/rv32m1_vega/doc/index', 'boards/riscv/rv32m1_vega/doc/index'),
('boards/x86/arduino_101/doc/board', 'boards/x86/arduino_101/doc/index'),
('boards/x86/galileo/doc/galileo', 'boards/x86/galileo/doc/index'),
('boards/x86/minnowboard/doc/minnowboard', 'boards/x86/minnowboard/doc/index'),
('boards/x86/qemu_x86/doc/board', 'boards/x86/qemu_x86/doc/index'),
('boards/x86/tinytile/doc/board', 'boards/x86/tinytile/doc/index'),
@@ -100,7 +100,7 @@ int riscv_plic_irq_is_enabled(u32_t irq)
* @brief Set priority of a riscv PLIC-specific interrupt line
*
* This routine set the priority of a RISCV PLIC-specific interrupt line.
* riscv_plic_irq_set_prio is called by riscv32 Z_ARCH_IRQ_CONNECT to set
* riscv_plic_irq_set_prio is called by riscv Z_ARCH_IRQ_CONNECT to set
* the priority of an interrupt whenever CONFIG_RISCV_HAS_PLIC variable is set.
* @param irq IRQ number for which to set priority
*
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@@ -3,7 +3,7 @@
* SPDX-License-Identifier: Apache-2.0
*/

#include <riscv32/rv32m1.dtsi>
#include <riscv/rv32m1.dtsi>

/ {
aliases {