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drivers/clock_control: STM32H7 support

Provide basic clock control driver for STM32H7.
Bus clock activation is done through CM7 and CM4 common registers
so we don't have to care to the CPU Id before accessing.
Accesses are not protected for now. Only possible configuration
is system clock source set to HSE driven PLL.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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erwango authored and nashif committed Jul 1, 2019
1 parent ecd23f4 commit 2805ea9193f89c365ac4cc23aaae6062632b9523
@@ -12,6 +12,8 @@ zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32
if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
if(CONFIG_SOC_SERIES_STM32MP1X)
zephyr_sources(clock_stm32_ll_mp1.c)
elseif(CONFIG_SOC_SERIES_STM32H7X)
zephyr_sources(clock_stm32_ll_h7.c)
else()
zephyr_sources(clock_stm32_ll_common.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X clock_stm32f0_f3.c)
@@ -122,12 +122,15 @@ endchoice
source "drivers/clock_control/Kconfig.stm32f0_f3"
source "drivers/clock_control/Kconfig.stm32f1"
source "drivers/clock_control/Kconfig.stm32f2_f4_f7"
source "drivers/clock_control/Kconfig.stm32h7"
source "drivers/clock_control/Kconfig.stm32l0_l1"
source "drivers/clock_control/Kconfig.stm32l4_wb"


# Bus clocks configuration options

if !SOC_SERIES_STM32H7X

config CLOCK_STM32_AHB_PRESCALER
int "AHB prescaler"
default 1
@@ -181,6 +184,7 @@ config CLOCK_STM32_AHB4_PRESCALER
HCLK4 prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128,
256, 512.

endif # !SOC_SERIES_STM32H7X

# Micro-controller Clock output configuration options

@@ -0,0 +1,98 @@
# Kconfig - STM32H7 PLL configuration options
#
# Copyright (c) 2019 Linaro
#
# SPDX-License-Identifier: Apache-2.0
#

if SOC_SERIES_STM32H7X

# Bus clocks configuration options

config CLOCK_STM32_D1CPRE
int "D1 Domain, CPU1 clock prescaler"
default 1
range 1 512
help
D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler),
allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

config CLOCK_STM32_HPRE
int "hclk prescaler, D2 domain (CPU2) Clock prescaler"
default 1
range 1 512
help
hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

config CLOCK_STM32_D2PPRE1
int "APB1 prescaler"
default 1
range 1 16
help
APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16

config CLOCK_STM32_D2PPRE2
int "D2 DOMAIN, APB2 prescaler"
default 1
range 1 16
help
APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16

config CLOCK_STM32_D1PPRE
int "D1 DOMAIN, APB3 prescaler"
default 1
range 1 16
help
APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16

config CLOCK_STM32_D3PPRE
int "APB4 prescaler"
default 1
range 1 16
help
APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16


# PLL settings

config CLOCK_STM32_PLL_M_DIVISOR
int "PLL divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 32
range 0 63
help
PLL divisor, allowed values: 0-63.

config CLOCK_STM32_PLL_N_MULTIPLIER
int "PLL1 VCO multiplier"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 129
range 4 512
help
PLL multiplier, allowed values: 4-512.

config CLOCK_STM32_PLL_P_DIVISOR
int "PLL P Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 2
range 1 128
help
PLL P Output divisor, allowed values: 1-128.

config CLOCK_STM32_PLL_Q_DIVISOR
int "PLL Q Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 2
range 1 128
help
PLL Q Output divisor, allowed values: 1-128.

config CLOCK_STM32_PLL_R_DIVISOR
int "PLL R Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 2
range 1 128
help
PLL R Output divisor, allowed values: 1-128.

endif # SOC_SERIES_STM32H7X

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