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drivers/gpio: Remove DTS fixups for SiFive GPIO

Change the DT macros used by the SiFive GPIO driver so that fixups
are no longer required.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
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nategraff-sifive authored and nashif committed Mar 20, 2019
1 parent 89d81ab commit 3093f5cd2ff4e3381343367c063af3665483982d
@@ -16,10 +16,6 @@ menuconfig GPIO_SIFIVE

if GPIO_SIFIVE

config GPIO_SIFIVE_GPIO_NAME
string "GPIO driver name"
default "gpio0"

config GPIO_SIFIVE_0_PRIORITY
int "GPIO 0 interrupt priority"
default 1
@@ -355,122 +355,122 @@ static int gpio_sifive_init(struct device *dev)
static void gpio_sifive_cfg_0(void);

static const struct gpio_sifive_config gpio_sifive_config0 = {
.gpio_base_addr = DT_SIFIVE_GPIO_0_BASE_ADDR,
.gpio_irq_base = RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_0,
.gpio_base_addr = DT_SIFIVE_GPIO0_0_BASE_ADDRESS,
.gpio_irq_base = RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO0_0_IRQ_0,
.gpio_cfg_func = gpio_sifive_cfg_0,
};

static struct gpio_sifive_data gpio_sifive_data0;

DEVICE_AND_API_INIT(gpio_sifive_0, CONFIG_GPIO_SIFIVE_GPIO_NAME,
DEVICE_AND_API_INIT(gpio_sifive_0, DT_SIFIVE_GPIO0_0_LABEL,
gpio_sifive_init,
&gpio_sifive_data0, &gpio_sifive_config0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_sifive_driver);

#define IRQ_INIT(n) \
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_##n, \
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO0_0_IRQ_##n, \
CONFIG_GPIO_SIFIVE_##n##_PRIORITY, \
gpio_sifive_irq_handler, \
DEVICE_GET(gpio_sifive_0), \
0);

static void gpio_sifive_cfg_0(void)
{
#ifdef DT_SIFIVE_GPIO_0_IRQ_0
#ifdef DT_SIFIVE_GPIO0_0_IRQ_0
IRQ_INIT(0);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_1
#ifdef DT_SIFIVE_GPIO0_0_IRQ_1
IRQ_INIT(1);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_2
#ifdef DT_SIFIVE_GPIO0_0_IRQ_2
IRQ_INIT(2);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_3
#ifdef DT_SIFIVE_GPIO0_0_IRQ_3
IRQ_INIT(3);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_4
#ifdef DT_SIFIVE_GPIO0_0_IRQ_4
IRQ_INIT(4);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_5
#ifdef DT_SIFIVE_GPIO0_0_IRQ_5
IRQ_INIT(5);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_6
#ifdef DT_SIFIVE_GPIO0_0_IRQ_6
IRQ_INIT(6);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_7
#ifdef DT_SIFIVE_GPIO0_0_IRQ_7
IRQ_INIT(7);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_8
#ifdef DT_SIFIVE_GPIO0_0_IRQ_8
IRQ_INIT(8);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_9
#ifdef DT_SIFIVE_GPIO0_0_IRQ_9
IRQ_INIT(9);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_10
#ifdef DT_SIFIVE_GPIO0_0_IRQ_10
IRQ_INIT(10);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_11
#ifdef DT_SIFIVE_GPIO0_0_IRQ_11
IRQ_INIT(11);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_12
#ifdef DT_SIFIVE_GPIO0_0_IRQ_12
IRQ_INIT(12);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_13
#ifdef DT_SIFIVE_GPIO0_0_IRQ_13
IRQ_INIT(13);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_14
#ifdef DT_SIFIVE_GPIO0_0_IRQ_14
IRQ_INIT(14);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_15
#ifdef DT_SIFIVE_GPIO0_0_IRQ_15
IRQ_INIT(15);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_16
#ifdef DT_SIFIVE_GPIO0_0_IRQ_16
IRQ_INIT(16);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_17
#ifdef DT_SIFIVE_GPIO0_0_IRQ_17
IRQ_INIT(17);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_18
#ifdef DT_SIFIVE_GPIO0_0_IRQ_18
IRQ_INIT(18);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_19
#ifdef DT_SIFIVE_GPIO0_0_IRQ_19
IRQ_INIT(19);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_20
#ifdef DT_SIFIVE_GPIO0_0_IRQ_20
IRQ_INIT(20);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_21
#ifdef DT_SIFIVE_GPIO0_0_IRQ_21
IRQ_INIT(21);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_22
#ifdef DT_SIFIVE_GPIO0_0_IRQ_22
IRQ_INIT(22);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_23
#ifdef DT_SIFIVE_GPIO0_0_IRQ_23
IRQ_INIT(23);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_24
#ifdef DT_SIFIVE_GPIO0_0_IRQ_24
IRQ_INIT(24);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_25
#ifdef DT_SIFIVE_GPIO0_0_IRQ_25
IRQ_INIT(25);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_26
#ifdef DT_SIFIVE_GPIO0_0_IRQ_26
IRQ_INIT(26);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_27
#ifdef DT_SIFIVE_GPIO0_0_IRQ_27
IRQ_INIT(27);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_28
#ifdef DT_SIFIVE_GPIO0_0_IRQ_28
IRQ_INIT(28);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_29
#ifdef DT_SIFIVE_GPIO0_0_IRQ_29
IRQ_INIT(29);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_30
#ifdef DT_SIFIVE_GPIO0_0_IRQ_30
IRQ_INIT(30);
#endif
#ifdef DT_SIFIVE_GPIO_0_IRQ_31
#ifdef DT_SIFIVE_GPIO0_0_IRQ_31
IRQ_INIT(31);
#endif
}
@@ -399,12 +399,12 @@ DEVICE_AND_API_INIT(uart_sifive_0, DT_SIFIVE_UART0_0_LABEL,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_sifive_irq_cfg_func_0(void)
{
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_UART_0_IRQ_0,
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_UART0_0_IRQ_0,
CONFIG_UART_SIFIVE_PORT_0_IRQ_PRIORITY,
uart_sifive_irq_handler, DEVICE_GET(uart_sifive_0),
0);

irq_enable(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_UART_0_IRQ_0);
irq_enable(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_UART0_0_IRQ_0);
}
#endif

@@ -438,12 +438,12 @@ DEVICE_AND_API_INIT(uart_sifive_1, DT_SIFIVE_UART0_1_LABEL,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_sifive_irq_cfg_func_1(void)
{
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_UART_1_IRQ_0,
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_UART0_1_IRQ_0,
CONFIG_UART_SIFIVE_PORT_1_IRQ_PRIORITY,
uart_sifive_irq_handler, DEVICE_GET(uart_sifive_1),
0);

irq_enable(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_UART_1_IRQ_0);
irq_enable(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_UART0_1_IRQ_0);
}
#endif

@@ -24,6 +24,12 @@ properties:
generation: define
category: required

label:
type: string
category: required
description: Human readable string describing the device (used by Zephyr for API name)
generation: define

interrupts:
type: int
generation: define
@@ -74,6 +74,7 @@
26 27 28 29 30 31 32 33 34 35 36 37 38 39>;
reg = <0x10012000 0x1000>;
reg-names = "control";
label = "gpio_0";
status = "disabled";
#gpio-cells = <2>;
};
@@ -4,42 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/

/* GPIO 0 */
#define DT_SIFIVE_GPIO_0_BASE_ADDR DT_SIFIVE_GPIO0_10012000_BASE_ADDRESS
#define DT_SIFIVE_GPIO_0_IRQ_0 DT_SIFIVE_GPIO0_10012000_IRQ_0
#define DT_SIFIVE_GPIO_0_IRQ_1 DT_SIFIVE_GPIO0_10012000_IRQ_1
#define DT_SIFIVE_GPIO_0_IRQ_2 DT_SIFIVE_GPIO0_10012000_IRQ_2
#define DT_SIFIVE_GPIO_0_IRQ_3 DT_SIFIVE_GPIO0_10012000_IRQ_3
#define DT_SIFIVE_GPIO_0_IRQ_4 DT_SIFIVE_GPIO0_10012000_IRQ_4
#define DT_SIFIVE_GPIO_0_IRQ_5 DT_SIFIVE_GPIO0_10012000_IRQ_5
#define DT_SIFIVE_GPIO_0_IRQ_6 DT_SIFIVE_GPIO0_10012000_IRQ_6
#define DT_SIFIVE_GPIO_0_IRQ_7 DT_SIFIVE_GPIO0_10012000_IRQ_7
#define DT_SIFIVE_GPIO_0_IRQ_8 DT_SIFIVE_GPIO0_10012000_IRQ_8
#define DT_SIFIVE_GPIO_0_IRQ_9 DT_SIFIVE_GPIO0_10012000_IRQ_9
#define DT_SIFIVE_GPIO_0_IRQ_10 DT_SIFIVE_GPIO0_10012000_IRQ_10
#define DT_SIFIVE_GPIO_0_IRQ_11 DT_SIFIVE_GPIO0_10012000_IRQ_11
#define DT_SIFIVE_GPIO_0_IRQ_12 DT_SIFIVE_GPIO0_10012000_IRQ_12
#define DT_SIFIVE_GPIO_0_IRQ_13 DT_SIFIVE_GPIO0_10012000_IRQ_13
#define DT_SIFIVE_GPIO_0_IRQ_14 DT_SIFIVE_GPIO0_10012000_IRQ_14
#define DT_SIFIVE_GPIO_0_IRQ_15 DT_SIFIVE_GPIO0_10012000_IRQ_15
#define DT_SIFIVE_GPIO_0_IRQ_16 DT_SIFIVE_GPIO0_10012000_IRQ_16
#define DT_SIFIVE_GPIO_0_IRQ_17 DT_SIFIVE_GPIO0_10012000_IRQ_17
#define DT_SIFIVE_GPIO_0_IRQ_18 DT_SIFIVE_GPIO0_10012000_IRQ_18
#define DT_SIFIVE_GPIO_0_IRQ_19 DT_SIFIVE_GPIO0_10012000_IRQ_19
#define DT_SIFIVE_GPIO_0_IRQ_20 DT_SIFIVE_GPIO0_10012000_IRQ_20
#define DT_SIFIVE_GPIO_0_IRQ_21 DT_SIFIVE_GPIO0_10012000_IRQ_21
#define DT_SIFIVE_GPIO_0_IRQ_22 DT_SIFIVE_GPIO0_10012000_IRQ_22
#define DT_SIFIVE_GPIO_0_IRQ_23 DT_SIFIVE_GPIO0_10012000_IRQ_23
#define DT_SIFIVE_GPIO_0_IRQ_24 DT_SIFIVE_GPIO0_10012000_IRQ_24
#define DT_SIFIVE_GPIO_0_IRQ_25 DT_SIFIVE_GPIO0_10012000_IRQ_25
#define DT_SIFIVE_GPIO_0_IRQ_26 DT_SIFIVE_GPIO0_10012000_IRQ_26
#define DT_SIFIVE_GPIO_0_IRQ_27 DT_SIFIVE_GPIO0_10012000_IRQ_27
#define DT_SIFIVE_GPIO_0_IRQ_28 DT_SIFIVE_GPIO0_10012000_IRQ_28
#define DT_SIFIVE_GPIO_0_IRQ_29 DT_SIFIVE_GPIO0_10012000_IRQ_29
#define DT_SIFIVE_GPIO_0_IRQ_30 DT_SIFIVE_GPIO0_10012000_IRQ_30
#define DT_SIFIVE_GPIO_0_IRQ_31 DT_SIFIVE_GPIO0_10012000_IRQ_31
#define DT_SIFIVE_GPIO_0_SIZE DT_SIFIVE_GPIO0_10012000_SIZE

/* PLIC */
#define DT_PLIC_MAX_PRIORITY \
DT_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY
@@ -15,7 +15,7 @@
#include <generated_dts_board.h>

/* PINMUX Configuration */
#define SIFIVE_PINMUX_0_BASE_ADDR (DT_SIFIVE_GPIO_0_BASE_ADDR + 0x38)
#define SIFIVE_PINMUX_0_BASE_ADDR (DT_SIFIVE_GPIO0_0_BASE_ADDRESS + 0x38)

/* PINMUX IO Hardware Functions */
#define SIFIVE_PINMUX_IOF0 0x00

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