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soc: nxp_imx: configure USB device EHCI controller driver for rt1050

add usbd1 definition to rt dts file,
set EHCI controller config default value in rt1050 default config file,
add EHCI controller driver MACROs to dts_fixup.h,
initialize EHCI clock in rt soc.c
add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
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MarkWangChinese authored and MaureenHelm committed May 5, 2019
1 parent 5f0d065 commit 32f8521ccea3d99b73c89830d398331105a53ce6
@@ -327,6 +327,17 @@
interrupts = <53 0>;
label = "TRNG";
};

usbd1: usbd@402E0000 {
compatible = "nxp,kinetis-usbd";
reg = <0x402E0200 0x1000>;
interrupts = <113 1>;
interrupt-names = "usb_otg";
num-bidir-endpoints = <8>;
maximum-speed = "full-speed";
status = "disabled";
label = "USBD_1";
};
};
};

@@ -121,6 +121,13 @@ config SRAM_BASE_ADDRESS

endif # DATA_SEMC

if USB

config USB_DC_NXP_EHCI
default y

endif # USB

source "soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt*"

endif # SOC_SERIES_IMX_RT
@@ -24,6 +24,7 @@ config SOC_MIMXRT1015
select INIT_SYS_PLL
select INIT_USB1_PLL
select INIT_ENET_PLL
select HAS_MCUX_USB_EHCI

config SOC_MIMXRT1021
bool "SOC_MIMXRT1021"
@@ -41,6 +42,7 @@ config SOC_MIMXRT1021
select INIT_SYS_PLL
select INIT_USB1_PLL
select INIT_ENET_PLL
select HAS_MCUX_USB_EHCI

config SOC_MIMXRT1051
bool "SOC_MIMXRT1051"
@@ -58,6 +60,7 @@ config SOC_MIMXRT1051
select INIT_ARM_PLL
select INIT_SYS_PLL
select INIT_USB1_PLL
select HAS_MCUX_USB_EHCI

config SOC_MIMXRT1052
bool "SOC_MIMXRT1052"
@@ -77,6 +80,7 @@ config SOC_MIMXRT1052
select INIT_SYS_PLL
select INIT_USB1_PLL
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
select HAS_MCUX_USB_EHCI

config SOC_MIMXRT1061
bool "SOC_MIMXRT1061"
@@ -93,6 +97,7 @@ config SOC_MIMXRT1061
select INIT_ARM_PLL
select INIT_SYS_PLL
select INIT_USB1_PLL
select HAS_MCUX_USB_EHCI

config SOC_MIMXRT1062
bool "SOC_MIMXRT1062"
@@ -111,6 +116,7 @@ config SOC_MIMXRT1062
select INIT_SYS_PLL
select INIT_USB1_PLL
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
select HAS_MCUX_USB_EHCI

config SOC_MIMXRT1064
bool "SOC_MIMXRT1064"
@@ -129,6 +135,7 @@ config SOC_MIMXRT1064
select INIT_SYS_PLL
select INIT_USB1_PLL
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
select HAS_MCUX_USB_EHCI

endchoice

@@ -118,4 +118,11 @@
#define DT_ENTROPY_MCUX_TRNG_NAME DT_NXP_KINETIS_TRNG_400CC000_LABEL
#define CONFIG_ENTROPY_NAME DT_NXP_KINETIS_TRNG_400CC000_LABEL

#define DT_USBD_MCUX_EHCI_NAME DT_NXP_KINETIS_USBD_402E0000_LABEL
#define DT_USBD_MCUX_EHCI_IRQ DT_NXP_KINETIS_USBD_402E0000_IRQ_USB_OTG
#define DT_USBD_MCUX_EHCI_IRQ_PRI DT_NXP_KINETIS_USBD_402E0000_IRQ_0_PRIORITY
#define DT_USBD_MCUX_EHCI_BASE_ADDRESS DT_NXP_KINETIS_USBD_402E0000_BASE_ADDRESS
#define DT_USBD_MCUX_EHCI_NUM_BIDIR_EP DT_NXP_KINETIS_USBD_402E0000_NUM_BIDIR_ENDPOINTS
#define DT_USBD_MCUX_EHCI_MAXIMUM_SPEED DT_NXP_KINETIS_USBD_402E0000_MAXIMUM_SPEED

/* End of SoC Level DTS fixup file */
@@ -13,6 +13,10 @@
#include <arch/cpu.h>
#include <cortex_m/exc.h>
#include <fsl_flexspi_nor_boot.h>
#if CONFIG_USB_DC_NXP_EHCI
#include "usb_phy.h"
#include "usb_dc_mcux.h"
#endif

#ifdef CONFIG_INIT_ARM_PLL
/* ARM PLL configuration for RUN mode */
@@ -35,6 +39,13 @@ const clock_usb_pll_config_t usb1PllConfig = {
};
#endif

#if CONFIG_USB_DC_NXP_EHCI
/* USB PHY condfiguration */
#define BOARD_USB_PHY_D_CAL (0x0CU)
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
#endif

#ifdef CONFIG_INIT_ENET_PLL
/* ENET PLL configuration for RUN mode */
const clock_enet_pll_config_t ethPllConfig = {
@@ -49,6 +60,12 @@ const clock_enet_pll_config_t ethPllConfig = {
};
#endif

#if CONFIG_USB_DC_NXP_EHCI
usb_phy_config_struct_t usbPhyConfig = {
BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
};
#endif

#ifdef CONFIG_INIT_VIDEO_PLL
const clock_video_pll_config_t videoPllConfig = {
.loopDivider = 31,
@@ -160,6 +177,14 @@ static ALWAYS_INLINE void clkInit(void)
CLOCK_SetDiv(kCLOCK_LcdifDiv, 1);
#endif

#if CONFIG_USB_DC_NXP_EHCI
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif

/* Keep the system clock running so SYSTICK can wake up the system from
* wfi.
*/

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