From 376f885b5e52c3aba4bd8ef2bfd3f14086b11c09 Mon Sep 17 00:00:00 2001 From: Dawid Niedzwiecki Date: Wed, 16 Aug 2023 11:45:55 +0200 Subject: [PATCH] counter: stm32 rtc: handle sub second registers Add support for using the sub second registers. It allows reading and setting alarm with the sub second tick resolution. The RTC module is configured to get as high frequency as possible, which equals the source clock (RTCCLK) divided by 2. To get such frequency, the asynchronous prescaler is set to 1. According to RM, setting the asynchronous prescaler to a high value minimize consumption, so the change increase the power consumption. Use a config to enable the sub second support. Signed-off-by: Dawid Niedzwiecki --- drivers/counter/Kconfig.stm32_rtc | 9 +++ drivers/counter/counter_ll_stm32_rtc.c | 83 ++++++++++++++++++++++++-- 2 files changed, 86 insertions(+), 6 deletions(-) diff --git a/drivers/counter/Kconfig.stm32_rtc b/drivers/counter/Kconfig.stm32_rtc index 03e72babc601cd6..08f8dfceec9e743 100644 --- a/drivers/counter/Kconfig.stm32_rtc +++ b/drivers/counter/Kconfig.stm32_rtc @@ -44,4 +44,13 @@ config COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS help Keep the counter value after each reset. +config COUNTER_RTC_STM32_SUBSECONDS_BASED + bool "Use the subseconds as a basic tick." + depends on !SOC_SERIES_STM32F1X + help + Use the subseconds as the basic time tick. It increases resolution + of the counter. The frequency of the time is RTC Source Clock divided + by 2. It is the clock after the first asynchronous prescaler. + The config increases power consumption. + endif # COUNTER_RTC_STM32 diff --git a/drivers/counter/counter_ll_stm32_rtc.c b/drivers/counter/counter_ll_stm32_rtc.c index 3e6fa92630d73da..49fd02189138ae2 100644 --- a/drivers/counter/counter_ll_stm32_rtc.c +++ b/drivers/counter/counter_ll_stm32_rtc.c @@ -70,7 +70,12 @@ LOG_MODULE_REGISTER(counter_rtc_stm32, CONFIG_COUNTER_LOG_LEVEL); #endif /* DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_LSI */ #if !defined(CONFIG_SOC_SERIES_STM32F1X) +#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED #define RTC_ASYNCPRE BIT_MASK(7) +#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ +/* Get the highest possible clock for the subsecond register */ +#define RTC_ASYNCPRE 1 +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ #else /* CONFIG_SOC_SERIES_STM32F1X */ #define RTC_ASYNCPRE (RTCCLK_FREQ - 1) #endif /* CONFIG_SOC_SERIES_STM32F1X */ @@ -181,12 +186,25 @@ static int rtc_stm32_stop(const struct device *dev) } -static uint32_t rtc_stm32_read(const struct device *dev) +#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED +static uint32_t +#else +static uint64_t +#endif +rtc_stm32_read(const struct device *dev) { #if !defined(COUNTER_NO_DATE) struct tm now = { 0 }; time_t ts; - uint32_t rtc_date, rtc_time, ticks; + uint32_t rtc_date, rtc_time; +#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED + uint32_t ticks; +#else + uint64_t ticks; +#endif +#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED + uint32_t rtc_subseconds; +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ #else uint32_t rtc_time, ticks; #endif @@ -201,6 +219,13 @@ static uint32_t rtc_stm32_read(const struct device *dev) do { rtc_time = LL_RTC_TIME_Get(RTC); + +#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED + do { + rtc_subseconds = LL_RTC_TIME_GetSubSecond(RTC); + } while (rtc_subseconds != LL_RTC_TIME_GetSubSecond(RTC)); +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ + } while (rtc_time != LL_RTC_TIME_Get(RTC)); } while (rtc_date != LL_RTC_DATE_Get(RTC)); @@ -228,7 +253,15 @@ static uint32_t rtc_stm32_read(const struct device *dev) ts -= T_TIME_OFFSET; __ASSERT(sizeof(time_t) == 8, "unexpected time_t definition"); + + +#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED + ticks = ts * counter_get_frequency(dev); + ticks += RTC_SYNCPRE - rtc_subseconds; +#else /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ ticks = counter_us_to_ticks(dev, ts * USEC_PER_SEC); +#endif /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ + #else ticks = rtc_time; #endif @@ -237,25 +270,41 @@ static uint32_t rtc_stm32_read(const struct device *dev) } static int rtc_stm32_get_value(const struct device *dev, uint32_t *ticks) +{ + *ticks = (uint32_t)rtc_stm32_read(dev); + return 0; +} + +#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED +static int rtc_stm32_get_value_64(const struct device *dev, uint64_t *ticks) { *ticks = rtc_stm32_read(dev); return 0; } +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ static int rtc_stm32_set_alarm(const struct device *dev, uint8_t chan_id, const struct counter_alarm_cfg *alarm_cfg) { #if !defined(COUNTER_NO_DATE) struct tm alarm_tm; - time_t alarm_val; + time_t alarm_val_s; +#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED + uint32_t alarm_val_ss; +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ #else uint32_t remain; #endif LL_RTC_AlarmTypeDef rtc_alarm; struct rtc_stm32_data *data = dev->data; +#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED uint32_t now = rtc_stm32_read(dev); uint32_t ticks = alarm_cfg->ticks; +#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ + uint64_t now = rtc_stm32_read(dev); + uint64_t ticks = alarm_cfg->ticks; +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ if (data->callback != NULL) { LOG_DBG("Alarm busy\n"); @@ -274,11 +323,16 @@ static int rtc_stm32_set_alarm(const struct device *dev, uint8_t chan_id, * that tick+1 event occurs before alarm setting is finished. */ ticks += now + 1; - alarm_val = (time_t)(counter_ticks_to_us(dev, ticks) / USEC_PER_SEC) + + alarm_val_s = (time_t)(ticks / counter_get_frequency(dev)) + T_TIME_OFFSET; } else { - alarm_val = (time_t)(counter_ticks_to_us(dev, ticks) / USEC_PER_SEC); + alarm_val_s = (time_t)(ticks / counter_get_frequency(dev)); } +#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED + alarm_val_ss = ticks % counter_get_frequency(dev); +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ + #else if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) { remain = ticks + now + 1; @@ -293,9 +347,13 @@ static int rtc_stm32_set_alarm(const struct device *dev, uint8_t chan_id, #endif #if !defined(COUNTER_NO_DATE) +#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED LOG_DBG("Set Alarm: %d\n", ticks); +#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ + LOG_DBG("Set Alarm: %llu\n", ticks); +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ - gmtime_r(&alarm_val, &alarm_tm); + gmtime_r(&alarm_val_s, &alarm_tm); /* Apply ALARM_A */ rtc_alarm.AlarmTime.TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24; @@ -323,6 +381,11 @@ static int rtc_stm32_set_alarm(const struct device *dev, uint8_t chan_id, } LL_RTC_DisableWriteProtection(RTC); +#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED + /* Care about all bits of the subsecond register */ + LL_RTC_ALMA_SetSubSecondMask(RTC, 0xF); + LL_RTC_ALMA_SetSubSecond(RTC, RTC_SYNCPRE - alarm_val_ss); +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ ll_func_enable_alarm(RTC); ll_func_clear_alarm_flag(RTC); ll_func_enable_interrupt_alarm(RTC); @@ -504,7 +567,12 @@ static const struct stm32_pclken rtc_clk[] = STM32_DT_INST_CLOCKS(0); static const struct rtc_stm32_config rtc_config = { .counter_info = { .max_top_value = UINT32_MAX, +#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED + /* freq = 1Hz for not subsec based driver */ .freq = RTCCLK_FREQ / ((RTC_ASYNCPRE + 1) * (RTC_SYNCPRE + 1)), +#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ + .freq = RTCCLK_FREQ / (RTC_ASYNCPRE + 1), +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ .flags = COUNTER_CONFIG_INFO_COUNT_UP, .channels = 1, }, @@ -525,6 +593,9 @@ static const struct counter_driver_api rtc_stm32_driver_api = { .start = rtc_stm32_start, .stop = rtc_stm32_stop, .get_value = rtc_stm32_get_value, +#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED + .get_value_64 = rtc_stm32_get_value_64, +#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS_BASED */ .set_alarm = rtc_stm32_set_alarm, .cancel_alarm = rtc_stm32_cancel_alarm, .set_top_value = rtc_stm32_set_top_value,