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drivers/clock_control: stm32: Factorize series specific code

RCC device could be common to various STM32 series.
Until now, PLL handling code was set in series specific files,
even if it was driving the same device than another series.
Minimize code duplication by factorizing code between series
when possible.
With this change, some series get additional features by getting
access to code developed for other series.

Additionally, while renaming the files, remove the non informative
'x' to minimize file name length

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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erwango authored and nashif committed May 28, 2019
1 parent ea1e191 commit 37c13eec7a4100c70a27ba5898deacca155fb6b4
@@ -10,18 +10,18 @@ zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32

if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
if(CONFIG_SOC_SERIES_STM32MP1X)
zephyr_sources(clock_stm32_ll_mp1x.c)
zephyr_sources(clock_stm32_ll_mp1.c)
else()
zephyr_sources(clock_stm32_ll_common.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X clock_stm32f0x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X clock_stm32f1x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F2X clock_stm32f2x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X clock_stm32f3x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X clock_stm32f4x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X clock_stm32f7x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l1x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32wbx.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X clock_stm32f0_f3.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X clock_stm32f1.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F2X clock_stm32f2_f4_f7.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X clock_stm32f0_f3.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X clock_stm32f2_f4_f7.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X clock_stm32f2_f4_f7.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0_l1.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_wb.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32l4_wb.c)
endif()
endif()
File renamed without changes.
@@ -37,6 +37,8 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
#if defined(CONFIG_CLOCK_STM32_PLL_SRC_HSI)
pllinit->PLLDiv = LL_RCC_PLLSOURCE_HSI;
#else

#if defined(CONFIG_CLOCK_STM32_PLL_PREDIV1)
/*
* PLL DIV
* 1 -> LL_RCC_PLLSOURCE_HSE_DIV_1 -> 0x00010000
@@ -47,6 +49,8 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
*/
pllinit->PLLDiv = (RCC_CFGR_PLLSRC_HSE_PREDIV |
(CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1));
#endif /* CONFIG_CLOCK_STM32_PLL_PREDIV1 */

#endif /* CONFIG_CLOCK_STM32_PLL_SRC_HSI */
#else
/*
@@ -68,10 +72,12 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
*/
void config_enable_default_clocks(void)
{
#ifndef CONFIG_SOC_SERIES_STM32F3X
#if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32)
/* Enable System Configuration Controller clock. */
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
#endif
#endif /* !CONFIG_SOC_SERIES_STM32F3X */
}

/**
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