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riscv: isr.S: fix a missing lw to LR conversion

This loads a pointer and therefore has to use LR to be 64-bit
compatible.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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Nicolas Pitre authored and carlescufi committed Aug 5, 2019
1 parent 7c60300 commit 39ada716887111fa36a3581ef8fe0ef367161fb3
Showing with 1 addition and 1 deletion.
  1. +1 −1 arch/riscv/core/isr.S
@@ -253,7 +253,7 @@ call_irq:
LR a0, 0x00(t0)

/* Load ISR function address in register t1 */
lw t1, RV_REGSIZE(t0)
LR t1, RV_REGSIZE(t0)

#ifdef CONFIG_EXECUTION_BENCHMARKING
addi sp, sp, -16

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