soc: arm: stm32h5 new soc serie

Introduce the new stm32h5 soc serie from STMIcroelectronics.
Note that stm32h503x do not have TrustZone nor SAU

Signed-off-by: Francois Ramu <francois.ramu@st.com>

soc/arm/st_stm32/stm32h5/CMakeLists.txt

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )

soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series

@@ -0,0 +1,16 @@
+# ST Microelectronics STM32H5 MCU line
+
+# Copyright (c) 2023 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_STM32H5X
+
+source "soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h5*"
+
+config SOC_SERIES
+	default "stm32h5"
+
+config ROM_START_OFFSET
+	default 0x400 if BOOTLOADER_MCUBOOT
+
+endif # SOC_SERIES_STM32H5X

soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx

@@ -0,0 +1,14 @@
+# STMicroelectronics STM32H503XX MCU
+
+# Copyright (c) 2023 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H503XX
+
+config SOC
+	default "stm32h503xx"
+
+config NUM_IRQS
+	default 134
+
+endif # SOC_STM32H503XX

soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx

@@ -0,0 +1,14 @@
+# STMicroelectronics STM32H562XX MCU
+
+# Copyright (c) 2023 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H562XX
+
+config SOC
+	default "stm32h562xx"
+
+config NUM_IRQS
+	default 131
+
+endif # SOC_STM32H562XX

soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx

@@ -0,0 +1,14 @@
+# STMicroelectronics STM32H563XX MCU
+
+# Copyright (c) 2023 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H563XX
+
+config SOC
+	default "stm32h563xx"
+
+config NUM_IRQS
+	default 131
+
+endif # SOC_STM32H563XX

soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx

@@ -0,0 +1,14 @@
+# STMicroelectronics STM32H573XX MCU
+
+# Copyright (c) 2023 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H573XX
+
+config SOC
+	default "stm32h573xx"
+
+config NUM_IRQS
+	default 131
+
+endif # SOC_STM32H573XX

soc/arm/st_stm32/stm32h5/Kconfig.series

@@ -0,0 +1,19 @@
+# ST Microelectronics STM32H5 MCU series
+
+# Copyright (c) 2023 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32H5X
+	bool "STM32H5x Series MCU"
+	select ARM
+	select CPU_CORTEX_M33
+	select SOC_FAMILY_STM32
+	select ARM_TRUSTZONE_M if !SOC_STM32H503XX
+	select CPU_HAS_ARM_SAU if !SOC_STM32H503XX
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select CPU_CORTEX_M_HAS_DWT
+	select HAS_STM32CUBE
+	help
+	  Enable support for STM32H5 MCU series

soc/arm/st_stm32/stm32h5/Kconfig.soc

@@ -0,0 +1,22 @@
+# ST Microelectronics STM32H5 MCU line
+
+# Copyright (c) 2023 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+prompt "STM32H5x MCU Selection"
+depends on SOC_SERIES_STM32H5X
+
+config SOC_STM32H503XX
+	bool "STM32H503XX"
+
+config SOC_STM32H562XX
+	bool "STM32H562XX"
+
+config SOC_STM32H563XX
+	bool "STM32H563XX"
+
+config SOC_STM32H573XX
+	bool "STM32H573XX"
+
+endchoice

soc/arm/st_stm32/stm32h5/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2023 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/st_stm32/stm32h5/soc.c

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2023 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32H5 processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <stm32_ll_bus.h>
+#include <stm32_ll_pwr.h>
+#include <stm32_ll_icache.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/arch/arm/aarch32/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+
+#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
+LOG_MODULE_REGISTER(soc);
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32h5_init(const struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Enable instruction cache in 1-way (direct mapped cache) */
+	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
+	LL_ICACHE_Enable();
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 32 MHz from HSI with a HSIDIV = 2 */
+	SystemCoreClock = 32000000;
+
+#if defined(PWR_UCPDR_UCPD_DBDIS)
+	/* Disable USB Type-C dead battery pull-down behavior */
+	LL_PWR_DisableUCPDDeadBattery();
+#endif /* PWR_UCPDR_UCPD_DBDIS */
+
+	return 0;
+}
+
+SYS_INIT(stm32h5_init, PRE_KERNEL_1, 0);

soc/arm/st_stm32/stm32h5/soc.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2023 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the STM32H5 family processors.
+ *
+ */
+
+
+#ifndef _STM32H5_SOC_H_
+#define _STM32H5_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32h5xx.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32H5_SOC_H_ */