From 3b1dd7380b90d8fe65c71373d088be2d12040b98 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Wed, 30 Nov 2022 09:06:42 +0100 Subject: [PATCH] soc: arm: stm32h5 new soc serie Introduce the new stm32h5 soc serie from STMIcroelectronics. Note that stm32h503x do not have TrustZone nor SAU Signed-off-by: Francois Ramu --- soc/arm/st_stm32/stm32h5/CMakeLists.txt | 6 ++ .../st_stm32/stm32h5/Kconfig.defconfig.series | 16 +++++ .../stm32h5/Kconfig.defconfig.stm32h503xx | 14 ++++ .../stm32h5/Kconfig.defconfig.stm32h562xx | 14 ++++ .../stm32h5/Kconfig.defconfig.stm32h563xx | 14 ++++ .../stm32h5/Kconfig.defconfig.stm32h573xx | 14 ++++ soc/arm/st_stm32/stm32h5/Kconfig.series | 19 ++++++ soc/arm/st_stm32/stm32h5/Kconfig.soc | 22 +++++++ soc/arm/st_stm32/stm32h5/linker.ld | 9 +++ soc/arm/st_stm32/stm32h5/soc.c | 65 +++++++++++++++++++ soc/arm/st_stm32/stm32h5/soc.h | 22 +++++++ 11 files changed, 215 insertions(+) create mode 100644 soc/arm/st_stm32/stm32h5/CMakeLists.txt create mode 100644 soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series create mode 100644 soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx create mode 100644 soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx create mode 100644 soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx create mode 100644 soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx create mode 100644 soc/arm/st_stm32/stm32h5/Kconfig.series create mode 100644 soc/arm/st_stm32/stm32h5/Kconfig.soc create mode 100644 soc/arm/st_stm32/stm32h5/linker.ld create mode 100644 soc/arm/st_stm32/stm32h5/soc.c create mode 100644 soc/arm/st_stm32/stm32h5/soc.h diff --git a/soc/arm/st_stm32/stm32h5/CMakeLists.txt b/soc/arm/st_stm32/stm32h5/CMakeLists.txt new file mode 100644 index 00000000000000..ac3ba70ace6e70 --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series new file mode 100644 index 00000000000000..201694ed708a12 --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series @@ -0,0 +1,16 @@ +# ST Microelectronics STM32H5 MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32H5X + +source "soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h5*" + +config SOC_SERIES + default "stm32h5" + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_STM32H5X diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx new file mode 100644 index 00000000000000..e7d7b508baace3 --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx @@ -0,0 +1,14 @@ +# STMicroelectronics STM32H503XX MCU + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H503XX + +config SOC + default "stm32h503xx" + +config NUM_IRQS + default 134 + +endif # SOC_STM32H503XX diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx new file mode 100644 index 00000000000000..eb76a2d798925a --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx @@ -0,0 +1,14 @@ +# STMicroelectronics STM32H562XX MCU + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H562XX + +config SOC + default "stm32h562xx" + +config NUM_IRQS + default 131 + +endif # SOC_STM32H562XX diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx new file mode 100644 index 00000000000000..94994a7d060ad8 --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx @@ -0,0 +1,14 @@ +# STMicroelectronics STM32H563XX MCU + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H563XX + +config SOC + default "stm32h563xx" + +config NUM_IRQS + default 131 + +endif # SOC_STM32H563XX diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx new file mode 100644 index 00000000000000..d6641c126eca8b --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx @@ -0,0 +1,14 @@ +# STMicroelectronics STM32H573XX MCU + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H573XX + +config SOC + default "stm32h573xx" + +config NUM_IRQS + default 131 + +endif # SOC_STM32H573XX diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.series b/soc/arm/st_stm32/stm32h5/Kconfig.series new file mode 100644 index 00000000000000..ceefa34869645b --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/Kconfig.series @@ -0,0 +1,19 @@ +# ST Microelectronics STM32H5 MCU series + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32H5X + bool "STM32H5x Series MCU" + select ARM + select CPU_CORTEX_M33 + select SOC_FAMILY_STM32 + select ARM_TRUSTZONE_M if !SOC_STM32H503XX + select CPU_HAS_ARM_SAU if !SOC_STM32H503XX + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + help + Enable support for STM32H5 MCU series diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.soc b/soc/arm/st_stm32/stm32h5/Kconfig.soc new file mode 100644 index 00000000000000..3bf6a3605c0ea6 --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/Kconfig.soc @@ -0,0 +1,22 @@ +# ST Microelectronics STM32H5 MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +choice +prompt "STM32H5x MCU Selection" +depends on SOC_SERIES_STM32H5X + +config SOC_STM32H503XX + bool "STM32H503XX" + +config SOC_STM32H562XX + bool "STM32H562XX" + +config SOC_STM32H563XX + bool "STM32H563XX" + +config SOC_STM32H573XX + bool "STM32H573XX" + +endchoice diff --git a/soc/arm/st_stm32/stm32h5/linker.ld b/soc/arm/st_stm32/stm32h5/linker.ld new file mode 100644 index 00000000000000..8bd989bc732f46 --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/linker.ld @@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2023 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/st_stm32/stm32h5/soc.c b/soc/arm/st_stm32/stm32h5/soc.c new file mode 100644 index 00000000000000..67483764ad796a --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/soc.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2023 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for STM32H5 processor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int stm32h5_init(const struct device *arg) +{ + uint32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + /* Enable instruction cache in 1-way (direct mapped cache) */ + LL_ICACHE_SetMode(LL_ICACHE_1WAY); + LL_ICACHE_Enable(); + + /* Update CMSIS SystemCoreClock variable (HCLK) */ + /* At reset, system core clock is set to 32 MHz from HSI with a HSIDIV = 2 */ + SystemCoreClock = 32000000; + +#if defined(PWR_UCPDR_UCPD_DBDIS) + /* Disable USB Type-C dead battery pull-down behavior */ + LL_PWR_DisableUCPDDeadBattery(); +#endif /* PWR_UCPDR_UCPD_DBDIS */ + + return 0; +} + +SYS_INIT(stm32h5_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/st_stm32/stm32h5/soc.h b/soc/arm/st_stm32/stm32h5/soc.h new file mode 100644 index 00000000000000..e84a2ffd0749c7 --- /dev/null +++ b/soc/arm/st_stm32/stm32h5/soc.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2023 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the STM32H5 family processors. + * + */ + + +#ifndef _STM32H5_SOC_H_ +#define _STM32H5_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* _STM32H5_SOC_H_ */