Skip to content
Permalink
Browse files

drivers: pinmux: Pinmux driver for Microchip SOCs

This driver introduces pinmux configuration capabilities
using zephyr apis for XEC SOCs.

Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
  • Loading branch information...
franciscomunoz authored and nashif committed Apr 22, 2019
1 parent 6992176 commit 3d180991bc56fa13c811377610e751b8a6e08ce3
Showing with 273 additions and 0 deletions.
  1. +1 −0 drivers/pinmux/CMakeLists.txt
  2. +2 −0 drivers/pinmux/Kconfig
  3. +77 −0 drivers/pinmux/Kconfig.xec
  4. +193 −0 drivers/pinmux/pinmux_mchp_xec.c
@@ -5,6 +5,7 @@ zephyr_sources_ifdef(CONFIG_PINMUX_CC13XX_CC26XX pinmux_cc13xx_cc26xx.c)
zephyr_sources_ifdef(CONFIG_PINMUX_CC2650 pinmux_cc2650.c)
zephyr_sources_ifdef(CONFIG_PINMUX_ESP32 pinmux_esp32.c)
zephyr_sources_ifdef(CONFIG_PINMUX_SIFIVE pinmux_sifive.c)
zephyr_sources_ifdef(CONFIG_PINMUX_XEC pinmux_mchp_xec.c)
zephyr_sources_ifdef(CONFIG_PINMUX_MCUX pinmux_mcux.c)
zephyr_sources_ifdef(CONFIG_PINMUX_MCUX_LPC pinmux_mcux_lpc.c)
zephyr_sources_ifdef(CONFIG_PINMUX_QMSI pinmux_qmsi.c)
@@ -61,4 +61,6 @@ source "drivers/pinmux/Kconfig.intel_s1000"

source "drivers/pinmux/Kconfig.rv32m1"

source "drivers/pinmux/Kconfig.xec"

endif # PINMUX
@@ -0,0 +1,77 @@
# Kconfig.xec - Microchip XEC pinmux configuration options
#
# Copyright (c) 2019 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
#

menuconfig PINMUX_XEC
bool "XEC Microchip Pinmux driver"
depends on SOC_FAMILY_MEC
help
Enable the Microchip XEC pinmux driver.

if PINMUX_XEC

config PINMUX_XEC_GPIO000_036
bool "Pinmux 000-036"
help
Enable Port 000-036 or what would be equivalent to Port A.

config PINMUX_XEC_GPIO000_036_NAME
string "Pinmux Port 000_036 driver name"
depends on PINMUX_XEC_GPIO000_036
default "port000_036"

config PINMUX_XEC_GPIO040_076
bool "Pinmux 040-036"
help
Enable Port 040-076 or what would be equivalent to Port B

config PINMUX_XEC_GPIO040_076_NAME
string "Pinmux Port 040_076 driver name"
depends on PINMUX_XEC_GPIO040_076
default "port040_076"

config PINMUX_XEC_GPIO100_136
bool "Pinmux 100-136"
help
Enable Port 100-136 or what would be equivalent to Port C

config PINMUX_XEC_GPIO100_136_NAME
string "Pinmux Port 100_136 driver name"
depends on PINMUX_XEC_GPIO100_136
default "port100_136"

config PINMUX_XEC_GPIO140_176
bool "Pinmux 140-176"
help
Enable Port 140-176 or what would be equivalent to Port C

config PINMUX_XEC_GPIO140_176_NAME
string "Pinmux Port 140_176 driver name"
depends on PINMUX_XEC_GPIO140_176
default "port140_176"

config PINMUX_XEC_GPIO200_236
bool "Pinmux 200-236"
help
Enable Port 200-236 or what would be equivalent to Port D

config PINMUX_XEC_GPIO200_236_NAME
string "Pinmux Port 200_236 driver name"
depends on PINMUX_XEC_GPIO200_236
default "port200_236"

config PINMUX_XEC_GPIO240_276
bool "Pinmux 240-276"
help
Enable Port 240-276 or what would be equivalent to Port E

config PINMUX_XEC_GPIO240_276_NAME
string "Pinmux Port 200_276 driver name"
depends on PINMUX_XEC_GPIO240_276
default "port200_276"

endif # PINMUX_XEC

@@ -0,0 +1,193 @@
/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <errno.h>
#include <device.h>
#include <pinmux.h>
#include <soc.h>

static const u32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
(MCHP_GPIO_PORT_A_BITMAP),
(MCHP_GPIO_PORT_B_BITMAP),
(MCHP_GPIO_PORT_C_BITMAP),
(MCHP_GPIO_PORT_D_BITMAP),
(MCHP_GPIO_PORT_E_BITMAP),
(MCHP_GPIO_PORT_F_BITMAP)
};

struct pinmux_xec_config {
__IO u32_t *pcr1_base;
u32_t port_num;
};

static int pinmux_xec_set(struct device *dev, u32_t pin, u32_t func)
{
const struct pinmux_xec_config *config = dev->config->config_info;
__IO u32_t *current_pcr1;
u32_t pcr1 = 0;
u32_t mask = 0;

/* Validate pin number in terms of current port */
if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0)
return -EINVAL;

mask |= MCHP_GPIO_CTRL_BUFT_MASK | MCHP_GPIO_CTRL_MUX_MASK;

/* Check for open drain/push_pull setting */
if (func & MCHP_GPIO_CTRL_BUFT_OPENDRAIN) {
pcr1 |= MCHP_GPIO_CTRL_BUFT_OPENDRAIN;
} else {
pcr1 |= MCHP_GPIO_CTRL_BUFT_PUSHPULL;
}

/* Parse mux mode */
pcr1 |= func & MCHP_GPIO_CTRL_MUX_MASK;

/* Figure out the pullup/pulldown configuration */
mask |= MCHP_GPIO_CTRL_PUD_MASK;

if (func & MCHP_GPIO_CTRL_PUD_PU) {
/* Enable the pull and select the pullup resistor. */
pcr1 |= MCHP_GPIO_CTRL_PUD_PU;
} else if (func & MCHP_GPIO_CTRL_PUD_PD) {
/* Enable the pull and select the pulldown resistor */
pcr1 |= MCHP_GPIO_CTRL_PUD_PD;
} else {
/* None : Pin tristates when no active driver is present
* on the pin. This is the POR setting
*/
pcr1 |= MCHP_GPIO_CTRL_PUD_NONE;
}

/* Make sure gpio isrs are disabled */
pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
mask |= MCHP_GPIO_CTRL_IDET_MASK;

/* Now write contents of pcr1 variable to the PCR1 register that
* corresponds to the pin configured
*/
current_pcr1 = config->pcr1_base + pin;
*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;

return 0;
}

static int pinmux_xec_get(struct device *dev, u32_t pin, u32_t *func)
{
const struct pinmux_xec_config *config = dev->config->config_info;
__IO u32_t *current_pcr1;

/* Validate pin number in terms of current port */
if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0)
return -EINVAL;

current_pcr1 = config->pcr1_base + pin;
*func = *current_pcr1 & (MCHP_GPIO_CTRL_BUFT_MASK
| MCHP_GPIO_CTRL_MUX_MASK
| MCHP_GPIO_CTRL_PUD_MASK);

return 0;
}

static int pinmux_xec_pullup(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}

static int pinmux_xec_input(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}

static int pinmux_xec_init(struct device *dev)
{
/* Nothing to do. The PCR clock is enabled at reset. */
return 0;
}

static const struct pinmux_driver_api pinmux_xec_driver_api = {
.set = pinmux_xec_set,
.get = pinmux_xec_get,
.pullup = pinmux_xec_pullup,
.input = pinmux_xec_input,
};

#ifdef CONFIG_PINMUX_XEC_GPIO000_036
static const struct pinmux_xec_config pinmux_xec_port000_036_config = {
.pcr1_base = (u32_t *) DT_PINMUX_XEC_GPIO000_036_BASE_ADDR,
.port_num = MCHP_GPIO_000_036,
};

DEVICE_AND_API_INIT(pinmux_xec_port000_036, CONFIG_PINMUX_XEC_GPIO000_036_NAME,
&pinmux_xec_init,
NULL, &pinmux_xec_port000_036_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_xec_driver_api);
#endif /* CONFIG_PINMUX_XEC_GPIO000_036 */

#ifdef CONFIG_PINMUX_XEC_GPIO040_076
static const struct pinmux_xec_config pinmux_xec_port040_076_config = {
.pcr1_base = (u32_t *) DT_PINMUX_XEC_GPIO040_076_BASE_ADDR,
.port_num = MCHP_GPIO_040_076,
};

DEVICE_AND_API_INIT(pinmux_xec_port040_076, CONFIG_PINMUX_XEC_GPIO040_076_NAME,
NULL, &pinmux_xec_port040_076_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_xec_driver_api);
#endif /* CONFIG_PINMUX_XEC_GPIO040_076 */

#ifdef CONFIG_PINMUX_XEC_GPIO100_136
static const struct pinmux_xec_config pinmux_xec_port100_136_config = {
.pcr1_base = (u32_t *) DT_PINMUX_XEC_GPIO100_136_BASE_ADDR,
.port_num = MCHP_GPIO_100_136,
};

DEVICE_AND_API_INIT(pinmux_xec_port100_136, CONFIG_PINMUX_XEC_GPIO100_136_NAME,
&pinmux_xec_init,
NULL, &pinmux_xec_port100_136_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_xec_driver_api);
#endif /* CONFIG_PINMUX_XEC_GPIO100_136 */

#ifdef CONFIG_PINMUX_XEC_GPIO140_176
static const struct pinmux_xec_config pinmux_xec_port140_176_config = {
.pcr1_base = (u32_t *) DT_PINMUX_XEC_GPIO140_176_BASE_ADDR,
.port_num = MCHP_GPIO_140_176,
};

DEVICE_AND_API_INIT(pinmux_xec_port140_176, CONFIG_PINMUX_XEC_GPIO140_176_NAME,
&pinmux_xec_init,
NULL, &pinmux_xec_port140_176_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_xec_driver_api);
#endif /* CONFIG_PINMUX_XEC_GPIO140_176 */

#ifdef CONFIG_PINMUX_XEC_GPIO200_236
static const struct pinmux_xec_config pinmux_xec_port200_236_config = {
.pcr1_base = (u32_t *) DT_PINMUX_XEC_GPIO200_236_BASE_ADDR,
.port_num = MCHP_GPIO_200_236,
};

DEVICE_AND_API_INIT(pinmux_xec_port200_236, CONFIG_PINMUX_XEC_GPIO200_236_NAME,
&pinmux_xec_init,
NULL, &pinmux_xec_port200_236_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_xec_driver_api);
#endif /* CONFIG_PINMUX_XEC_GPIO200_236 */

#ifdef CONFIG_PINMUX_XEC_GPIO240_276
static const struct pinmux_xec_config pinmux_xec_port240_276_config = {
.pcr1_base = (u32_t *) DT_PINMUX_XEC_GPIO240_276_BASE_ADDR,
.port_num = MCHP_GPIO_240_276,
};

DEVICE_AND_API_INIT(pinmux_xec_port240_276, CONFIG_PINMUX_XEC_GPIO240_276_NAME,
&pinmux_xec_init,
NULL, &pinmux_xec_port240_276_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_xec_driver_api);
#endif /* CONFIG_PINMUX_XEC_GPIO240_276 */

0 comments on commit 3d18099

Please sign in to comment.
You can’t perform that action at this time.