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drivers/interrupt_controller/mvic.c: remove MVIC interrupt controller

The Quark D2000 is the only x86 with an MVIC, and since support for
it has been dropped, the interrupt controller is orphaned. Removed.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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Charles E. Youse authored and nashif committed Jun 23, 2019
1 parent c6c9dcf commit 3dc7c7a6ea077b51c4f0b642e9de5a808ca73169
@@ -230,7 +230,6 @@
/include/drivers/modem/ @mike-scott
/include/drivers/ioapic.h @andrewboie
/include/drivers/loapic.h @andrewboie
/include/drivers/mvic.h @andrewboie
/include/drivers/pcie/ @gnuless
/include/drivers/serial/uart_ns16550.h @gnuless
/include/dt-bindings/clock/kinetis_scg.h @henrikbrixandersen
@@ -345,27 +345,19 @@ config X86_KERNEL_OOPS

config X86_KERNEL_OOPS_VECTOR
int "IDT vector to use for kernel oops"
default 62 if MVIC
default 33 if !MVIC
default 33
range 32 255
depends on X86_KERNEL_OOPS
help
Specify the IDT vector to use for the kernel oops exception handler.
The default should be fine for most arches, but on systems like MVIC
where there is a fixed IRQ-to-vector mapping another value may be
needed to avoid collision.

config IRQ_OFFLOAD_VECTOR
int "IDT vector to use for IRQ offload"
default 63 if MVIC
default 32 if !MVIC
default 32
range 32 255
depends on IRQ_OFFLOAD
help
Specify the IDT vector to use for the IRQ offload interrupt handler.
The default should be fine for most arches, but on systems like MVIC
where there is a fixed IRQ-to-vector mapping another value may be
needed to avoid collision.

config X86_DYNAMIC_IRQ_STUBS
int "Number of dynamic interrupt stubs"
@@ -249,10 +249,6 @@ static void idt_vector_install(int vector, void *irq_handler)
key = irq_lock();
z_init_irq_gate(&z_x86_idt.entries[vector], CODE_SEG,
(u32_t)irq_handler, 0);
#ifdef CONFIG_MVIC
/* MVIC requires IDT be reloaded if the entries table is ever changed */
z_set_idt(&z_x86_idt);
#endif
irq_unlock(key);
}

@@ -320,10 +320,7 @@ There can be significant differences between the interrupt controllers and the
interrupt concepts across architectures.

For example, x86 has the concept of an :abbr:`IDT (Interrupt Descriptor Table)`
and different interrupt controllers. Although modern systems mostly
standardized on the :abbr:`APIC (Advanced Programmable Interrupt Controller)`,
some small Quark-based systems use the :abbr:`MVIC (Micro-controller Vectored
Interrupt Controller)`. Also, the position of an interrupt in the IDT
and different interrupt controllers. The position of an interrupt in the IDT
determines its priority.

On the other hand, the ARM Cortex-M has the :abbr:`NVIC (Nested Vectored
@@ -389,10 +389,6 @@ scheme, interrupts of priority level 0 will be placed in vectors 32-47, level 1
configures an interrupt it will look for a free vector in the appropriate range
for the requested priority level and set the handler there.

There are some APIC variants (such as MVIC) where priorities cannot be set
by the user and the position in the vector table does correspond to the
IRQ line. Systems like this will enable CONFIG_X86_FIXED_IRQ_MAPPING.

On x86 when an interrupt or exception vector is executed by the CPU, there is
no foolproof way to determine which vector was fired, so a software ISR table
indexed by IRQ line is not used. Instead, the :c:macro:`IRQ_CONNECT` call
@@ -4,7 +4,6 @@ zephyr_sources_ifdef(CONFIG_ARCV2_INTERRUPT_UNIT arcv2_irq_unit.c)
zephyr_sources_ifdef(CONFIG_IOAPIC ioapic_intr.c)
zephyr_sources_ifdef(CONFIG_LOAPIC loapic_intr.c system_apic.c)
zephyr_sources_ifdef(CONFIG_LOAPIC_SPURIOUS_VECTOR loapic_spurious.S)
zephyr_sources_ifdef(CONFIG_MVIC mvic.c)
zephyr_sources_ifdef(CONFIG_PLIC plic.c)
zephyr_sources_ifdef(CONFIG_SHARED_IRQ shared_irq.c)
zephyr_sources_ifdef(CONFIG_EXTI_STM32 exti_stm32.c)
@@ -84,27 +84,6 @@ config IOAPIC_MASK_RTE

endif #LOAPIC

config MVIC
bool "Intel Quark D2000 Interrupt Controller (MVIC)"
depends on X86
select X86_FIXED_IRQ_MAPPING
help
The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is
configured by default to support 32 external interrupt lines. Unlike the
traditional IA LAPIC/IOAPIC, the interrupt vectors in MVIC are fixed and
not programmable. In addition, the priorities of these interrupt
lines are also fixed.

config MVIC_TIMER_IRQ
int "IRQ line to use for timer interrupt"
range 0 15
default 10
depends on MVIC
help
Specify the IRQ line to use for the timer interrupt. This should be
an IRQ line unused by any hardware. If nested interrupts are enabled,
higher interrupt lines have priority.

config ARCV2_INTERRUPT_UNIT
bool "ARCv2 Interrupt Unit"
default y

This file was deleted.

@@ -6,7 +6,7 @@
#include <errno.h>

#include <device.h>
#if defined(CONFIG_IOAPIC) || defined(CONFIG_MVIC)
#if defined(CONFIG_IOAPIC)
#include <ioapic.h>
#endif
#include <uart.h>
@@ -44,7 +44,7 @@ endif #HPET_TIMER

menuconfig LOAPIC_TIMER
bool "LOAPIC timer"
depends on (LOAPIC || MVIC) && X86
depends on LOAPIC && X86
help
This option selects LOAPIC timer as a system timer.

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