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board/nsim: Add support of multi-core ARC HS platform in nSIM

Now when SMP support for ARC is available we may introduce a simulation
platform which might be used for testing & development for SMP setups.

One important note is stand-alone nSIM (as well as its "Free" flavour)
doesn't support SMP simulation so we have to switch to use of nSIM via
proprietary MetaWare debugger [1] and so:
 1. We introduce new emulation target "mdb"
 2. It's only possible to run that platform for those who
    have MetaWare tools installed and valid license.

Though QEMU port for ARC is in work at the moment and once we
open that port and it has SMP support we'll switch to it and everybody
will be able to try ARC HS with SMP.

[1] https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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abrodkin authored and ioannisg committed Jul 25, 2019
1 parent 3e0e378 commit 408433d5c74951d4a464089c33a7393bb3b3f14d
@@ -1,9 +1,15 @@
# SPDX-License-Identifier: Apache-2.0

if(${CONFIG_SOC_NSIM_HS_SMP})
set(EMU_PLATFORM mdb)
else()
set(EMU_PLATFORM nsim)
endif()

if(NOT ${CONFIG_SOC_NSIM_HS_SMP})
board_set_flasher_ifnset(arc-nsim)
board_set_debugger_ifnset(arc-nsim)
endif()

if(${CONFIG_SOC_NSIM_EM})
board_runner_args(arc-nsim "--props=nsim_em.props")
@@ -13,16 +13,18 @@ ARC EM or ARC HS based board including the following features:
* ARC internal timer
* a virtual output only console (uart-nsim)

There are three supported board sub-configurations:
There are four supported board sub-configurations:

* ``nsim_em`` which includes normal ARC EM features and ARC MPUv2
* ``nsim_sem`` which includes secure ARC EM features and ARC MPUv3
* ``nsim_hs`` which includes base ARC HS features, i.e. w/o PMU and MMU
* ``nsim_hs_smp`` which includes base ARC HS features in multi-core cluster, still w/o PMU and MMU

For detailed arc features, please refer to
:zephyr_file:`boards/arc/nsim/support/nsim_em.props`,
:zephyr_file:`boards/arc/nsim/support/nsim_sem.props` and
:zephyr_file:`boards/arc/nsim/support/nsim_hs.props`.
:zephyr_file:`boards/arc/nsim/support/nsim_sem.props`,
:zephyr_file:`boards/arc/nsim/support/nsim_hs.props` and
:zephyr_file:`boards/arc/nsim/support/mdb_hs_smp.args`


Hardware
@@ -0,0 +1,31 @@
/*
* Copyright (c) 2019, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/

/dts-v1/;

#include "nsim.dtsi"

/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";

cpus {
#address-cells = <1>;
#size-cells = <0>;

cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};

cpu@1 {
device_type = "cpu";
compatible = "snps,archs";
reg = <1>;
};
};
};
@@ -0,0 +1,11 @@
identifier: nsim_hs_smp
name: Multi-core HS nSIM simulator
type: mcu
simulation: nsim
arch: arc
toolchain:
- zephyr
testing:
ignore_tags:
- net
- bluetooth
@@ -0,0 +1,18 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_ARC=y
CONFIG_CPU_ARCHS=y
CONFIG_SOC_NSIM=y
CONFIG_SOC_NSIM_HS_SMP=y
CONFIG_BOARD_NSIM=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_XIP=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_PRINTK=y
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_ARC_EXCEPTION_DEBUG=y
CONFIG_SMP=y
@@ -0,0 +1,51 @@
-arcv2hs
-core2
-rgf_num_banks=2
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xcode_density
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-Xshift_assist
-Xbarrel_shifter
-Xfpud_div
-Xfpu_mac
-Xtimer0
-Xtimer0_level=1
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-Xstack_check
-interrupts=72
-interrupt_priorities=2
-ext_interrupts=70
-interrupt_base=0x0
-dcache=65536,64,2,a
-dcache_feature=2
-dcache_uncached_region
-dcache_mem_cycles=2
-icache=65536,64,4,a
-icache_feature=2
-arconnect
-connect_ics=1
-connect_ics_num_semas=16
-connect_icm=1
-connect_icm_sram_size=512
-connect_icm_sram_prot=none
-connect_pmu=1
-connect_idu=2
-connect_idu_cirqnum=64
-connect_gfrc=1
-connect_icd=2
-connect_ici=2
-prop=nsim_mem-dev=uart0,base=0xf0000000,irq=0,use_connect=1
-on=nsim_print-sys-arch
-noprofile
-nogoifmain
-instrs_per_pass=10
@@ -0,0 +1,22 @@
# SPDX-License-Identifier: Apache-2.0

find_program(
MDB
mdb
)

if(${CONFIG_SOC_NSIM_HS_SMP})
set(MDB_ARGS mdb_hs_smp.args)
endif()

add_custom_target(run
COMMAND
${MDB} -pset=1 -psetname=core0 -prop=ident=0x00000050 -cmpd=soc
@${BOARD_DIR}/support/${MDB_ARGS} ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} &&
${MDB} -pset=2 -psetname=core1 -prop=ident=0x00000150 -cmpd=soc
@${BOARD_DIR}/support/${MDB_ARGS} ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} &&
NSIM_MULTICORE=1 ${MDB} -multifiles=core0,core1 -cmpd=soc -run -cl
DEPENDS ${logical_target_for_zephyr_elf}
WORKING_DIRECTORY ${APPLICATION_BINARY_DIR}
USES_TERMINAL
)
@@ -25,6 +25,10 @@ config SOC_NSIM_HS
bool "Synopsys ARC HS in nSIM"
select CPU_HAS_FPU

config SOC_NSIM_HS_SMP
bool "Multi-core Synopsys ARC HS in nSIM"
select CPU_HAS_FPU

endchoice

endif #SOC_NSIM
@@ -17,5 +17,6 @@ config UART_CONSOLE_ON_DEV_NAME
source "soc/arc/snps_nsim/Kconfig.defconfig.em"
source "soc/arc/snps_nsim/Kconfig.defconfig.sem"
source "soc/arc/snps_nsim/Kconfig.defconfig.hs"
source "soc/arc/snps_nsim/Kconfig.defconfig.hs_smp"

endif #SOC_NSIM
@@ -0,0 +1,39 @@
#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#

if SOC_NSIM_HS_SMP

config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
default 2

config NUM_IRQS
# must be > the highest interrupt number used
default 88

config RGF_NUM_BANKS
default 2

config SYS_CLOCK_HW_CYCLES_PER_SEC
default 500000

config HARVARD
default y

config ARC_FIRQ
default y

config CACHE_FLUSHING
default y

config ARC_CONNECT
default y

config MP_NUM_CPUS
default 2

endif #SOC_NSIM_HS_SMP
@@ -1,14 +1,45 @@
/* soc.c - system/hardware module for nsim */

/*
* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
* Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/

/**
* This module provides routines to initialize and support board-level hardware
* for the ARC EM Starter kit board.
* for the ARC EM and HS cores in nSIM simulator.
*
* Nothing to be done for now.
*/

#include <device.h>
#include <init.h>
#include "soc.h"

#ifdef CONFIG_SMP
static int arc_nsim_init(struct device *dev)
{
ARG_UNUSED(dev);

u32_t core;
u32_t i;

/* allocate all IDU interrupts to master core */
core = z_arc_v2_core_id();

z_arc_connect_idu_disable();

for (i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) {
z_arc_connect_idu_set_mode(i, ARC_CONNECT_INTRPT_TRIGGER_LEVEL,
ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN);
z_arc_connect_idu_set_dest(i, 1 << core);
z_arc_connect_idu_set_mask(i, 0x0);
}

z_arc_connect_idu_enable();

return 0;
}

SYS_INIT(arc_nsim_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /* CONFIG_SMP */

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