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soc: riscv32: fix zero-riscy zephyr,flash node

For OpenVega board, in the case of the Zero Riscy core,
the flash partition used for the code and data is the
M0 ARM core's 256KB flash region. This is closest to
the RISC core.
The m0_flash node defines where the interrupt vector
is located for the Zero Riscy core, and one needs to
restrict the application so its interrupt vector is
placed accordingly.

Fixes: 34b0516 ("boards: riscv32: rv32m1_vega:
                      enable MCUboot for ri5cy core")

Signed-off-by: Alex Porosanu <>
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alexandru-porosanu-nxp authored and MaureenHelm committed Jul 5, 2019
1 parent ea366e9 commit 453ee5e782caba77fcd76f3ca1464f7dce88642a
Showing with 2 additions and 1 deletion.
  1. +2 −1 boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts
@@ -14,8 +14,9 @@

chosen {
zephyr,sram = &m0_tcm;
zephyr,flash = &zero_riscy_code_partition;
zephyr,flash = &m0_flash;
zephyr,console = &uart0;
zephyr,uart-pipe = &uart0;
zephyr,code-partition = &zero_riscy_code_partition;

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