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style: add braces around if/while statements

Per guidelines, all statements should have braces around them. We do not
have a CI check for this, so a few went in unnoticed.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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nashif authored and carlescufi committed Jun 4, 2019
1 parent 912e117 commit 4c32258606b4a36e78b9b5c61848c1e1ad4ef7ad
Showing with 281 additions and 195 deletions.
  1. +2 −1 arch/riscv32/core/fatal.c
  2. +2 −1 arch/riscv32/core/irq_offload.c
  3. +2 −1 arch/x86_64/core/xuk-stub16.c
  4. +6 −6 drivers/adc/adc_intel_quark_d2000.c
  5. +4 −4 drivers/adc/adc_stm32.c
  6. +19 −11 drivers/audio/intel_dmic.c
  7. +6 −4 drivers/bluetooth/hci/ipm_stm32wb.c
  8. +5 −4 drivers/counter/counter_ll_stm32_rtc.c
  9. +2 −1 drivers/dma/dma_stm32f4x.c
  10. +2 −2 drivers/flash/flash_stm32.c
  11. +0 −1 drivers/flash/soc_flash_nrf.c
  12. +2 −1 drivers/gpio/gpio_cc13xx_cc26xx.c
  13. +3 −2 drivers/gpio/gpio_pcal9535a.c
  14. +45 −26 drivers/gpio/gpio_sifive.c
  15. +17 −8 drivers/gpio/gpio_sx1509b.c
  16. +2 −1 drivers/i2c/i2c_imx.c
  17. +6 −9 drivers/i2c/i2c_ll_stm32_v1.c
  18. +1 −1 drivers/i2c/i2c_ll_stm32_v2.c
  19. +2 −1 drivers/i2c/i2c_mchp_xec.c
  20. +2 −1 drivers/i2c/i2c_qmsi.c
  21. +12 −12 drivers/i2c/i2c_sifive.c
  22. +4 −2 drivers/interrupt_controller/loapic_intr.c
  23. +2 −1 drivers/pcie/msi.c
  24. +3 −2 drivers/pwm/pwm_pca9685.c
  25. +5 −4 drivers/rtc/rtc_ll_stm32.c
  26. +2 −1 drivers/sensor/adt7420/adt7420.c
  27. +0 −1 drivers/sensor/hp206c/hp206c.c
  28. +0 −2 drivers/sensor/th02/th02.c
  29. +4 −4 drivers/serial/uart_imx.c
  30. +2 −2 drivers/serial/uart_liteuart.c
  31. +2 −2 drivers/serial/uart_mcux.c
  32. +2 −2 drivers/serial/uart_mcux_lpsci.c
  33. +2 −2 drivers/serial/uart_mcux_lpuart.c
  34. +2 −2 drivers/serial/uart_miv.c
  35. +6 −4 drivers/serial/uart_ns16550.c
  36. +2 −2 drivers/serial/uart_nsim.c
  37. +2 −2 drivers/serial/uart_psoc6.c
  38. +2 −2 drivers/serial/uart_rv32m1_lpuart.c
  39. +4 −4 drivers/serial/uart_sam.c
  40. +4 −3 drivers/serial/uart_sifive.c
  41. +8 −7 drivers/serial/uart_stellaris.c
  42. +6 −6 drivers/serial/uart_stm32.c
  43. +2 −2 drivers/serial/usart_mcux_lpc.c
  44. +0 −2 drivers/serial/usart_sam.c
  45. +4 −4 drivers/spi/spi_sifive.c
  46. +2 −2 drivers/usb/device/usb_dc_dw.c
  47. +4 −2 drivers/watchdog/wdt_qmsi.c
  48. +2 −1 drivers/watchdog/wdt_sam0.c
  49. +2 −1 drivers/wifi/eswifi/eswifi_core.c
  50. +2 −1 drivers/wifi/eswifi/eswifi_offload.c
  51. +8 −2 lib/libc/minimal/source/stdlib/strtol.c
  52. +5 −1 lib/libc/minimal/source/stdlib/strtoul.c
  53. +13 −5 lib/libc/minimal/source/stdout/prf.c
  54. +4 −2 lib/libc/minimal/source/string/string.c
  55. +3 −2 lib/libc/minimal/source/string/strstr.c
  56. +2 −1 lib/os/printk.c
  57. +4 −2 subsys/bluetooth/host/smp.c
  58. +2 −1 subsys/bluetooth/host/uuid.c
  59. +2 −1 subsys/bluetooth/shell/gatt.c
  60. +0 −1 subsys/cpp/cpp_virtual.c
  61. +5 −2 subsys/net/ip/utils.c
  62. +3 −2 subsys/shell/shell_utils.c
  63. +6 −3 subsys/usb/usb_device.c
@@ -105,8 +105,9 @@ FUNC_NORETURN void z_NanoFatalErrorHandler(unsigned int reason,

z_SysFatalErrorHandler(reason, esf);
/* spin forever */
for (;;)
for (;;) {
__asm__ volatile("nop");
}
}


@@ -21,8 +21,9 @@ void z_irq_do_offload(void)
{
irq_offload_routine_t tmp;

if (!_offload_routine)
if (!_offload_routine) {
return;
}

tmp = _offload_routine;
_offload_routine = NULL;
@@ -56,8 +56,9 @@ void _start16(void)
*/
volatile unsigned short *vga = (unsigned short *)0xb8000;

for (int i = 0; i < 240; i++)
for (int i = 0; i < 240; i++) {
vga[i] = 0xcc20;
}

/* Spin again waiting on the BSP processor to give us a stack. We
* won't use it until the entry code of stub32, but we want to
@@ -136,8 +136,8 @@ static void adc_quark_d2000_set_mode(struct device *dev, int mode)

/* Set mode and wait for change */
adc_regs->op_mode = mode;
while ((adc_regs->op_mode & ADC_OP_MODE_OM_MASK) != mode)
;
while ((adc_regs->op_mode & ADC_OP_MODE_OM_MASK) != mode) {
}

/* Perform a dummy conversion if going into normal mode */
if (mode >= ADC_MODE_NORM_CAL) {
@@ -149,8 +149,8 @@ static void adc_quark_d2000_set_mode(struct device *dev, int mode)

/* run dummy conversion and wait for completion */
adc_regs->cmd = (ADC_CMD_IE | ADC_CMD_START_SINGLE);
while (!(adc_regs->intr_status & ADC_INTR_STATUS_CC))
;
while (!(adc_regs->intr_status & ADC_INTR_STATUS_CC)) {
}

/* flush FIFO */
adc_regs->sample = ADC_FIFO_CLEAR;
@@ -176,8 +176,8 @@ static void adc_quark_d2000_goto_normal_mode(struct device *dev)

/* start the calibration and wait for completion */
adc_regs->cmd = (ADC_CMD_IE | ADC_CMD_START_CAL);
while (!(adc_regs->intr_status & ADC_INTR_STATUS_CC))
;
while (!(adc_regs->intr_status & ADC_INTR_STATUS_CC)) {
}

/* clear command complete interrupt */
adc_regs->intr_status = ADC_INTR_STATUS_CC;
@@ -460,8 +460,8 @@ static void adc_stm32_calib(struct device *dev)
defined(CONFIG_SOC_SERIES_STM32L0X)
LL_ADC_StartCalibration(adc);
#endif
while (LL_ADC_IsCalibrationOnGoing(adc))
;
while (LL_ADC_IsCalibrationOnGoing(adc)) {
}
}
#endif

@@ -560,8 +560,8 @@ static int adc_stm32_init(struct device *dev)
wait_cycles = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / adc_rate *
LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES;

for (int i = wait_cycles; i >= 0; i--)
;
for (int i = wait_cycles; i >= 0; i--) {
}
#endif

LL_ADC_Enable(adc);
@@ -157,8 +157,9 @@ int find_equal_int16(s16_t idx[], s16_t vec[], int n, int vec_length,
for (i = 0; i < vec_length; i++) {
if (vec[i] == n) {
idx[nresults++] = i;
if (nresults == max_results)
if (nresults == max_results) {
break;
}
}
}

@@ -171,8 +172,9 @@ s16_t find_min_int16(s16_t vec[], int vec_length)
int i;
int min = vec[0];

for (i = 1; i < vec_length; i++)
for (i = 1; i < vec_length; i++) {
min = (vec[i] < min) ? vec[i] : min;
}

return min;
}
@@ -418,8 +420,9 @@ static struct pdm_decim *get_fir(struct dmic_configuration *cfg, int mfir)
struct pdm_decim *fir = NULL;
struct pdm_decim **fir_list;

if (mfir <= 0)
if (mfir <= 0) {
return fir;
}

cic_fs = DMIC_HW_IOCLK / cfg->clkdiv / cfg->mcic;
fs = cic_fs / mfir;
@@ -467,8 +470,9 @@ static int fir_coef_scale(s32_t *fir_scale, int *fir_shift, int add_shift,
/* Scale max. tap value with FIR gain. */
new_amax = Q_MULTSR_32X32((s64_t)amax, fir_gain, 31,
DMIC_FIR_SCALE_Q, DMIC_FIR_SCALE_Q);
if (new_amax <= 0)
if (new_amax <= 0) {
return -EINVAL;
}

/* Get left shifts count to normalize the fractional value as 32 bit.
* We need right shifts count for scaling so need to invert. The
@@ -483,14 +487,16 @@ static int fir_coef_scale(s32_t *fir_scale, int *fir_shift, int add_shift,
*/
*fir_shift = -shift + add_shift;
if (*fir_shift < DMIC_HW_FIR_SHIFT_MIN ||
*fir_shift > DMIC_HW_FIR_SHIFT_MAX)
*fir_shift > DMIC_HW_FIR_SHIFT_MAX) {
return -EINVAL;
}

/* Compensate shift into FIR coef scaler and store as Q4.20. */
if (shift < 0)
if (shift < 0) {
*fir_scale = (fir_gain << -shift);
else
} else {
*fir_scale = (fir_gain >> shift);
}

return 0;
}
@@ -541,10 +547,11 @@ static int select_mode(struct dmic_configuration *cfg,
* factor in 1st element. If FIR A is not used get decimation factors
* from FIR B instead.
*/
if (modes->mfir_a[0] > 0)
if (modes->mfir_a[0] > 0) {
mfir = modes->mfir_a;
else
} else {
mfir = modes->mfir_b;
}

mmin = find_min_int16(mfir, modes->num_of_modes);
count = find_equal_int16(idx, mfir, mmin, modes->num_of_modes, 0);
@@ -599,10 +606,11 @@ static int select_mode(struct dmic_configuration *cfg,
* values.
*/
fir_in_max = (1 << (DMIC_HW_BITS_FIR_INPUT - 1));
if (cfg->cic_shift >= 0)
if (cfg->cic_shift >= 0) {
cic_out_max = g_cic >> cfg->cic_shift;
else
} else {
cic_out_max = g_cic << -cfg->cic_shift;
}

gain_to_fir = (s32_t)((((s64_t)fir_in_max) << DMIC_FIR_SCALE_Q) /
cic_out_max);
@@ -302,8 +302,9 @@ static void start_ble_rf(void)

/* Select LSE clock */
LL_RCC_LSE_Enable();
while (!LL_RCC_LSE_IsReady())
;
while (!LL_RCC_LSE_IsReady()) {
}

/* Select wakeup source of BLE RF */
LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
@@ -312,8 +313,9 @@ static void start_ble_rf(void)
LL_RCC_LSI1_Disable();
/* Set RNG on HSI48 */
LL_RCC_HSI48_Enable();
while (!LL_RCC_HSI48_IsReady())
;
while (!LL_RCC_HSI48_IsReady()) {
}

LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
}

@@ -269,8 +269,9 @@ static int rtc_stm32_init(struct device *dev)
#if defined(CONFIG_COUNTER_RTC_STM32_CLOCK_LSI)

LL_RCC_LSI_Enable();
while (LL_RCC_LSI_IsReady() != 1)
;
while (LL_RCC_LSI_IsReady() != 1) {
}

LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSI);

#else /* CONFIG_COUNTER_RTC_STM32_CLOCK_LSE */
@@ -286,8 +287,8 @@ static int rtc_stm32_init(struct device *dev)
LL_RCC_LSE_Enable();

/* Wait until LSE is ready */
while (LL_RCC_LSE_IsReady() != 1)
;
while (LL_RCC_LSE_IsReady() != 1) {
}

LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);

@@ -508,8 +508,9 @@ static int dma_stm32_stop(struct device *dev, u32_t id)

/* Disable stream */
ret = dma_stm32_disable_stream(ddata, id);
if (ret)
if (ret) {
return ret;
}

/* Clear remanent IRQs from previous transfers */
irqstatus = dma_stm32_irq_status(ddata, id);
@@ -45,8 +45,8 @@ static inline void flash_stm32_sem_take(struct device *dev)
{

#ifdef CONFIG_SOC_SERIES_STM32WBX
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID))
;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
}
#endif /* CONFIG_SOC_SERIES_STM32WBX */

k_sem_take(&FLASH_STM32_PRIV(dev)->sem, K_FOREVER);
@@ -128,7 +128,6 @@ static inline bool is_addr_valid(off_t addr, size_t len)
static void nvmc_wait_ready(void)
{
while (!nrfx_nvmc_write_done_check()) {
;
}
}

@@ -29,8 +29,9 @@ static int gpio_cc13xx_cc26xx_config(struct device *port, int access_op,
{
u32_t config;

if (access_op != GPIO_ACCESS_BY_PIN)
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}

__ASSERT_NO_MSG(pin < NUM_IO_MAX);

@@ -60,10 +60,11 @@ static inline int has_i2c_master(struct device *dev)
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
struct device * const i2c_master = drv_data->i2c_master;

if (i2c_master)
if (i2c_master) {
return 1;
else
} else {
return 0;
}
}

/**

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