From 5a00895ebcbc00bd27a9a0d64ec681e95a13e846 Mon Sep 17 00:00:00 2001 From: Prashanth S Date: Tue, 27 Jun 2023 18:56:50 +0530 Subject: [PATCH] drivers: interrupt-controller: Add VIM Interrupt Controller support Add TI VIM (Vectored Interrupt Manager) interrupt controller support. VIM is a TI specific custom interrupt controller for ARM cores. In J721E soc, VIM aggregates interrupts to Cortex R5 cores. TRM for J721e https://www.ti.com/lit/zip/spruil1 File: spruil1c.pdf VIM: section 6.3.3.6 Signed-off-by: Prashanth S --- drivers/interrupt_controller/CMakeLists.txt | 1 + drivers/interrupt_controller/Kconfig | 2 + drivers/interrupt_controller/Kconfig.vim | 16 + drivers/interrupt_controller/intc_vim.c | 151 ++++++++ dts/bindings/interrupt-controller/ti,vim.yaml | 22 ++ .../drivers/interrupt_controller/intc_vim.h | 344 ++++++++++++++++++ .../dt-bindings/interrupt-controller/ti-vim.h | 17 + .../testsuite/include/zephyr/interrupt_util.h | 9 + 8 files changed, 562 insertions(+) create mode 100644 drivers/interrupt_controller/Kconfig.vim create mode 100644 drivers/interrupt_controller/intc_vim.c create mode 100644 dts/bindings/interrupt-controller/ti,vim.yaml create mode 100644 include/zephyr/drivers/interrupt_controller/intc_vim.h create mode 100644 include/zephyr/dt-bindings/interrupt-controller/ti-vim.h diff --git a/drivers/interrupt_controller/CMakeLists.txt b/drivers/interrupt_controller/CMakeLists.txt index 5864ff4b550352..90163e7eaa5b23 100644 --- a/drivers/interrupt_controller/CMakeLists.txt +++ b/drivers/interrupt_controller/CMakeLists.txt @@ -30,6 +30,7 @@ zephyr_library_sources_ifdef(CONFIG_INTC_ESP32 intc_esp32.c) zephyr_library_sources_ifdef(CONFIG_INTC_ESP32C3 intc_esp32c3.c) zephyr_library_sources_ifdef(CONFIG_SWERV_PIC intc_swerv_pic.c) zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ intc_vexriscv_litex.c) +zephyr_library_sources_ifdef(CONFIG_VIM intc_vim.c) zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC intc_nuclei_eclic.c) zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ intc_eirq_nxp_s32.c) zephyr_library_sources_ifdef(CONFIG_XMC4XXX_INTC intc_xmc4xxx.c) diff --git a/drivers/interrupt_controller/Kconfig b/drivers/interrupt_controller/Kconfig index 02f11b3571d91e..16ed7d4091072a 100644 --- a/drivers/interrupt_controller/Kconfig +++ b/drivers/interrupt_controller/Kconfig @@ -100,4 +100,6 @@ source "drivers/interrupt_controller/Kconfig.xmc4xxx" source "drivers/interrupt_controller/Kconfig.nxp_pint" +source "drivers/interrupt_controller/Kconfig.vim" + endmenu diff --git a/drivers/interrupt_controller/Kconfig.vim b/drivers/interrupt_controller/Kconfig.vim new file mode 100644 index 00000000000000..19c61255fdc955 --- /dev/null +++ b/drivers/interrupt_controller/Kconfig.vim @@ -0,0 +1,16 @@ +# Copyright (C) 2023 BeagleBoard.org Foundation +# Copyright (C) 2023 S Prashanth +# +# SPDX-License-Identifier: Apache-2.0 + +if CPU_CORTEX_R5 + +config VIM + bool "TI Vectored Interrupt Manager" + default y + depends on DT_HAS_TI_VIM_ENABLED + help + The TI Vectored Interrupt Manager provides hardware assistance for prioritizing + and aggregating the interrupt sources for ARM Cortex-R5 processor cores. + +endif # CPU_CORTEX_R5 diff --git a/drivers/interrupt_controller/intc_vim.c b/drivers/interrupt_controller/intc_vim.c new file mode 100644 index 00000000000000..df4eb4a960523a --- /dev/null +++ b/drivers/interrupt_controller/intc_vim.c @@ -0,0 +1,151 @@ +/* Copyright (C) 2023 BeagleBoard.org Foundation + * Copyright (C) 2023 S Prashanth + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_vim + +#include + +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(vim); + +unsigned int z_vim_irq_get_active(void) +{ + uint32_t irq_group_num, irq_bit_num; + uint32_t actirq, vec_addr; + + /* Reading IRQVEC register, ACTIRQ gets loaded with valid IRQ values */ + vec_addr = sys_read32(VIM_IRQVEC); + + /* ACTIRQ register should be read only after reading IRQVEC register */ + actirq = sys_read32(VIM_ACTIRQ); + + /* Check if the irq number is valid, else return invalid irq number. + * which will be considered as spurious interrupt + */ + if ((actirq & (VIM_ACTIRQ_VALID_MASK)) == 0) { + return CONFIG_NUM_IRQS + 1; + } + + irq_group_num = VIM_GET_IRQ_GROUP_NUM(actirq & VIM_PRIIRQ_NUM_MASK); + irq_bit_num = VIM_GET_IRQ_BIT_NUM(actirq & VIM_PRIIRQ_NUM_MASK); + + /* Ack the interrupt in IRQSTS register */ + sys_write32(BIT(irq_bit_num), VIM_IRQSTS(irq_group_num)); + + if (irq_group_num > VIM_MAX_GROUP_NUM) { + return (CONFIG_NUM_IRQS + 1); + } + + return (actirq & VIM_ACTIRQ_NUM_MASK); +} + +void z_vim_irq_eoi(unsigned int irq) +{ + sys_write32(0, VIM_IRQVEC); +} + +void z_vim_irq_init(void) +{ + uint32_t num_of_irqs = sys_read32(VIM_INFO_INTERRUPTS_MASK); + + LOG_DBG("VIM: Number of IRQs = %u\n", num_of_irqs); +} + +void z_vim_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) +{ + uint32_t irq_group_num, irq_bit_num, regval; + + if (irq > CONFIG_NUM_IRQS || prio > VIM_PRI_INT_MAX || + (flags != IRQ_TYPE_EDGE && flags != IRQ_TYPE_LEVEL)) { + LOG_ERR("%s: Invalid argument irq = %u prio = %u flags = %u\n", + __func__, irq, prio, flags); + return; + } + + sys_write8(prio, VIM_PRI_INT(irq)); + + irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq); + irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq); + + regval = sys_read32(VIM_INTTYPE(irq_group_num)); + + if (flags == IRQ_TYPE_EDGE) { + regval |= (BIT(irq_bit_num)); + } else { + regval &= ~(BIT(irq_bit_num)); + } + + sys_write32(regval, VIM_INTTYPE(irq_group_num)); +} + +void z_vim_irq_enable(unsigned int irq) +{ + uint32_t irq_group_num, irq_bit_num; + + if (irq > CONFIG_NUM_IRQS) { + LOG_ERR("%s: Invalid irq number = %u\n", __func__, irq); + return; + } + + irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq); + irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq); + + sys_write32(BIT(irq_bit_num), VIM_INTR_EN_SET(irq_group_num)); +} + +void z_vim_irq_disable(unsigned int irq) +{ + uint32_t irq_group_num, irq_bit_num; + + if (irq > CONFIG_NUM_IRQS) { + LOG_ERR("%s: Invalid irq number = %u\n", __func__, irq); + return; + } + + irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq); + irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq); + + sys_write32(BIT(irq_bit_num), VIM_INTR_EN_CLR(irq_group_num)); +} + +int z_vim_irq_is_enabled(unsigned int irq) +{ + uint32_t irq_group_num, irq_bit_num, regval; + + if (irq > CONFIG_NUM_IRQS) { + LOG_ERR("%s: Invalid irq number = %u\n", __func__, irq); + return -EINVAL; + } + + irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq); + irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq); + + regval = sys_read32(VIM_INTR_EN_SET(irq_group_num)); + + return !!(regval & (BIT(irq_bit_num))); +} + +void z_vim_arm_enter_irq(int irq) +{ + uint32_t irq_group_num, irq_bit_num; + + if (irq > CONFIG_NUM_IRQS) { + LOG_ERR("%s: Invalid irq number = %u\n", __func__, irq); + return; + } + + irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq); + irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq); + + sys_write32(BIT(irq_bit_num), VIM_RAW(irq_group_num)); +} diff --git a/dts/bindings/interrupt-controller/ti,vim.yaml b/dts/bindings/interrupt-controller/ti,vim.yaml new file mode 100644 index 00000000000000..5af72fea8ec612 --- /dev/null +++ b/dts/bindings/interrupt-controller/ti,vim.yaml @@ -0,0 +1,22 @@ +# Copyright (C) 2023 BeagleBoard.org Foundation +# Copyright (C) 2023 S Prashanth +# +# SPDX-License-Identifier: Apache-2.0 + +description: | + TI Vectored Interrupt Manager is a external interrupt controller + (TI specific IP) which is compatible with R5F VIC port. + +compatible: "ti,vim" + +include: base.yaml + +properties: + reg: + required: true + +interrupt-cells: + - type + - irq + - flags + - priority diff --git a/include/zephyr/drivers/interrupt_controller/intc_vim.h b/include/zephyr/drivers/interrupt_controller/intc_vim.h new file mode 100644 index 00000000000000..c177943b2c8ae3 --- /dev/null +++ b/include/zephyr/drivers/interrupt_controller/intc_vim.h @@ -0,0 +1,344 @@ +/* Copyright (C) 2023 BeagleBoard.org Foundation + * Copyright (C) 2023 S Prashanth + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_INTC_VIM_H_ +#define ZEPHYR_DRIVERS_INTC_VIM_H_ + +#include + +#include +#include +#include + +#define VIM_BASE_ADDR DT_REG_ADDR(DT_INST(0, ti_vim)) + +#define VIM_MAX_IRQ_PER_GROUP (32) +#define VIM_MAX_GROUP_NUM ((uint32_t)(CONFIG_NUM_IRQS / VIM_MAX_IRQ_PER_GROUP)) + +#define VIM_GET_IRQ_GROUP_NUM(n) ((uint32_t)((n) / VIM_MAX_IRQ_PER_GROUP)) +#define VIM_GET_IRQ_BIT_NUM(n) ((uint32_t)((n) % VIM_MAX_IRQ_PER_GROUP)) + +#define VIM_PRI_INT_MAX (15) + +#define VIM_PID (VIM_BASE_ADDR + 0x0000) +#define VIM_INFO (VIM_BASE_ADDR + 0x0004) +#define VIM_PRIIRQ (VIM_BASE_ADDR + 0x0008) +#define VIM_PRIFIQ (VIM_BASE_ADDR + 0x000C) +#define VIM_IRQGSTS (VIM_BASE_ADDR + 0x0010) +#define VIM_FIQGSTS (VIM_BASE_ADDR + 0x0014) +#define VIM_IRQVEC (VIM_BASE_ADDR + 0x0018) +#define VIM_FIQVEC (VIM_BASE_ADDR + 0x001C) +#define VIM_ACTIRQ (VIM_BASE_ADDR + 0x0020) +#define VIM_ACTFIQ (VIM_BASE_ADDR + 0x0024) +#define VIM_DEDVEC (VIM_BASE_ADDR + 0x0030) + +#define VIM_RAW(n) (VIM_BASE_ADDR + (0x400) + ((n) * 0x20)) +#define VIM_STS(n) (VIM_BASE_ADDR + (0x404) + ((n) * 0x20)) +#define VIM_INTR_EN_SET(n) (VIM_BASE_ADDR + (0x408) + ((n) * 0x20)) +#define VIM_INTR_EN_CLR(n) (VIM_BASE_ADDR + (0x40c) + ((n) * 0x20)) +#define VIM_IRQSTS(n) (VIM_BASE_ADDR + (0x410) + ((n) * 0x20)) +#define VIM_FIQSTS(n) (VIM_BASE_ADDR + (0x414) + ((n) * 0x20)) +#define VIM_INTMAP(n) (VIM_BASE_ADDR + (0x418) + ((n) * 0x20)) +#define VIM_INTTYPE(n) (VIM_BASE_ADDR + (0x41c) + ((n) * 0x20)) +#define VIM_PRI_INT(n) (VIM_BASE_ADDR + (0x1000) + ((n) * 0x4)) +#define VIM_VEC_INT(n) (VIM_BASE_ADDR + (0x2000) + ((n) * 0x4)) + +/* RAW */ + +#define VIM_GRP_RAW_STS_MASK (BIT_MASK(32)) +#define VIM_GRP_RAW_STS_SHIFT (0x00000000U) +#define VIM_GRP_RAW_STS_RESETVAL (0x00000000U) +#define VIM_GRP_RAW_STS_MAX (BIT_MASK(32)) + +#define VIM_GRP_RAW_RESETVAL (0x00000000U) + +/* STS */ + +#define VIM_GRP_STS_MSK_MASK (BIT_MASK(32)) +#define VIM_GRP_STS_MSK_SHIFT (0x00000000U) +#define VIM_GRP_STS_MSK_RESETVAL (0x00000000U) +#define VIM_GRP_STS_MSK_MAX (BIT_MASK(32)) + +#define VIM_GRP_STS_RESETVAL (0x00000000U) + +/* INTR_EN_SET */ + +#define VIM_GRP_INTR_EN_SET_MSK_MASK (BIT_MASK(32)) +#define VIM_GRP_INTR_EN_SET_MSK_SHIFT (0x00000000U) +#define VIM_GRP_INTR_EN_SET_MSK_RESETVAL (0x00000000U) +#define VIM_GRP_INTR_EN_SET_MSK_MAX (BIT_MASK(32)) + +#define VIM_GRP_INTR_EN_SET_RESETVAL (0x00000000U) + +/* INTR_EN_CLR */ + +#define VIM_GRP_INTR_EN_CLR_MSK_MASK (BIT_MASK(32)) +#define VIM_GRP_INTR_EN_CLR_MSK_SHIFT (0x00000000U) +#define VIM_GRP_INTR_EN_CLR_MSK_RESETVAL (0x00000000U) +#define VIM_GRP_INTR_EN_CLR_MSK_MAX (BIT_MASK(32)) + +#define VIM_GRP_INTR_EN_CLR_RESETVAL (0x00000000U) + +/* IRQSTS */ + +#define VIM_GRP_IRQSTS_MSK_MASK (BIT_MASK(32)) +#define VIM_GRP_IRQSTS_MSK_SHIFT (0x00000000U) +#define VIM_GRP_IRQSTS_MSK_RESETVAL (0x00000000U) +#define VIM_GRP_IRQSTS_MSK_MAX (BIT_MASK(32)) + +#define VIM_GRP_IRQSTS_RESETVAL (0x00000000U) + +/* FIQSTS */ + +#define VIM_GRP_FIQSTS_MSK_MASK (BIT_MASK(32)) +#define VIM_GRP_FIQSTS_MSK_SHIFT (0x00000000U) +#define VIM_GRP_FIQSTS_MSK_RESETVAL (0x00000000U) +#define VIM_GRP_FIQSTS_MSK_MAX (BIT_MASK(32)) + +#define VIM_GRP_FIQSTS_RESETVAL (0x00000000U) + +/* INTMAP */ + +#define VIM_GRP_INTMAP_MSK_MASK (BIT_MASK(32)) +#define VIM_GRP_INTMAP_MSK_SHIFT (0x00000000U) +#define VIM_GRP_INTMAP_MSK_RESETVAL (0x00000000U) +#define VIM_GRP_INTMAP_MSK_MAX (BIT_MASK(32)) + +#define VIM_GRP_INTMAP_RESETVAL (0x00000000U) + +/* INTTYPE */ + +#define VIM_GRP_INTTYPE_MSK_MASK (BIT_MASK(32)) +#define VIM_GRP_INTTYPE_MSK_SHIFT (0x00000000U) +#define VIM_GRP_INTTYPE_MSK_RESETVAL (0x00000000U) +#define VIM_GRP_INTTYPE_MSK_MAX (BIT_MASK(32)) + +#define VIM_GRP_INTTYPE_RESETVAL (0x00000000U) + +/* INT */ + +#define VIM_PRI_INT_VAL_MASK (BIT_MASK(4)) +#define VIM_PRI_INT_VAL_SHIFT (0x00000000U) +#define VIM_PRI_INT_VAL_RESETVAL (BIT_MASK(4)) +#define VIM_PRI_INT_VAL_MAX (BIT_MASK(4)) + +#define VIM_PRI_INT_RESETVAL (BIT_MASK(4)) + +/* INT */ + +#define VIM_VEC_INT_VAL_MASK (0xFFFFFFFCU) +#define VIM_VEC_INT_VAL_SHIFT (0x00000002U) +#define VIM_VEC_INT_VAL_RESETVAL (0x00000000U) +#define VIM_VEC_INT_VAL_MAX (BIT_MASK(30)) + +#define VIM_VEC_INT_RESETVAL (0x00000000U) + +/* INFO */ + +#define VIM_INFO_INTERRUPTS_MASK (BIT_MASK(11)) +#define VIM_INFO_INTERRUPTS_SHIFT (0x00000000U) +#define VIM_INFO_INTERRUPTS_RESETVAL (0x00000400U) +#define VIM_INFO_INTERRUPTS_MAX (BIT_MASK(11)) + +#define VIM_INFO_RESETVAL (0x00000400U) + +/* PRIIRQ */ + +#define VIM_PRIIRQ_VALID_MASK (0x80000000U) +#define VIM_PRIIRQ_VALID_SHIFT (BIT_MASK(5)) +#define VIM_PRIIRQ_VALID_RESETVAL (0x00000000U) +#define VIM_PRIIRQ_VALID_MAX (0x00000001U) + +#define VIM_PRIIRQ_VALID_VAL_TRUE (0x1U) +#define VIM_PRIIRQ_VALID_VAL_FALSE (0x0U) + +#define VIM_PRIIRQ_PRI_MASK (0x000F0000U) +#define VIM_PRIIRQ_PRI_SHIFT (0x00000010U) +#define VIM_PRIIRQ_PRI_RESETVAL (0x00000000U) +#define VIM_PRIIRQ_PRI_MAX (BIT_MASK(4)) + +#define VIM_PRIIRQ_NUM_MASK (BIT_MASK(10)) +#define VIM_PRIIRQ_NUM_SHIFT (0x00000000U) +#define VIM_PRIIRQ_NUM_RESETVAL (0x00000000U) +#define VIM_PRIIRQ_NUM_MAX (BIT_MASK(10)) + +#define VIM_PRIIRQ_RESETVAL (0x00000000U) + +/* PRIFIQ */ + +#define VIM_PRIFIQ_VALID_MASK (0x80000000U) +#define VIM_PRIFIQ_VALID_SHIFT (BIT_MASK(5)) +#define VIM_PRIFIQ_VALID_RESETVAL (0x00000000U) +#define VIM_PRIFIQ_VALID_MAX (0x00000001U) + +#define VIM_PRIFIQ_VALID_VAL_TRUE (0x1U) +#define VIM_PRIFIQ_VALID_VAL_FALSE (0x0U) + +#define VIM_PRIFIQ_PRI_MASK (0x000F0000U) +#define VIM_PRIFIQ_PRI_SHIFT (0x00000010U) +#define VIM_PRIFIQ_PRI_RESETVAL (0x00000000U) +#define VIM_PRIFIQ_PRI_MAX (BIT_MASK(4)) + +#define VIM_PRIFIQ_NUM_MASK (BIT_MASK(10)) +#define VIM_PRIFIQ_NUM_SHIFT (0x00000000U) +#define VIM_PRIFIQ_NUM_RESETVAL (0x00000000U) +#define VIM_PRIFIQ_NUM_MAX (BIT_MASK(10)) + +#define VIM_PRIFIQ_RESETVAL (0x00000000U) + +/* IRQGSTS */ + +#define VIM_IRQGSTS_STS_MASK (BIT_MASK(32)) +#define VIM_IRQGSTS_STS_SHIFT (0x00000000U) +#define VIM_IRQGSTS_STS_RESETVAL (0x00000000U) +#define VIM_IRQGSTS_STS_MAX (BIT_MASK(32)) + +#define VIM_IRQGSTS_RESETVAL (0x00000000U) + +/* FIQGSTS */ + +#define VIM_FIQGSTS_STS_MASK (BIT_MASK(32)) +#define VIM_FIQGSTS_STS_SHIFT (0x00000000U) +#define VIM_FIQGSTS_STS_RESETVAL (0x00000000U) +#define VIM_FIQGSTS_STS_MAX (BIT_MASK(32)) + +#define VIM_FIQGSTS_RESETVAL (0x00000000U) + +/* IRQVEC */ + +#define VIM_IRQVEC_ADDR_MASK (0xFFFFFFFCU) +#define VIM_IRQVEC_ADDR_SHIFT (0x00000002U) +#define VIM_IRQVEC_ADDR_RESETVAL (0x00000000U) +#define VIM_IRQVEC_ADDR_MAX (BIT_MASK(30)) + +#define VIM_IRQVEC_RESETVAL (0x00000000U) + +/* FIQVEC */ + +#define VIM_FIQVEC_ADDR_MASK (0xFFFFFFFCU) +#define VIM_FIQVEC_ADDR_SHIFT (0x00000002U) +#define VIM_FIQVEC_ADDR_RESETVAL (0x00000000U) +#define VIM_FIQVEC_ADDR_MAX (BIT_MASK(30)) + +#define VIM_FIQVEC_RESETVAL (0x00000000U) + +/* ACTIRQ */ + +#define VIM_ACTIRQ_VALID_MASK (0x80000000U) +#define VIM_ACTIRQ_VALID_SHIFT (BIT_MASK(5)) +#define VIM_ACTIRQ_VALID_RESETVAL (0x00000000U) +#define VIM_ACTIRQ_VALID_MAX (0x00000001U) + +#define VIM_ACTIRQ_VALID_VAL_TRUE (0x1U) +#define VIM_ACTIRQ_VALID_VAL_FALSE (0x0U) + +#define VIM_ACTIRQ_PRI_MASK (0x000F0000U) +#define VIM_ACTIRQ_PRI_SHIFT (0x00000010U) +#define VIM_ACTIRQ_PRI_RESETVAL (0x00000000U) +#define VIM_ACTIRQ_PRI_MAX (BIT_MASK(4)) + +#define VIM_ACTIRQ_NUM_MASK (BIT_MASK(10)) +#define VIM_ACTIRQ_NUM_SHIFT (0x00000000U) +#define VIM_ACTIRQ_NUM_RESETVAL (0x00000000U) +#define VIM_ACTIRQ_NUM_MAX (BIT_MASK(10)) + +#define VIM_ACTIRQ_RESETVAL (0x00000000U) + +/* ACTFIQ */ + +#define VIM_ACTFIQ_VALID_MASK (0x80000000U) +#define VIM_ACTFIQ_VALID_SHIFT (BIT_MASK(5)) +#define VIM_ACTFIQ_VALID_RESETVAL (0x00000000U) +#define VIM_ACTFIQ_VALID_MAX (0x00000001U) + +#define VIM_ACTFIQ_VALID_VAL_TRUE (0x1U) +#define VIM_ACTFIQ_VALID_VAL_FALSE (0x0U) + +#define VIM_ACTFIQ_PRI_MASK (0x000F0000U) +#define VIM_ACTFIQ_PRI_SHIFT (0x00000010U) +#define VIM_ACTFIQ_PRI_RESETVAL (0x00000000U) +#define VIM_ACTFIQ_PRI_MAX (BIT_MASK(4)) + +#define VIM_ACTFIQ_NUM_MASK (BIT_MASK(10)) +#define VIM_ACTFIQ_NUM_SHIFT (0x00000000U) +#define VIM_ACTFIQ_NUM_RESETVAL (0x00000000U) +#define VIM_ACTFIQ_NUM_MAX (BIT_MASK(10)) + +#define VIM_ACTFIQ_RESETVAL (0x00000000U) + +/* DEDVEC */ + +#define VIM_DEDVEC_ADDR_MASK (0xFFFFFFFCU) +#define VIM_DEDVEC_ADDR_SHIFT (0x00000002U) +#define VIM_DEDVEC_ADDR_RESETVAL (0x00000000U) +#define VIM_DEDVEC_ADDR_MAX (BIT_MASK(30)) + +#define VIM_DEDVEC_RESETVAL (0x00000000U) + +/* + * VIM Driver Interface Functions + */ + +/** + * @brief Get active interrupt ID. + * + * @return Returns the ID of an active interrupt. + */ +unsigned int z_vim_irq_get_active(void); + +/** + * @brief Signal end-of-interrupt. + * + * @param irq interrupt ID. + */ +void z_vim_irq_eoi(unsigned int irq); + +/** + * @brief Interrupt controller initialization. + */ +void z_vim_irq_init(void); + +/** + * @brief Configure priority, irq type for the interrupt ID. + * + * @param irq interrupt ID. + * @param prio interrupt priority. + * @param flags interrupt flags. + */ +void z_vim_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags); + +/** + * @brief Enable Interrupt. + * + * @param irq interrupt ID. + */ +void z_vim_irq_enable(unsigned int irq); + +/** + * @brief Disable Interrupt. + * + * @param irq interrupt ID. + */ +void z_vim_irq_disable(unsigned int irq); + +/** + * @brief Check if an interrupt is enabled. + * + * @param irq interrupt ID. + * + * @retval 0 If interrupt is disabled. + * @retval 1 If interrupt is enabled. + */ +int z_vim_irq_is_enabled(unsigned int irq); + +/** + * @brief Raise a software interrupt. + * + * @param irq interrupt ID. + */ +void z_vim_arm_enter_irq(int irq); + +#endif /* ZEPHYR_DRIVERS_INTC_VIM_H_ */ diff --git a/include/zephyr/dt-bindings/interrupt-controller/ti-vim.h b/include/zephyr/dt-bindings/interrupt-controller/ti-vim.h new file mode 100644 index 00000000000000..30485bd20e6947 --- /dev/null +++ b/include/zephyr/dt-bindings/interrupt-controller/ti-vim.h @@ -0,0 +1,17 @@ +/* Copyright (C) 2023 BeagleBoard.org Foundation + * Copyright (C) 2023 S Prashanth + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DT_BINDING_TI_VIM_H +#define __DT_BINDING_TI_VIM_H + +#include + +#define IRQ_TYPE_LEVEL BIT(1) +#define IRQ_TYPE_EDGE BIT(2) + +#define IRQ_DEFAULT_PRIORITY 0xf + +#endif /* __DT_BINDING_TI_VIM_H */ diff --git a/subsys/testsuite/include/zephyr/interrupt_util.h b/subsys/testsuite/include/zephyr/interrupt_util.h index 68f2632235f8c2..deaf148e1c0e98 100644 --- a/subsys/testsuite/include/zephyr/interrupt_util.h +++ b/subsys/testsuite/include/zephyr/interrupt_util.h @@ -197,6 +197,15 @@ static inline void trigger_irq(int irq) z_mips_enter_irq(irq); } +#elif defined(CONFIG_CPU_CORTEX_R5) && defined(CONFIG_VIM) + +extern void z_vim_arm_enter_irq(int); + +static inline void trigger_irq(int irq) +{ + z_vim_arm_enter_irq(irq); +} + #else /* So far, Nios II does not support this */ #define NO_TRIGGER_FROM_SW