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dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values

Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0
binding. The new binding adds a required riscv,ndev property, which
gives the number of external interrupts supported.

Use the new binding for microsemi-miv.dtsi (with a value of 31 for
riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf)
and riscv32-fe310.dtsi (which already assigns riscv,ndev).

Also remove a spurious riscv,ndev assignment from
riscv32-litex-vexriscv.dtsi.

Also make edtlib and the old scripts/dts/ scripts replace '.' in
compatible strings with '_' when generating identifiers.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
  • Loading branch information...
ulfalizer authored and carlescufi committed Aug 1, 2019
1 parent e81332d commit 5d0db517b995f69e863a651423bedc79a9e2a40f
@@ -42,7 +42,7 @@ void riscv_plic_irq_enable(u32_t irq)
u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;

key = irq_lock();
en += (plic_irq >> 5);
@@ -68,7 +68,7 @@ void riscv_plic_irq_disable(u32_t irq)
u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;

key = irq_lock();
en += (plic_irq >> 5);
@@ -88,7 +88,7 @@ void riscv_plic_irq_disable(u32_t irq)
int riscv_plic_irq_is_enabled(u32_t irq)
{
volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;

en += (plic_irq >> 5);
@@ -109,14 +109,14 @@ int riscv_plic_irq_is_enabled(u32_t irq)
void riscv_plic_set_priority(u32_t irq, u32_t priority)
{
volatile u32_t *prio =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_PRIO_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;

/* Can set priority only for PLIC-specific interrupt line */
if (irq <= RISCV_MAX_GENERIC_IRQ)
return;

if (priority > DT_INST_0_RISCV_PLIC0_RISCV_MAX_PRIORITY)
priority = DT_INST_0_RISCV_PLIC0_RISCV_MAX_PRIORITY;
if (priority > DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY)
priority = DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY;

prio += (irq - RISCV_MAX_GENERIC_IRQ);
*prio = priority;
@@ -140,7 +140,7 @@ int riscv_plic_get_irq(void)
static void plic_irq_handler(void *arg)
{
volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *) DT_INST_0_RISCV_PLIC0_REG_BASE_ADDRESS;
(volatile struct plic_regs_t *) DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS;

u32_t irq;
struct _isr_table_entry *ite;
@@ -186,11 +186,11 @@ static int plic_init(struct device *dev)
ARG_UNUSED(dev);

volatile u32_t *en =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
volatile u32_t *prio =
(volatile u32_t *)DT_INST_0_RISCV_PLIC0_PRIO_BASE_ADDRESS;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;
volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *)DT_INST_0_RISCV_PLIC0_REG_BASE_ADDRESS;
(volatile struct plic_regs_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS;
int i;

/* Ensure that all interrupts are disabled initially */
@@ -13,9 +13,6 @@ inherits:
!include base.yaml

properties:
compatible:
constraint: "riscv,plic0"

reg:
category: required

@@ -0,0 +1,18 @@
# Copyright (c) 2018, SiFive Inc.
#
# SPDX-License-Identifier: Apache-2.0

title: SiFive PLIC
description: SiFive RISCV-V platform-local interrupt controller

inherits:
!include riscv,plic0.yaml

properties:
compatible:
constraint: "sifive,plic-1.0.0"

riscv,ndev:
type: int
description: Number of external interrupts supported
category: required
@@ -44,14 +44,15 @@

plic: interrupt-controller@40000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
compatible = "sifive,plic-1.0.0";
interrupt-controller;
interrupts-extended = <&hlic 11>;
reg = <0x40000000 0x2000
0x40002000 0x1fe000
0x40200000 0x2000000>;
reg-names = "prio", "irq_en", "reg";
riscv,max-priority = <1>;
riscv,ndev = <31>;
};

uart0: uart@70001000 {
@@ -91,7 +91,7 @@
};
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
compatible = "sifive,plic-1.0.0";
interrupt-controller;
interrupts-extended = <&hlic 11>;
reg = <0xc000000 0x2000
@@ -34,7 +34,6 @@
reg = <0xbc0 0x4 0xfc0 0x4>;
reg-names = "irq_mask", "irq_pending";
riscv,max-priority = <7>;
riscv,ndev = <52>;
};
uart0: serial@e0001800 {
compatible = "litex,uart0";
@@ -51,6 +51,7 @@ def str_to_label(s):
.replace(',', '_') \
.replace('@', '_') \
.replace('/', '_') \
.replace('.', '_') \
.replace('+', 'PLUS') \
.upper()

@@ -524,6 +524,7 @@ def str2ident(s):
.replace(",", "_") \
.replace("@", "_") \
.replace("/", "_") \
.replace(".", "_") \
.replace("+", "PLUS") \
.upper()

@@ -3,13 +3,13 @@

/* PLIC */
#define DT_PLIC_MAX_PRIORITY \
DT_RISCV_PLIC0_40000000_RISCV_MAX_PRIORITY
DT_SIFIVE_PLIC_1_0_0_40000000_RISCV_MAX_PRIORITY
#define DT_PLIC_PRIO_BASE_ADDR \
DT_RISCV_PLIC0_40000000_PRIO_BASE_ADDRESS
DT_SIFIVE_PLIC_1_0_0_40000000_PRIO_BASE_ADDRESS
#define DT_PLIC_IRQ_EN_BASE_ADDR \
DT_RISCV_PLIC0_40000000_IRQ_EN_BASE_ADDRESS
DT_SIFIVE_PLIC_1_0_0_40000000_IRQ_EN_BASE_ADDRESS
#define DT_PLIC_REG_BASE_ADDR \
DT_RISCV_PLIC0_40000000_REG_BASE_ADDRESS
DT_SIFIVE_PLIC_1_0_0_40000000_REG_BASE_ADDRESS

/* UART 0 */
#define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS

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