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dts: riscv32: microsemi-miv: add flash and sram

Add flash and SRAM to the Microsemi MiV device tree.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
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fkokosinski authored and MaureenHelm committed Apr 18, 2019
1 parent ff16799 commit 6299890b0e69fb107213f63379e7f905ca4e1650
Showing with 11 additions and 0 deletions.
  1. +11 −0 dts/riscv32/microsemi-miv.dtsi
@@ -31,6 +31,17 @@
compatible = "microsemi,miv-soc", "simple-bus";
ranges;

flash0: flash@80000000 {
compatible = "soc-nv-flash";
reg = <0x80000000 0x40000>;
};

sram0: memory@80040000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x80040000 0x40000>;
};

plic: interrupt-controller@40000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";

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