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boards/x86/gpmrb: add Gordon Peak MRB board

Add board support (and documentation) for the Intel Gordon Peak
Module Reference Board, a dev board based on the Apollo Lake SoC.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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Charles E. Youse authored and nashif committed Jun 3, 2019
1 parent deb7ff5 commit 69c01d11e557e97fe32c9fe32418cee997e9c57d
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#
# Copyright (c) 2018 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
#

config BOARD_GPMRB
bool "Gordon Peak MRB"
depends on SOC_APOLLO_LAKE
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# Copyright (c) 2019 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0

if BOARD_GPMRB

config BOARD
default "gpmrb"

config BUILD_OUTPUT_STRIPPED
default y

if UART_NS16550

config UART_NS16550_PORT_0
default y

config UART_NS16550_PORT_1
default y

config UART_NS16550_PORT_2
default y

config UART_NS16550_PORT_3
default y

endif # UART_NS16550

if I2C

config I2C_0
default y

config I2C_1
default y

endif # I2C

config SYS_CLOCK_HW_CYCLES_PER_SEC
default 19200000 if HPET_TIMER # guess
default 1100000000 if LOAPIC_TIMER # another guess

endif # BOARD_GPMRB
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.. _gpmrb:

Gordon Peak MRB
###############

Overview
********

The Intel Gordon Peak Module Reference Board (GP MRB) is used in
the automotive industry for the development of in-vehicle applications
such as heads-up displays and entertainment systems.

.. figure:: img/gpmrb.jpg
:width: 500px
:align: center
:alt: Gordon Peak MRB

Gordon Peak MRB

Hardware
********

.. include:: ../../../../soc/x86/apollo_lake/doc/supported_features.rst

Building and Running Zephyr
***************************

Use the following procedure to boot a Zephyr application on the Gordon Peak
MRB.

Build Zephyr Application
========================

Build a Zephyr application; for instance, to build the ``hello_world``
application for the GP MRB:

.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:tool: all
:board: gpmrb
:goals: build

This will create a standard ELF binary application file named
:file:`zephyr.elf`, and the same binary with debugging information
removed named :file:`zephyr.strip`. Because of the limited firmware
flash area on board, we'll use the smaller, stripped version.

Move the stripped application to your home directory for use
in the next steps:

.. code-block:: console

$ cp zephyr/zephyr.strip ~

Get the Leaf Hill Firmware Files
================================

The Slim Bootloader (see the next step) requires binary firmware images
specific to the GP MRB: in this instance, the "Leaf Hill" firmware.
This can be downloaded from Intel:

.. code-block:: console

$ cd
$ wget https://firmware.intel.com/sites/default/files/leafhill-0.70-firmwareimages.zip
$ unzip leafhill-0.70-firmwareimages.zip

There will now be two files named :file:`LEAFHILD.X64.0070.D01.1805070344.bin`
and :file:`LEAFHILD.X64.0070.R01.1805070352.bin` or similar in your home
directory, which are the debug (``D``) and release (``R``) versions of the
binary packages, respectively. Make note of the release (:file:`*R01*`)
file name for the next step.

Build Slim Bootloader
=====================

Zephyr runs as a direct payload of the Slim Bootloader (SBL). For more
complete information on SBL, including comprehensive build instructions,
see the `Slim Bootloader <https://slimbootloader.github.io/>`_ site.

.. code-block:: console

$ cd
$ git clone https://github.com/slimbootloader/slimbootloader.git
$ cd slimbootloader
$ python BuildLoader.py clean
$ python BuildLoader.py build apl -p ~/zephyr.strip

Now that the SBL has been built with the Zephyr application as the direct
payload, we need to "stitch" together SBL with the board firmware package.
Be sure to replace the release filename with the one noted in the previous
step:

.. code-block:: console

$ python Platform/ApollolakeBoardPkg/Script/StitchLoader.py \
-i ~/LEAFHILD.X64.0070.R01.1805070352.bin \
-s Outputs/apl/Stitch_Components.zip \
-o ~/sbl.bin

Now the file :file:`sbl.bin` in your home directory contains a firmware
image with SBL and the Zephyr application, ready to flash to the GP MRB.

Flash the Image
===============

Connect the IOC to the GP MRB and connect the USB cable to your development
machine. Then, using the Intel Platform Flash tools supplied with your
board, flash the firmware:

.. code-block:: console

$ sudo /opt/intel/platformflashtool/bin/ias-spi-programmer --write ~/sbl.bin

.. note::

Refer to the instructions with the IOC and/or GP MRB for further
information on flashing the firmware.

Launch Zephyr
=============

Connect to UART 2 on the GP MRB and press the "ignition" button. After
initialization messages, you will the Zephyr banner:

.. code-block:: console

***** Booting Zephyr OS v1.14.0-rc3-1254-g2a086e4c13ef *****
Hello World! gpmrb


Congratulations! You are running Zephyr on your Gordon Peak MRB!
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/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/

/dts-v1/;

#include <mem.h>

#define DT_FLASH_SIZE DT_SIZE_K(8912)
#define DT_SRAM_SIZE DT_SIZE_M(2048)

#include <apollo_lake.dtsi>

/ {
model = "gpmrb";
compatible = "intel,apollo_lake";

chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart2;
zephyr,shell-uart = &uart2;
zephyr,bt-uart = &uart1;
zephyr,uart-pipe = &uart1;
zephyr,bt-mon-uart = &uart1;
};
};

&uart0 { interrupts = <4 IRQ_TYPE_LEVEL_LOW 3>; };
&uart1 { interrupts = <5 IRQ_TYPE_LEVEL_LOW 3>; };
&uart2 { interrupts = <6 IRQ_TYPE_LEVEL_LOW 3>; };
&uart3 { interrupts = <7 IRQ_TYPE_LEVEL_LOW 3>; };
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identifier: gpmrb
name: Gordon Peak MRB
type: mcu
arch: x86
toolchain:
- zephyr
ram: 256
testing:
ignore_tags:
- net
- bluetooth
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# Copyright (c) 2019 Intel Corporation
# SPDX-License-Identifier: Apache-2.0

CONFIG_X86=y
CONFIG_SOC_APOLLO_LAKE=y
CONFIG_BOARD_GPMRB=y
CONFIG_HPET_TIMER=y
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_I2C=y
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Supported Features
==================

In addition to the standard architecture devices (HPET, local and I/O APICs,
etc.), Zephyr supports the following Apollo Lake-specific SoC devices:

* HSUART

* GPIO

* I2C

HSUART High-Speed Serial Port Support
-------------------------------------

The Apollo Lake UARTs are NS16550-compatible, with "high-speed" capability.

Baud rates beyond 115.2kbps (up to 3.6864Mbps) are supported, with additional
configuration. The UARTs are fed a master clock which is fed into a PLL which
in turn outputs the baud master clock. The PLL is controlled by a per-UART
32-bit register called ``PRV_CLOCK_PARAMS`` (aka the ``PCP``), the format of
which is:

+--------+---------+--------+--------+
| [31] | [30:16] | [15:1] | [0] |
+========+=========+========+========+
| enable | ``m`` | ``n`` | toggle |
+--------+---------+--------+--------+

The resulting baud master clock frequency is ``(n/m)`` * master.

Typically, the master clock is 100MHz, and the firmware by default sets
the ``PCP`` to ``0x3d090240``, i.e., ``n = 288``, ``m = 15625``, which
results in the de-facto standard 1.8432MHz master clock and a max baud rate
of 115.2k. Higher baud rates are enabled by changing the PCP and telling
Zephyr what the resulting master clock is.

Use devicetree to set the value of the ``PRV_CLOCK_PARAMS`` register in
the UART block of interest. Typically an overlay ``up_squared.overlay``
would be present in the application directory, and would look something
like this:

.. code-block:: console

/ {
soc {
uart@0 {
pcp = <0x3d090900>;
clock-frequency = <7372800>;
current-speed = <230400>;
};
};
};

The relevant variables are ``pcp`` (the value to use for ``PRV_CLOCK_PARAMS``),
and ``clock-frequency`` (the resulting baud master clock). The meaning of
``current-speed`` is unchanged, and as usual indicates the initial baud rate.

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