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x86/apollo_lake: add I2C interfaces to devicetree

The Apollo Lake devicetree is augmented with its 8 I2C interfaces.
The default number of dynamic IRQ stubs is increased to deal with
these new interfaces having IRQ vector detection at runtime.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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Charles E. Youse authored and nashif committed May 17, 2019
1 parent 309dfef commit 6b5f05fe20bb5f9d2966b00115026e4e1a913b39
Showing with 120 additions and 0 deletions.
  1. +113 −0 dts/x86/apollo_lake.dtsi
  2. +7 −0 soc/x86/apollo_lake/Kconfig.defconfig
@@ -6,6 +6,7 @@

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/intel-ioapic.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pcie/pcie.h>

/ {
@@ -104,6 +105,118 @@
current-speed = <115200>;
};

i2c0: i2c@0 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x16,0) PCIE_ID(0x8086,0x5aac)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_0";

status = "disabled";
};

i2c1: i2c@1 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x16,1) PCIE_ID(0x8086,0x5aae)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_1";

status = "disabled";
};

i2c2: i2c@2 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x16,2) PCIE_ID(0x8086,0x5ab0)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_2";

status = "disabled";
};

i2c3: i2c@3 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x16,3) PCIE_ID(0x8086,0x5ab2)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_3";

status = "disabled";
};

i2c4: i2c@4 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x17,0) PCIE_ID(0x8086,0x5ab4)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_4";

status = "disabled";
};

i2c5: i2c@5 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x17,1) PCIE_ID(0x8086,0x5ab6)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_5";

status = "disabled";
};

i2c6: i2c@6 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x17,2) PCIE_ID(0x8086,0x5ab8)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_6";

status = "disabled";
};

i2c7: i2c@7 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x17,3) PCIE_ID(0x8086,0x5aba)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_7";

status = "disabled";
};

gpio: gpio@d0c50000 {
compatible = "intel,apl-gpio";
reg = <0xd0c50000 0x1000>,
@@ -19,6 +19,13 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config CLFLUSH_DETECT
default y if CACHE_FLUSHING

if DYNAMIC_INTERRUPTS

config X86_DYNAMIC_IRQ_STUBS
default 16

endif # DYNAMIC_INTERRUPTS

if UART_NS16550

config UART_NS16550_PORT_0

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