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stm32: clock_control: Enforce HCLK prescaler value

STM32 clock control subsystem allows to configure a different
frequency value for core clock (SYSCLK) and AHB clock (HCLK).
Though, it is HCLK which is used to feed Cortex Systick timer
which  is used in zephyr as reference system clock.
If HCLK frequency is configured to a different value from SYSCLK
frequency, whole system is exposed to desynchro between zephyr clock
subsytem and STM32 HW configuration.
To prevent this, and until zephyr clock subsystem is changed to be
aware of this potential configuration, enforce AHB prescaler value
to 1 (which is current default value in use for all STM32 based
boards).

On STM32H7, enforce D1CPRE which fills the same role as ABH precaler.

On STM32MP1, the equivalent setting is done on A7 core, so it is
not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC
is set with the 'mlhclk_ck' clock frequency value. Update
matching boards documentation.

Fixes #17188

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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erwango authored and galak committed Aug 2, 2019
1 parent fe2d858 commit 77db273f6f84b3d94d34b5e72070ec6bc31e41cf
@@ -3,7 +3,7 @@ CONFIG_BOARD_96B_AVENGER96=y
CONFIG_SOC_SERIES_STM32MP1X=y
CONFIG_SOC_STM32MP15_M4=y
CONFIG_CORTEX_M_SYSTICK=y
# 209 MHz system clock
# 209 MHz system clock (mlhclk_ck)
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=209000000

# enable GPIO
@@ -185,7 +185,8 @@ Default Zephyr Peripheral Mapping:
System Clock
------------

The Cortex®-M4 Core is configured to run at a 209 MHz clock speed.
The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value
must match the configured mlhclk_ck frequency.

Serial Port
-----------
@@ -199,7 +199,8 @@ Default Zephyr Peripheral Mapping:
System Clock
------------

The Cortex®-M4 Core is configured to run at a 209 MHz clock speed.
The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value
must match the configured mlhclk_ck frequency.

Serial Port
-----------
@@ -3,7 +3,7 @@ CONFIG_BOARD_STM32MP157C_DK2=y
CONFIG_SOC_SERIES_STM32MP1X=y
CONFIG_SOC_STM32MP15_M4=y
CONFIG_CORTEX_M_SYSTICK=y
# 209 MHz system clock
# 209 MHz system clock (mlhclk_ck)
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=209000000

# enable GPIO
@@ -34,6 +34,17 @@
#define __LL_RCC_CALC_HCLK_FREQ __LL_RCC_CALC_HCLK1_FREQ
#endif /* CONFIG_SOC_SERIES_STM32F0X */

#if CONFIG_CLOCK_STM32_AHB_PRESCALER > 1
/*
* AHB prescaler allows to set a HCLK frequency (feeding cortex systick)
* lower than SYSCLK frequency (actual core frequency).
* Though, zephyr doesn't make a difference today between these two clocks.
* So, changing this prescaler is not allowed until it is made possible to
* use them independently in zephyr clock subsystem.
*/
#error "AHB presacler can't be higher than 1"
#endif

/**
* @brief fill in AHB/APB buses configuration structure
*/
@@ -29,6 +29,18 @@
#define z_apb4_prescaler(v) LL_RCC_APB4_DIV_ ## v
#define apb4_prescaler(v) z_apb4_prescaler(v)

#if defined(CONFIG_CPU_CORTEX_M7)
#if CONFIG_CLOCK_STM32_D1CPRE > 1
/*
* D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
* Though, zephyr doesn't make a difference today between these two clocks.
* So, changing this prescaler is not allowed until it is made possible to
* use them independently in zephyr clock subsystem.
*/
#error "D1CPRE presacler can't be higher than 1"
#endif
#endif /* CONFIG_CPU_CORTEX_M7 */

/**
* @brief fill in AHB/APB buses configuration structure
*/

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