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ext : hal : microchip Header updates for MEC1501

Updated MEC1501 HAL headers. Add interrupt routing defines for timers.
Fix eSPI virtual wire source access. Add new headers for Port80
capture and TFDP.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
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scottwcpg authored and nashif committed Jun 7, 2019
1 parent d4083b6 commit 7808b6e92c51dbf362b217fd732efdcec38525a9
@@ -303,9 +303,9 @@ typedef enum IRQn {
*/

/* Peripheral and SRAM base address */
#define CODE_SRAM_BASE (0x000E0000UL) /*!< (CODE SRAM ) Base Address */
#define DATA_SRAM_BASE (0x00118000UL) /*!< (DATA SRAM ) Base Address */
#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
#define CODE_SRAM_BASE 0x000E0000UL /*!< (CODE SRAM ) Base Address */
#define DATA_SRAM_BASE 0x00118000UL /*!< (DATA SRAM ) Base Address */
#define PERIPH_BASE 0x40000000UL /*!< (Peripheral) Base Address */

/* Peripheral memory map */
#define WDT_BASE (PERIPH_BASE + 0x0400ul) /*!< (WDT0 ) Base Address */
@@ -445,8 +445,10 @@ typedef enum IRQn {
#include "component/led.h"
#include "component/mailbox.h"
#include "component/pcr.h"
#include "component/port80cap.h"
#include "component/port92.h"
#include "component/smb.h"
#include "component/tfdp.h"
#include "component/timer.h"
#include "component/uart.h"
#include "component/vbat.h"
@@ -464,8 +466,8 @@ typedef enum IRQn {
#define B16TMR0_REGS ((BTMR_Type *) B16TMR0_BASE)
#define B16TMR1_REGS ((BTMR_Type *) B16TMR1_BASE)
#define B32TMR0_REGS ((BTMR_Type *) B32TMR0_BASE)
#define B32TMR1_REGS ((BTMR_Type *) B32TMR1_BASE)
#define CCT_REGS ((CCT_Type *) CCT_BASE)
#define B32TMR1_REGS ((BTMR_Type *) B32TMR1_BASE)
#define CCT_REGS ((CCT_Type *) (CCT_BASE))

#define DMAM_REGS ((DMAM_Type *) DMA_BASE)
/* Individual DMA channels */
@@ -490,6 +492,8 @@ typedef enum IRQn {

#define RTMR_REGS ((RTMR_Type *) RTMR_BASE)

#define TFDP_REGS ((TFDP_Type *) TFDP_BASE)

#define HTMR0_REGS ((HTMR_Type *) HTMR0_BASE)
#define HTMR1_REGS ((HTMR_Type *) HTMR1_BASE)

@@ -569,14 +573,17 @@ typedef enum IRQn {
#define ESPI_MEM_BM_REGS ((ESPI_MEM_BM_Type *)(ESPI_MEM_BM_BASE))

/* eSPI Virtual Wire registers in IO component */
#define ESPI_IO_VW_REGS ((ESPI_IO_VW_Type *) ESPI_IO_VW_BASE)
#define ESPI_IO_VW_REGS ((ESPI_IO_VW_Type *) (ESPI_IO_VW_BASE))
/* eSPI Virtual Wire registers for each group of 4 VWires */
#define ESPI_M2S_VW_REGS ((ESPI_M2S_VW_Type *) ESPI_VW_BASE)
#define ESPI_M2S_VW_REGS ((ESPI_M2S_VW_Type *) (ESPI_VW_BASE))
#define ESPI_S2M_VW_REGS ((ESPI_S2M_VW_Type *) (ESPI_SMVW_BASE))

#define EMI0_REGS ((EMI_Type *)(EMI0_BASE))
#define EMI1_REGS ((EMI_Type *)(EMI0_BASE))

#define PORT80_CAP0_REGS ((PORT80_CAP_Type *)(P80CAP0_BASE))
#define PORT80_CAP1_REGS ((PORT80_CAP_Type *)(P80CAP1_BASE))

/** @} *//* End of group MEC1501 */

/** @} *//* End of group MCHP */
@@ -262,7 +262,7 @@ typedef struct {
__IOM uint8_t VW_RDY; /*! (@ 0x003D) VW ready */
uint8_t RSVD3[0x102];
__IOM uint32_t VW_ERR_STS; /*! (@ 0x0140) IO Virtual Wire Error */
} ESPI_IO_VW;
} ESPI_IO_VW_Type;

/* Master-to-Slave Virtual Wire 96-bit register */

@@ -328,7 +328,7 @@ typedef struct {
ESPI_MSVW_REG MSVW08;
ESPI_MSVW_REG MSVW09;
ESPI_MSVW_REG MSVW10;
} ESPI_M2S_VW;
} ESPI_M2S_VW_Type;

/* Slave-to-Master Virtual Wire 64-bit register */

@@ -352,7 +352,7 @@ typedef struct {
ESPI_SMVW_REG SMVW08;
ESPI_SMVW_REG SMVW09;
ESPI_SMVW_REG SMVW10;
} ESPI_S2M_VW;
} ESPI_S2M_VW_Type;

/* MSVW helper inline functions */

@@ -415,12 +415,29 @@ mec_espi_msvw_mtos_set(ESPI_MSVW_REG * p, enum espi_vw_rst_src rst_src,
p->MTOS = (rst_src & 0x03u) | ((rst_val & 0x0Fu) << 4);
}

/*
* Set the specified Master-to-Slave VWire's interrupt select field for
* the specified edge, level, or disabled.
* MSVW IRQ_SELECT is a 32-bit register where the four VWire's
* interrupt select fields are located on byte boundaries.
* Param p is a pointer to the 96-bit MSVW register.
* Param src is in [0:3] specifying one of the four VWire's.
* Param isel is the new value for the specified VWire's interrupt
* select field. IRQ_SELECT is the 32-bit word at bits[63:32] in the
* 96-bit MSVW register.
* IRQ_SELECT[3:0] = SRC0_IRQ_SELECT
* IRQ_SELECT[11:8] = SRC1_IRQ_SELECT
* IRQ_SELECT[19:16] = SRC1_IRQ_SELECT
* IRQ_SELECT[27:24] = SRC1_IRQ_SELECT
* The MSVW registers are byte accessible allowing us to avoid a
* read-modify-write.
*/
static __attribute__ ((always_inline))
inline void
mec_espi_msvw_irq_sel_set(ESPI_MSVW_REG * p, enum espi_msvw_src src,
enum espi_msvw_irq_sel isel)
{
volatile uint8_t *psrc = (volatile uint8_t *)p->SRC_IRQ_SEL;
volatile uint8_t *psrc = (volatile uint8_t *)&p->SRC_IRQ_SEL;

*(psrc + (uintptr_t) src) = isel;
}
@@ -436,11 +453,26 @@ inline void mec_espi_msvw_irq_sel_set_all(ESPI_MSVW_REG * p, uint32_t isel_all)
p->SRC_IRQ_SEL = isel_all;
}

/*
* Set the specified Master-to-Slave VWire state.
* MSVW.SRC is a 32-bit component at bits[95:64] where states of the
* four VWire's it controls are located on byte boundaries.
* Param p is a pointer to the 96-bit MSVW register.
* Param src is in [0:3] specifying one of the four VWire's.
* Param src_val is the new VWire state.
* SRC member is the 32-bit word at bits[95:64] in the MSVW structure.
* SRC[3:0] = SRC0 VWire state
* SRC[11:8] = SRC1 VWire state
* SRC[19:16] = SRC1 VWire state
* SRC[27:24] = SRC1 VWire state
* The MSVW registers are byte accessible allowing us to avoid a
* read-modify-write.
*/
static __attribute__ ((always_inline))
inline void
mec_espi_msvw_set(ESPI_MSVW_REG * p, enum espi_msvw_src src, uint8_t src_val)
{
volatile uint8_t *psrc = (volatile uint8_t *)p->SRC;
volatile uint8_t *psrc = (volatile uint8_t *)&p->SRC;

*(psrc + (uintptr_t) src) = src_val;
}
@@ -562,12 +594,40 @@ inline void mec_espi_smvw_set_all_bitmap(ESPI_SMVW_REG * p, uint8_t src_bitmap)
p->SRC = srcs;
}

/*
* Get the specified Slave-to-Master VWire state.
* SMVW.SRC is a 32-bit register located at bits[63:32] where the four
* VWire's it controls are located on byte boundaries.
* Param p is a pointer to the 64-bit SMVW register.
* Param src is in [0:3] specifying one of the four VWire's.
* Param src_val is the new VWire state.
* SRC member is the 32-bit word at bits[63:32] in the SMVW structure.
* SRC[3:0] = SRC0 VWire state
* SRC[11:8] = SRC1 VWire state
* SRC[19:16] = SRC1 VWire state
* SRC[27:24] = SRC1 VWire state
*/
static __attribute__ ((always_inline))
inline uint8_t mec_espi_smvw_get(ESPI_SMVW_REG * p, enum espi_smvw_src src)
{
return (uint8_t) ((p->SRC >> (src << 3)) & 0x01ul);
}

/*
* Set the specified Slave-to-Master VWire state.
* SMVW.SRC is a 32-bit register located at bits[63:32] where the four
* VWire's it controls are located on byte boundaries.
* Param p is a pointer to the 64-bit SMVW register.
* Param src is in [0:3] specifying one of the four VWire's.
* Param src_val is the new VWire state.
* SRC member is the 32-bit word at bits[63:32] in the SMVW structure.
* SRC[3:0] = SRC0 VWire state
* SRC[11:8] = SRC1 VWire state
* SRC[19:16] = SRC1 VWire state
* SRC[27:24] = SRC1 VWire state
* The SMVW registers are byte accessible allowing us to avoid a
* read-modify-write.
*/
static __attribute__ ((always_inline))
inline void
mec_espi_smvw_set(ESPI_SMVW_REG * p, enum espi_smvw_src src, uint8_t new_val)
@@ -154,7 +154,7 @@
* bit[8]==1 system will allow entry to heavy sleep before PLL is locked.
*/
#define MCHP_PCR_SYS_SLP_CTRL_SLP_PLL_LOCK (0ul << 8)
#define MCHP_PCR_SYS_SLP_CTRL_ALLOW_SLP_NO_PLL_LOCK (0ul << 8)
#define MCHP_PCR_SYS_SLP_CTRL_ALLOW_SLP_NO_PLL_LOCK (1ul << 8)

#define MCHP_PCR_SYS_SLP_LIGHT 0x08ul
#define MCHP_PCR_SYS_SLP_HEAVY 0x09ul
@@ -489,6 +489,18 @@ mchp_pcr_periph_slp_ctrl(PCR_ID pcr_id, uint8_t enable)
}
}

static __attribute__ ((always_inline)) inline void
mchp_pcr_periph_reset(PCR_ID pcr_id)
{
uintptr_t raddr = (uintptr_t) (MCHP_PCR_PERIPH_RST0_ADDR);
uint32_t bitpos = (uint32_t) pcr_id & 0x1F;

raddr += ((uint32_t) pcr_id >> 5);
REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR) = MCHP_PCR_RSTEN_UNLOCK;
REG32(raddr) = (1ul << bitpos);
REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR) = MCHP_PCR_RSTEN_LOCK;
}

#endif // #ifndef _DEFS_H
/* end pcr.h */
/** @}
@@ -0,0 +1,152 @@
/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/

/** @file port80cap.h
*MEC1501 Port80 Capture Registers
*/
/** @defgroup MEC1501 Peripherals Port80 Capture
*/

#ifndef _PORT80CAP_H
#define _PORT80CAP_H

#include <stdint.h>
#include <stddef.h>

#include "regaccess.h"

/* ========================================================================*/
/* ================ PORT80 Capture ===========*/
/* ========================================================================*/

#define MCHP_PORT80_CAP_0_BASE_ADDR 0x400F8000ul
#define MCHP_PORT80_CAP_1_BASE_ADDR 0x400F8000ul

#define MCHP_PORT80_CAP_0_GIRQ 15u
#define MCHP_PORT80_CAP_0_GIRQ_POS 22u
#define MCHP_PORT80_CAP_0_GIRQ_VAL (1ul << 22)
#define MCHP_PORT80_CAP_0_NVIC_AGGR 7u
#define MCHP_PORT80_CAP_0_NVIC_DIRECT 62u

#define MCHP_PORT80_CAP_1_GIRQ 15u
#define MCHP_PORT80_CAP_1_GIRQ_POS 23u
#define MCHP_PORT80_CAP_1_GIRQ_VAL (1ul << 23)
#define MCHP_PORT80_CAP_1_NVIC_AGGR 7u
#define MCHP_PORT80_CAP_1_NVIC_DIRECT 63u

/* Port80 Capture receive FIFO number of entries */
#define MCHP_PORT80_CAP_MAX_FIFO_ENTRIES 16u

/*
* HOST_DATA - Write-Only
*/
#define MCHP_PORT80_CAP_HOST_DATA_REG_MASK 0xFFul

/*
* EC_DATA - Read-Only. Read as 32-bit.
* b[7:0] = Read captured data byte from FIFO
* b[31:8] = Timestamp if enabled.
*/
#define MCHP_PORT80_CAP_EC_DATA_REG_MASK 0xFFFFFFFFul
#define MCHP_PORT80_CAP_EC_DATA_POS 0u
#define MCHP_PORT80_CAP_EC_DATA_MASK 0xFFul
#define MCHP_PORT80_CAP_EC_DATA_TIMESTAMP_POS 8u
#define MCHP_PORT80_CAP_EC_DATA_TIMESTAMP_MASK0 0x00FFFFFFul
#define MCHP_PORT80_CAP_EC_DATA_TIMESTAMP_MASK 0xFFFFFF00ul

/*
* Configuration
*/
#define MCHP_PORT80_CAP_CFG_REG_MASK 0xFFul
/* Flush FIFO (Write-Only) */
#define MCHP_PORT80_CAP_CFG_FLUSH_POS 1u
#define MCHP_PORT80_CAP_CFG_FLUSH (1ul << 1)
/* Reset Timestamp (Write-Only) */
#define MCHP_PORT80_CAP_CFG_TSRST_POS 2u
#define MCHP_PORT80_CAP_CFG_TSRST (1ul << 2u)
/* Timestamp clock divider */
#define MCHP_PORT80_CAP_CFG_TSDIV_POS 3u
#define MCHP_PORT80_CAP_CFG_TSDIV_MASK0 0x03ul
#define MCHP_PORT80_CAP_CFG_TSDIV_MASK (0x03ul << 3)
#define MCHP_PORT80_CAP_CFG_TSDIV_6MHZ (0x00ul << 3)
#define MCHP_PORT80_CAP_CFG_TSDIV_3MHZ (0x01ul << 3)
#define MCHP_PORT80_CAP_CFG_TSDIV_1P5MHZ (0x02ul << 3)
#define MCHP_PORT80_CAP_CFG_TSDIV_750KHZ (0x03ul << 3)
/* Timestamp Enable */
#define MCHP_PORT80_CAP_CFG_TSEN_POS 5u
#define MCHP_PORT80_CAP_CFG_TSEN_MASK (1ul << 5)
#define MCHP_PORT80_CAP_CFG_TSEN_ENABLE (1ul << 5)
/* FIFO threshold */
#define MCHP_PORT80_CAP_CFG_FIFO_THR_POS 6u
#define MCHP_PORT80_CAP_CFG_FIFO_THR_MASK0 0x03ul
#define MCHP_PORT80_CAP_CFG_FIFO_THR_MASK (0x03ul << 6)
#define MCHP_PORT80_CAP_CFG_FIFO_THR_1 (0x00ul << 6)
#define MCHP_PORT80_CAP_CFG_FIFO_THR_4 (0x01ul << 6)
#define MCHP_PORT80_CAP_CFG_FIFO_THR_8 (0x02ul << 6)
#define MCHP_PORT80_CAP_CFG_FIFO_THR_14 (0x03ul << 6)

/*
* Status - Read-only does not clear status on read.
*/
#define MCHP_PORT80_CAP_STS_REG_MASK 0x03ul;
/* Bit[0] FIFO not empty. Cleared by FW reading all content from FIFO */
#define MCHP_PORT80_CAP_STS_NOT_EMPTY_POS 0u
#define MCHP_PORT80_CAP_STS_NOT_EMPTY (1ul << 0)
/* Bit[1] Overrun. Host wrote data when FIFO is full */
#define MCHP_PORT80_CAP_STS_OVERRUN_POS 1u
#define MCHP_PORT80_CAP_STS_OVERRUN (1u << 1)

/*
* Count - R/W access to Port 80 counter
*/
#define MCHP_PORT80_CAP_CNT_REG_MASK 0xFFFFFF00ul
#define MCHP_PORT80_CAP_CNT_POS 8u

/*
* Port80 Capture Logical Device Activate register
*/
#define MCHP_PORT80_CAP_ACTV_MASK 0x01ul
#define MCHP_PORT80_CAP_ACTV_ENABLE 0x01ul

/**
* @brief Fast Port80 Capture Registers (PORT80_CAP_Type)
*/
typedef struct port80cap_regs
{
__OM uint32_t HOST_DATA; /*!< (@ 0x0000) Host Data b[7:0] write-only */
uint8_t RSVD1[0x100u - 0x04u];
__IM uint32_t EC_DATA; /*!< (@ 0x0100) EC Data. Read-only. */
__IOM uint32_t CONFIG; /*!< (@ 0x0104) Configuration Mix of R/W and WO */
__IOM uint32_t STATUS; /*!< (@ 0x0108) Status. Read-only */
__IOM uint32_t COUNT; /*!< (@ 0x010C) Counter. R/W */
uint8_t RSVD3[0x0330ul - 0x0110ul];
__IOM uint32_t ACTV; /*!< (@ 0x0330) Logical device Activate */
} PORT80_CAP_Type;

#endif /* #ifndef _PORT80CAP_H */
/* end port80cap.h */
/** @}
*/

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