diff --git a/dts/arm/st/l4/stm32l451.dtsi b/dts/arm/st/l4/stm32l451.dtsi new file mode 100644 index 000000000000000..a80f3a0012915f4 --- /dev/null +++ b/dts/arm/st/l4/stm32l451.dtsi @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2023 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + compatible = "st,stm32l451", "st,stm32l4", "simple-bus"; + + clocks { + clk_hsi48: clk-hsi48 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + status = "disabled"; + }; + }; + + pinctrl: pin-controller@48000000 { + gpiod: gpio@48000c00 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000c00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; + }; + + gpioe: gpio@48001000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; + }; + }; + + rng: rng@50060800 { + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>, + <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; + }; + + i2c2: i2c@40005800 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; + interrupts = <33 0>, <34 0>; + interrupt-names = "event", "error"; + status = "disabled"; + }; + + i2c4: i2c@40008400 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40008400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>; + interrupts = <83 0>, <84 0>; + interrupt-names = "event", "error"; + status = "disabled"; + }; + + spi2: spi@40003800 { + compatible = "st,stm32-spi-fifo", "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; + interrupts = <36 5>; + status = "disabled"; + }; + + spi3: spi@40003c00 { + compatible = "st,stm32-spi-fifo", "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; + interrupts = <51 5>; + status = "disabled"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; + resets = <&rctl STM32_RESET(APB1L, 18U)>; + interrupts = <39 0>; + status = "disabled"; + }; + + uart4: serial@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; + resets = <&rctl STM32_RESET(APB1L, 19U)>; + interrupts = <52 0>; + status = "disabled"; + }; + + timers3: timers@40000400 { + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; + resets = <&rctl STM32_RESET(APB1L, 1U)>; + interrupts = <29 0>; + interrupt-names = "global"; + st,prescaler = <0>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; + + dac1: dac@40007400 { + compatible = "st,stm32-dac"; + reg = <0x40007400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + can1: can@40006400 { + compatible = "st,stm32-can"; + reg = <0x40006400 0x400>; + interrupts = <19 0>, <20 0>, <21 0>, <22 0>; + interrupt-names = "TX", "RX0", "RX1", "SCE"; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN + status = "disabled"; + sjw = <1>; + sample-point = <875>; + }; + + sdmmc1: sdmmc@40012800 { + compatible = "st,stm32-sdmmc"; + reg = <0x40012800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>, + <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; + resets = <&rctl STM32_RESET(APB2, 10U)>; + interrupts = <49 0>; + status = "disabled"; + }; + + rtc@40002800 { + bbram: backup_regs { + compatible = "st,stm32-bbram"; + st,backup-regs = <32>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/st/l4/stm32l451Xc.dtsi b/dts/arm/st/l4/stm32l451Xc.dtsi new file mode 100644 index 000000000000000..1eaeaf76a5caa33 --- /dev/null +++ b/dts/arm/st/l4/stm32l451Xc.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2023 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(160)>; + }; + + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(256)>; + }; + }; + }; +}; diff --git a/dts/arm/st/l4/stm32l451Xe.dtsi b/dts/arm/st/l4/stm32l451Xe.dtsi new file mode 100644 index 000000000000000..e9eccfa6f9a1206 --- /dev/null +++ b/dts/arm/st/l4/stm32l451Xe.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2023 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(160)>; + }; + + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(512)>; + }; + }; + }; +}; diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l451xx b/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l451xx new file mode 100644 index 000000000000000..d3f5867a8dc123d --- /dev/null +++ b/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l451xx @@ -0,0 +1,14 @@ +# ST Microelectronics STM32L451XX MCU + +# Copyright (c) 2023 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32L451XX + +config SOC + default "stm32l451xx" + +config NUM_IRQS + default 85 + +endif # SOC_STM32L451XX diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.soc b/soc/arm/st_stm32/stm32l4/Kconfig.soc index f3e042c000841fd..9719ff4b73d9a29 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.soc +++ b/soc/arm/st_stm32/stm32l4/Kconfig.soc @@ -37,6 +37,9 @@ config SOC_STM32L432XX config SOC_STM32L433XX bool "STM32L433XX" +config SOC_STM32L451XX + bool "STM32L451XX" + config SOC_STM32L452XX bool "STM32L452XX"