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soc: arm: st_stm32: Add STM32G071 SoC series

This patch adds support for the STM32G071xx
 from STMicroelectronics.

Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
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FRASTM authored and MaureenHelm committed Jul 1, 2019
1 parent 3d32acf commit 7ea00134f55656a52bd65eade227239d6771a4d9
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/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2019 ST Microelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <st/g0/stm32g0-pinctrl.dtsi>
#include <arm/armv6-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/gpio/gpio.h>

/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;

cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
};
};

sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
};

soc {
flash-controller@40022000 {
compatible = "st,stm32g0-flash-controller";
label = "FLASH_CTRL";
reg = <0x40022000 0x400>;
interrupts = <3 0>;

#address-cells = <1>;
#size-cells = <1>;

flash0: flash@8000000 {
compatible = "soc-nv-flash";
label = "FLASH_STM32";

write-block-size = <8>;
erase-block-size = <2048>;
};
};

};
};

&nvic {
arm,num-irq-priority-bits = <2>;
};
@@ -0,0 +1,8 @@
/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2019 ST Microelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <st/g0/stm32g0.dtsi>
@@ -0,0 +1,23 @@
/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2019 ST Microelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <mem.h>
#include <st/g0/stm32g071.dtsi>

/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(36)>;
};

soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
};
};
};
};
@@ -0,0 +1,6 @@
# SPDX-License-Identifier: Apache-2.0

zephyr_include_directories(${ZEPHYR_BASE}/drivers)
zephyr_sources(
soc.c
)
@@ -0,0 +1,20 @@
# Kconfig - STMicroelectronics STM32G0 MCU line
#
# Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
# Copyright (c) 2019 STMicroelectronics
#
# SPDX-License-Identifier: Apache-2.0
#

if SOC_SERIES_STM32G0X

source "soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0*"

config SOC_SERIES
default "stm32g0"

if GPIO_STM32

endif # GPIO_STM32

endif # SOC_SERIES_STM32G0X
@@ -0,0 +1,22 @@
# Kconfig - STMicroelectronics STM32G071RB MCU
#
# Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
# Copyright (c) 2019 STMicroelectronics
#
# SPDX-License-Identifier: Apache-2.0
#

if SOC_STM32G071XX

config SOC
string
default "stm32g071xx"

config NUM_IRQS
int
default 32

if GPIO_STM32

endif # GPIO_STM32
endif # SOC_STM32G071XX
@@ -0,0 +1,18 @@
# Kconfig - STMicroelectronics STM32G0 MCU series
#
# Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
# Copyright (c) 2019 STMicroelectronics
#
# SPDX-License-Identifier: Apache-2.0
#

config SOC_SERIES_STM32G0X
bool "STM32G0x Series MCU"
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_VTOR
select SOC_FAMILY_STM32
select HAS_STM32CUBE
select CPU_CORTEX_M_HAS_SYSTICK
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
help
Enable support for STM32G0 MCU series
@@ -0,0 +1,17 @@
# Kconfig - STMicroelectronics STM32G0 MCU line
#
# Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
# Copyright (c) 2019 STMicroelectronics
#
# SPDX-License-Identifier: Apache-2.0
#

choice
prompt "STM32G0x MCU Selection"
depends on SOC_SERIES_STM32G0X

config SOC_STM32G071XX
bool "STM32G071XX"


endchoice
@@ -0,0 +1,11 @@
/*
* Copyright (c) 2019 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/

/* SoC level DTS fixup file */

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

/* End of SoC Level DTS fixup file */
@@ -0,0 +1,10 @@
/* linker.ld - Linker command/script file */

/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2019 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <arch/arm/cortex_m/scripts/linker.ld>
@@ -0,0 +1,50 @@
/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2019 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/

/**
* @file
* @brief System/hardware module for STM32G0 processor
*/

#include <device.h>
#include <init.h>
#include <arch/cpu.h>
#include <cortex_m/exc.h>
#include <linker/linker-defs.h>
#include <string.h>

/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int stm32g0_init(struct device *arg)
{
u32_t key;

ARG_UNUSED(arg);

key = irq_lock();

/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();

irq_unlock(key);

/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 16 MHz from HSI */
SystemCoreClock = 16000000;

return 0;
}

SYS_INIT(stm32g0_init, PRE_KERNEL_1, 0);
@@ -0,0 +1,41 @@
/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2019 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/

/**
* @file SoC configuration macros for the STM32G0 family processors.
*
* Based on reference manual:
* STM32G0X advanced ARM ® -based 32-bit MCUs
*
* Chapter 2.2: Memory organization
*/


#ifndef _STM32G0_SOC_H_
#define _STM32G0_SOC_H_

#ifndef _ASMLANGUAGE

#include <stm32g0xx.h>

/* ARM CMSIS definitions must be included before kernel_includes.h.
* Therefore, it is essential to include kernel_includes.h after including
* core SOC-specific headers.
*/
#include <kernel_includes.h>

#include <stm32g0xx_ll_system.h>

#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#include <stm32g0xx_ll_utils.h>
#include <stm32g0xx_ll_bus.h>
#include <stm32g0xx_ll_rcc.h>
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */

#endif /* !_ASMLANGUAGE */

#endif /* _STM32G0_SOC_H_ */

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