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riscv: add a qemu_riscv64 board

This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board.
Memory is tight so a few tests had to be disabled due to the extra
memory usage compared to qemu_riscv32.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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Nicolas Pitre authored and galak committed Jul 19, 2019
1 parent c351492 commit 7f74825958a8891b516e3064072c9d9c7196958d
@@ -0,0 +1,8 @@
# Copyright (c) 2019 BayLibre SAS
# SPDX-License-Identifier: Apache-2.0

config BOARD_QEMU_RISCV64
bool "QEMU RISCV64 target"
depends on SOC_RISCV_SIFIVE_FREEDOM
select QEMU_TARGET
select 64BIT
@@ -0,0 +1,12 @@
# Copyright (c) 2019 BayLibre SAS
# SPDX-License-Identifier: Apache-2.0

if BOARD_QEMU_RISCV64

config BUILD_OUTPUT_BIN
default n

config BOARD
default "qemu_riscv64"

endif
@@ -0,0 +1,13 @@
# SPDX-License-Identifier: Apache-2.0

set(EMU_PLATFORM qemu)

set(QEMU_binary_suffix riscv64)
set(QEMU_CPU_TYPE_${ARCH} riscv64)

set(QEMU_FLAGS_${ARCH}
-nographic
-machine sifive_e
)

board_set_debugger_ifnset(qemu)
@@ -0,0 +1,68 @@
.. _qemu_riscv64:

RISCV64 Emulation (QEMU)
########################

Overview
********

The RISCV64 QEMU board configuration is used to emulate the RISCV64 architecture.

.. figure:: qemu_riscv64.png
:width: 600px
:align: center
:alt: QEMU

QEMU (Credit: qemu.org)

Get the Toolchain and QEMU
**************************

The minimum version of the `Zephyr SDK tools
<https://www.zephyrproject.org/developers/#downloads>`_
with toolchain and QEMU support for the RISV64 architecture is v0.10.2.
Please see the `installation instructions
<https://docs.zephyrproject.org/latest/getting_started/index.html#install-the-required-tools>`_
for more details.

Programming and Debugging
*************************

Applications for the ``qemu_riscv64`` board configuration can be built and run in
the usual way for emulated boards (see :ref:`build_an_application` and
:ref:`application_run` for more details).

Flashing
========

While this board is emulated and you can't "flash" it, you can use this
configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment. For example, with the :ref:`synchronization_sample`:

.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_riscv64
:goals: run

This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:

.. code-block:: console

***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!

Debugging
=========

Refer to the detailed overview about :ref:`application_debugging`.
Binary file not shown.
@@ -0,0 +1,52 @@
/* Copyright (c) 2019 BayLibre SAS */
/* SPDX-License-Identifier: Apache-2.0 */

/dts-v1/;

#include <riscv32-fe310.dtsi>

/ {
model = "SiFive HiFive 1";
compatible = "sifive,hifive1";

chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &dtim;
zephyr,flash = &flash0;
};
};

&cpu {
riscv,isa = "rv64imac";
};

&gpio0 {
status = "okay";
};

&uart0 {
status = "okay";
current-speed = <115200>;
clock-frequency = <16000000>;
};

&uart1 {
clock-frequency = <16000000>;
};

&spi0 {
status = "okay";

#address-cells = <1>;
#size-cells = <0>;
reg = <0x10014000 0x1000 0x20400000 0xc00000>;
flash0: flash@0 {
compatible = "issi,is25lp128", "jedec,spi-nor";
label = "FLASH0";
jedec-id = [96 60 18];
reg = <0>;
// Dummy entry
spi-max-frequency = <0>;
};
};
@@ -0,0 +1,13 @@
identifier: qemu_riscv64
name: QEMU Emulation for RISC V 64-bit
type: qemu
simulation: qemu
arch: riscv64
ram: 16
toolchain:
- zephyr
testing:
default: true
ignore_tags:
- net
- bluetooth
@@ -0,0 +1,22 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_RISCV=y
CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV_SIFIVE_FREEDOM=y
CONFIG_BOARD_QEMU_RISCV64=y
CONFIG_64BIT=y
CONFIG_CONSOLE=y
CONFIG_PRINTK=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_PLIC=y
CONFIG_PINMUX=y
CONFIG_PINMUX_SIFIVE=y
CONFIG_RISCV_MACHINE_TIMER=y
CONFIG_GPIO=y
CONFIG_GPIO_SIFIVE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000
CONFIG_STACK_SENTINEL=y
CONFIG_TEST_EXTRA_STACKSIZE=256
@@ -10,7 +10,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
device_type = "cpu";
@@ -2,3 +2,4 @@ tests:
libraries.data_structures.rbtree:
tags: rbtree
filter: not CONFIG_MISRA_SANE
platform_exclude: qemu_riscv64
@@ -3,3 +3,4 @@ tests:
tags: log_core logging
platform_exclude: nucleo_l053r8 nucleo_f030r8
stm32f0_disco native_posix native_posix_64 nrf52_bsim
qemu_riscv64

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