diff --git a/boards/arm/v2m_musca/CMakeLists.txt b/boards/arm/v2m_musca/CMakeLists.txt new file mode 100644 index 00000000000000..04cd9994743cc1 --- /dev/null +++ b/boards/arm/v2m_musca/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(pinmux.c) +zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers) diff --git a/boards/arm/v2m_musca/Kconfig.board b/boards/arm/v2m_musca/Kconfig.board new file mode 100644 index 00000000000000..725f840d4396af --- /dev/null +++ b/boards/arm/v2m_musca/Kconfig.board @@ -0,0 +1,9 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_MUSCA_A + bool "ARM Cortex-M33 SMM on V2M-MUSCA" + depends on SOC_SERIES_MUSCA diff --git a/boards/arm/v2m_musca/Kconfig.defconfig b/boards/arm/v2m_musca/Kconfig.defconfig new file mode 100644 index 00000000000000..2ce96e5862c7e2 --- /dev/null +++ b/boards/arm/v2m_musca/Kconfig.defconfig @@ -0,0 +1,79 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_MUSCA_A + +if TRUSTED_EXECUTION_SECURE || !TRUSTED_EXECUTION_NONSECURE + +config BOARD + default "musca_a" + +endif + +if TRUSTED_EXECUTION_NONSECURE + +config BOARD + default "musca_a_nonsecure" + +endif + + + +if SERIAL + +config UART_PL011 + def_bool y + +config UART_INTERRUPT_DRIVEN + def_bool y + +config UART_PL011_PORT0 + def_bool y + +config UART_PL011_PORT1 + def_bool y + +endif # SERIAL + +if COUNTER + +if COUNTER_TMR_CMSDK_APB + +config COUNTER_TMR_CMSDK_APB_0 + def_bool y + +config COUNTER_TMR_CMSDK_APB_1 + def_bool y + +endif # COUNTER_TMR_CMSDK_APB + +if TIMER_TMR_CMSDK_APB + +config TIMER_TMR_CMSDK_APB_0 + def_bool y + +config TIMER_TMR_CMSDK_APB_1 + def_bool y + +endif # TIMER_TMR_CMSDK_APB + +if COUNTER_DTMR_CMSDK_APB + +config COUNTER_DTMR_CMSDK_APB_0 + def_bool y + +endif # COUNTER_DTMR_CMSDK_APB + +if TIMER_DTMR_CMSDK_APB + +config TIMER_DTMR_CMSDK_APB_0 + def_bool y + +endif # TIMER_DTMR_CMSDK_APB + +endif # COUNTER + +endif diff --git a/boards/arm/v2m_musca/doc/img/v2m_musca.png b/boards/arm/v2m_musca/doc/img/v2m_musca.png new file mode 100644 index 00000000000000..6ec2cf2b253c08 Binary files /dev/null and b/boards/arm/v2m_musca/doc/img/v2m_musca.png differ diff --git a/boards/arm/v2m_musca/doc/v2m_musca.rst b/boards/arm/v2m_musca/doc/v2m_musca.rst new file mode 100644 index 00000000000000..42dd277471f796 --- /dev/null +++ b/boards/arm/v2m_musca/doc/v2m_musca.rst @@ -0,0 +1,445 @@ +.. _v2m_musca_board: + +ARM V2M Musca +############## + +Overview +******** + +The v2m_musca board configuration is used by Zephyr applications that run on +the V2M Musca board. It provides support for the Musca ARM Cortex-M33 CPU and +the following devices: + +- Nested Vectored Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) +- Cortex-M System Design Kit GPIO +- Cortex-M System Design Kit UART + +.. image:: img/v2m_musca.png + :width: 442px + :align: center + :height: 377px + :alt: ARM V2M Musca + +More information about the board can be found at the `V2M Musca Website`_. + +Hardware +******** + +ARM V2M MUSCA provides the following hardware components: + + + +- ARM Cortex-M33 +- ARM IoT Subsystem for Cortex-M33 +- Memory + + - 128KB SRAM + - 2MB of external SRAM + - 8MB of external QSPI flash. + +- Debug + + - JTAG, SWD & 4 bit TRACE + - DAPLink with a virtual UART port + +- Arduino interface + + - 16 3V3 GPIO. + - UART. + - SPI. + - I2C. + - I2S. + - 3-channel PWM. + - 6-channel analog interface. + +- On-board Peripherals + + - User RGB LED + - Gyro sensor + - Combined ADC/DAC/temperature sensor + + +User push buttons +================= + +The v2m_musca board provides the following user push buttons: + +- PBON power on/off. +- nSRST: Cortex-M33 system reset and CoreSight debug reset. +- ISP: Updates DAPLink firmware. +- HWRST: Resets DAPLink. + + +Supported Features +=================== + +The v2m_musca board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TIMER | on-chip | timer | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. +See the `V2M Musca Website`_ for a complete list of V2M Musca board hardware +features. + +The default configuration can be found in the defconfig file: +``boards/arm/v2m_musca/v2m_musca_defconfig``. + +Interrupt Controller +==================== + +Musca is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs. + +A Cortex-M33-based board uses vectored exceptions. This means each exception +calls a handler directly from the vector table. + +Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed +in the following table: + ++------+------------+----------------+--------------------------+ +| Exc# | Name | Remarks | Used by Zephyr Kernel | ++======+============+================+==========================+ +| 1 | Reset | | system initialization | ++------+------------+----------------+--------------------------+ +| 2 | NMI | | system fatal error | ++------+------------+----------------+--------------------------+ +| 3 | Hard fault | | system fatal error | ++------+------------+----------------+--------------------------+ +| 4 | MemManage | MPU fault | system fatal error | ++------+------------+----------------+--------------------------+ +| 5 | Bus | | system fatal error | ++------+------------+----------------+--------------------------+ +| 6 | Usage | Undefined | system fatal error | +| | fault | instruction, | | +| | | or switch | | +| | | attempt to ARM | | +| | | mode | | ++------+------------+----------------+--------------------------+ +| 7 |SecureFault | Unauthorized | system fatal error | +| | | access to | | +| | | secure region | | +| | | from ns space | | ++------+------------+----------------+--------------------------+ +| 8 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 9 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 10 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 11 | SVC | | context switch and | +| | | | software interrupts | ++------+------------+----------------+--------------------------+ +| 12 | Debug | | system fatal error | +| | monitor | | | ++------+------------+----------------+--------------------------+ +| 13 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 14 | PendSV | | context switch | ++------+------------+----------------+--------------------------+ +| 15 | SYSTICK | | system clock | ++------+------------+----------------+--------------------------+ +| 16 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 17 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 18 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ + +Pin Mapping +=========== + +The ARM V2M Musca Board has 4 GPIO controllers. These controllers are +responsible for pin-muxing, input/output, pull-up, etc. + +All GPIO controller pins are exposed via the following sequence of pin numbers: + +- Pins 0 - 15 are for GPIO 0 +- Pins 16 - 31 are for GPIO 1 + +Mapping from the ARM V2M Musca Board pins to GPIO controllers: + +.. hlist:: + :columns: 3 + + - D0 : P0_0 + - D1 : P0_1 + - D2 : P0_2 + - D3 : P0_3 + - D4 : P0_4 + - D5 : P0_5 + - D6 : P0_6 + - D7 : P0_7 + - D8 : P0_8 + - D9 : P0_9 + - D10 : P0_10 + - D11 : P0_11 + - D12 : P0_12 + - D13 : P0_13 + - D14 : P0_14 + - D15 : P0_15 + - D16 : P1_0 + - D17 : P1_1 + - D18 : P1_2 + - D19 : P1_3 + - D20 : P1_4 + - D21 : P1_5 + - D22 : P1_6 + - D23 : P1_7 + - D24 : P1_8 + - D25 : P1_9 + - D26 : P1_10 + - D27 : P1_11 + - D28 : P1_12 + - D29 : P1_13 + - D30c : P1_14 + - D31 : P1_15 + +Peripheral Mapping: + +.. hlist:: + :columns: 3 + + - UART_0_RX : D0 + - UART_0_TX : D1 + - SPI_0_CS : D10 + - SPI_0_MOSI : D11 + - SPI_0_MISO : D12 + - SPI_0_SCLK : D13 + - I2C_0_SCL : D14 + - I2C_0_SDA : D15 + - UART_1_RX : D16 + - UART_1_TX : D17 + - SPI_1_CS : D18 + - SPI_1_MOSI : D19 + - SPI_1_MISO : D20 + - SPI_1_SCK : D21 + - I2C_1_SDA : D22 + - I2C_1_SCL : D23 + +For mode details please refer to `Musca Technical Reference Manual (TRM)`_. + + +RGB LED +============ + +Musca has a built-in RGB LED connected to GPIO[4:2] pins. + +- Red LED connected at GPIO[2] pin,with optional PWM0. +- Green LED connected at GPIO[3] pin,with optional PWM0. +- Blue LED connected at GPIO[4] pin,with optional PWM0. + +.. note:: The SCC registers select the functions of pins GPIO[4:2]. + +System Clock +============ + +V2M Musca has a 32.768kHz crystal clock. The clock goes to a PLL and is +multiplied to drive the Cortex-M33 processors and SSE-200 subsystem. The +default is 50MHz but can be increased to 170MHz maximum for the secondary +processor (CPU1) via software configuration. The maximum clock frequency +for the primary processor (CPU0) is 50MHz. + +Serial Port +=========== + +The ARM Musca processor has two UARTs. Both the UARTs have only two wires for +RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by +default, uses UART1. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define + secure and non-secure memory maps. By default, all of the memory space is + defined to be secure accessible only. +- Secure and Non-secure peripherals via the Peripheral Protection Controller + (PPC). Peripherals can be assigned as secure or non-secure accessible. +- Secure boot. +- Secure `AMBA®`_ interconnect. + +Serial Configuration Controller (SCC) +===================================== + +The ARM Musca test chip implements a Serial Configuration Control (SCC) +register. The purpose of this register is to allow individual control of +clocks, reset-signals and interrupts to peripherals, and pin-muxing. + +QSPI boot memory +================ +Normal Musca-A test chip boot operation is from external QSPI 8MB flash memory. +Only the lowest 256KB of QSPI memory is directly accessible. +More memory is accessible through indirect addressing. + +Programming and Debugging +************************* + +Musca supports the v8m security extension, and by default boots to the secure +state. + +When building a secure/non-secure application, the secure application will +have to set the idau/sau and mpc configuration to permit access from the +non-secure application before jumping. + +The following system components are required to be properly configured during the +secure firmware: + +- AHB5 TrustZone Memory Protection Controller (MPC). +- AHB5 TrustZone Peripheral Protection Controller (PPC). +- Implementation-Defined Attribution Unit (IDAU). + +For more details please refer to `Corelink SSE-200 Subsystem`_. + +Flashing +======== + +DAPLink +--------- + +V2M Musca provides: + +- A USB connection to the host computer, which exposes a Mass Storage and an + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +This interfaces are exposed via DAPLink which provides: + +- Serial Wire Debug (SWD). +- USB Mass Storage Device (USBMSD). +- UART. +- Remote reset. + +For more details please refer +to the `DAPLink Website`_. + + +Building a secure only application +---------------------------------- + + +You can build applications in the usual way. Here is an example for +the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: v2m_musca + :goals: build + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! arm + +Building a secure/non-secure with Trusted Firmware +-------------------------------------------------- + +The process requires five steps: + +1. Build Trusted Firmware (tfm). +2. Import it as a library to the Zepyhr source folder. +3. Build Zephyr with a non-secure configuration. +4. Merge the two binaries together and sign them. +5. Concatenate the bootloader with the signed image blob. + +In order to build tfm please refer to `Trusted Firmware M Guide`_. +Follow the build steps for AN521 target while replacing the platform with +``-DTARGET_PLATFORM=MUSCA_A`` and compiler (if required) with ``-DCOMPILER=GCC`` + +Copy over tf-m as a library to the zephyr project source and create a shortcut +for the secure veneers. + +.. code-block:: bash + + cp -r install/ $ZEPHYR_PROJECT/src/ext + cp $ZEPHYR_PROJECT/src/ext/install/export/tfm/veneers/s_veneers.o $ZEPHYR_PROJECT/src/ext + + +Build the Zephyr app in the usual way. + +Uploading an application to V2M Musca +------------------------------------- + +Applications must be converted to Intel's hex format before being flashed to a +V2M Musca. An optional bootloader can be prepended to the image. +The QSPI flash base address alias is 0x200000. + +The image offset is calculated by adding the flash offset to the +bootloader partition size. + +A third-party tool (srecord) is used to generate the Intel formatted hex image. For more information +refer to the `Srecord Manual`_. + +.. code-block:: bash + + srec_cat $BIN_BOOLOADER -Binary -offset $QSPI_FLASH_OFFSET $BIN_SNS -Binary -offset $IMAGE_OFFSET -o $HEX_FLASHABLE -Intel + + # For a 64K bootloader IMAGE_OFFSET = $QSPI_FLASH_OFFSET + 0x10000 + srec_cat $BIN_BOOLOADER -Binary -offset 0x200000 $BIN_SNS -Binary -offset 0x210000 -o $HEX_FLASHABLE -Intel + + # For a 256K bootloader IMAGE_OFFSET = $QSPI_FLASH_OFFSET + 0x40000 + srec_cat $BIN_BOOLOADER -Binary -offset 0x200000 $BIN_SNS -Binary -offset 0x240000 -o $HEX_FLASHABLE -Intel + +Connect the V2M Musca to your host computer using the USB port. You should +see a USB connection exposing a Mass Storage (MBED) and a USB Serial Port. +Copy the generated ``zephyr.hex`` in the MBED drive. + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! arm + + +.. _V2M Musca Website: + https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board + +.. _Musca Technical Reference Manual (TRM): + http://infocenter.arm.com/help/topic/com.arm.doc.101107_0000_00_en/arm_musca_a_test_chip_and_board_technical_reference_manual_101107_0000_00_en.pdf + +.. _DAPLink Website: + https://github.com/ARMmbed/DAPLink + +.. _Cortex M33 Generic User Guide: + http://infocenter.arm.com/help/topic/com.arm.doc.100235_0004_00_en/arm_cortex_m33_dgug_100235_0004_00_en.pdf + +.. _Trusted Firmware M Guide: + https://git.trustedfirmware.org/trusted-firmware-m.git/about/docs/user_guides/tfm_build_instruction.md + +.. _Corelink SSE-200 Subsystem: + https://developer.arm.com/products/system-design/subsystems/corelink-sse-200-subsystem + +.. _Srecord Manual: + http://srecord.sourceforge.net/man/man1/srec_cat.html + +.. _IDAU: + https://developer.arm.com/products/architecture/cpu-architecture/m-profile/docs/100690/latest/attribution-units-sau-and-idau + +.. _AMBA®: + https://developer.arm.com/products/architecture/system-architectures/amba diff --git a/boards/arm/v2m_musca/pinmux.c b/boards/arm/v2m_musca/pinmux.c new file mode 100644 index 00000000000000..3368aa8679082d --- /dev/null +++ b/boards/arm/v2m_musca/pinmux.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinmux/pinmux.h" + +#define IOMUX_MAIN_INSEL (0x30 >> 2) +#define IOMUX_MAIN_OUTSEL (0x34 >> 2) +#define IOMUX_MAIN_OENSEL (0x38 >> 2) +#define IOMUX_MAIN_DEFAULT_IN (0x3c >> 2) +#define IOMUX_ALTF1_INSEL (0x40 >> 2) +#define IOMUX_ALTF1_OUTSEL (0x44 >> 2) +#define IOMUX_ALTF1_OENSEL (0x48 >> 2) +#define IOMUX_ALTF1_DEFAULT_IN (0x4c >> 2) + +#ifdef CONFIG_TRUSTED_EXECUTION_SECURE +/* + * Only configure pins if we are secure. Otherwise secure violation will occur +*/ +static void arm_musca_pinmux_defaults(void) +{ + volatile u32_t *scc = (u32_t *)DT_ARM_SCC_BASE_ADDRESS; + + /* there is only altfunc1, so steer all alt funcs to use 1 */ + scc[IOMUX_ALTF1_INSEL] = 0xffff; + scc[IOMUX_ALTF1_OUTSEL] = 0xffff; + scc[IOMUX_ALTF1_OENSEL] = 0xffff; + +#if defined(CONFIG_UART_PL011_PORT0) + /* clear bit 0/1 for GPIO0/1 to steer from ALTF1 */ + scc[IOMUX_MAIN_INSEL] &= ~(BIT(0) | BIT(1)); + scc[IOMUX_MAIN_OUTSEL] &= ~(BIT(0) | BIT(1)); + scc[IOMUX_MAIN_OENSEL] &= ~(BIT(0) | BIT(1)); +#endif + +} +#else +static void arm_musca_pinmux_defaults(void) +{ +} +#endif + +static int arm_musca_pinmux_init(struct device *port) +{ + ARG_UNUSED(port); + + arm_musca_pinmux_defaults(); + + return 0; +} + +SYS_INIT(arm_musca_pinmux_init, PRE_KERNEL_1, + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/boards/arm/v2m_musca/v2m_musca-common.dtsi b/boards/arm/v2m_musca/v2m_musca-common.dtsi new file mode 100644 index 00000000000000..c919cbe72d4735 --- /dev/null +++ b/boards/arm/v2m_musca/v2m_musca-common.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +timer0: timer@0 { + compatible = "arm,cmsdk-timer"; + reg = <0x0 0x1000>; + interrupts = <3 3>; +}; + +timer1: timer@1000 { + compatible = "arm,cmsdk-timer"; + reg = <0x1000 0x1000>; + interrupts = <4 3>; +}; + +dtimer0: dtimer@2000 { + compatible = "arm,cmsdk-dtimer"; + reg = <0x2000 0x1000>; + interrupts = <5 3>; +}; + +wdog0: wdog@81000 { + compatible = "arm,cmsdk-watchdog"; + reg = <0x81000 0x1000>; +}; + +uart0: uart@101000 { + compatible = "arm,pl011"; + reg = <0x101000 0x1000>; + interrupts = <39 3 40 3 41 3 43 3>; + interrupt-names = "rx", "tx", "rxtim", "err"; + current-speed = <115200>; + label = "UART_0"; +}; + +uart1: uart@102000 { + compatible = "arm,pl011"; + reg = <0x102000 0x1000>; + interrupts = <45 3 46 3 47 3 49 3>; + interrupt-names = "rx", "tx", "rxtim", "err"; + current-speed = <115200>; + label = "UART_1"; +}; + +scc@10c000 { + compatible = "arm,scc"; + reg = <0x10c000 0x1000>; +}; diff --git a/boards/arm/v2m_musca/v2m_musca.dts b/boards/arm/v2m_musca/v2m_musca.dts new file mode 100644 index 00000000000000..23aaec1389bb0d --- /dev/null +++ b/boards/arm/v2m_musca/v2m_musca.dts @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + compatible = "arm,v2m-musca"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,shell-uart = &uart1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + }; + }; + + flash0: flash@10200000 { + /* QSPI flash */ + reg = <0x10200000 0x800000>; + }; + + sram0: memory@30000000 { + compatible = "mmio-sram"; + reg = <0x30000000 0x20000>; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "v2m_musca-common.dtsi" + }; + }; + +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/boards/arm/v2m_musca/v2m_musca.yaml b/boards/arm/v2m_musca/v2m_musca.yaml new file mode 100644 index 00000000000000..32893dd0092025 --- /dev/null +++ b/boards/arm/v2m_musca/v2m_musca.yaml @@ -0,0 +1,7 @@ +identifier: v2m_musca +name: ARM V2M MUSCA +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools diff --git a/boards/arm/v2m_musca/v2m_musca_defconfig b/boards/arm/v2m_musca/v2m_musca_defconfig new file mode 100644 index 00000000000000..736a79f8b20bae --- /dev/null +++ b/boards/arm/v2m_musca/v2m_musca_defconfig @@ -0,0 +1,26 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_ARM=y +CONFIG_SOC_FAMILY_ARM=y +CONFIG_SOC_SERIES_MUSCA=y +CONFIG_SOC_V2M_MUSCA_A=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + + +# PinMuxing +CONFIG_PINMUX=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Watchdog +CONFIG_WATCHDOG=y diff --git a/boards/arm/v2m_musca/v2m_musca_nonsecure.dts b/boards/arm/v2m_musca/v2m_musca_nonsecure.dts new file mode 100644 index 00000000000000..31d9aa0034d4a9 --- /dev/null +++ b/boards/arm/v2m_musca/v2m_musca_nonsecure.dts @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + compatible = "arm,v2m-musca"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,shell-uart = &uart1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + }; + }; + + flash0: flash@230400 { + /* QSPI flash */ + reg = <0x00230400 0x1ffc00>; + }; + + sram0: memory@20010000 { + compatible = "mmio-sram"; + reg = <0x20010000 0x10000>; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "v2m_musca-common.dtsi" + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/boards/arm/v2m_musca/v2m_musca_nonsecure.yaml b/boards/arm/v2m_musca/v2m_musca_nonsecure.yaml new file mode 100644 index 00000000000000..018b4073cbca6e --- /dev/null +++ b/boards/arm/v2m_musca/v2m_musca_nonsecure.yaml @@ -0,0 +1,8 @@ +identifier: v2m_musca_nonsecure +name: ARM V2M MUSCA NonSecure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools +ram: 64 diff --git a/boards/arm/v2m_musca/v2m_musca_nonsecure_defconfig b/boards/arm/v2m_musca/v2m_musca_nonsecure_defconfig new file mode 100644 index 00000000000000..743af68dde6b6a --- /dev/null +++ b/boards/arm/v2m_musca/v2m_musca_nonsecure_defconfig @@ -0,0 +1,26 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_ARM=y +CONFIG_SOC_FAMILY_ARM=y +CONFIG_SOC_SERIES_MUSCA=y +CONFIG_SOC_V2M_MUSCA_A=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_RUNTIME_NMI=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y +CONFIG_ARM_MPU=y + +# PinMuxing +CONFIG_PINMUX=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Watchdog +CONFIG_WATCHDOG=y diff --git a/dts/bindings/arm/arm,scc.yaml b/dts/bindings/arm/arm,scc.yaml new file mode 100644 index 00000000000000..360d017396d645 --- /dev/null +++ b/dts/bindings/arm/arm,scc.yaml @@ -0,0 +1,26 @@ +# +# Copyright (c) 2018, Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# +--- +title: ARM Serial Configuration Control +version: 0.1 + +description: > + This binding gives a base representation of the ARM SCC + +properties: + compatible: + type: string + category: required + description: compatible strings + constraint: "arm,scc" + + reg: + type: array + description: mmio register space + generation: define + category: required + +... diff --git a/soc/arm/arm/musca_a/CMakeLists.txt b/soc/arm/arm/musca_a/CMakeLists.txt new file mode 100644 index 00000000000000..c279a10318e3bd --- /dev/null +++ b/soc/arm/arm/musca_a/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + arm_mpu_regions.c + ) diff --git a/soc/arm/arm/musca_a/Kconfig.defconfig.musca_a b/soc/arm/arm/musca_a/Kconfig.defconfig.musca_a new file mode 100644 index 00000000000000..6a746940638bc7 --- /dev/null +++ b/soc/arm/arm/musca_a/Kconfig.defconfig.musca_a @@ -0,0 +1,16 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_V2M_MUSCA_A + +config SOC + default "musca_a" + +config NUM_IRQS + int + default 96 + +endif diff --git a/soc/arm/arm/musca_a/Kconfig.defconfig.series b/soc/arm/arm/musca_a/Kconfig.defconfig.series new file mode 100644 index 00000000000000..b61c66625f5ac7 --- /dev/null +++ b/soc/arm/arm/musca_a/Kconfig.defconfig.series @@ -0,0 +1,18 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_MUSCA + +config SOC_SERIES + default "musca_a" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +source "soc/arm/arm/musca_a/Kconfig.defconfig.musca_a" + +endif # SOC_SERIES_MUSCA diff --git a/soc/arm/arm/musca_a/Kconfig.series b/soc/arm/arm/musca_a/Kconfig.series new file mode 100644 index 00000000000000..cdc5454852c42b --- /dev/null +++ b/soc/arm/arm/musca_a/Kconfig.series @@ -0,0 +1,13 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_MUSCA + bool "ARM v2m MUSCA MCU Series" + select SOC_FAMILY_ARM + select CPU_HAS_SYSTICK + select BUILD_OUTPUT_HEX + help + Enable support for ARM MPS2 MCU Series diff --git a/soc/arm/arm/musca_a/Kconfig.soc b/soc/arm/arm/musca_a/Kconfig.soc new file mode 100644 index 00000000000000..896fe10d15b38a --- /dev/null +++ b/soc/arm/arm/musca_a/Kconfig.soc @@ -0,0 +1,17 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +choice +prompt "ARM Musca SoCs" +depends on SOC_SERIES_MUSCA + +config SOC_V2M_MUSCA_A + bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA" + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + +endchoice diff --git a/soc/arm/arm/musca_a/arm_mpu_regions.c b/soc/arm/arm/musca_a/arm_mpu_regions.c new file mode 100644 index 00000000000000..38d6f91afe6928 --- /dev/null +++ b/soc/arm/arm/musca_a/arm_mpu_regions.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2018 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +static const struct arm_mpu_region mpu_regions[] = { + /* Region 0 */ + { CONFIG_FLASH_BASE_ADDRESS, + "FLASH_0", + REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, + CONFIG_FLASH_SIZE*1024)}, + /* Region 1 */ + { CONFIG_SRAM_BASE_ADDRESS, + "SRAM_0", + REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, + CONFIG_SRAM_SIZE*1024)} +}; + +const struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +}; diff --git a/soc/arm/arm/musca_a/dts_fixup.h b/soc/arm/arm/musca_a/dts_fixup.h new file mode 100644 index 00000000000000..bb0300394c6454 --- /dev/null +++ b/soc/arm/arm/musca_a/dts_fixup.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* SoC level DTS fixup file */ + +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS + +#if defined (CONFIG_ARM_NONSECURE_FIRMWARE) +/* CMSDK APB Timers */ +#define DT_CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_40000000_BASE_ADDRESS +#define DT_CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_40000000_IRQ_0 + +#define DT_CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_40001000_BASE_ADDRESS +#define DT_CMSDK_APB_TIMER_1_IRQ DT_ARM_CMSDK_TIMER_40001000_IRQ_0 + +/* CMSDK APB Dual Timer */ +#define DT_CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS +#define DT_CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_40002000_IRQ_0 + +/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */ +#define DT_PL011_PORT0_BASE_ADDRESS DT_ARM_PL011_40101000_BASE_ADDRESS +#define DT_PL011_PORT0_IRQ_TX DT_ARM_PL011_40101000_IRQ_TX +#define DT_PL011_PORT0_IRQ_RX DT_ARM_PL011_40101000_IRQ_RX +#define DT_PL011_PORT0_IRQ_RXTIM DT_ARM_PL011_40101000_IRQ_RXTIM +#define DT_PL011_PORT0_IRQ_ERR DT_ARM_PL011_40101000_IRQ_ERR +#define DT_PL011_PORT0_IRQ_PRI DT_ARM_PL011_40101000_IRQ_0_PRIORITY +#define DT_PL011_PORT0_BAUD_RATE DT_ARM_PL011_40101000_CURRENT_SPEED +#define DT_PL011_PORT0_NAME DT_ARM_PL011_40101000_LABEL + +#define DT_PL011_PORT1_BASE_ADDRESS DT_ARM_PL011_40102000_BASE_ADDRESS +#define DT_PL011_PORT1_IRQ_TX DT_ARM_PL011_40102000_IRQ_TX +#define DT_PL011_PORT1_IRQ_RX DT_ARM_PL011_40102000_IRQ_RX +#define DT_PL011_PORT1_IRQ_RXTIM DT_ARM_PL011_40102000_IRQ_RXTIM +#define DT_PL011_PORT1_IRQ_ERR DT_ARM_PL011_40102000_IRQ_ERR +#define DT_PL011_PORT1_IRQ_PRI DT_ARM_PL011_40102000_IRQ_0_PRIORITY +#define DT_PL011_PORT1_BAUD_RATE DT_ARM_PL011_40102000_CURRENT_SPEED +#define DT_PL011_PORT1_NAME DT_ARM_PL011_40102000_LABEL + +/* CMSDK APB Watchdog */ +#define DT_CMSDK_APB_WDOG DT_ARM_CMSDK_WATCHDOG_40081000_BASE_ADDRESS + +/* SCC */ +#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_4010C000_BASE_ADDRESS + +#else + +/* CMSDK APB Timers */ +#define DT_CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_50000000_BASE_ADDRESS +#define DT_CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_50000000_IRQ_0 + +#define DT_CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_50001000_BASE_ADDRESS +#define DT_CMSDK_APB_TIMER_1_IRQ DT_ARM_CMSDK_TIMER_50001000_IRQ_0 + +/* CMSDK APB Dual Timer */ +#define DT_CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_50002000_BASE_ADDRESS +#define DT_CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_50002000_IRQ_0 + +/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */ +#define DT_PL011_PORT0_BASE_ADDRESS DT_ARM_PL011_50101000_BASE_ADDRESS +#define DT_PL011_PORT0_IRQ_TX DT_ARM_PL011_50101000_IRQ_TX +#define DT_PL011_PORT0_IRQ_RX DT_ARM_PL011_50101000_IRQ_RX +#define DT_PL011_PORT0_IRQ_RXTIM DT_ARM_PL011_50101000_IRQ_RXTIM +#define DT_PL011_PORT0_IRQ_ERR DT_ARM_PL011_50101000_IRQ_ERR +#define DT_PL011_PORT0_IRQ_PRI DT_ARM_PL011_50101000_IRQ_0_PRIORITY +#define DT_PL011_PORT0_BAUD_RATE DT_ARM_PL011_50101000_CURRENT_SPEED +#define DT_PL011_PORT0_NAME DT_ARM_PL011_50101000_LABEL + +#define DT_PL011_PORT1_BASE_ADDRESS DT_ARM_PL011_50102000_BASE_ADDRESS +#define DT_PL011_PORT1_IRQ_TX DT_ARM_PL011_50102000_IRQ_TX +#define DT_PL011_PORT1_IRQ_RX DT_ARM_PL011_50102000_IRQ_RX +#define DT_PL011_PORT1_IRQ_RXTIM DT_ARM_PL011_50102000_IRQ_RXTIM +#define DT_PL011_PORT1_IRQ_ERR DT_ARM_PL011_50102000_IRQ_ERR +#define DT_PL011_PORT1_IRQ_PRI DT_ARM_PL011_50102000_IRQ_0_PRIORITY +#define DT_PL011_PORT1_BAUD_RATE DT_ARM_PL011_50102000_CURRENT_SPEED +#define DT_PL011_PORT1_NAME DT_ARM_PL011_50102000_LABEL + +/* CMSDK APB Watchdog */ +#define DT_CMSDK_APB_WDOG DT_ARM_CMSDK_WATCHDOG_50081000_BASE_ADDRESS + +/* SCC */ +#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_5010C000_BASE_ADDRESS + +#endif + +/* End of SoC Level DTS fixup file */ diff --git a/soc/arm/arm/musca_a/linker.ld b/soc/arm/arm/musca_a/linker.ld new file mode 100644 index 00000000000000..b6ccb02793c627 --- /dev/null +++ b/soc/arm/arm/musca_a/linker.ld @@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/arm/musca_a/soc.c b/soc/arm/arm/musca_a/soc.c new file mode 100644 index 00000000000000..e2b3ee2d17219e --- /dev/null +++ b/soc/arm/arm/musca_a/soc.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/** + * @brief Perform basic hardware initialization at boot. + * + * @return 0 + */ +static int arm_musca_init(struct device *arg) +{ + ARG_UNUSED(arg); + + /* + * Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + return 0; +} + +SYS_INIT(arm_musca_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/arm/arm/musca_a/soc.h b/soc/arm/arm/musca_a/soc.h new file mode 100644 index 00000000000000..1e56deffdad5a4 --- /dev/null +++ b/soc/arm/arm/musca_a/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#ifndef _ASMLANGUAGE +#include "system_cmsdk_musca.h" +#include +#include +#endif + +#endif /* _SOC_H_ */ diff --git a/soc/arm/arm/musca_a/system_cmsdk_musca.h b/soc/arm/arm/musca_a/system_cmsdk_musca.h new file mode 100644 index 00000000000000..d9d5ac77c28ff9 --- /dev/null +++ b/soc/arm/arm/musca_a/system_cmsdk_musca.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2017-2018 Arm Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h + */ + +#ifndef SYSTEM_CMSDK_MUSCA_H +#define SYSTEM_CMSDK_MUSCA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum IRQn { +/* =========================================== Core Specific Interrupt Numbers ============================================= */ + NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* -13 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt */ + BusFault_IRQn = -11, /* -11 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* -5 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* -2 Pend SV Interrupt */ + SysTick_IRQn = -1, /* -1 System Tick Interrupt */ + +/* ======================================== Musca Specific SSE-200 Interrupt Numbers ====================================== */ + NS_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset Request Interrupt */ + NS_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */ + S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */ + TIMER0_IRQn = 3, /* CMSDK Timer 0 Interrupt */ + TIMER1_IRQn = 4, /* CMSDK Timer 1 Interrupt */ + DUALTIMER_IRQn = 5, /* CMSDK Dual Timer Interrupt */ + MHU0_IRQn = 6, /* Message Handling Unit 0 Interrupt */ + MHU1_IRQn = 7, /* Message Handling Unit 1 Interrupt */ + CRYPTOCELL_IRQn = 8, /* CryptoCell-312 Interrupt */ + S_MPC_COMBINED_IRQn = 9, /* Secure Combined MPC Interrupt */ + S_PPC_COMBINED_IRQn = 10, /* Secure Combined PPC Interrupt */ + S_MSC_COMBINED_IRQn = 11, /* Secure Combined MSC Interrupt */ + S_BRIDGE_ERR_IRQn = 12, /* Secure Bridge Error Combined Interrupt */ + I_CACHE_INV_ERR_IRQn = 13, /* Instruction Cache Invalidation Interrupt */ + /* Reserved = 14, Reserved */ + SYS_PPU_IRQn = 15, /* System PPU Interrupt */ + CPU0_PPU_IRQn = 16, /* CPU0 PPU Interrupt */ + CPU1_PPU_IRQn = 17, /* CPU1 PPU Interrupt */ + CPU0_DGB_PPU_IRQn = 18, /* CPU0 Debug PPU Interrupt */ + CPU1_DGB_PPU_IRQn = 19, /* CPU1 Debug PPU Interrupt */ + CRYPTOCELL_PPU_IRQn = 20, /* CryptoCell PPU Interrupt */ + /* Reserved = 21, Reserved */ + RAM0_PPU_IRQn = 22, /* RAM 0 PPU Interrupt */ + RAM1_PPU_IRQn = 23, /* RAM 1 PPU Interrupt */ + RAM2_PPU_IRQn = 24, /* RAM 2 PPU Interrupt */ + RAM3_PPU_IRQn = 25, /* RAM 3 PPU Interrupt */ + DEBUG_PPU_IRQn = 26, /* Debug PPU Interrupt */ + /* Reserved = 27, Reserved */ + CPU0_CTI_IRQn = 28, /* CPU0 CTI Interrupt */ + CPU1_CTI_IRQn = 29, /* CPU1 CTI Interrupt */ + /* Reserved = 30, Reserved */ + /* Reserved = 31, Reserved */ +/* ========================================== Musca Specific Expansion Interrupt Numbers =================================== */ + /* None = 32, Not used. Tied to 0 */ + GpTimer_IRQn = 33, /* General Purpose Timer Interrupt */ + I2C0_IRQn = 34, /* I2C0 Interrupt */ + I2C1_IRQn = 35, /* I2C1 Interrupt */ + I2S_IRQn = 36, /* I2S Interrupt */ + SPI_IRQn = 37, /* SPI Interrupt */ + QSPI_IRQn = 38, /* QSPI Interrupt */ + UART0_Rx_IRQn = 39, /* UART0 receive FIFO interrupt */ + UART0_Tx_IRQn = 40, /* UART0 transmit FIFO interrupt */ + UART0_RxTimeout_IRQn = 41, /* UART0 receive timeout interrupt */ + UART0_ModemStatus_IRQn = 42, /* UART0 modem status interrupt */ + UART0_Error_IRQn = 43, /* UART0 error interrupt */ + UART0_IRQn = 44, /* UART0 interrupt */ + UART1_Rx_IRQn = 45, /* UART1 receive FIFO interrupt */ + UART1_Tx_IRQn = 46, /* UART1 transmit FIFO interrupt */ + UART1_RxTimeout_IRQn = 47, /* UART1 receive timeout interrupt */ + UART1_ModemStatus_IRQn = 48, /* UART1 modem status interrupt */ + UART1_Error_IRQn = 49, /* UART1 error interrupt */ + UART1_IRQn = 50, /* UART1 interrupt */ + GPIO_0_IRQn = 51, /* GPIO 0 interrupt */ + GPIO_1_IRQn = 52, /* GPIO 1 interrupt */ + GPIO_2_IRQn = 53, /* GPIO 2 interrupt */ + GPIO_3_IRQn = 54, /* GPIO 3 interrupt */ + GPIO_4_IRQn = 55, /* GPIO 4 interrupt */ + GPIO_5_IRQn = 56, /* GPIO 5 interrupt */ + GPIO_6_IRQn = 57, /* GPIO 6 interrupt */ + GPIO_7_IRQn = 58, /* GPIO 7 interrupt */ + GPIO_8_IRQn = 59, /* GPIO 8 interrupt */ + GPIO_9_IRQn = 60, /* GPIO 9 interrupt */ + GPIO_10_IRQn = 61, /* GPIO 10 interrupt */ + GPIO_11_IRQn = 62, /* GPIO 11 interrupt */ + GPIO_12_IRQn = 63, /* GPIO 12 interrupt */ + GPIO_13_IRQn = 64, /* GPIO 13 interrupt */ + GPIO_14_IRQn = 65, /* GPIO 14 interrupt */ + GPIO_15_IRQn = 66, /* GPIO 15 interrupt */ + Combined_IRQn = 67, /* Combined interrupt */ + PVT_IRQn = 68, /* PVT sensor interrupt */ + /* Reserved = 69, Reserved */ + PWM_0_IRQn = 70, /* PWM0 interrupt */ + RTC_IRQn = 71, /* RTC interrupt */ + GpTimer0_IRQn = 72, /* General Purpose Timer0 Interrupt */ + GpTimer1_IRQn = 73, /* General Purpose Timer1 Interrupt */ + PWM_1_IRQn = 74, /* PWM1 interrupt */ + PWM_2_IRQn = 75, /* PWM2 interrupt */ + IOMUX_IRQn = 76, /* IOMUX interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ + +/* CORE 0 doesn't have FPU or DSP */ +#define __FPU_PRESENT 0U /* no FPU present */ +#define __DSP_PRESENT 0U /* no DSP extension present */ + + +#include /*!< ARM Cortex-M33 processor and core peripherals */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_MUSCA_H */