Skip to content
Permalink
Browse files

drivers: adc: enable ADC on STM32WB

Enable ADC on STM32WB

Signed-off-by: Rick Conrey <rick.conrey@witiproducts.com>
  • Loading branch information...
Rick Conrey authored and galak committed Jul 1, 2019
1 parent 12a9ff3 commit 837f07a301d222f1b780df50b237896e056b3048
Showing with 37 additions and 16 deletions.
  1. +26 −16 drivers/adc/adc_stm32.c
  2. +7 −0 soc/arm/st_stm32/stm32wb/dts_fixup.h
  3. +4 −0 soc/arm/st_stm32/stm32wb/soc.h
@@ -147,7 +147,8 @@ static const u32_t table_samp_time[] = {
SMP_TIME(79, S_5),
SMP_TIME(160, S_5),
};
#elif defined(CONFIG_SOC_SERIES_STM32L4X)
#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
static const u16_t acq_time_tbl[8] = {3, 7, 13, 25, 48, 93, 248, 641};
static const u32_t table_samp_time[] = {
SMP_TIME(2, S_5),
@@ -216,7 +217,8 @@ static void adc_stm32_start_conversion(struct device *dev)
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32L4X)
defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
LL_ADC_REG_StartConversion(adc);
#else
LL_ADC_REG_StartConversionSWStart(adc);
@@ -279,7 +281,8 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence)
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32L4X)
defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
LL_ADC_EnableIT_EOC(adc);
#elif defined(CONFIG_SOC_SERIES_STM32F1X)
LL_ADC_EnableIT_EOS(adc);
@@ -454,7 +457,8 @@ static void adc_stm32_calib(struct device *dev)
ADC_TypeDef *adc = config->base;

#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32L4X)
defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
#elif defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32L0X)
@@ -491,20 +495,22 @@ static int adc_stm32_init(struct device *dev)
return -EIO;
}

#if defined(CONFIG_SOC_SERIES_STM32L4X)
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
/*
* L4 series STM32 needs to be awaken from deep sleep mode, and restore
* its calibration parameters if there are some previously stored
* calibration parameters.
* L4 and WB series STM32 needs to be awaken from deep sleep mode, and
* restore its calibration parameters if there are some previously
* stored calibration parameters.
*/
LL_ADC_DisableDeepPowerDown(adc);
#endif
/*
* F3 and L4 ADC modules need some time to be stabilized before
* F3, L4, and WB ADC modules need some time to be stabilized before
* performing any enable or calibration actions.
*/
#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32L4X)
defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
LL_ADC_EnableInternalRegulator(adc);
k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);
#endif
@@ -513,7 +519,8 @@ static int adc_stm32_init(struct device *dev)
defined(CONFIG_SOC_SERIES_STM32L0X)
LL_ADC_SetClock(adc, LL_ADC_CLOCK_SYNC_PCLK_DIV4);
#elif defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32L4X)
defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(),
LL_ADC_CLOCK_SYNC_PCLK_DIV4);
#endif
@@ -530,7 +537,8 @@ static int adc_stm32_init(struct device *dev)
#endif

#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32L0X)
defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
if (LL_ADC_IsActiveFlag_ADRDY(adc)) {
LL_ADC_ClearFlag_ADRDY(adc);
}
@@ -545,7 +553,8 @@ static int adc_stm32_init(struct device *dev)
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32L4X)
defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
/*
* ADC modules on these series have to wait for some cycles to be
* enabled.
@@ -566,10 +575,11 @@ static int adc_stm32_init(struct device *dev)

LL_ADC_Enable(adc);

#ifdef CONFIG_SOC_SERIES_STM32L4X
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
/*
* Enabling ADC modules in L4 series may fail if they are still not
* stabilized, this will wait for a short time to ensure ADC modules
* Enabling ADC modules in L4 and WB series may fail if they are still
* not stabilized, this will wait for a short time to ensure ADC modules
* are properly enabled.
*/
u32_t countTimeout = 0;
@@ -148,4 +148,11 @@
#define DT_TIM_STM32_17_CLOCK_BITS DT_ST_STM32_TIMERS_40014800_CLOCK_BITS
#define DT_TIM_STM32_17_CLOCK_BUS DT_ST_STM32_TIMERS_40014800_CLOCK_BUS

#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_50040000_BASE_ADDRESS
#define DT_ADC_1_IRQ DT_ST_STM32_ADC_50040000_IRQ_0
#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_50040000_IRQ_0_PRIORITY
#define DT_ADC_1_NAME DT_ST_STM32_ADC_50040000_LABEL
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_50040000_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_50040000_CLOCK_BUS_0

/* End of SoC Level DTS fixup file */
@@ -61,6 +61,10 @@
#include <stm32wbxx_ll_spi.h>
#endif /* CONFIG_SPI_STM32 */

#ifdef CONFIG_ADC_STM32
#include <stm32wbxx_ll_adc.h>
#endif

#endif /* !_ASMLANGUAGE */

#endif /* _STM32WBX_SOC_H_ */

0 comments on commit 837f07a

Please sign in to comment.
You can’t perform that action at this time.