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boards/riscv32: Add support for the HiFive1 Rev B

The HiFive1 Rev B adds the following features to the
original HiFive1:

 - A second UART peripheral 'uart_1'
 - A hardware I2C peripheral 'i2c_0'
 - Segger J-Link OB
 - An ESP32-WROOM attached to the 'spi_1' peripheral bus

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
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nategraff-sifive authored and nashif committed Mar 19, 2019
1 parent bd2919d commit 8b402602835f3b9a673a280b3ce3c9d79b7129f9
@@ -0,0 +1,6 @@
# Copyright (c) 2019 SiFive Inc.
# SPDX-License-Identifier: Apache-2.0
zephyr_library()
zephyr_library_sources(pinmux.c)
zephyr_library_sources(clock.c)
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
@@ -0,0 +1,5 @@
# Copyright (c) 2019 SiFive Inc.
# SPDX-License-Identifier: Apache-2.0
config BOARD_HIFIVE1_REVB
bool "HiFive1 Rev B target"
depends on SOC_RISCV32_SIFIVE_FREEDOM
@@ -0,0 +1,35 @@
# Copyright (c) 2019 SiFive Inc.
# SPDX-License-Identifier: Apache-2.0
if BOARD_HIFIVE1_REVB

config BOARD
default "hifive1_revb"

config HAS_FLASH_LOAD_OFFSET
default y

config FLASH_BASE_ADDRESS
default $(dt_hex_val,DT_FLASH_BASE_ADDRESS)

config FLASH_LOAD_OFFSET
default 0x0

if PWM
config PWM_SIFIVE
default y
endif

if SPI
config SPI_SIFIVE
default y
endif

if I2C
config I2C_SIFIVE
default y
endif

config HAS_DTS_I2C
default y

endif
@@ -0,0 +1,8 @@
# Copyright (c) 2019 SiFive Inc.
# SPDX-License-Identifier: Apache-2.0
board_runner_args(jlink "--device=FE310")
board_runner_args(jlink "--iface=JTAG")
board_runner_args(jlink "--speed=4000")
board_runner_args(jlink "--tool-opt=-jtagconf -1,-1")
board_runner_args(jlink "--tool-opt=-autoconnect 1")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
@@ -0,0 +1,25 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Copyright (c) 2017 Palmer Dabbelt <palmer@dabbelt.com>
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <init.h>
#include "prci.h"

/* Selects the 16MHz oscilator on the HiFive1 board, which provides a clock
* that's accurate enough to actually drive serial ports off of.
*/
static int hifive1_revb_clock_init(struct device *dev)
{
ARG_UNUSED(dev);

PRCI_REG(PRCI_PLLCFG) = PLL_REFSEL(1) | PLL_BYPASS(1);
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
return 0;
}

SYS_INIT(hifive1_revb_clock_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);
@@ -0,0 +1,46 @@
.. _hifive1_revb:

SiFive HiFive1 Rev B
####################

Overview
********

The HiFive1 Rev B is an Arduino-compatible development board with
a SiFive FE310-G002 RISC-V SoC.

Programming and debugging
*************************

Building
========

Applications for the ``hifive1_revb`` board configuration can be built as usual
(see :ref:`build_an_application`) using the corresponding board name:

.. zephyr-app-commands::
:board: hifive1_revb
:goals: build

Flashing
========

The HiFive 1 Rev B uses Segger J-Link OB for flashing and debugging. To flash and
debug the board, you'll need to install the
`Segger J-Link Software and Documentation Pack
<https://www.segger.com/downloads/jlink#J-LinkSoftwareAndDocumentationPack>`_
and choose version V6.46a or later (Downloads for Windows, Linux, and MacOS are
available).

With the Segger J-Link Software installed, you can flash the application as usual
(see :ref:`build_an_application` and :ref:`application_run` for more details):

.. code-block:: console

west flash

Debugging
=========

Refer to the detailed overview about :ref:`application_debugging`.

@@ -0,0 +1,101 @@
/* Copyright (c) 2019 SiFive, Inc. */
/* SPDX-License-Identifier: Apache-2.0 */

/dts-v1/;

#include <riscv32-fe310.dtsi>

/ {
model = "SiFive HiFive 1 Rev B";
compatible = "sifive,hifive1-revb";
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
};

chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &dtim;
zephyr,flash = &flash0;
};

leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 19 0>;
label = "Green LED";
};
led1: led_1 {
gpios = <&gpio0 21 0>;
label = "Blue LED";
};
led2: led_2 {
gpios = <&gpio0 22 0>;
label = "Red LED";
};
};
};

&gpio0 {
status = "ok";
};

&uart0 {
status = "ok";
current-speed = <115200>;
clock-frequency = <16000000>;
};

&uart1 {
status = "ok";
current-speed = <115200>;
clock-frequency = <16000000>;
};

&spi0 {
status = "ok";
clock-frequency = <16000000>;

#address-cells = <1>;
#size-cells = <0>;
reg = <0x10014000 0x1000 0x20010000 0x3c0900>;
flash0: flash@0 {
compatible = "issi,is25lp128", "jedec,spi-nor";
jedec-id = <0x96 0x60 0x18>;
reg = <0>;
};
};

&spi1 {
status = "ok";
clock-frequency = <16000000>;
};

&spi2 {
status = "ok";
clock-frequency = <16000000>;
};

&pwm0 {
status = "ok";
clock-frequency = <16000000>;
};

&pwm1 {
status = "ok";
clock-frequency = <16000000>;
};

&pwm2 {
status = "ok";
clock-frequency = <16000000>;
};

&i2c0 {
status = "ok";
input-frequency = <16000000>;
clock-frequency = <100000>;
};

@@ -0,0 +1,11 @@
identifier: hifive1_revb
name: SiFive HiFive1 Rev B
type: mcu
arch: riscv32
toolchain:
- zephyr
ram: 16
testing:
ignore_tags:
- net
- bluetooth
@@ -0,0 +1,17 @@
CONFIG_RISCV32=y
CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
CONFIG_BOARD_HIFIVE1_REVB=y
CONFIG_RISCV_MACHINE_TIMER=y
CONFIG_PLIC=y
CONFIG_GPIO=y
CONFIG_GPIO_SIFIVE=y
CONFIG_PINMUX=y
CONFIG_PINMUX_SIFIVE=y
CONFIG_CONSOLE=y
CONFIG_PRINTK=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_BOOT_BANNER=y
@@ -0,0 +1,45 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <init.h>
#include <pinmux.h>
#include <soc.h>

static int hifive1_revb_pinmux_init(struct device *dev)
{
ARG_UNUSED(dev);

struct device *p = device_get_binding(CONFIG_PINMUX_SIFIVE_0_NAME);

#ifdef CONFIG_UART_SIFIVE
#ifdef CONFIG_UART_SIFIVE_PORT_0
/* UART0 RX */
pinmux_pin_set(p, 16, SIFIVE_PINMUX_IOF0);
/* UART0 TX */
pinmux_pin_set(p, 17, SIFIVE_PINMUX_IOF0);
#endif /* CONFIG_UART_SIFIVE_PORT_0 */
#endif /* CONFIG_UART_SIFIVE */

#ifdef CONFIG_SPI_SIFIVE
/* SPI1 */
pinmux_pin_set(p, 2, SIFIVE_PINMUX_IOF0); /* SS0 */
pinmux_pin_set(p, 3, SIFIVE_PINMUX_IOF0); /* MOSI */
pinmux_pin_set(p, 4, SIFIVE_PINMUX_IOF0); /* MISO */
pinmux_pin_set(p, 5, SIFIVE_PINMUX_IOF0); /* SCK */
pinmux_pin_set(p, 9, SIFIVE_PINMUX_IOF0); /* SS2 */
pinmux_pin_set(p, 10, SIFIVE_PINMUX_IOF0); /* SS3 */
#endif /* CONFIG_SPI_SIFIVE */

#ifdef CONFIG_I2C_SIFIVE
/* I2C 0 */
pinmux_pin_set(p, 12, SIFIVE_PINMUX_IOF0);
pinmux_pin_set(p, 13, SIFIVE_PINMUX_IOF0);
#endif /* CONFIG_I2C_SIFIVE */

return 0;
}

SYS_INIT(hifive1_revb_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);
@@ -0,0 +1,63 @@
/*
* Copyright (c) 2017 SiFive Inc
*
* SPDX-License-Identifier: Apache-2.0
*/

#ifndef _SIFIVE_PRCI_H
#define _SIFIVE_PRCI_H

#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)

/* Register offsets */

#define PRCI_HFROSCCFG (0x0000)
#define PRCI_HFXOSCCFG (0x0004)
#define PRCI_PLLCFG (0x0008)
#define PRCI_PLLDIV (0x000C)
#define PRCI_PROCMONCFG (0x00F0)

/* Fields */
#define ROSC_DIV(x) (((x) & 0x2F) << 0)
#define ROSC_TRIM(x) (((x) & 0x1F) << 16)
#define ROSC_EN(x) (((x) & 0x1) << 30)
#define ROSC_RDY(x) (((x) & 0x1) << 31)

#define XOSC_EN(x) (((x) & 0x1) << 30)
#define XOSC_RDY(x) (((x) & 0x1) << 31)

#define PLL_R(x) (((x) & 0x7) << 0)
/* single reserved bit for F LSB. */
#define PLL_F(x) (((x) & 0x3F) << 4)
#define PLL_Q(x) (((x) & 0x3) << 10)
#define PLL_SEL(x) (((x) & 0x1) << 16)
#define PLL_REFSEL(x) (((x) & 0x1) << 17)
#define PLL_BYPASS(x) (((x) & 0x1) << 18)
#define PLL_LOCK(x) (((x) & 0x1) << 31)

#define PLL_R_default 0x1
#define PLL_F_default 0x1F
#define PLL_Q_default 0x3

#define PLL_REFSEL_HFROSC 0x0
#define PLL_REFSEL_HFXOSC 0x1

#define PLL_SEL_HFROSC 0x0
#define PLL_SEL_PLL 0x1

#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)
#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1) << 8)

#define PROCMON_DIV(x) (((x) & 0x1F) << 0)
#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)
#define PROCMON_EN(x) (((x) & 0x1) << 16)
#define PROCMON_SEL(x) (((x) & 0x3) << 24)
#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)

#define PROCMON_SEL_HFCLK 0
#define PROCMON_SEL_HFXOSCIN 1
#define PROCMON_SEL_PLLOUTDIV 2
#define PROCMON_SEL_PROCMON 3

#endif /* _SIFIVE_PRCI_H */
@@ -64,5 +64,6 @@
#define DT_SIFIVE_UART_1_IRQ_0 DT_SIFIVE_UART0_10023000_IRQ_0
#define DT_SIFIVE_UART_1_LABEL DT_SIFIVE_UART0_10023000_LABEL
#define DT_SIFIVE_UART_1_SIZE DT_SIFIVE_UART0_10023000_SIZE
#define DT_SIFIVE_UART_1_LABEL DT_SIFIVE_UART0_10023000_LABEL
#define DT_SIFIVE_UART_1_CLK_FREQ DT_SIFIVE_UART0_10023000_CLOCK_FREQUENCY

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