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soc: riscv32: Use same clock freq for both rv32m1 cores

Both the ri5cy and zero-riscy cores in the rv32m1 soc use the same
source clock, so we don't need to conditionalize
SYS_CLOCK_HW_CYCLES_PER_SEC on the ri5cy core.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
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MaureenHelm authored and galak committed Dec 3, 2018
1 parent 2261d3e commit 8fa5353bd2bb0975b638d95d1636b9bfe41edb62
Showing with 1 addition and 1 deletion.
  1. +1 −1 soc/riscv32/openisa_rv32m1/Kconfig.defconfig
@@ -81,7 +81,7 @@ config RISCV32_RV32M1_VECTOR_SIZE

config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 8000000 if SOC_OPENISA_RV32M1_RI5CY # SIRC at 8MHz
default 8000000

if MULTI_LEVEL_INTERRUPTS

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