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soc: riscv32: Use same clock freq for both rv32m1 cores
Both the ri5cy and zero-riscy cores in the rv32m1 soc use the same source clock, so we don't need to conditionalize SYS_CLOCK_HW_CYCLES_PER_SEC on the ri5cy core. Signed-off-by: Maureen Helm <email@example.com>
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