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soc: arm: ke1xf: add NXP Kinetis KE1xF SoC series support

Add initial support for the NXP Kinetis KE1xF SoC series (MKE14F16,
MKE16F16, and MKE18F16).

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
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henrikbrixandersen authored and MaureenHelm committed May 4, 2019
1 parent d4b9c0d commit 918579ebbfd7f29d1e0281652c9c770abce9e34f
@@ -213,6 +213,7 @@
/include/drivers/mvic.h @andrewboie
/include/drivers/pcie/ @gnuless
/include/drivers/serial/uart_ns16550.h @gnuless
/include/dt-bindings/clock/kinetis_scg.h @henrikbrixandersen
/include/dt-bindings/pcie/ @gnuless
/include/fs.h @nashif @wentongwu
/include/fs/ @nashif @wentongwu
@@ -0,0 +1,7 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <nxp/nxp_ke1xf256vlx16.dtsi>
@@ -0,0 +1,7 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <nxp/nxp_ke1xf512vlx16.dtsi>
@@ -0,0 +1,7 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <nxp/nxp_ke1xf256vlx16.dtsi>
@@ -0,0 +1,7 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <nxp/nxp_ke1xf512vlx16.dtsi>
@@ -0,0 +1,7 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <nxp/nxp_ke1xf256vlx16.dtsi>
@@ -0,0 +1,7 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <nxp/nxp_ke1xf512vlx16.dtsi>
@@ -0,0 +1,186 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <arm/armv7-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>

/ {
aliases {
uart-0 = &uart0;
uart-1 = &uart1;
uart-2 = &uart2;
pinmux-a = &pinmux_a;
pinmux-b = &pinmux_b;
pinmux-c = &pinmux_c;
pinmux-d = &pinmux_d;
pinmux-e = &pinmux_e;
gpio-a = &gpioa;
gpio-b = &gpiob;
gpio-c = &gpioc;
gpio-d = &gpiod;
gpio-e = &gpioe;
};

cpus {
#address-cells = <1>;
#size-cells = <0>;

cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};

soc {
mpu: mpu@4000d000 {
compatible = "nxp,kinetis-mpu";
reg = <0x4000d000 0x1000>;
status = "disabled";
};

sim: sim@40048000 {
compatible = "nxp,kinetis-sim";
reg = <0x40048000 0x1000>;
label = "SIM";
};

scg: scg@40064000 {
compatible = "nxp,kinetis-scg";
reg = <0x40064000 0x1000>;
label = "SCG";
};

pcc: pcc@40065000 {
compatible = "nxp,kinetis-pcc";
reg = <0x40065000 0x1000>;
label = "PCC";
clock-controller;
#clock-cells = <1>;
};

flash_controller: flash-controller@40020000 {
compatible = "nxp,kinetis-ftfe";
label = "FLASH_CTRL";
reg = <0x40020000 0x1000>;
interrupts = <18 0>, <19 0>;
interrupt-names = "command-complete", "read-collision";

#address-cells = <1>;
#size-cells = <1>;
};

uart0: uart@4006a000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x4006a000 0x1000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "transmit", "receive";
clocks = <&pcc 0x1a8>;
label = "UART_0";
status = "disabled";
};

uart1: uart@4006b000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x4006b000 0x1000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "transmit", "receive";
clocks = <&pcc 0x1ac>;
label = "UART_1";
status = "disabled";
};

uart2: uart@4006c000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x4006c000 0x1000>;
interrupts = <35 0>, <36 0>;
interrupt-names = "transmit", "receive";
clocks = <&pcc 0x1b0>;
label = "UART_2";
status = "disabled";
};

pinmux_a: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0x1000>;
clocks = <&pcc 0x124>;
};

pinmux_b: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0x1000>;
clocks = <&pcc 0x128>;
};

pinmux_c: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0x1000>;
clocks = <&pcc 0x12c>;
};

pinmux_d: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004c000 0x1000>;
clocks = <&pcc 0x130>;
};

pinmux_e: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004d000 0x1000>;
clocks = <&pcc 0x134>;
};

gpioa: gpio@400ff000 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff000 0x40>;
interrupts = <59 2>;
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
};

gpiob: gpio@400ff040 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff040 0x40>;
interrupts = <60 2>;
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
};

gpioc: gpio@400ff080 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff080 0x40>;
interrupts = <61 2>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
};

gpiod: gpio@400ff0c0 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff0c0 0x40>;
interrupts = <62 2>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
};

gpioe: gpio@400ff100 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff100 0x40>;
interrupts = <63 2>;
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
};
};
};

&nvic {
arm,num-irq-priority-bits = <4>;
};
@@ -0,0 +1,41 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <mem.h>
#include <nxp/nxp_ke1xf.dtsi>

/ {
/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
* contiguous block in the memory map, however misaligned accesses
* across the 0x2000_0000 boundary are not supported in the Arm
* Cortex-M4 architecture. For clarity and to avoid the temptation for
* someone to extend sram0 without solving this issue, we define two
* separate memory nodes here and only use the upper one for now. A
* potential solution has been proposed in binutils:
* https://sourceware.org/ml/binutils/2017-02/msg00250.html
*/
sram_l: memory@1fffc000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x1fffc000 DT_SIZE_K(16)>;
};

sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(16)>;
};
};

&flash_controller {
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "MCUX_FLASH";
reg = <0 DT_SIZE_K(256)>;
erase-block-size = <DT_SIZE_K(4)>;
write-block-size = <8>;
};
};
@@ -0,0 +1,41 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <mem.h>
#include <nxp/nxp_ke1xf.dtsi>

/ {
/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
* contiguous block in the memory map, however misaligned accesses
* across the 0x2000_0000 boundary are not supported in the Arm
* Cortex-M4 architecture. For clarity and to avoid the temptation for
* someone to extend sram0 without solving this issue, we define two
* separate memory nodes here and only use the upper one for now. A
* potential solution has been proposed in binutils:
* https://sourceware.org/ml/binutils/2017-02/msg00250.html
*/
sram_l: memory@1fff8000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x1fff8000 DT_SIZE_K(32)>;
};

sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(32)>;
};
};

&flash_controller {
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "MCUX_FLASH";
reg = <0 DT_SIZE_K(512)>;
erase-block-size = <DT_SIZE_K(4)>;
write-block-size = <8>;
};
};

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