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soc: arm: st_stm32: Add STM32L1 SoC series

Add STM32L1 SoC series support with STM32L15XXB as the target
SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Mani-Sadhasivam authored and galak committed Feb 1, 2019
1 parent 9f82604 commit 92ac6d8fc66153155bd8d1ceea94a55f8f565d8d
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/*
* Copyright (c) 2019 Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <arm/armv7-m.dtsi>

/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;

cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
};
};

sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
};

soc {
flash-controller@40023c00 {
compatible = "st,stm32l1-flash-controller";
label = "FLASH_CTRL";
reg = <0x40023c00 0x400>;
interrupts = <4 0>;

#address-cells = <1>;
#size-cells = <1>;

flash0: flash@8000000 {
compatible = "soc-nv-flash";
label = "FLASH_STM32";

write-block-size = <4>;
};
};

};
};

&nvic {
arm,num-irq-priority-bits = <4>;
};
@@ -0,0 +1,7 @@
/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <st/l1/stm32l1.dtsi>
@@ -0,0 +1,22 @@
/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <mem.h>
#include <st/l1/stm32l151.dtsi>

/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(16)>;
};

soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
};
};
};
};
@@ -0,0 +1,15 @@
---
title: STM32 L1 Flash Controller
version: 0.1

description: >
This binding gives a base representation of the STM32 L1 Flash Controller
inherits:
!include flash-controller.yaml

properties:
compatible:
constraint: "st,stm32l1-flash-controller"

...
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zephyr_include_directories(${ZEPHYR_BASE}/drivers)
zephyr_sources(
soc.c
)
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# Kconfig - ST Microelectronics STM32L1 MCU line
#
# Copyright (c) 2019 Linaro Ltd.
#
# SPDX-License-Identifier: Apache-2.0
#

if SOC_SERIES_STM32L1X

source "soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l1*"

config SOC_SERIES
default "stm32l1"

endif # SOC_SERIES_STM32L1X
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# Kconfig - ST Microelectronics STM32L151XB MCU
#
# Copyright (c) 2019 Linaro Ltd.
#
# SPDX-License-Identifier: Apache-2.0
#

if SOC_STM32L151XB

config SOC
string
default "stm32l151xb"

config NUM_IRQS
int
default 45

endif # SOC_STM32L151XB
@@ -0,0 +1,16 @@
# Kconfig - ST Microelectronics STM32L1 MCU series
#
# Copyright (c) 2019 Linaro Ltd.
#
# SPDX-License-Identifier: Apache-2.0
#

config SOC_SERIES_STM32L1X
bool "STM32L1x Series MCU"
select CPU_CORTEX_M3
select SOC_FAMILY_STM32
select HAS_STM32CUBE
select CPU_HAS_SYSTICK
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
help
Enable support for STM32L1 MCU series
@@ -0,0 +1,15 @@
# Kconfig - ST Microelectronics STM32L1 MCU line
#
# Copyright (c) 2019 Linaro Ltd.
#
# SPDX-License-Identifier: Apache-2.0
#

choice
prompt "STM32L1x MCU Selection"
depends on SOC_SERIES_STM32L1X

config SOC_STM32L151XB
bool "STM32L151XB"

endchoice
@@ -0,0 +1,11 @@
/*
* Copyright (c) 2019 Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/

/* SoC level DTS fixup file */

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

/* End of SoC Level DTS fixup file */
@@ -0,0 +1,9 @@
/* linker.ld - Linker command/script file */

/*
* Copyright (c) 2019 Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <arch/arm/cortex_m/scripts/linker.ld>
@@ -0,0 +1,51 @@
/*
* Copyright (c) 2019 Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/

/**
* @file
* @brief System/hardware module for STM32L1 processor
*/

#include <device.h>
#include <init.h>
#include <arch/cpu.h>
#include <cortex_m/exc.h>
#include <linker/linker-defs.h>
#include <string.h>

/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int stm32l1_init(struct device *arg)
{
u32_t key;

ARG_UNUSED(arg);

key = irq_lock();

z_clearfaults();

/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();

irq_unlock(key);

/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 2.1 MHz from MSI */
SystemCoreClock = 2097000;

return 0;
}

SYS_INIT(stm32l1_init, PRE_KERNEL_1, 0);
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2019 Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/

/**
* @file SoC configuration macros for the STM32L1 family processors.
*
* Based on reference manual:
* STM32L1X advanced ARM ® -based 32-bit MCUs
*
* Chapter 2.2: Memory organization
*/


#ifndef _STM32L1_SOC_H_
#define _STM32L1_SOC_H_

#ifndef _ASMLANGUAGE

#include <stm32l1xx.h>

/* ARM CMSIS definitions must be included before kernel_includes.h.
* Therefore, it is essential to include kernel_includes.h after including
* core SOC-specific headers.
*/
#include <kernel_includes.h>

#include <stm32l1xx_ll_system.h>

#endif /* !_ASMLANGUAGE */

#endif /* _STM32L1_SOC_H_ */
@@ -0,0 +1,12 @@
/*
* Copyright (c) 2019 Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/

#ifndef _STM32L1X_SOC_REGISTERS_H_
#define _STM32L1X_SOC_REGISTERS_H_

/* include register mapping headers */

#endif /* _STM32L1X_SOC_REGISTERS_H_ */

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