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drivers/interrupt_controller/loapic_intr.c: enable x2APIC support

When CONFIG_X2APIC is enabled, twiddle the appropriate MSR during
initialization to enable x2APIC mode.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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Charles E. Youse authored and nashif committed Jun 7, 2019
1 parent e9f6cb2 commit 9a1e92735c047c8a95b6eb204fe5b5a15bd3aaa7
Showing with 23 additions and 2 deletions.
  1. +20 −2 drivers/interrupt_controller/loapic_intr.c
  2. +3 −0 include/arch/x86/msr.h
@@ -13,6 +13,7 @@
#include <zephyr/types.h>
#include <string.h>
#include <misc/__assert.h>
#include <arch/x86/msr.h>

#include <toolchain.h>
#include <linker/sections.h>
@@ -93,8 +94,25 @@ static int loapic_init(struct device *unused)
ARG_UNUSED(unused);
s32_t loApicMaxLvt; /* local APIC Max LVT */

/* enable the Local APIC */
x86_write_loapic(LOAPIC_SVR, x86_read_loapic(LOAPIC_SVR) | LOAPIC_ENABLE);
/*
* enable the local APIC. note that we use xAPIC mode here, since
* x2APIC access is not enabled until the next step (if at all).
*/

x86_write_xapic(LOAPIC_SVR,
x86_read_xapic(LOAPIC_SVR) | LOAPIC_ENABLE);

#ifdef CONFIG_X2APIC
/*
* turn on x2APIC mode. we trust the config option, so
* we don't check CPUID to see if x2APIC is supported.
*/

u64_t msr = z_x86_msr_read(X86_APIC_BASE_MSR);
msr |= X86_APIC_BASE_MSR_X2APIC;
z_x86_msr_write(X86_APIC_BASE_MSR, msr);
#endif

loApicMaxLvt = (x86_read_loapic(LOAPIC_VER) & LOAPIC_MAXLVT_MASK) >> 16;

/* reset the DFR, TPR, TIMER_CONFIG, and TIMER_ICR */
@@ -18,7 +18,10 @@
#define X86_MONITOR_FILTER_SIZE_MSR 0x0006
#define X86_TIME_STAMP_COUNTER_MSR 0x0010
#define X86_X86_SOC_ID_MSR 0x0017

#define X86_APIC_BASE_MSR 0x001b
#define X86_APIC_BASE_MSR_X2APIC BIT(10)

#define X86_FEATURE_CONTROL_MSR 0x003a
#define X86_BIOS_SIGN_MSR 0x008b
#define X86_SMM_MONITOR_CTL_MSR 0x009b

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