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drivers: pinmux: Add STM32G0X pinmux support

Add pinmux support for STM32G0X SoC series.

Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>

# Conflicts:
#	drivers/pinmux/stm32/pinmux_stm32.h
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FRASTM authored and MaureenHelm committed Jul 1, 2019
1 parent da48451 commit 9b2025c8915d39dc1c0b19c87f504b53eb0bb1b6
@@ -222,6 +222,8 @@ const int gpio_stm32_enable_int(int port, int pin)
line = ((pin % 4 * 4) << 16) | (pin / 4);
#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
line = (((pin * 8) % 32) << 16) | (pin / 4);
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
line = ((pin & 0x3) << (16 + 3)) | (pin >> 2);
#else
line = (0xF << ((pin % 4 * 4) + 16)) | (pin / 4);
#endif
@@ -241,6 +243,8 @@ const int gpio_stm32_enable_int(int port, int pin)
LL_GPIO_AF_SetEXTISource(port, line);
#elif CONFIG_SOC_SERIES_STM32MP1X
LL_EXTI_SetEXTISource(port, line);
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
LL_EXTI_SetEXTISource(port, line);
#else
LL_SYSCFG_SetEXTISource(port, line);
#endif
@@ -113,6 +113,8 @@ void stm32_setup_pins(const struct pin_config *pinconf,
#include "pinmux_stm32f7.h"
#elif CONFIG_SOC_SERIES_STM32H7X
#include "pinmux_stm32h7.h"
#elif CONFIG_SOC_SERIES_STM32G0X
#include "pinmux_stm32g0.h"
#elif CONFIG_SOC_SERIES_STM32L0X
#include "pinmux_stm32l0.h"
#elif CONFIG_SOC_SERIES_STM32L1X
@@ -0,0 +1,29 @@
/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2019 ST Microelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/

#ifndef ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32G0_H_
#define ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32G0_H_

/**
* @file Header for STM32G0 pin multiplexing helper
*/
#define STM32G0_PINMUX_FUNC_PA2_USART2_TX \
(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_NOPULL)
#define STM32G0_PINMUX_FUNC_PA3_USART2_RX \
(STM32_PINMUX_ALT_FUNC_1 | STM32_PUPDR_NO_PULL)

#define STM32G0_PINMUX_FUNC_PB6_USART1_TX \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32G0_PINMUX_FUNC_PB7_USART1_RX \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUPDR_NO_PULL)
#define STM32G0_PINMUX_FUNC_PB6_USART1_TX_RX \
(STM32_PINMUX_ALT_FUNC_0 | STM32_OPENDRAIN_PULLUP)

#define STM32G0_PINMUX_FUNC_PA7_TIM3_CH2 \
(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_NOPULL)

#endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32G0_H_ */
@@ -0,0 +1,32 @@
/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2019 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <dt-bindings/pinctrl/stm32-pinctrl.h>

/ {
soc {
pinctrl: pin-controller@50000000 {
usart2_pins_a: usart2_a {
rx_tx {
rx = <STM32_PIN_PA3 (STM32_PINMUX_ALT_FUNC_1 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PA2 (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_NOPULL)>;
};
};
usart1_pins_a: usart1_a {
rx_tx {
rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_0 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)>;
};
};
usart1_pins_a_hd: usart1_a_hd {
rx_tx {
tx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_0 | STM32_OPENDRAIN_PULLUP)>;
};
};
};
};
};
@@ -54,6 +54,13 @@
label = "STM32_CLK_RCC";
};

pinctrl: pin-controller@50000000 {
compatible = "st,stm32-pinmux";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x2000>;
};

timers3: timers@40000400 {
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;

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