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dts: LPC55S69 initial device tree

Create device tree for LPCXpresso55S69 board.
Single core (cpu0) is currently supported.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
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agansari authored and MaureenHelm committed Apr 24, 2019
1 parent e90d184 commit b342258b85222b03faa7c2e7bbf141e64be30f08
Showing with 101 additions and 0 deletions.
  1. +88 −0 dts/arm/nxp/nxp_lpc55S6x.dtsi
  2. +13 −0 dts/arm/nxp/nxp_lpc55S6x_cpu0.dtsi
@@ -0,0 +1,88 @@
/*
* Copyright (c) 2019, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <dt-bindings/gpio/gpio.h>

/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;

cpu@0 {
compatible = "arm,cortex-m33f";
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-m33";
reg = <1>;
};
};

sram0:memory@30000000 {
compatible = "mmio-sram";
reg = <0x30000000 DT_SIZE_K(64)>;
};

sram1:memory@30010000 {
compatible = "mmio-sram";
reg = <0x30010000 DT_SIZE_K(64)>;
};

sram2:memory@30020000 {
compatible = "mmio-sram";
reg = <0x30020000 DT_SIZE_K(64)>;
};

sram3:memory@30030000 {
compatible = "mmio-sram";
reg = <0x30030000 DT_SIZE_K(64)>;
};

sramx:memory@50000000{
compatible = "mmio-sram";
reg = <0x40000000 DT_SIZE_K(32)>;
};

soc {

flash0:flash@10000000 {
compatible = "soc-nv-flash";
reg = <0x10000000 DT_SIZE_K(630)>;
};

usart0:usart@50086000 {
compatible = "nxp,lpc-usart";
reg = <0x50086000 0xE44>;
interrupts = <14 0>;
label = "USART_0";
status = "disabled";
};

gpio0: gpio@0 {
compatible = "nxp,kinetis-gpio";
reg = <0x5008c000 0x2488>;
interrupts = <2 2>;
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
};

gpio1: gpio@1 {
compatible = "nxp,kinetis-gpio";
reg = <0x5008c000 0x2488>;
interrupts = <3 2>;
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
};
};
};

&nvic {
arm,num-irq-priority-bits = <3>;
};
@@ -0,0 +1,13 @@
/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <nxp/nxp_lpc55S6x.dtsi>

/ {
cpus {
/delete-node/ cpu@1;
};
};

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