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gpio: Add stm32mp157c_dk2 board support

Add support for stm32mp1x GPIO with Zephyr GPIO driver

Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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yboutreux authored and galak committed Apr 1, 2019
1 parent 524c625 commit b4b7020b035384f94d3b9e5de706ae2fc03c6f46
@@ -168,6 +168,8 @@ features:
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+

The default configuration can be found in the defconfig file:
``boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig``
@@ -6,6 +6,8 @@ toolchain:
- zephyr
- gccarmemb
- xtools
supported:
- gpio
testing:
ignore_tags:
- cmsis_rtos_v2
@@ -17,7 +19,6 @@ testing:
- cmm
- shell
- LED
- gpio
- nfc
ram: 256
flash: 64
@@ -6,6 +6,9 @@ CONFIG_CORTEX_M_SYSTICK=y
# 209 MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=209000000

# enable GPIO
CONFIG_GPIO=y

# clock configuration
CONFIG_CLOCK_CONTROL=y

@@ -214,6 +214,8 @@ const int gpio_stm32_enable_int(int port, int pin)
#if defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32F0X)
line = ((pin % 4 * 4) << 16) | (pin / 4);
#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
line = (((pin * 8) % 32) << 16) | (pin / 4);
#else
line = (0xF << ((pin % 4 * 4) + 16)) | (pin / 4);
#endif
@@ -231,6 +233,8 @@ const int gpio_stm32_enable_int(int port, int pin)

#ifdef CONFIG_SOC_SERIES_STM32F1X
LL_GPIO_AF_SetEXTISource(port, line);
#elif CONFIG_SOC_SERIES_STM32MP1X
LL_EXTI_SetEXTISource(port, line);
#else
LL_SYSCFG_SetEXTISource(port, line);
#endif
@@ -112,6 +112,19 @@
#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
#define STM32_PERIPH_GPIOI LL_AHB2_GRP1_PERIPH_GPIOI
#elif CONFIG_SOC_SERIES_STM32MP1X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4
#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH
#define STM32_PERIPH_GPIOI LL_AHB4_GRP1_PERIPH_GPIOI
#define STM32_PERIPH_GPIOJ LL_AHB4_GRP1_PERIPH_GPIOJ
#define STM32_PERIPH_GPIOK LL_AHB4_GRP1_PERIPH_GPIOK
#elif CONFIG_SOC_SERIES_STM32WBX
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
@@ -6,6 +6,8 @@

#include <mem.h>
#include <arm/armv7-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/stm32_clock.h>

/ {
cpus {
@@ -39,6 +41,111 @@
label = "STM32_CLK_RCC";
};

pinctrl: pin-controller@50002000 {
compatible = "st,stm32-pinmux";
reg = <0x50002000 0x9000>;
#address-cells = <1>;
#size-cells = <1>;

gpioa: gpio@50002000 {
compatible = "st,stm32-gpio";
reg = <0x50002000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
label = "GPIOA";
};

gpiob: gpio@50003000 {
compatible = "st,stm32-gpio";
reg = <0x50003000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
label = "GPIOB";
};

gpioc: gpio@50004000 {
compatible = "st,stm32-gpio";
reg = <0x50004000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
label = "GPIOC";
};

gpiod: gpio@50005000 {
compatible = "st,stm32-gpio";
reg = <0x50005000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
label = "GPIOD";
};

gpioe: gpio@50006000 {
compatible = "st,stm32-gpio";
reg = <0x50006000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
label = "GPIOE";
};

gpiof: gpio@50007000 {
compatible = "st,stm32-gpio";
reg = <0x50007000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
label = "GPIOF";
};

gpiog: gpio@50008000 {
compatible = "st,stm32-gpio";
reg = <0x50008000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
label = "GPIOG";
};

gpioh: gpio@50009000 {
compatible = "st,stm32-gpio";
reg = <0x50009000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
label = "GPIOH";
};

gpioi: gpio@5000a000 {
compatible = "st,stm32-gpio";
reg = <0x5000a000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
label = "GPIOI";
};

gpioj: gpio@5000b000 {
compatible = "st,stm32-gpio";
reg = <0x5000b000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
label = "GPIOJ";
};

gpiok: gpio@5000c000 {
compatible = "st,stm32-gpio";
reg = <0x5000c000 0x400>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
label = "GPIOK";
};
};
};
};

@@ -16,4 +16,32 @@ config STM32_CORE_CM4
bool "define stm32 core"
default y

if GPIO_STM32

config GPIO_STM32_PORTD
default y

config GPIO_STM32_PORTE
default y

config GPIO_STM32_PORTF
default y

config GPIO_STM32_PORTG
default y

config GPIO_STM32_PORTH
default y

config GPIO_STM32_PORTI
default y

config GPIO_STM32_PORTJ
default y

config GPIO_STM32_PORTK
default y

endif # GPIO_STM32

endif # SOC_SERIES_STM32MP1X

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