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drivers: flash: Add STM32G0XX flash support

Add flash support for STM32G0X SoC series.

Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
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FRASTM authored and MaureenHelm committed Jul 5, 2019
1 parent 7ea0013 commit bfc2ea6dd5508a34e7d22439665334556de4c5ca
@@ -26,6 +26,7 @@ if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X flash_stm32f7x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X flash_stm32l4x.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX flash_stm32wbx.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X flash_stm32g0x.c)
endif()

zephyr_include_directories_ifdef(
@@ -10,23 +10,24 @@ if SOC_FAMILY_STM32

menuconfig SOC_FLASH_STM32
bool "STM32 flash driver"
depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX)
depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32G0X)
select FLASH_HAS_DRIVER_ENABLED
default y
select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F0X
select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F3X
select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32G0X
select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F4X
select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F7X
select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32L4X
select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32WBX
select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F0X
select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F3X
select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32G0X
select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F4X
select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F7X
select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32L4X
select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32WBX
help
Enable STM32F0x, STM32F3x, STM32F4x, STM32F7x, STM32L4x or
STM32WBx series flash driver.
Enable STM32F0x, STM32F3x, STM32F4x, STM32F7x, STM32L4x, STM32WBx or STM32G0x series flash driver.

endif
@@ -33,6 +33,9 @@
/* STM32WB: maximum erase time of 24.5ms for a 4K sector */
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
#define STM32_FLASH_MAX_ERASE_TIME (K_MSEC(25))
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
/* STM32G0: maximum erase time of 40ms for a 2K sector */
#define STM32_FLASH_MAX_ERASE_TIME (K_MSEC(40))
#endif

/* Let's wait for double the max erase time to be sure that the operation is
@@ -123,7 +126,8 @@ int flash_stm32_wait_flash_idle(struct device *dev)
static void flash_stm32_flush_caches(struct device *dev,
off_t offset, size_t len)
{
#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F3X)
#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32G0X)
ARG_UNUSED(dev);
ARG_UNUSED(offset);
ARG_UNUSED(len);
@@ -226,6 +230,8 @@ static int flash_stm32_write_protection(struct device *dev, bool enable)
struct stm32l4x_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev);
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev);
#endif
int rc = 0;

@@ -269,6 +275,10 @@ static struct flash_stm32_priv flash_data = {
.enr = LL_AHB1_GRP1_PERIPH_FLASH },
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
.regs = (struct stm32wbx_flash *) DT_FLASH_DEV_BASE_ADDRESS,
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
.regs = (struct stm32g0x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH },
#endif
};

@@ -294,7 +304,8 @@ static int stm32_flash_init(struct device *dev)
struct flash_stm32_priv *p = FLASH_STM32_PRIV(dev);
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F3X)
defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32G0X)
struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);

/*
@@ -12,7 +12,8 @@

#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F3X)
defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32G0X)
#include <drivers/clock_control.h>
#include <clock_control/stm32_clock_control.h>
#endif
@@ -36,6 +37,10 @@ struct flash_stm32_priv {
struct stm32_pclken pclken;
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
struct stm32wbx_flash *regs;
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
struct stm32g0x_flash *regs;
/* clock subsystem driving this peripheral */
struct stm32_pclken pclken;
#endif
struct k_sem sem;
};
@@ -0,0 +1,174 @@
/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2017 Linaro Limited
* Copyright (c) 2017 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/

#define LOG_DOMAIN flash_stm32g0
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);

#include <kernel.h>
#include <device.h>
#include <string.h>
#include <flash.h>
#include <init.h>
#include <soc.h>

#include "flash_stm32.h"


#define STM32G0X_PAGE_SHIFT 11


/*
* offset and len must be aligned on 8 for write,
* positive and not beyond end of flash
*/
bool flash_stm32_valid_range(struct device *dev, off_t offset, u32_t len,
bool write)
{
return (!write || (offset % 8 == 0 && len % 8 == 0)) &&
flash_stm32_range_exists(dev, offset, len);
}

/*
* STM32G0xx devices can have up to 64 2K pages
*/
static unsigned int get_page(off_t offset)
{
return offset >> STM32G0X_PAGE_SHIFT;
}

static int write_dword(struct device *dev, off_t offset, u64_t val)
{
volatile u32_t *flash = (u32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;

/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
return -EIO;
}

/* Check that no Flash main memory operation is ongoing */
rc = flash_stm32_wait_flash_idle(dev);
if (rc < 0) {
return rc;
}

/* Check if this double word is erased */
if (flash[0] != 0xFFFFFFFFUL ||
flash[1] != 0xFFFFFFFFUL) {
return -EIO;
}

/* Set the PG bit */
regs->cr |= FLASH_CR_PG;

/* Flush the register write */
tmp = regs->cr;

/* Perform the data write operation at the desired memory address */
flash[0] = (u32_t)val;
flash[1] = (u32_t)(val >> 32);

/* Wait until the BSY bit is cleared */
rc = flash_stm32_wait_flash_idle(dev);

/* Clear the PG bit */
regs->cr &= (~FLASH_CR_PG);

return rc;
}

static int erase_page(struct device *dev, unsigned int page)
{
struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev);
u32_t tmp;
int rc;

/* if the control register is locked, do not fail silently */
if (regs->cr & FLASH_CR_LOCK) {
return -EIO;
}

/* Check that no Flash memory operation is ongoing */
rc = flash_stm32_wait_flash_idle(dev);
if (rc < 0) {
return rc;
}

/* Set the PER bit and select the page you wish to erase */
regs->cr |= FLASH_CR_PER;
regs->cr &= ~FLASH_CR_PNB_Msk;
regs->cr |= ((page % 256) << 3);

/* Set the STRT bit */
regs->cr |= FLASH_CR_STRT;

/* flush the register write */
tmp = regs->cr;

/* Wait for the BSY bit */
rc = flash_stm32_wait_flash_idle(dev);

regs->cr &= ~FLASH_CR_PER;

return rc;
}

int flash_stm32_block_erase_loop(struct device *dev, unsigned int offset,
unsigned int len)
{
int i, rc = 0;

i = get_page(offset);
for (; i <= get_page(offset + len - 1) ; ++i) {
rc = erase_page(dev, i);
if (rc < 0) {
break;
}
}

return rc;
}

int flash_stm32_write_range(struct device *dev, unsigned int offset,
const void *data, unsigned int len)
{
int i, rc = 0;

for (i = 0; i < len; i += 8, offset += 8) {
rc = write_dword(dev, offset, ((const u64_t *) data)[i>>3]);
if (rc < 0) {
return rc;
}
}

return rc;
}

void flash_stm32_page_layout(struct device *dev,
const struct flash_pages_layout **layout,
size_t *layout_size)
{
static struct flash_pages_layout stm32g0_flash_layout = {
.pages_count = 0,
.pages_size = 0,
};

ARG_UNUSED(dev);

if (stm32g0_flash_layout.pages_count == 0) {
stm32g0_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
stm32g0_flash_layout.pages_size = FLASH_PAGE_SIZE;
}

*layout = &stm32g0_flash_layout;
*layout_size = 1;
}
@@ -0,0 +1,13 @@

title: STM32 G0 Flash Controller
version: 0.1

description: >
This binding gives a base representation of the STM32 G0 Flash Controller
inherits:
!include flash-controller.yaml

properties:
compatible:
constraint: "st,stm32g0-flash-controller"
@@ -8,4 +8,7 @@

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32G0_FLASH_CONTROLLER_40022000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_ST_STM32G0_FLASH_CONTROLLER_40022000_LABEL

/* End of SoC Level DTS fixup file */
@@ -0,0 +1,53 @@
/*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
*
* SPDX-License-Identifier: Apache-2.0
*/

#ifndef _STM32G0X_FLASH_REGISTERS_H_
#define _STM32G0X_FLASH_REGISTERS_H_

#define FLASH_SR_BSY FLASH_SR_BSY1

enum {
STM32_FLASH_LATENCY_0 = 0x0,
STM32_FLASH_LATENCY_1 = 0x1,
STM32_FLASH_LATENCY_2 = 0x2,
};

/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3_7 :5 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t rsvd__10 :1 __packed;
u32_t icrst :1 __packed;
u32_t rsvd__12_15 :4 __packed;
u32_t empty :1 __packed;
u32_t rsvd__17 :1 __packed;
u32_t dbg_swend :1 __packed;
u32_t rsvd__19_31 :13 __packed;
} bit;
};

/* FLASH register map */
struct stm32g0x_flash {
volatile union __ef_acr acr;
volatile u32_t rsvd__4;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t rsvd_0;
volatile u32_t optr;
volatile u32_t pcrop1sr;
volatile u32_t pcrop1er;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
};

#endif /* _STM32G0X_FLASH_REGISTERS_H_ */

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