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soc/apollo_lake: boards/up_squared: move UART fixups to SoC

The UART references in dts_fixup.h are actually SoC-specific, not
board-specific, so they are moved. Since this leaves the board fixups
empty, the file is removed.

The SoC fixups are expanded to include the additional two ports that
are present on some revisions of the Apollo Lake.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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Charles E. Youse authored and nashif committed May 23, 2019
1 parent 629805d commit c0502d9602e7395c60c409094477846515ecbbf4
Showing with 56 additions and 37 deletions.
  1. +0 −37 boards/x86/up_squared/dts_fixup.h
  2. +56 −0 soc/x86/apollo_lake/dts_fixup.h

This file was deleted.

@@ -37,4 +37,60 @@
#define DT_APL_GPIO_LABEL_SW_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_0"
#define DT_APL_GPIO_LABEL_SW_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_1"

#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_0_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_SIZE DT_NS16550_0_SIZE
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_0_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_0_LABEL
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_0_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_0_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_0_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_0_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_PCIE DT_NS16550_0_PCIE

#ifdef DT_NS16550_0_PCP
#define DT_UART_NS16550_PORT_0_PCP DT_NS16550_0_PCP
#endif

#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_1_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_SIZE DT_NS16550_1_SIZE
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_1_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_1_LABEL
#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_1_IRQ_0
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_1_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_1_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_1_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_1_PCIE DT_NS16550_1_PCIE

#ifdef DT_NS16550_1_PCP
#define DT_UART_NS16550_PORT_1_PCP DT_NS16550_1_PCP
#endif

#define DT_UART_NS16550_PORT_2_BASE_ADDR DT_NS16550_2_BASE_ADDRESS
#define DT_UART_NS16550_PORT_2_SIZE DT_NS16550_2_SIZE
#define DT_UART_NS16550_PORT_2_BAUD_RATE DT_NS16550_2_CURRENT_SPEED
#define DT_UART_NS16550_PORT_2_NAME DT_NS16550_2_LABEL
#define DT_UART_NS16550_PORT_2_IRQ DT_NS16550_2_IRQ_0
#define DT_UART_NS16550_PORT_2_IRQ_PRI DT_NS16550_2_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_2_IRQ_FLAGS DT_NS16550_2_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_2_CLK_FREQ DT_NS16550_2_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_2_PCIE DT_NS16550_2_PCIE

#ifdef DT_NS16550_2_PCP
#define DT_UART_NS16550_PORT_2_PCP DT_NS16550_2_PCP
#endif

#define DT_UART_NS16550_PORT_3_BASE_ADDR DT_NS16550_3_BASE_ADDRESS
#define DT_UART_NS16550_PORT_3_SIZE DT_NS16550_3_SIZE
#define DT_UART_NS16550_PORT_3_BAUD_RATE DT_NS16550_3_CURRENT_SPEED
#define DT_UART_NS16550_PORT_3_NAME DT_NS16550_3_LABEL
#define DT_UART_NS16550_PORT_3_IRQ DT_NS16550_3_IRQ_0
#define DT_UART_NS16550_PORT_3_IRQ_PRI DT_NS16550_3_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_3_IRQ_FLAGS DT_NS16550_3_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_3_CLK_FREQ DT_NS16550_3_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_3_PCIE DT_NS16550_3_PCIE

#ifdef DT_NS16550_3_PCP
#define DT_UART_NS16550_PORT_3_PCP DT_NS16550_3_PCP
#endif

/* End of SoC Level DTS fixup file */

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