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arch/x86: clean up model-specific register definitions in msr.h

Eliminate definitions for MSRs that we don't use. Centralize the
definitions for the MSRs that we do use, including their fields.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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Charles E. Youse authored and nashif committed Jun 27, 2019
1 parent 8a8e6a1 commit c7bc7a8c8641d268d7f43ffe2f2242881dde75b8
Showing with 11 additions and 249 deletions.
  1. +2 −6 arch/x86/core/ia32/spec_ctrl.c
  2. +9 −243 include/arch/x86/msr.h
@@ -24,10 +24,6 @@
#define CPUID_SPEC_CTRL_SSBD BIT(31)
#define CPUID_SPEC_CTRL_IBRS BIT(26)

/* Bits to set in X86_SPEC_CTRL_MSR to enable */
#define SPEC_CTRL_IBRS BIT(0)
#define SPEC_CTRL_SSBD BIT(2)

#if defined(CONFIG_DISABLE_SSBD) || defined(CONFIG_ENABLE_EXTENDED_IBRS)
static u32_t cpuid_extended_features(void)
{
@@ -50,12 +46,12 @@ static int spec_ctrl_init(struct device *dev)

#ifdef CONFIG_DISABLE_SSBD
if ((cpuid7 & CPUID_SPEC_CTRL_SSBD) != 0U) {
enable_bits |= SPEC_CTRL_SSBD;
enable_bits |= X86_SPEC_CTRL_MSR_SSBD;
}
#endif
#ifdef CONFIG_ENABLE_EXTENDED_IBRS
if ((cpuid7 & CPUID_SPEC_CTRL_IBRS) != 0U) {
enable_bits |= SPEC_CTRL_IBRS;
enable_bits |= X86_SPEC_CTRL_MSR_IBRS;
}
#endif
if (enable_bits != 0U) {
@@ -7,254 +7,20 @@
#define ZEPHYR_INCLUDE_ARCH_X86_MSR_H_

/*
* Model specific register (MSR) definitions. Use the z_x86_msr_read() and
* z_x86_msr_write() primitives to read/write the MSRs. Only the so-called
* "Architectural MSRs" are listed, i.e. the subset of MSRs and associated
* bit fields which will not change on future processor generations.
* Model specific registers (MSR). Access with z_x86_msr_read/write().
*/

#define X86_P5_MC_ADDR_MSR 0x0000
#define X86_P5_MC_TYPE_MSR 0x0001
#define X86_MONITOR_FILTER_SIZE_MSR 0x0006
#define X86_TIME_STAMP_COUNTER_MSR 0x0010
#define X86_X86_SOC_ID_MSR 0x0017
#define X86_SPEC_CTRL_MSR 0x0048
#define X86_SPEC_CTRL_MSR_IBRS BIT(0)
#define X86_SPEC_CTRL_MSR_SSBD BIT(2)

#define X86_APIC_BASE_MSR 0x001b
#define X86_APIC_BASE_MSR_X2APIC BIT(10)
#define X86_APIC_BASE_MSR 0x001b
#define X86_APIC_BASE_MSR_X2APIC BIT(10)

#define X86_FEATURE_CONTROL_MSR 0x003a
#define X86_BIOS_SIGN_MSR 0x008b
#define X86_SMM_MONITOR_CTL_MSR 0x009b
#define X86_PMC0_MSR 0x00c1
#define X86_PMC1_MSR 0x00c2
#define X86_PMC2_MSR 0x00c3
#define X86_PMC3_MSR 0x00c4
#define X86_MPERF_MSR 0x00e7
#define X86_APERF_MSR 0x00e8
#define X86_MTRRCAP_MSR 0x00fe
#define X86_SYSENTER_CS_MSR 0x0174
#define X86_SYSENTER_ESP_MSR 0x0175
#define X86_SYSENTER_EIP_MSR 0x0176
#define X86_MCG_CAP_MSR 0x0179
#define X86_MCG_STATUS_MSR 0x017a
#define X86_MCG_CTL_MSR 0x017b
#define X86_PERFEVTSEL0_MSR 0x0186
#define X86_PERFEVTSEL1_MSR 0x0187
#define X86_PERFEVTSEL2_MSR 0x0188
#define X86_PERFEVTSEL3_MSR 0x0188
#define X86_PERF_STATUS_MSR 0x0198
#define X86_PERF_CTL_MSR 0x0199
#define X86_CLOCK_MODULATION_MSR 0x019a
#define X86_THERM_INTERRUPT_MSR 0x019b
#define X86_THERM_STATUS_MSR 0x019c
#define X86_MISC_ENABLE_MSR 0x01a0
#define X86_ENERGY_PERF_BIAS_MSR 0x01b0
#define X86_DEBUGCTL_MSR 0x01d9
#define X86_SMRR_PHYSBASE_MSR 0x01f2
#define X86_SMRR_PHYSMASK_MSR 0x01f3
#define X86_SOC_DCA_CAP_MSR 0x01f8
#define X86_CPU_DCA_CAP_MSR 0x01f9
#define X86_DCA_0_CAP_MSR 0x01fa
#define X86_MTRR_PHYSBASE0_MSR 0x0200
#define X86_MTRR_PHYSMASK0_MSR 0x0201
#define X86_MTRR_PHYSBASE1_MSR 0x0202
#define X86_MTRR_PHYSMASK1_MSR 0x0203
#define X86_MTRR_PHYSBASE2_MSR 0x0204
#define X86_MTRR_PHYSMASK2_MSR 0x0205
#define X86_MTRR_PHYSBASE3_MSR 0x0206
#define X86_MTRR_PHYSMASK3_MSR 0x0207
#define X86_MTRR_PHYSBASE4_MSR 0x0208
#define X86_MTRR_PHYSMASK4_MSR 0x0209
#define X86_MTRR_PHYSBASE5_MSR 0x020a
#define X86_MTRR_PHYSMASK5_MSR 0x020b
#define X86_MTRR_PHYSBASE6_MSR 0x020c
#define X86_MTRR_PHYSMASK6_MSR 0x020d
#define X86_MTRR_PHYSBASE7_MSR 0x020e
#define X86_MTRR_PHYSMASK7_MSR 0x020f
#define X86_MTRR_FIX64K_00000_MSR 0x0250
#define X86_MTRR_FIX16K_80000_MSR 0x0258
#define X86_MTRR_FIX16K_A0000_MSR 0x0259
#define X86_MTRR_FIX4K_C0000_MSR 0x0268
#define X86_MTRR_FIX4K_C8000_MSR 0x0269
#define X86_MTRR_FIX4K_D0000_MSR 0x026a
#define X86_MTRR_FIX4K_D8000_MSR 0x026b
#define X86_MTRR_FIX4K_E0000_MSR 0x026c
#define X86_MTRR_FIX4K_E8000_MSR 0x026d
#define X86_MTRR_FIX4K_F0000_MSR 0x026e
#define X86_MTRR_FIX4K_F8000_MSR 0x026f
#define X86_PAT_MSR 0x0277
#define X86_MC0_CTL2_MSR 0x0280
#define X86_MC1_CTL2_MSR 0x0281
#define X86_MC2_CTL2_MSR 0x0282
#define X86_MC3_CTL2_MSR 0x0283
#define X86_MC4_CTL2_MSR 0x0284
#define X86_MC5_CTL2_MSR 0x0285
#define X86_MC6_CTL2_MSR 0x0286
#define X86_MC7_CTL2_MSR 0x0287
#define X86_MC8_CTL2_MSR 0x0288
#define X86_MC9_CTL2_MSR 0x0289
#define X86_MC10_CTL2_MSR 0x028a
#define X86_MC11_CTL2_MSR 0x028b
#define X86_MC12_CTL2_MSR 0x028c
#define X86_MC13_CTL2_MSR 0x028d
#define X86_MC14_CTL2_MSR 0x028e
#define X86_MC15_CTL2_MSR 0x028f
#define X86_MC16_CTL2_MSR 0x0290
#define X86_MC17_CTL2_MSR 0x0291
#define X86_MC18_CTL2_MSR 0x0292
#define X86_MC19_CTL2_MSR 0x0293
#define X86_MC20_CTL2_MSR 0x0294
#define X86_MC21_CTL2_MSR 0x0295
#define X86_MTRR_DEF_TYPE_MSR 0x02ff
#define X86_MTRR_DEF_TYPE_MSR_ENABLE BIT(11)

#define X86_MTRR_DEF_TYPE_MSR 0x02ff
#define X86_MTRR_DEF_TYPE_MSR_ENABLE BIT(11)

#define X86_FIXED_CTR0_MSR 0x0309
#define X86_FIXED_CTR1_MSR 0x030a
#define X86_FIXED_CTR2_MSR 0x030b
#define X86_PERF_CAPABILITIES_MSR 0x0345
#define X86_FIXED_CTR_CTL_MSR 0x038d
#define X86_PERF_GLOBAL_STATUS_MSR 0x038e
#define X86_PERF_GLOBAL_CTRL_MSR 0x038f
#define X86_PERF_GLOBAL_OVF_CTRL_MSR 0x0390
#define X86_PEBS_ENABLE_MSR 0x03f1
#define X86_MC0_CTL_MSR 0x0400
#define X86_MC0_STATUS 0x0401
#define X86_MC0_ADDR_MSR 0x0402
#define X86_MC0_MISC_MSR 0x0403
#define X86_MC1_CTL_MSR 0x0404
#define X86_MC1_STATUS_MSR 0x0405
#define X86_MC1_ADDR_MSR 0x0406
#define X86_MC1_MISC_MSR 0x0407
#define X86_MC2_CTL_MSR 0x0408
#define X86_MC2_STATUS_MSR 0x0409
#define X86_MC2_ADDR_MSR 0x040a
#define X86_MC2_MISC_MSR 0x040b
#define X86_MC3_CTL_MSR 0x040c
#define X86_MC3_STATUS_MSR 0x040d
#define X86_MC3_ADDR_MSR 0x040e
#define X86_MC3_MISC_MSR 0x040f
#define X86_MC4_CTL_MSR 0x0410
#define X86_MC4_STATUS_MSR 0x0411
#define X86_MC4_ADDR_MSR 0x0412
#define X86_MC4_MISC_MSR 0x0413
#define X86_MC5_CTL_MSR 0x0414
#define X86_MC5_STATUS_MSR 0x0415
#define X86_MC5_ADDR_MSR 0x0416
#define X86_MC5_MISC_MSR 0x0417
#define X86_MC6_CTL_MSR 0x0418
#define X86_MC6_STATUS_MSR 0x0419
#define X86_MC6_ADDR_MSR 0x041a
#define X86_MC6_MISC_MSR 0x041b
#define X86_MC7_CTL_MSR 0x041c
#define X86_MC7_STATUS_MSR 0x041d
#define X86_MC7_ADDR_MSR 0x041e
#define X86_MC7_MISC_MSR 0x041f
#define X86_MC8_CTL_MSR 0x0420
#define X86_MC8_STATUS_MSR 0x0421
#define X86_MC8_ADDR_MSR 0x0422
#define X86_MC8_MISC_MSR 0x0423
#define X86_MC9_CTL_MSR 0x0424
#define X86_MC9_STATUS_MSR 0x0425
#define X86_MC9_ADDR_MSR 0x0426
#define X86_MC9_MISC_MSR 0x0427
#define X86_MC9_CTL_MSR 0x0424
#define X86_MC9_STATUS_MSR 0x0425
#define X86_MC9_ADDR_MSR 0x0426
#define X86_MC9_MISC_MSR 0x0427
#define X86_MC9_CTL_MSR 0x0424
#define X86_MC9_STATUS_MSR 0x0425
#define X86_MC9_ADDR_MSR 0x0426
#define X86_MC9_MISC_MSR 0x0427
#define X86_MC9_CTL_MSR 0x0424
#define X86_MC9_STATUS_MSR 0x0425
#define X86_MC9_ADDR_MSR 0x0426
#define X86_MC9_MISC_MSR 0x0427
#define X86_MC10_CTL_MSR 0x0428
#define X86_MC10_STATUS_MSR 0x0429
#define X86_MC10_ADDR_MSR 0x042a
#define X86_MC10_MISC_MSR 0x042b
#define X86_MC11_CTL_MSR 0x042c
#define X86_MC11_STATUS_MSR 0x042d
#define X86_MC11_ADDR_MSR 0x042e
#define X86_MC11_MISC_MSR 0x042f
#define X86_MC12_CTL_MSR 0x0430
#define X86_MC12_STATUS_MSR 0x0431
#define X86_MC12_ADDR_MSR 0x0432
#define X86_MC12_MISC_MSR 0x0433
#define X86_MC13_CTL_MSR 0x0434
#define X86_MC13_STATUS_MSR 0x0435
#define X86_MC13_ADDR_MSR 0x0436
#define X86_MC13_MISC_MSR 0x0437
#define X86_MC14_CTL_MSR 0x0438
#define X86_MC14_STATUS_MSR 0x0439
#define X86_MC14_ADDR_MSR 0x043a
#define X86_MC14_MISC_MSR 0x043b
#define X86_MC15_CTL_MSR 0x043c
#define X86_MC15_STATUS_MSR 0x043d
#define X86_MC15_ADDR_MSR 0x043e
#define X86_MC15_MISC_MSR 0x043f
#define X86_MC16_CTL_MSR 0x0440
#define X86_MC16_STATUS_MSR 0x0441
#define X86_MC16_ADDR_MSR 0x0442
#define X86_MC16_MISC_MSR 0x0443
#define X86_MC17_CTL_MSR 0x0444
#define X86_MC17_STATUS_MSR 0x0445
#define X86_MC17_ADDR_MSR 0x0446
#define X86_MC17_MISC_MSR 0x0447
#define X86_MC18_CTL_MSR 0x0448
#define X86_MC18_STATUS_MSR 0x0449
#define X86_MC18_ADDR_MSR 0x044a
#define X86_MC18_MISC_MSR 0x044b
#define X86_MC19_CTL_MSR 0x044c
#define X86_MC19_STATUS_MSR 0x044d
#define X86_MC19_ADDR_MSR 0x044e
#define X86_MC19_MISC_MSR 0x044f
#define X86_MC20_CTL_MSR 0x0450
#define X86_MC20_STATUS_MSR 0x0451
#define X86_MC20_ADDR_MSR 0x0452
#define X86_MC20_MISC_MSR 0x0453
#define X86_MC21_CTL_MSR 0x0454
#define X86_MC21_STATUS_MSR 0x0455
#define X86_MC21_ADDR_MSR 0x0456
#define X86_MC21_MISC_MSR 0x0457
#define X86_VMX_BASIC_MSR 0x0480
#define X86_VMX_PINBASED_CTLS_MSR 0x0481
#define X86_VMX_PROCBASED_CTLS_MSR 0x0482
#define X86_VMX_EXIT_CTLS_MSR 0x0483
#define X86_VMX_ENTRY_CTLS_MSR 0x0484
#define X86_VMX_MISC_MSR 0x0485
#define X86_VMX_CRO_FIXED0_MSR 0x0486
#define X86_VMX_CRO_FIXED1_MSR 0x0487
#define X86_VMX_CR4_FIXED0_MSR 0x0488
#define X86_VMX_CR4_FIXED1_MSR 0x0489
#define X86_VMX_VMCS_ENUM_MSR 0x048a
#define X86_VMX_PROCBASED_CTLS2_MSR 0x048b
#define X86_VMX_EPT_VPID_CAP_MSR 0x048c
#define X86_VMX_TRUE_PINBASED_CTLS_MSR 0x048d
#define X86_VMX_TRUE_PROCBASED_CTLS_MSR 0x048e
#define X86_VMX_TRUE_EXIT_CTLS_MSR 0x048f
#define X86_VMX_TRUE_ENTRY_CTLS_MSR 0x0490
#define X86_DS_AREA_MSR 0x0600

/*
* MSRs 0x0800 to 0x0BFF are reserved for x2APIC access.
*
* We only record the base address here, as the local APIC code
* knows how to find the registers, see include/drivers/interrupt_controller/loapic.h.
*/

#define X86_X2APIC_BASE_MSR 0x0800

#define X86_EFER_MSR 0xc0000080
#define X86_STAR_MSR 0xc0000081
#define X86_LSTAR_MSR 0xc0000082
#define X86_FMASK_MSR 0xc0000084
#define X86_FS_BASE_MSR 0xc0000100
#define X86_GS_BASE_MSR 0xc0000101
#define X86_KERNEL_GS_BASE_MSR 0xc0000102
#define X86_TSC_AUX_MSR 0xc0000103
#define X86_SPEC_CTRL_MSR 0x48
#define X86_X2APIC_BASE_MSR 0x0800 /* 0x0800-0x0BFF -> x2APIC */

#ifndef _ASMLANGUAGE
#ifdef __cplusplus

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